ARMInstrInfo.td revision 234353
1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21 22def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 23 24def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 25 26def SDT_ARMCMov : SDTypeProfile<1, 3, 27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 28 SDTCisVT<3, i32>]>; 29 30def SDT_ARMBrcond : SDTypeProfile<0, 2, 31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 32 33def SDT_ARMBrJT : SDTypeProfile<0, 3, 34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 35 SDTCisVT<2, i32>]>; 36 37def SDT_ARMBr2JT : SDTypeProfile<0, 4, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 40 41def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 42 [SDTCisVT<0, i32>, 43 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 44 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 45 SDTCisVT<5, OtherVT>]>; 46 47def SDT_ARMAnd : SDTypeProfile<1, 2, 48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 49 SDTCisVT<2, i32>]>; 50 51def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 52 53def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 55 56def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 57def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 58 SDTCisInt<2>]>; 59def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 60 61def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 62 63def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 64 SDTCisInt<1>]>; 65 66def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 67 68def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 69 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 70 71def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 72 [SDTCisSameAs<0, 2>, 73 SDTCisSameAs<0, 3>, 74 SDTCisInt<0>, SDTCisVT<1, i32>]>; 75 76// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 77def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 78 [SDTCisSameAs<0, 2>, 79 SDTCisSameAs<0, 3>, 80 SDTCisInt<0>, 81 SDTCisVT<1, i32>, 82 SDTCisVT<4, i32>]>; 83// Node definitions. 84def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 85def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>; 86def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 87def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 88 89def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 90 [SDNPHasChain, SDNPOutGlue]>; 91def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 92 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 93 94def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 95 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 96 SDNPVariadic]>; 97def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 98 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 99 SDNPVariadic]>; 100def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 101 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 102 SDNPVariadic]>; 103 104def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 105 [SDNPHasChain, SDNPOptInGlue]>; 106 107def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 108 [SDNPInGlue]>; 109 110def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 111 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 112 113def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 114 [SDNPHasChain]>; 115def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 116 [SDNPHasChain]>; 117 118def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 119 [SDNPHasChain]>; 120 121def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 122 [SDNPOutGlue]>; 123 124def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 125 [SDNPOutGlue, SDNPCommutative]>; 126 127def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 128 129def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 130def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 131def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 132 133def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 134 [SDNPCommutative]>; 135def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 136def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 137def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 138 139def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 140def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 141 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>; 142def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 143 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>; 144 145def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER, 146 [SDNPHasChain]>; 147def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 148 [SDNPHasChain]>; 149def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 150 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 151 152def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 153 154def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 156 157 158def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 159 160//===----------------------------------------------------------------------===// 161// ARM Instruction Predicate Definitions. 162// 163def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 164 AssemblerPredicate<"HasV4TOps">; 165def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 166def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 167def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 168 AssemblerPredicate<"HasV5TEOps">; 169def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 170 AssemblerPredicate<"HasV6Ops">; 171def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 172def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 173 AssemblerPredicate<"HasV6T2Ops">; 174def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 175def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 176 AssemblerPredicate<"HasV7Ops">; 177def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 178def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 179 AssemblerPredicate<"FeatureVFP2">; 180def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 181 AssemblerPredicate<"FeatureVFP3">; 182def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 183 AssemblerPredicate<"FeatureVFP4">; 184def HasNEON : Predicate<"Subtarget->hasNEON()">, 185 AssemblerPredicate<"FeatureNEON">; 186def HasFP16 : Predicate<"Subtarget->hasFP16()">, 187 AssemblerPredicate<"FeatureFP16">; 188def HasDivide : Predicate<"Subtarget->hasDivide()">, 189 AssemblerPredicate<"FeatureHWDiv">; 190def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">, 191 AssemblerPredicate<"FeatureT2XtPk">; 192def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">, 193 AssemblerPredicate<"FeatureDSPThumb2">; 194def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 195 AssemblerPredicate<"FeatureDB">; 196def HasMP : Predicate<"Subtarget->hasMPExtension()">, 197 AssemblerPredicate<"FeatureMP">; 198def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 199def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 200def IsThumb : Predicate<"Subtarget->isThumb()">, 201 AssemblerPredicate<"ModeThumb">; 202def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 203def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 204 AssemblerPredicate<"ModeThumb,FeatureThumb2">; 205def IsMClass : Predicate<"Subtarget->isMClass()">, 206 AssemblerPredicate<"FeatureMClass">; 207def IsARClass : Predicate<"!Subtarget->isMClass()">, 208 AssemblerPredicate<"!FeatureMClass">; 209def IsARM : Predicate<"!Subtarget->isThumb()">, 210 AssemblerPredicate<"!ModeThumb">; 211def IsIOS : Predicate<"Subtarget->isTargetIOS()">; 212def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">; 213def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 214 215// FIXME: Eventually this will be just "hasV6T2Ops". 216def UseMovt : Predicate<"Subtarget->useMovt()">; 217def DontUseMovt : Predicate<"!Subtarget->useMovt()">; 218def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; 219 220// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 221// But only select them if more precision in FP computation is allowed. 222def UseFusedMAC : Predicate<"!TM.Options.NoExcessFPPrecision">; 223def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4()">; 224 225//===----------------------------------------------------------------------===// 226// ARM Flag Definitions. 227 228class RegConstraint<string C> { 229 string Constraints = C; 230} 231 232//===----------------------------------------------------------------------===// 233// ARM specific transformation functions and pattern fragments. 234// 235 236// so_imm_neg_XFORM - Return a so_imm value packed into the format described for 237// so_imm_neg def below. 238def so_imm_neg_XFORM : SDNodeXForm<imm, [{ 239 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 240}]>; 241 242// so_imm_not_XFORM - Return a so_imm value packed into the format described for 243// so_imm_not def below. 244def so_imm_not_XFORM : SDNodeXForm<imm, [{ 245 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 246}]>; 247 248/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 249def imm16_31 : ImmLeaf<i32, [{ 250 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 251}]>; 252 253def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; } 254def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 255 int64_t Value = -(int)N->getZExtValue(); 256 return Value && ARM_AM::getSOImmVal(Value) != -1; 257 }], so_imm_neg_XFORM> { 258 let ParserMatchClass = so_imm_neg_asmoperand; 259} 260 261// Note: this pattern doesn't require an encoder method and such, as it's 262// only used on aliases (Pat<> and InstAlias<>). The actual encoding 263// is handled by the destination instructions, which use so_imm. 264def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; } 265def so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 266 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 267 }], so_imm_not_XFORM> { 268 let ParserMatchClass = so_imm_not_asmoperand; 269} 270 271// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 272def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 273 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 274}]>; 275 276/// Split a 32-bit immediate into two 16 bit parts. 277def hi16 : SDNodeXForm<imm, [{ 278 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 279}]>; 280 281def lo16AllZero : PatLeaf<(i32 imm), [{ 282 // Returns true if all low 16-bits are 0. 283 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 284}], hi16>; 285 286class BinOpWithFlagFrag<dag res> : 287 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>; 288class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 289class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 290 291// An 'and' node with a single use. 292def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 293 return N->hasOneUse(); 294}]>; 295 296// An 'xor' node with a single use. 297def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 298 return N->hasOneUse(); 299}]>; 300 301// An 'fmul' node with a single use. 302def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 303 return N->hasOneUse(); 304}]>; 305 306// An 'fadd' node which checks for single non-hazardous use. 307def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 308 return hasNoVMLxHazardUse(N); 309}]>; 310 311// An 'fsub' node which checks for single non-hazardous use. 312def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 313 return hasNoVMLxHazardUse(N); 314}]>; 315 316//===----------------------------------------------------------------------===// 317// Operand Definitions. 318// 319 320// Immediate operands with a shared generic asm render method. 321class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; } 322 323// Branch target. 324// FIXME: rename brtarget to t2_brtarget 325def brtarget : Operand<OtherVT> { 326 let EncoderMethod = "getBranchTargetOpValue"; 327 let OperandType = "OPERAND_PCREL"; 328 let DecoderMethod = "DecodeT2BROperand"; 329} 330 331// FIXME: get rid of this one? 332def uncondbrtarget : Operand<OtherVT> { 333 let EncoderMethod = "getUnconditionalBranchTargetOpValue"; 334 let OperandType = "OPERAND_PCREL"; 335} 336 337// Branch target for ARM. Handles conditional/unconditional 338def br_target : Operand<OtherVT> { 339 let EncoderMethod = "getARMBranchTargetOpValue"; 340 let OperandType = "OPERAND_PCREL"; 341} 342 343// Call target. 344// FIXME: rename bltarget to t2_bl_target? 345def bltarget : Operand<i32> { 346 // Encoded the same as branch targets. 347 let EncoderMethod = "getBranchTargetOpValue"; 348 let OperandType = "OPERAND_PCREL"; 349} 350 351// Call target for ARM. Handles conditional/unconditional 352// FIXME: rename bl_target to t2_bltarget? 353def bl_target : Operand<i32> { 354 let EncoderMethod = "getARMBLTargetOpValue"; 355 let OperandType = "OPERAND_PCREL"; 356} 357 358def blx_target : Operand<i32> { 359 let EncoderMethod = "getARMBLXTargetOpValue"; 360 let OperandType = "OPERAND_PCREL"; 361} 362 363// A list of registers separated by comma. Used by load/store multiple. 364def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 365def reglist : Operand<i32> { 366 let EncoderMethod = "getRegisterListOpValue"; 367 let ParserMatchClass = RegListAsmOperand; 368 let PrintMethod = "printRegisterList"; 369 let DecoderMethod = "DecodeRegListOperand"; 370} 371 372def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; } 373def dpr_reglist : Operand<i32> { 374 let EncoderMethod = "getRegisterListOpValue"; 375 let ParserMatchClass = DPRRegListAsmOperand; 376 let PrintMethod = "printRegisterList"; 377 let DecoderMethod = "DecodeDPRRegListOperand"; 378} 379 380def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; } 381def spr_reglist : Operand<i32> { 382 let EncoderMethod = "getRegisterListOpValue"; 383 let ParserMatchClass = SPRRegListAsmOperand; 384 let PrintMethod = "printRegisterList"; 385 let DecoderMethod = "DecodeSPRRegListOperand"; 386} 387 388// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 389def cpinst_operand : Operand<i32> { 390 let PrintMethod = "printCPInstOperand"; 391} 392 393// Local PC labels. 394def pclabel : Operand<i32> { 395 let PrintMethod = "printPCLabel"; 396} 397 398// ADR instruction labels. 399def adrlabel : Operand<i32> { 400 let EncoderMethod = "getAdrLabelOpValue"; 401} 402 403def neon_vcvt_imm32 : Operand<i32> { 404 let EncoderMethod = "getNEONVcvtImm32OpValue"; 405 let DecoderMethod = "DecodeVCVTImmOperand"; 406} 407 408// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 409def rot_imm_XFORM: SDNodeXForm<imm, [{ 410 switch (N->getZExtValue()){ 411 default: assert(0); 412 case 0: return CurDAG->getTargetConstant(0, MVT::i32); 413 case 8: return CurDAG->getTargetConstant(1, MVT::i32); 414 case 16: return CurDAG->getTargetConstant(2, MVT::i32); 415 case 24: return CurDAG->getTargetConstant(3, MVT::i32); 416 } 417}]>; 418def RotImmAsmOperand : AsmOperandClass { 419 let Name = "RotImm"; 420 let ParserMethod = "parseRotImm"; 421} 422def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 423 int32_t v = N->getZExtValue(); 424 return v == 8 || v == 16 || v == 24; }], 425 rot_imm_XFORM> { 426 let PrintMethod = "printRotImmOperand"; 427 let ParserMatchClass = RotImmAsmOperand; 428} 429 430// shift_imm: An integer that encodes a shift amount and the type of shift 431// (asr or lsl). The 6-bit immediate encodes as: 432// {5} 0 ==> lsl 433// 1 asr 434// {4-0} imm5 shift amount. 435// asr #32 encoded as imm5 == 0. 436def ShifterImmAsmOperand : AsmOperandClass { 437 let Name = "ShifterImm"; 438 let ParserMethod = "parseShifterImm"; 439} 440def shift_imm : Operand<i32> { 441 let PrintMethod = "printShiftImmOperand"; 442 let ParserMatchClass = ShifterImmAsmOperand; 443} 444 445// shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm. 446def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 447def so_reg_reg : Operand<i32>, // reg reg imm 448 ComplexPattern<i32, 3, "SelectRegShifterOperand", 449 [shl, srl, sra, rotr]> { 450 let EncoderMethod = "getSORegRegOpValue"; 451 let PrintMethod = "printSORegRegOperand"; 452 let DecoderMethod = "DecodeSORegRegOperand"; 453 let ParserMatchClass = ShiftedRegAsmOperand; 454 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 455} 456 457def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 458def so_reg_imm : Operand<i32>, // reg imm 459 ComplexPattern<i32, 2, "SelectImmShifterOperand", 460 [shl, srl, sra, rotr]> { 461 let EncoderMethod = "getSORegImmOpValue"; 462 let PrintMethod = "printSORegImmOperand"; 463 let DecoderMethod = "DecodeSORegImmOperand"; 464 let ParserMatchClass = ShiftedImmAsmOperand; 465 let MIOperandInfo = (ops GPR, i32imm); 466} 467 468// FIXME: Does this need to be distinct from so_reg? 469def shift_so_reg_reg : Operand<i32>, // reg reg imm 470 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 471 [shl,srl,sra,rotr]> { 472 let EncoderMethod = "getSORegRegOpValue"; 473 let PrintMethod = "printSORegRegOperand"; 474 let DecoderMethod = "DecodeSORegRegOperand"; 475 let ParserMatchClass = ShiftedRegAsmOperand; 476 let MIOperandInfo = (ops GPR, GPR, i32imm); 477} 478 479// FIXME: Does this need to be distinct from so_reg? 480def shift_so_reg_imm : Operand<i32>, // reg reg imm 481 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 482 [shl,srl,sra,rotr]> { 483 let EncoderMethod = "getSORegImmOpValue"; 484 let PrintMethod = "printSORegImmOperand"; 485 let DecoderMethod = "DecodeSORegImmOperand"; 486 let ParserMatchClass = ShiftedImmAsmOperand; 487 let MIOperandInfo = (ops GPR, i32imm); 488} 489 490 491// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 492// 8-bit immediate rotated by an arbitrary number of bits. 493def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; } 494def so_imm : Operand<i32>, ImmLeaf<i32, [{ 495 return ARM_AM::getSOImmVal(Imm) != -1; 496 }]> { 497 let EncoderMethod = "getSOImmOpValue"; 498 let ParserMatchClass = SOImmAsmOperand; 499 let DecoderMethod = "DecodeSOImmOperand"; 500} 501 502// Break so_imm's up into two pieces. This handles immediates with up to 16 503// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 504// get the first/second pieces. 505def so_imm2part : PatLeaf<(imm), [{ 506 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 507}]>; 508 509/// arm_i32imm - True for +V6T2, or true only if so_imm2part is true. 510/// 511def arm_i32imm : PatLeaf<(imm), [{ 512 if (Subtarget->hasV6T2Ops()) 513 return true; 514 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 515}]>; 516 517/// imm0_1 predicate - Immediate in the range [0,1]. 518def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; } 519def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 520 521/// imm0_3 predicate - Immediate in the range [0,3]. 522def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; } 523def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 524 525/// imm0_7 predicate - Immediate in the range [0,7]. 526def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; } 527def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 528 return Imm >= 0 && Imm < 8; 529}]> { 530 let ParserMatchClass = Imm0_7AsmOperand; 531} 532 533/// imm8 predicate - Immediate is exactly 8. 534def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; } 535def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 536 let ParserMatchClass = Imm8AsmOperand; 537} 538 539/// imm16 predicate - Immediate is exactly 16. 540def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; } 541def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 542 let ParserMatchClass = Imm16AsmOperand; 543} 544 545/// imm32 predicate - Immediate is exactly 32. 546def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; } 547def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 548 let ParserMatchClass = Imm32AsmOperand; 549} 550 551/// imm1_7 predicate - Immediate in the range [1,7]. 552def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; } 553def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 554 let ParserMatchClass = Imm1_7AsmOperand; 555} 556 557/// imm1_15 predicate - Immediate in the range [1,15]. 558def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; } 559def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 560 let ParserMatchClass = Imm1_15AsmOperand; 561} 562 563/// imm1_31 predicate - Immediate in the range [1,31]. 564def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; } 565def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 566 let ParserMatchClass = Imm1_31AsmOperand; 567} 568 569/// imm0_15 predicate - Immediate in the range [0,15]. 570def Imm0_15AsmOperand: ImmAsmOperand { let Name = "Imm0_15"; } 571def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 572 return Imm >= 0 && Imm < 16; 573}]> { 574 let ParserMatchClass = Imm0_15AsmOperand; 575} 576 577/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 578def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; } 579def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 580 return Imm >= 0 && Imm < 32; 581}]> { 582 let ParserMatchClass = Imm0_31AsmOperand; 583} 584 585/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 586def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; } 587def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 588 return Imm >= 0 && Imm < 32; 589}]> { 590 let ParserMatchClass = Imm0_32AsmOperand; 591} 592 593/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 594def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; } 595def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 596 return Imm >= 0 && Imm < 64; 597}]> { 598 let ParserMatchClass = Imm0_63AsmOperand; 599} 600 601/// imm0_255 predicate - Immediate in the range [0,255]. 602def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; } 603def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 604 let ParserMatchClass = Imm0_255AsmOperand; 605} 606 607/// imm0_65535 - An immediate is in the range [0.65535]. 608def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; } 609def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 610 return Imm >= 0 && Imm < 65536; 611}]> { 612 let ParserMatchClass = Imm0_65535AsmOperand; 613} 614 615// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 616// a relocatable expression. 617// 618// FIXME: This really needs a Thumb version separate from the ARM version. 619// While the range is the same, and can thus use the same match class, 620// the encoding is different so it should have a different encoder method. 621def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; } 622def imm0_65535_expr : Operand<i32> { 623 let EncoderMethod = "getHiLo16ImmOpValue"; 624 let ParserMatchClass = Imm0_65535ExprAsmOperand; 625} 626 627/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 628def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; } 629def imm24b : Operand<i32>, ImmLeaf<i32, [{ 630 return Imm >= 0 && Imm <= 0xffffff; 631}]> { 632 let ParserMatchClass = Imm24bitAsmOperand; 633} 634 635 636/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 637/// e.g., 0xf000ffff 638def BitfieldAsmOperand : AsmOperandClass { 639 let Name = "Bitfield"; 640 let ParserMethod = "parseBitfield"; 641} 642 643def bf_inv_mask_imm : Operand<i32>, 644 PatLeaf<(imm), [{ 645 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 646}] > { 647 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 648 let PrintMethod = "printBitfieldInvMaskImmOperand"; 649 let DecoderMethod = "DecodeBitfieldMaskOperand"; 650 let ParserMatchClass = BitfieldAsmOperand; 651} 652 653def imm1_32_XFORM: SDNodeXForm<imm, [{ 654 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 655}]>; 656def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; } 657def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 658 uint64_t Imm = N->getZExtValue(); 659 return Imm > 0 && Imm <= 32; 660 }], 661 imm1_32_XFORM> { 662 let PrintMethod = "printImmPlusOneOperand"; 663 let ParserMatchClass = Imm1_32AsmOperand; 664} 665 666def imm1_16_XFORM: SDNodeXForm<imm, [{ 667 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32); 668}]>; 669def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; } 670def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }], 671 imm1_16_XFORM> { 672 let PrintMethod = "printImmPlusOneOperand"; 673 let ParserMatchClass = Imm1_16AsmOperand; 674} 675 676// Define ARM specific addressing modes. 677// addrmode_imm12 := reg +/- imm12 678// 679def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 680def addrmode_imm12 : Operand<i32>, 681 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 682 // 12-bit immediate operand. Note that instructions using this encode 683 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 684 // immediate values are as normal. 685 686 let EncoderMethod = "getAddrModeImm12OpValue"; 687 let PrintMethod = "printAddrModeImm12Operand"; 688 let DecoderMethod = "DecodeAddrModeImm12Operand"; 689 let ParserMatchClass = MemImm12OffsetAsmOperand; 690 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 691} 692// ldst_so_reg := reg +/- reg shop imm 693// 694def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 695def ldst_so_reg : Operand<i32>, 696 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 697 let EncoderMethod = "getLdStSORegOpValue"; 698 // FIXME: Simplify the printer 699 let PrintMethod = "printAddrMode2Operand"; 700 let DecoderMethod = "DecodeSORegMemOperand"; 701 let ParserMatchClass = MemRegOffsetAsmOperand; 702 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 703} 704 705// postidx_imm8 := +/- [0,255] 706// 707// 9 bit value: 708// {8} 1 is imm8 is non-negative. 0 otherwise. 709// {7-0} [0,255] imm8 value. 710def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 711def postidx_imm8 : Operand<i32> { 712 let PrintMethod = "printPostIdxImm8Operand"; 713 let ParserMatchClass = PostIdxImm8AsmOperand; 714 let MIOperandInfo = (ops i32imm); 715} 716 717// postidx_imm8s4 := +/- [0,1020] 718// 719// 9 bit value: 720// {8} 1 is imm8 is non-negative. 0 otherwise. 721// {7-0} [0,255] imm8 value, scaled by 4. 722def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 723def postidx_imm8s4 : Operand<i32> { 724 let PrintMethod = "printPostIdxImm8s4Operand"; 725 let ParserMatchClass = PostIdxImm8s4AsmOperand; 726 let MIOperandInfo = (ops i32imm); 727} 728 729 730// postidx_reg := +/- reg 731// 732def PostIdxRegAsmOperand : AsmOperandClass { 733 let Name = "PostIdxReg"; 734 let ParserMethod = "parsePostIdxReg"; 735} 736def postidx_reg : Operand<i32> { 737 let EncoderMethod = "getPostIdxRegOpValue"; 738 let DecoderMethod = "DecodePostIdxReg"; 739 let PrintMethod = "printPostIdxRegOperand"; 740 let ParserMatchClass = PostIdxRegAsmOperand; 741 let MIOperandInfo = (ops GPRnopc, i32imm); 742} 743 744 745// addrmode2 := reg +/- imm12 746// := reg +/- reg shop imm 747// 748// FIXME: addrmode2 should be refactored the rest of the way to always 749// use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg). 750def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; } 751def addrmode2 : Operand<i32>, 752 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 753 let EncoderMethod = "getAddrMode2OpValue"; 754 let PrintMethod = "printAddrMode2Operand"; 755 let ParserMatchClass = AddrMode2AsmOperand; 756 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 757} 758 759def PostIdxRegShiftedAsmOperand : AsmOperandClass { 760 let Name = "PostIdxRegShifted"; 761 let ParserMethod = "parsePostIdxReg"; 762} 763def am2offset_reg : Operand<i32>, 764 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 765 [], [SDNPWantRoot]> { 766 let EncoderMethod = "getAddrMode2OffsetOpValue"; 767 let PrintMethod = "printAddrMode2OffsetOperand"; 768 // When using this for assembly, it's always as a post-index offset. 769 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 770 let MIOperandInfo = (ops GPRnopc, i32imm); 771} 772 773// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 774// the GPR is purely vestigal at this point. 775def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 776def am2offset_imm : Operand<i32>, 777 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 778 [], [SDNPWantRoot]> { 779 let EncoderMethod = "getAddrMode2OffsetOpValue"; 780 let PrintMethod = "printAddrMode2OffsetOperand"; 781 let ParserMatchClass = AM2OffsetImmAsmOperand; 782 let MIOperandInfo = (ops GPRnopc, i32imm); 783} 784 785 786// addrmode3 := reg +/- reg 787// addrmode3 := reg +/- imm8 788// 789// FIXME: split into imm vs. reg versions. 790def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 791def addrmode3 : Operand<i32>, 792 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 793 let EncoderMethod = "getAddrMode3OpValue"; 794 let PrintMethod = "printAddrMode3Operand"; 795 let ParserMatchClass = AddrMode3AsmOperand; 796 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 797} 798 799// FIXME: split into imm vs. reg versions. 800// FIXME: parser method to handle +/- register. 801def AM3OffsetAsmOperand : AsmOperandClass { 802 let Name = "AM3Offset"; 803 let ParserMethod = "parseAM3Offset"; 804} 805def am3offset : Operand<i32>, 806 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 807 [], [SDNPWantRoot]> { 808 let EncoderMethod = "getAddrMode3OffsetOpValue"; 809 let PrintMethod = "printAddrMode3OffsetOperand"; 810 let ParserMatchClass = AM3OffsetAsmOperand; 811 let MIOperandInfo = (ops GPR, i32imm); 812} 813 814// ldstm_mode := {ia, ib, da, db} 815// 816def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 817 let EncoderMethod = "getLdStmModeOpValue"; 818 let PrintMethod = "printLdStmModeOperand"; 819} 820 821// addrmode5 := reg +/- imm8*4 822// 823def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 824def addrmode5 : Operand<i32>, 825 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 826 let PrintMethod = "printAddrMode5Operand"; 827 let EncoderMethod = "getAddrMode5OpValue"; 828 let DecoderMethod = "DecodeAddrMode5Operand"; 829 let ParserMatchClass = AddrMode5AsmOperand; 830 let MIOperandInfo = (ops GPR:$base, i32imm); 831} 832 833// addrmode6 := reg with optional alignment 834// 835def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 836def addrmode6 : Operand<i32>, 837 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 838 let PrintMethod = "printAddrMode6Operand"; 839 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 840 let EncoderMethod = "getAddrMode6AddressOpValue"; 841 let DecoderMethod = "DecodeAddrMode6Operand"; 842 let ParserMatchClass = AddrMode6AsmOperand; 843} 844 845def am6offset : Operand<i32>, 846 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 847 [], [SDNPWantRoot]> { 848 let PrintMethod = "printAddrMode6OffsetOperand"; 849 let MIOperandInfo = (ops GPR); 850 let EncoderMethod = "getAddrMode6OffsetOpValue"; 851 let DecoderMethod = "DecodeGPRRegisterClass"; 852} 853 854// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 855// (single element from one lane) for size 32. 856def addrmode6oneL32 : Operand<i32>, 857 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 858 let PrintMethod = "printAddrMode6Operand"; 859 let MIOperandInfo = (ops GPR:$addr, i32imm); 860 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 861} 862 863// Special version of addrmode6 to handle alignment encoding for VLD-dup 864// instructions, specifically VLD4-dup. 865def addrmode6dup : Operand<i32>, 866 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 867 let PrintMethod = "printAddrMode6Operand"; 868 let MIOperandInfo = (ops GPR:$addr, i32imm); 869 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 870 // FIXME: This is close, but not quite right. The alignment specifier is 871 // different. 872 let ParserMatchClass = AddrMode6AsmOperand; 873} 874 875// addrmodepc := pc + reg 876// 877def addrmodepc : Operand<i32>, 878 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 879 let PrintMethod = "printAddrModePCOperand"; 880 let MIOperandInfo = (ops GPR, i32imm); 881} 882 883// addr_offset_none := reg 884// 885def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 886def addr_offset_none : Operand<i32>, 887 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 888 let PrintMethod = "printAddrMode7Operand"; 889 let DecoderMethod = "DecodeAddrMode7Operand"; 890 let ParserMatchClass = MemNoOffsetAsmOperand; 891 let MIOperandInfo = (ops GPR:$base); 892} 893 894def nohash_imm : Operand<i32> { 895 let PrintMethod = "printNoHashImmediate"; 896} 897 898def CoprocNumAsmOperand : AsmOperandClass { 899 let Name = "CoprocNum"; 900 let ParserMethod = "parseCoprocNumOperand"; 901} 902def p_imm : Operand<i32> { 903 let PrintMethod = "printPImmediate"; 904 let ParserMatchClass = CoprocNumAsmOperand; 905 let DecoderMethod = "DecodeCoprocessor"; 906} 907 908def CoprocRegAsmOperand : AsmOperandClass { 909 let Name = "CoprocReg"; 910 let ParserMethod = "parseCoprocRegOperand"; 911} 912def c_imm : Operand<i32> { 913 let PrintMethod = "printCImmediate"; 914 let ParserMatchClass = CoprocRegAsmOperand; 915} 916def CoprocOptionAsmOperand : AsmOperandClass { 917 let Name = "CoprocOption"; 918 let ParserMethod = "parseCoprocOptionOperand"; 919} 920def coproc_option_imm : Operand<i32> { 921 let PrintMethod = "printCoprocOptionImm"; 922 let ParserMatchClass = CoprocOptionAsmOperand; 923} 924 925//===----------------------------------------------------------------------===// 926 927include "ARMInstrFormats.td" 928 929//===----------------------------------------------------------------------===// 930// Multiclass helpers... 931// 932 933/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 934/// binop that produces a value. 935multiclass AsI1_bin_irs<bits<4> opcod, string opc, 936 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 937 PatFrag opnode, string baseOpc, bit Commutable = 0> { 938 // The register-immediate version is re-materializable. This is useful 939 // in particular for taking the address of a local. 940 let isReMaterializable = 1 in { 941 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 942 iii, opc, "\t$Rd, $Rn, $imm", 943 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> { 944 bits<4> Rd; 945 bits<4> Rn; 946 bits<12> imm; 947 let Inst{25} = 1; 948 let Inst{19-16} = Rn; 949 let Inst{15-12} = Rd; 950 let Inst{11-0} = imm; 951 } 952 } 953 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 954 iir, opc, "\t$Rd, $Rn, $Rm", 955 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> { 956 bits<4> Rd; 957 bits<4> Rn; 958 bits<4> Rm; 959 let Inst{25} = 0; 960 let isCommutable = Commutable; 961 let Inst{19-16} = Rn; 962 let Inst{15-12} = Rd; 963 let Inst{11-4} = 0b00000000; 964 let Inst{3-0} = Rm; 965 } 966 967 def rsi : AsI1<opcod, (outs GPR:$Rd), 968 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 969 iis, opc, "\t$Rd, $Rn, $shift", 970 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> { 971 bits<4> Rd; 972 bits<4> Rn; 973 bits<12> shift; 974 let Inst{25} = 0; 975 let Inst{19-16} = Rn; 976 let Inst{15-12} = Rd; 977 let Inst{11-5} = shift{11-5}; 978 let Inst{4} = 0; 979 let Inst{3-0} = shift{3-0}; 980 } 981 982 def rsr : AsI1<opcod, (outs GPR:$Rd), 983 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 984 iis, opc, "\t$Rd, $Rn, $shift", 985 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> { 986 bits<4> Rd; 987 bits<4> Rn; 988 bits<12> shift; 989 let Inst{25} = 0; 990 let Inst{19-16} = Rn; 991 let Inst{15-12} = Rd; 992 let Inst{11-8} = shift{11-8}; 993 let Inst{7} = 0; 994 let Inst{6-5} = shift{6-5}; 995 let Inst{4} = 1; 996 let Inst{3-0} = shift{3-0}; 997 } 998 999 // Assembly aliases for optional destination operand when it's the same 1000 // as the source operand. 1001 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 1002 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, 1003 so_imm:$imm, pred:$p, 1004 cc_out:$s)>, 1005 Requires<[IsARM]>; 1006 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"), 1007 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, 1008 GPR:$Rm, pred:$p, 1009 cc_out:$s)>, 1010 Requires<[IsARM]>; 1011 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1012 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, 1013 so_reg_imm:$shift, pred:$p, 1014 cc_out:$s)>, 1015 Requires<[IsARM]>; 1016 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1017 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, 1018 so_reg_reg:$shift, pred:$p, 1019 cc_out:$s)>, 1020 Requires<[IsARM]>; 1021 1022} 1023 1024/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1025/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1026/// it is equivalent to the AsI1_bin_irs counterpart. 1027multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1028 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1029 PatFrag opnode, string baseOpc, bit Commutable = 0> { 1030 // The register-immediate version is re-materializable. This is useful 1031 // in particular for taking the address of a local. 1032 let isReMaterializable = 1 in { 1033 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, 1034 iii, opc, "\t$Rd, $Rn, $imm", 1035 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> { 1036 bits<4> Rd; 1037 bits<4> Rn; 1038 bits<12> imm; 1039 let Inst{25} = 1; 1040 let Inst{19-16} = Rn; 1041 let Inst{15-12} = Rd; 1042 let Inst{11-0} = imm; 1043 } 1044 } 1045 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1046 iir, opc, "\t$Rd, $Rn, $Rm", 1047 [/* pattern left blank */]> { 1048 bits<4> Rd; 1049 bits<4> Rn; 1050 bits<4> Rm; 1051 let Inst{11-4} = 0b00000000; 1052 let Inst{25} = 0; 1053 let Inst{3-0} = Rm; 1054 let Inst{15-12} = Rd; 1055 let Inst{19-16} = Rn; 1056 } 1057 1058 def rsi : AsI1<opcod, (outs GPR:$Rd), 1059 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1060 iis, opc, "\t$Rd, $Rn, $shift", 1061 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> { 1062 bits<4> Rd; 1063 bits<4> Rn; 1064 bits<12> shift; 1065 let Inst{25} = 0; 1066 let Inst{19-16} = Rn; 1067 let Inst{15-12} = Rd; 1068 let Inst{11-5} = shift{11-5}; 1069 let Inst{4} = 0; 1070 let Inst{3-0} = shift{3-0}; 1071 } 1072 1073 def rsr : AsI1<opcod, (outs GPR:$Rd), 1074 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1075 iis, opc, "\t$Rd, $Rn, $shift", 1076 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> { 1077 bits<4> Rd; 1078 bits<4> Rn; 1079 bits<12> shift; 1080 let Inst{25} = 0; 1081 let Inst{19-16} = Rn; 1082 let Inst{15-12} = Rd; 1083 let Inst{11-8} = shift{11-8}; 1084 let Inst{7} = 0; 1085 let Inst{6-5} = shift{6-5}; 1086 let Inst{4} = 1; 1087 let Inst{3-0} = shift{3-0}; 1088 } 1089 1090 // Assembly aliases for optional destination operand when it's the same 1091 // as the source operand. 1092 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 1093 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, 1094 so_imm:$imm, pred:$p, 1095 cc_out:$s)>, 1096 Requires<[IsARM]>; 1097 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"), 1098 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, 1099 GPR:$Rm, pred:$p, 1100 cc_out:$s)>, 1101 Requires<[IsARM]>; 1102 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1103 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, 1104 so_reg_imm:$shift, pred:$p, 1105 cc_out:$s)>, 1106 Requires<[IsARM]>; 1107 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1108 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, 1109 so_reg_reg:$shift, pred:$p, 1110 cc_out:$s)>, 1111 Requires<[IsARM]>; 1112 1113} 1114 1115/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1116/// 1117/// These opcodes will be converted to the real non-S opcodes by 1118/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1119let hasPostISelHook = 1, Defs = [CPSR] in { 1120multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1121 InstrItinClass iis, PatFrag opnode, 1122 bit Commutable = 0> { 1123 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1124 4, iii, 1125 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>; 1126 1127 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1128 4, iir, 1129 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> { 1130 let isCommutable = Commutable; 1131 } 1132 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1133 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1134 4, iis, 1135 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1136 so_reg_imm:$shift))]>; 1137 1138 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1139 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1140 4, iis, 1141 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1142 so_reg_reg:$shift))]>; 1143} 1144} 1145 1146/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1147/// operands are reversed. 1148let hasPostISelHook = 1, Defs = [CPSR] in { 1149multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1150 InstrItinClass iis, PatFrag opnode, 1151 bit Commutable = 0> { 1152 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p), 1153 4, iii, 1154 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>; 1155 1156 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1157 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1158 4, iis, 1159 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1160 GPR:$Rn))]>; 1161 1162 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1163 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1164 4, iis, 1165 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1166 GPR:$Rn))]>; 1167} 1168} 1169 1170/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 1171/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1172/// a explicit result, only implicitly set CPSR. 1173let isCompare = 1, Defs = [CPSR] in { 1174multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1175 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1176 PatFrag opnode, bit Commutable = 0> { 1177 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii, 1178 opc, "\t$Rn, $imm", 1179 [(opnode GPR:$Rn, so_imm:$imm)]> { 1180 bits<4> Rn; 1181 bits<12> imm; 1182 let Inst{25} = 1; 1183 let Inst{20} = 1; 1184 let Inst{19-16} = Rn; 1185 let Inst{15-12} = 0b0000; 1186 let Inst{11-0} = imm; 1187 } 1188 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1189 opc, "\t$Rn, $Rm", 1190 [(opnode GPR:$Rn, GPR:$Rm)]> { 1191 bits<4> Rn; 1192 bits<4> Rm; 1193 let isCommutable = Commutable; 1194 let Inst{25} = 0; 1195 let Inst{20} = 1; 1196 let Inst{19-16} = Rn; 1197 let Inst{15-12} = 0b0000; 1198 let Inst{11-4} = 0b00000000; 1199 let Inst{3-0} = Rm; 1200 } 1201 def rsi : AI1<opcod, (outs), 1202 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1203 opc, "\t$Rn, $shift", 1204 [(opnode GPR:$Rn, so_reg_imm:$shift)]> { 1205 bits<4> Rn; 1206 bits<12> shift; 1207 let Inst{25} = 0; 1208 let Inst{20} = 1; 1209 let Inst{19-16} = Rn; 1210 let Inst{15-12} = 0b0000; 1211 let Inst{11-5} = shift{11-5}; 1212 let Inst{4} = 0; 1213 let Inst{3-0} = shift{3-0}; 1214 } 1215 def rsr : AI1<opcod, (outs), 1216 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1217 opc, "\t$Rn, $shift", 1218 [(opnode GPR:$Rn, so_reg_reg:$shift)]> { 1219 bits<4> Rn; 1220 bits<12> shift; 1221 let Inst{25} = 0; 1222 let Inst{20} = 1; 1223 let Inst{19-16} = Rn; 1224 let Inst{15-12} = 0b0000; 1225 let Inst{11-8} = shift{11-8}; 1226 let Inst{7} = 0; 1227 let Inst{6-5} = shift{6-5}; 1228 let Inst{4} = 1; 1229 let Inst{3-0} = shift{3-0}; 1230 } 1231 1232} 1233} 1234 1235/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1236/// register and one whose operand is a register rotated by 8/16/24. 1237/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1238class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1239 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1240 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1241 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1242 Requires<[IsARM, HasV6]> { 1243 bits<4> Rd; 1244 bits<4> Rm; 1245 bits<2> rot; 1246 let Inst{19-16} = 0b1111; 1247 let Inst{15-12} = Rd; 1248 let Inst{11-10} = rot; 1249 let Inst{3-0} = Rm; 1250} 1251 1252class AI_ext_rrot_np<bits<8> opcod, string opc> 1253 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1254 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1255 Requires<[IsARM, HasV6]> { 1256 bits<2> rot; 1257 let Inst{19-16} = 0b1111; 1258 let Inst{11-10} = rot; 1259} 1260 1261/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1262/// register and one whose operand is a register rotated by 8/16/24. 1263class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1264 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1265 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1266 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1267 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1268 Requires<[IsARM, HasV6]> { 1269 bits<4> Rd; 1270 bits<4> Rm; 1271 bits<4> Rn; 1272 bits<2> rot; 1273 let Inst{19-16} = Rn; 1274 let Inst{15-12} = Rd; 1275 let Inst{11-10} = rot; 1276 let Inst{9-4} = 0b000111; 1277 let Inst{3-0} = Rm; 1278} 1279 1280class AI_exta_rrot_np<bits<8> opcod, string opc> 1281 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1282 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1283 Requires<[IsARM, HasV6]> { 1284 bits<4> Rn; 1285 bits<2> rot; 1286 let Inst{19-16} = Rn; 1287 let Inst{11-10} = rot; 1288} 1289 1290/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1291multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 1292 string baseOpc, bit Commutable = 0> { 1293 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1294 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1295 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1296 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>, 1297 Requires<[IsARM]> { 1298 bits<4> Rd; 1299 bits<4> Rn; 1300 bits<12> imm; 1301 let Inst{25} = 1; 1302 let Inst{15-12} = Rd; 1303 let Inst{19-16} = Rn; 1304 let Inst{11-0} = imm; 1305 } 1306 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1307 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1308 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1309 Requires<[IsARM]> { 1310 bits<4> Rd; 1311 bits<4> Rn; 1312 bits<4> Rm; 1313 let Inst{11-4} = 0b00000000; 1314 let Inst{25} = 0; 1315 let isCommutable = Commutable; 1316 let Inst{3-0} = Rm; 1317 let Inst{15-12} = Rd; 1318 let Inst{19-16} = Rn; 1319 } 1320 def rsi : AsI1<opcod, (outs GPR:$Rd), 1321 (ins GPR:$Rn, so_reg_imm:$shift), 1322 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1323 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1324 Requires<[IsARM]> { 1325 bits<4> Rd; 1326 bits<4> Rn; 1327 bits<12> shift; 1328 let Inst{25} = 0; 1329 let Inst{19-16} = Rn; 1330 let Inst{15-12} = Rd; 1331 let Inst{11-5} = shift{11-5}; 1332 let Inst{4} = 0; 1333 let Inst{3-0} = shift{3-0}; 1334 } 1335 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1336 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1337 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1338 [(set GPRnopc:$Rd, CPSR, (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1339 Requires<[IsARM]> { 1340 bits<4> Rd; 1341 bits<4> Rn; 1342 bits<12> shift; 1343 let Inst{25} = 0; 1344 let Inst{19-16} = Rn; 1345 let Inst{15-12} = Rd; 1346 let Inst{11-8} = shift{11-8}; 1347 let Inst{7} = 0; 1348 let Inst{6-5} = shift{6-5}; 1349 let Inst{4} = 1; 1350 let Inst{3-0} = shift{3-0}; 1351 } 1352 } 1353 1354 // Assembly aliases for optional destination operand when it's the same 1355 // as the source operand. 1356 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 1357 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, 1358 so_imm:$imm, pred:$p, 1359 cc_out:$s)>, 1360 Requires<[IsARM]>; 1361 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"), 1362 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, 1363 GPR:$Rm, pred:$p, 1364 cc_out:$s)>, 1365 Requires<[IsARM]>; 1366 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1367 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, 1368 so_reg_imm:$shift, pred:$p, 1369 cc_out:$s)>, 1370 Requires<[IsARM]>; 1371 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1372 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPRnopc:$Rdn, GPRnopc:$Rdn, 1373 so_reg_reg:$shift, pred:$p, 1374 cc_out:$s)>, 1375 Requires<[IsARM]>; 1376} 1377 1378/// AI1_rsc_irs - Define instructions and patterns for rsc 1379multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode, 1380 string baseOpc> { 1381 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1382 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), 1383 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1384 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>, 1385 Requires<[IsARM]> { 1386 bits<4> Rd; 1387 bits<4> Rn; 1388 bits<12> imm; 1389 let Inst{25} = 1; 1390 let Inst{15-12} = Rd; 1391 let Inst{19-16} = Rn; 1392 let Inst{11-0} = imm; 1393 } 1394 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1395 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1396 [/* pattern left blank */]> { 1397 bits<4> Rd; 1398 bits<4> Rn; 1399 bits<4> Rm; 1400 let Inst{11-4} = 0b00000000; 1401 let Inst{25} = 0; 1402 let Inst{3-0} = Rm; 1403 let Inst{15-12} = Rd; 1404 let Inst{19-16} = Rn; 1405 } 1406 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1407 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1408 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1409 Requires<[IsARM]> { 1410 bits<4> Rd; 1411 bits<4> Rn; 1412 bits<12> shift; 1413 let Inst{25} = 0; 1414 let Inst{19-16} = Rn; 1415 let Inst{15-12} = Rd; 1416 let Inst{11-5} = shift{11-5}; 1417 let Inst{4} = 0; 1418 let Inst{3-0} = shift{3-0}; 1419 } 1420 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1421 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1422 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1423 Requires<[IsARM]> { 1424 bits<4> Rd; 1425 bits<4> Rn; 1426 bits<12> shift; 1427 let Inst{25} = 0; 1428 let Inst{19-16} = Rn; 1429 let Inst{15-12} = Rd; 1430 let Inst{11-8} = shift{11-8}; 1431 let Inst{7} = 0; 1432 let Inst{6-5} = shift{6-5}; 1433 let Inst{4} = 1; 1434 let Inst{3-0} = shift{3-0}; 1435 } 1436 } 1437 1438 // Assembly aliases for optional destination operand when it's the same 1439 // as the source operand. 1440 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 1441 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, 1442 so_imm:$imm, pred:$p, 1443 cc_out:$s)>, 1444 Requires<[IsARM]>; 1445 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"), 1446 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, 1447 GPR:$Rm, pred:$p, 1448 cc_out:$s)>, 1449 Requires<[IsARM]>; 1450 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1451 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn, 1452 so_reg_imm:$shift, pred:$p, 1453 cc_out:$s)>, 1454 Requires<[IsARM]>; 1455 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"), 1456 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn, 1457 so_reg_reg:$shift, pred:$p, 1458 cc_out:$s)>, 1459 Requires<[IsARM]>; 1460} 1461 1462let canFoldAsLoad = 1, isReMaterializable = 1 in { 1463multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1464 InstrItinClass iir, PatFrag opnode> { 1465 // Note: We use the complex addrmode_imm12 rather than just an input 1466 // GPR and a constrained immediate so that we can use this to match 1467 // frame index references and avoid matching constant pool references. 1468 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1469 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1470 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1471 bits<4> Rt; 1472 bits<17> addr; 1473 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1474 let Inst{19-16} = addr{16-13}; // Rn 1475 let Inst{15-12} = Rt; 1476 let Inst{11-0} = addr{11-0}; // imm12 1477 } 1478 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1479 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1480 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1481 bits<4> Rt; 1482 bits<17> shift; 1483 let shift{4} = 0; // Inst{4} = 0 1484 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1485 let Inst{19-16} = shift{16-13}; // Rn 1486 let Inst{15-12} = Rt; 1487 let Inst{11-0} = shift{11-0}; 1488 } 1489} 1490} 1491 1492let canFoldAsLoad = 1, isReMaterializable = 1 in { 1493multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1494 InstrItinClass iir, PatFrag opnode> { 1495 // Note: We use the complex addrmode_imm12 rather than just an input 1496 // GPR and a constrained immediate so that we can use this to match 1497 // frame index references and avoid matching constant pool references. 1498 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr), 1499 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1500 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1501 bits<4> Rt; 1502 bits<17> addr; 1503 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1504 let Inst{19-16} = addr{16-13}; // Rn 1505 let Inst{15-12} = Rt; 1506 let Inst{11-0} = addr{11-0}; // imm12 1507 } 1508 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift), 1509 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1510 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1511 bits<4> Rt; 1512 bits<17> shift; 1513 let shift{4} = 0; // Inst{4} = 0 1514 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1515 let Inst{19-16} = shift{16-13}; // Rn 1516 let Inst{15-12} = Rt; 1517 let Inst{11-0} = shift{11-0}; 1518 } 1519} 1520} 1521 1522 1523multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1524 InstrItinClass iir, PatFrag opnode> { 1525 // Note: We use the complex addrmode_imm12 rather than just an input 1526 // GPR and a constrained immediate so that we can use this to match 1527 // frame index references and avoid matching constant pool references. 1528 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1529 (ins GPR:$Rt, addrmode_imm12:$addr), 1530 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1531 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1532 bits<4> Rt; 1533 bits<17> addr; 1534 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1535 let Inst{19-16} = addr{16-13}; // Rn 1536 let Inst{15-12} = Rt; 1537 let Inst{11-0} = addr{11-0}; // imm12 1538 } 1539 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1540 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1541 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1542 bits<4> Rt; 1543 bits<17> shift; 1544 let shift{4} = 0; // Inst{4} = 0 1545 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1546 let Inst{19-16} = shift{16-13}; // Rn 1547 let Inst{15-12} = Rt; 1548 let Inst{11-0} = shift{11-0}; 1549 } 1550} 1551 1552multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1553 InstrItinClass iir, PatFrag opnode> { 1554 // Note: We use the complex addrmode_imm12 rather than just an input 1555 // GPR and a constrained immediate so that we can use this to match 1556 // frame index references and avoid matching constant pool references. 1557 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1558 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1559 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1560 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1561 bits<4> Rt; 1562 bits<17> addr; 1563 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1564 let Inst{19-16} = addr{16-13}; // Rn 1565 let Inst{15-12} = Rt; 1566 let Inst{11-0} = addr{11-0}; // imm12 1567 } 1568 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1569 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1570 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1571 bits<4> Rt; 1572 bits<17> shift; 1573 let shift{4} = 0; // Inst{4} = 0 1574 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1575 let Inst{19-16} = shift{16-13}; // Rn 1576 let Inst{15-12} = Rt; 1577 let Inst{11-0} = shift{11-0}; 1578 } 1579} 1580 1581 1582//===----------------------------------------------------------------------===// 1583// Instructions 1584//===----------------------------------------------------------------------===// 1585 1586//===----------------------------------------------------------------------===// 1587// Miscellaneous Instructions. 1588// 1589 1590/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1591/// the function. The first operand is the ID# for this instruction, the second 1592/// is the index into the MachineConstantPool that this is, the third is the 1593/// size in bytes of this constant pool entry. 1594let neverHasSideEffects = 1, isNotDuplicable = 1 in 1595def CONSTPOOL_ENTRY : 1596PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1597 i32imm:$size), NoItinerary, []>; 1598 1599// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 1600// from removing one half of the matched pairs. That breaks PEI, which assumes 1601// these will always be in pairs, and asserts if it finds otherwise. Better way? 1602let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 1603def ADJCALLSTACKUP : 1604PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 1605 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 1606 1607def ADJCALLSTACKDOWN : 1608PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 1609 [(ARMcallseq_start timm:$amt)]>; 1610} 1611 1612// Atomic pseudo-insts which will be lowered to ldrexd/strexd loops. 1613// (These pseudos use a hand-written selection code). 1614let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in { 1615def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1616 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1617 NoItinerary, []>; 1618def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1619 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1620 NoItinerary, []>; 1621def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1622 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1623 NoItinerary, []>; 1624def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1625 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1626 NoItinerary, []>; 1627def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1628 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1629 NoItinerary, []>; 1630def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1631 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1632 NoItinerary, []>; 1633def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1634 (ins GPR:$addr, GPR:$src1, GPR:$src2), 1635 NoItinerary, []>; 1636def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2), 1637 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2, 1638 GPR:$set1, GPR:$set2), 1639 NoItinerary, []>; 1640} 1641 1642def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>, 1643 Requires<[IsARM, HasV6T2]> { 1644 let Inst{27-16} = 0b001100100000; 1645 let Inst{15-8} = 0b11110000; 1646 let Inst{7-0} = 0b00000000; 1647} 1648 1649def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>, 1650 Requires<[IsARM, HasV6T2]> { 1651 let Inst{27-16} = 0b001100100000; 1652 let Inst{15-8} = 0b11110000; 1653 let Inst{7-0} = 0b00000001; 1654} 1655 1656def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>, 1657 Requires<[IsARM, HasV6T2]> { 1658 let Inst{27-16} = 0b001100100000; 1659 let Inst{15-8} = 0b11110000; 1660 let Inst{7-0} = 0b00000010; 1661} 1662 1663def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>, 1664 Requires<[IsARM, HasV6T2]> { 1665 let Inst{27-16} = 0b001100100000; 1666 let Inst{15-8} = 0b11110000; 1667 let Inst{7-0} = 0b00000011; 1668} 1669 1670def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 1671 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> { 1672 bits<4> Rd; 1673 bits<4> Rn; 1674 bits<4> Rm; 1675 let Inst{3-0} = Rm; 1676 let Inst{15-12} = Rd; 1677 let Inst{19-16} = Rn; 1678 let Inst{27-20} = 0b01101000; 1679 let Inst{7-4} = 0b1011; 1680 let Inst{11-8} = 0b1111; 1681} 1682 1683def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "", 1684 []>, Requires<[IsARM, HasV6T2]> { 1685 let Inst{27-16} = 0b001100100000; 1686 let Inst{15-8} = 0b11110000; 1687 let Inst{7-0} = 0b00000100; 1688} 1689 1690// The i32imm operand $val can be used by a debugger to store more information 1691// about the breakpoint. 1692def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 1693 "bkpt", "\t$val", []>, Requires<[IsARM]> { 1694 bits<16> val; 1695 let Inst{3-0} = val{3-0}; 1696 let Inst{19-8} = val{15-4}; 1697 let Inst{27-20} = 0b00010010; 1698 let Inst{7-4} = 0b0111; 1699} 1700 1701// Change Processor State 1702// FIXME: We should use InstAlias to handle the optional operands. 1703class CPS<dag iops, string asm_ops> 1704 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 1705 []>, Requires<[IsARM]> { 1706 bits<2> imod; 1707 bits<3> iflags; 1708 bits<5> mode; 1709 bit M; 1710 1711 let Inst{31-28} = 0b1111; 1712 let Inst{27-20} = 0b00010000; 1713 let Inst{19-18} = imod; 1714 let Inst{17} = M; // Enabled if mode is set; 1715 let Inst{16-9} = 0b00000000; 1716 let Inst{8-6} = iflags; 1717 let Inst{5} = 0; 1718 let Inst{4-0} = mode; 1719} 1720 1721let DecoderMethod = "DecodeCPSInstruction" in { 1722let M = 1 in 1723 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 1724 "$imod\t$iflags, $mode">; 1725let mode = 0, M = 0 in 1726 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 1727 1728let imod = 0, iflags = 0, M = 1 in 1729 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 1730} 1731 1732// Preload signals the memory system of possible future data/instruction access. 1733multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 1734 1735 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload, 1736 !strconcat(opc, "\t$addr"), 1737 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> { 1738 bits<4> Rt; 1739 bits<17> addr; 1740 let Inst{31-26} = 0b111101; 1741 let Inst{25} = 0; // 0 for immediate form 1742 let Inst{24} = data; 1743 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1744 let Inst{22} = read; 1745 let Inst{21-20} = 0b01; 1746 let Inst{19-16} = addr{16-13}; // Rn 1747 let Inst{15-12} = 0b1111; 1748 let Inst{11-0} = addr{11-0}; // imm12 1749 } 1750 1751 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 1752 !strconcat(opc, "\t$shift"), 1753 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> { 1754 bits<17> shift; 1755 let Inst{31-26} = 0b111101; 1756 let Inst{25} = 1; // 1 for register form 1757 let Inst{24} = data; 1758 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1759 let Inst{22} = read; 1760 let Inst{21-20} = 0b01; 1761 let Inst{19-16} = shift{16-13}; // Rn 1762 let Inst{15-12} = 0b1111; 1763 let Inst{11-0} = shift{11-0}; 1764 let Inst{4} = 0; 1765 } 1766} 1767 1768defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 1769defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 1770defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 1771 1772def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 1773 "setend\t$end", []>, Requires<[IsARM]> { 1774 bits<1> end; 1775 let Inst{31-10} = 0b1111000100000001000000; 1776 let Inst{9} = end; 1777 let Inst{8-0} = 0; 1778} 1779 1780def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 1781 []>, Requires<[IsARM, HasV7]> { 1782 bits<4> opt; 1783 let Inst{27-4} = 0b001100100000111100001111; 1784 let Inst{3-0} = opt; 1785} 1786 1787// A5.4 Permanently UNDEFINED instructions. 1788let isBarrier = 1, isTerminator = 1 in 1789def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 1790 "trap", [(trap)]>, 1791 Requires<[IsARM]> { 1792 let Inst = 0xe7ffdefe; 1793} 1794 1795// Address computation and loads and stores in PIC mode. 1796let isNotDuplicable = 1 in { 1797def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 1798 4, IIC_iALUr, 1799 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; 1800 1801let AddedComplexity = 10 in { 1802def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 1803 4, IIC_iLoad_r, 1804 [(set GPR:$dst, (load addrmodepc:$addr))]>; 1805 1806def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1807 4, IIC_iLoad_bh_r, 1808 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 1809 1810def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1811 4, IIC_iLoad_bh_r, 1812 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 1813 1814def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1815 4, IIC_iLoad_bh_r, 1816 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 1817 1818def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 1819 4, IIC_iLoad_bh_r, 1820 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 1821} 1822let AddedComplexity = 10 in { 1823def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1824 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 1825 1826def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1827 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 1828 addrmodepc:$addr)]>; 1829 1830def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 1831 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 1832} 1833} // isNotDuplicable = 1 1834 1835 1836// LEApcrel - Load a pc-relative address into a register without offending the 1837// assembler. 1838let neverHasSideEffects = 1, isReMaterializable = 1 in 1839// The 'adr' mnemonic encodes differently if the label is before or after 1840// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 1841// know until then which form of the instruction will be used. 1842def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 1843 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> { 1844 bits<4> Rd; 1845 bits<14> label; 1846 let Inst{27-25} = 0b001; 1847 let Inst{24} = 0; 1848 let Inst{23-22} = label{13-12}; 1849 let Inst{21} = 0; 1850 let Inst{20} = 0; 1851 let Inst{19-16} = 0b1111; 1852 let Inst{15-12} = Rd; 1853 let Inst{11-0} = label{11-0}; 1854} 1855def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 1856 4, IIC_iALUi, []>; 1857 1858def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 1859 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1860 4, IIC_iALUi, []>; 1861 1862//===----------------------------------------------------------------------===// 1863// Control Flow Instructions. 1864// 1865 1866let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 1867 // ARMV4T and above 1868 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1869 "bx", "\tlr", [(ARMretflag)]>, 1870 Requires<[IsARM, HasV4T]> { 1871 let Inst{27-0} = 0b0001001011111111111100011110; 1872 } 1873 1874 // ARMV4 only 1875 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 1876 "mov", "\tpc, lr", [(ARMretflag)]>, 1877 Requires<[IsARM, NoV4T]> { 1878 let Inst{27-0} = 0b0001101000001111000000001110; 1879 } 1880} 1881 1882// Indirect branches 1883let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1884 // ARMV4T and above 1885 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 1886 [(brind GPR:$dst)]>, 1887 Requires<[IsARM, HasV4T]> { 1888 bits<4> dst; 1889 let Inst{31-4} = 0b1110000100101111111111110001; 1890 let Inst{3-0} = dst; 1891 } 1892 1893 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 1894 "bx", "\t$dst", [/* pattern left blank */]>, 1895 Requires<[IsARM, HasV4T]> { 1896 bits<4> dst; 1897 let Inst{27-4} = 0b000100101111111111110001; 1898 let Inst{3-0} = dst; 1899 } 1900} 1901 1902// SP is marked as a use to prevent stack-pointer assignments that appear 1903// immediately before calls from potentially appearing dead. 1904let isCall = 1, 1905 // FIXME: Do we really need a non-predicated version? If so, it should 1906 // at least be a pseudo instruction expanding to the predicated version 1907 // at MC lowering time. 1908 Defs = [LR], Uses = [SP] in { 1909 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops), 1910 IIC_Br, "bl\t$func", 1911 [(ARMcall tglobaladdr:$func)]>, 1912 Requires<[IsARM]> { 1913 let Inst{31-28} = 0b1110; 1914 bits<24> func; 1915 let Inst{23-0} = func; 1916 let DecoderMethod = "DecodeBranchImmInstruction"; 1917 } 1918 1919 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops), 1920 IIC_Br, "bl", "\t$func", 1921 [(ARMcall_pred tglobaladdr:$func)]>, 1922 Requires<[IsARM]> { 1923 bits<24> func; 1924 let Inst{23-0} = func; 1925 let DecoderMethod = "DecodeBranchImmInstruction"; 1926 } 1927 1928 // ARMv5T and above 1929 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 1930 IIC_Br, "blx\t$func", 1931 [(ARMcall GPR:$func)]>, 1932 Requires<[IsARM, HasV5T]> { 1933 bits<4> func; 1934 let Inst{31-4} = 0b1110000100101111111111110011; 1935 let Inst{3-0} = func; 1936 } 1937 1938 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 1939 IIC_Br, "blx", "\t$func", 1940 [(ARMcall_pred GPR:$func)]>, 1941 Requires<[IsARM, HasV5T]> { 1942 bits<4> func; 1943 let Inst{27-4} = 0b000100101111111111110011; 1944 let Inst{3-0} = func; 1945 } 1946 1947 // ARMv4T 1948 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 1949 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 1950 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 1951 Requires<[IsARM, HasV4T]>; 1952 1953 // ARMv4 1954 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), 1955 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 1956 Requires<[IsARM, NoV4T]>; 1957 1958 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 1959 // return stack predictor. 1960 def BMOVPCB_CALL : ARMPseudoInst<(outs), 1961 (ins bl_target:$func, variable_ops), 1962 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 1963 Requires<[IsARM]>; 1964} 1965 1966let isBranch = 1, isTerminator = 1 in { 1967 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 1968 // a two-value operand where a dag node expects two operands. :( 1969 def Bcc : ABI<0b1010, (outs), (ins br_target:$target), 1970 IIC_Br, "b", "\t$target", 1971 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> { 1972 bits<24> target; 1973 let Inst{23-0} = target; 1974 let DecoderMethod = "DecodeBranchImmInstruction"; 1975 } 1976 1977 let isBarrier = 1 in { 1978 // B is "predicable" since it's just a Bcc with an 'always' condition. 1979 let isPredicable = 1 in 1980 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 1981 // should be sufficient. 1982 // FIXME: Is B really a Barrier? That doesn't seem right. 1983 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br, 1984 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>; 1985 1986 let isNotDuplicable = 1, isIndirectBranch = 1 in { 1987 def BR_JTr : ARMPseudoInst<(outs), 1988 (ins GPR:$target, i32imm:$jt, i32imm:$id), 1989 0, IIC_Br, 1990 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; 1991 // FIXME: This shouldn't use the generic "addrmode2," but rather be split 1992 // into i12 and rs suffixed versions. 1993 def BR_JTm : ARMPseudoInst<(outs), 1994 (ins addrmode2:$target, i32imm:$jt, i32imm:$id), 1995 0, IIC_Br, 1996 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 1997 imm:$id)]>; 1998 def BR_JTadd : ARMPseudoInst<(outs), 1999 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id), 2000 0, IIC_Br, 2001 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 2002 imm:$id)]>; 2003 } // isNotDuplicable = 1, isIndirectBranch = 1 2004 } // isBarrier = 1 2005 2006} 2007 2008// BLX (immediate) 2009def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary, 2010 "blx\t$target", []>, 2011 Requires<[IsARM, HasV5T]> { 2012 let Inst{31-25} = 0b1111101; 2013 bits<25> target; 2014 let Inst{23-0} = target{24-1}; 2015 let Inst{24} = target{0}; 2016} 2017 2018// Branch and Exchange Jazelle 2019def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2020 [/* pattern left blank */]> { 2021 bits<4> func; 2022 let Inst{23-20} = 0b0010; 2023 let Inst{19-8} = 0xfff; 2024 let Inst{7-4} = 0b0010; 2025 let Inst{3-0} = func; 2026} 2027 2028// Tail calls. 2029 2030let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2031 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops), 2032 IIC_Br, []>; 2033 2034 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops), 2035 IIC_Br, []>; 2036 2037 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops), 2038 4, IIC_Br, [], 2039 (Bcc br_target:$dst, (ops 14, zero_reg))>, 2040 Requires<[IsARM]>; 2041 2042 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops), 2043 4, IIC_Br, [], 2044 (BX GPR:$dst)>, 2045 Requires<[IsARM]>; 2046} 2047 2048// Secure Monitor Call is a system instruction. 2049def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2050 []> { 2051 bits<4> opt; 2052 let Inst{23-4} = 0b01100000000000000111; 2053 let Inst{3-0} = opt; 2054} 2055 2056// Supervisor Call (Software Interrupt) 2057let isCall = 1, Uses = [SP] in { 2058def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> { 2059 bits<24> svc; 2060 let Inst{23-0} = svc; 2061} 2062} 2063 2064// Store Return State 2065class SRSI<bit wb, string asm> 2066 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2067 NoItinerary, asm, "", []> { 2068 bits<5> mode; 2069 let Inst{31-28} = 0b1111; 2070 let Inst{27-25} = 0b100; 2071 let Inst{22} = 1; 2072 let Inst{21} = wb; 2073 let Inst{20} = 0; 2074 let Inst{19-16} = 0b1101; // SP 2075 let Inst{15-5} = 0b00000101000; 2076 let Inst{4-0} = mode; 2077} 2078 2079def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2080 let Inst{24-23} = 0; 2081} 2082def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2083 let Inst{24-23} = 0; 2084} 2085def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2086 let Inst{24-23} = 0b10; 2087} 2088def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2089 let Inst{24-23} = 0b10; 2090} 2091def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2092 let Inst{24-23} = 0b01; 2093} 2094def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2095 let Inst{24-23} = 0b01; 2096} 2097def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2098 let Inst{24-23} = 0b11; 2099} 2100def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2101 let Inst{24-23} = 0b11; 2102} 2103 2104// Return From Exception 2105class RFEI<bit wb, string asm> 2106 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2107 NoItinerary, asm, "", []> { 2108 bits<4> Rn; 2109 let Inst{31-28} = 0b1111; 2110 let Inst{27-25} = 0b100; 2111 let Inst{22} = 0; 2112 let Inst{21} = wb; 2113 let Inst{20} = 1; 2114 let Inst{19-16} = Rn; 2115 let Inst{15-0} = 0xa00; 2116} 2117 2118def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2119 let Inst{24-23} = 0; 2120} 2121def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2122 let Inst{24-23} = 0; 2123} 2124def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2125 let Inst{24-23} = 0b10; 2126} 2127def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2128 let Inst{24-23} = 0b10; 2129} 2130def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2131 let Inst{24-23} = 0b01; 2132} 2133def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2134 let Inst{24-23} = 0b01; 2135} 2136def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2137 let Inst{24-23} = 0b11; 2138} 2139def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2140 let Inst{24-23} = 0b11; 2141} 2142 2143//===----------------------------------------------------------------------===// 2144// Load / Store Instructions. 2145// 2146 2147// Load 2148 2149 2150defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, 2151 UnOpFrag<(load node:$Src)>>; 2152defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2153 UnOpFrag<(zextloadi8 node:$Src)>>; 2154defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, 2155 BinOpFrag<(store node:$LHS, node:$RHS)>>; 2156defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2157 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 2158 2159// Special LDR for loads from non-pc-relative constpools. 2160let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, 2161 isReMaterializable = 1, isCodeGenOnly = 1 in 2162def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2163 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2164 []> { 2165 bits<4> Rt; 2166 bits<17> addr; 2167 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2168 let Inst{19-16} = 0b1111; 2169 let Inst{15-12} = Rt; 2170 let Inst{11-0} = addr{11-0}; // imm12 2171} 2172 2173// Loads with zero extension 2174def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2175 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2176 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2177 2178// Loads with sign extension 2179def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2180 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2181 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2182 2183def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2184 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2185 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2186 2187let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 2188// Load doubleword 2189def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2), 2190 (ins addrmode3:$addr), LdMiscFrm, 2191 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr", 2192 []>, Requires<[IsARM, HasV5TE]>; 2193} 2194 2195// Indexed loads 2196multiclass AI2_ldridx<bit isByte, string opc, 2197 InstrItinClass iii, InstrItinClass iir> { 2198 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2199 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii, 2200 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2201 bits<17> addr; 2202 let Inst{25} = 0; 2203 let Inst{23} = addr{12}; 2204 let Inst{19-16} = addr{16-13}; 2205 let Inst{11-0} = addr{11-0}; 2206 let DecoderMethod = "DecodeLDRPreImm"; 2207 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12"; 2208 } 2209 2210 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2211 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2212 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2213 bits<17> addr; 2214 let Inst{25} = 1; 2215 let Inst{23} = addr{12}; 2216 let Inst{19-16} = addr{16-13}; 2217 let Inst{11-0} = addr{11-0}; 2218 let Inst{4} = 0; 2219 let DecoderMethod = "DecodeLDRPreReg"; 2220 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2"; 2221 } 2222 2223 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2224 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2225 IndexModePost, LdFrm, iir, 2226 opc, "\t$Rt, $addr, $offset", 2227 "$addr.base = $Rn_wb", []> { 2228 // {12} isAdd 2229 // {11-0} imm12/Rm 2230 bits<14> offset; 2231 bits<4> addr; 2232 let Inst{25} = 1; 2233 let Inst{23} = offset{12}; 2234 let Inst{19-16} = addr; 2235 let Inst{11-0} = offset{11-0}; 2236 2237 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2238 } 2239 2240 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2241 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2242 IndexModePost, LdFrm, iii, 2243 opc, "\t$Rt, $addr, $offset", 2244 "$addr.base = $Rn_wb", []> { 2245 // {12} isAdd 2246 // {11-0} imm12/Rm 2247 bits<14> offset; 2248 bits<4> addr; 2249 let Inst{25} = 0; 2250 let Inst{23} = offset{12}; 2251 let Inst{19-16} = addr; 2252 let Inst{11-0} = offset{11-0}; 2253 2254 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2255 } 2256 2257} 2258 2259let mayLoad = 1, neverHasSideEffects = 1 in { 2260// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2261// IIC_iLoad_siu depending on whether it the offset register is shifted. 2262defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2263defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2264} 2265 2266multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2267 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2268 (ins addrmode3:$addr), IndexModePre, 2269 LdMiscFrm, itin, 2270 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2271 bits<14> addr; 2272 let Inst{23} = addr{8}; // U bit 2273 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2274 let Inst{19-16} = addr{12-9}; // Rn 2275 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2276 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2277 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3"; 2278 let DecoderMethod = "DecodeAddrMode3Instruction"; 2279 } 2280 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2281 (ins addr_offset_none:$addr, am3offset:$offset), 2282 IndexModePost, LdMiscFrm, itin, 2283 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2284 []> { 2285 bits<10> offset; 2286 bits<4> addr; 2287 let Inst{23} = offset{8}; // U bit 2288 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2289 let Inst{19-16} = addr; 2290 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2291 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2292 let DecoderMethod = "DecodeAddrMode3Instruction"; 2293 } 2294} 2295 2296let mayLoad = 1, neverHasSideEffects = 1 in { 2297defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2298defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2299defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2300let hasExtraDefRegAllocReq = 1 in { 2301def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2302 (ins addrmode3:$addr), IndexModePre, 2303 LdMiscFrm, IIC_iLoad_d_ru, 2304 "ldrd", "\t$Rt, $Rt2, $addr!", 2305 "$addr.base = $Rn_wb", []> { 2306 bits<14> addr; 2307 let Inst{23} = addr{8}; // U bit 2308 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2309 let Inst{19-16} = addr{12-9}; // Rn 2310 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2311 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2312 let DecoderMethod = "DecodeAddrMode3Instruction"; 2313 let AsmMatchConverter = "cvtLdrdPre"; 2314} 2315def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2316 (ins addr_offset_none:$addr, am3offset:$offset), 2317 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2318 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2319 "$addr.base = $Rn_wb", []> { 2320 bits<10> offset; 2321 bits<4> addr; 2322 let Inst{23} = offset{8}; // U bit 2323 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2324 let Inst{19-16} = addr; 2325 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2326 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2327 let DecoderMethod = "DecodeAddrMode3Instruction"; 2328} 2329} // hasExtraDefRegAllocReq = 1 2330} // mayLoad = 1, neverHasSideEffects = 1 2331 2332// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2333let mayLoad = 1, neverHasSideEffects = 1 in { 2334def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2335 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2336 IndexModePost, LdFrm, IIC_iLoad_ru, 2337 "ldrt", "\t$Rt, $addr, $offset", 2338 "$addr.base = $Rn_wb", []> { 2339 // {12} isAdd 2340 // {11-0} imm12/Rm 2341 bits<14> offset; 2342 bits<4> addr; 2343 let Inst{25} = 1; 2344 let Inst{23} = offset{12}; 2345 let Inst{21} = 1; // overwrite 2346 let Inst{19-16} = addr; 2347 let Inst{11-5} = offset{11-5}; 2348 let Inst{4} = 0; 2349 let Inst{3-0} = offset{3-0}; 2350 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2351} 2352 2353def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2354 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2355 IndexModePost, LdFrm, IIC_iLoad_ru, 2356 "ldrt", "\t$Rt, $addr, $offset", 2357 "$addr.base = $Rn_wb", []> { 2358 // {12} isAdd 2359 // {11-0} imm12/Rm 2360 bits<14> offset; 2361 bits<4> addr; 2362 let Inst{25} = 0; 2363 let Inst{23} = offset{12}; 2364 let Inst{21} = 1; // overwrite 2365 let Inst{19-16} = addr; 2366 let Inst{11-0} = offset{11-0}; 2367 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2368} 2369 2370def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2371 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2372 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2373 "ldrbt", "\t$Rt, $addr, $offset", 2374 "$addr.base = $Rn_wb", []> { 2375 // {12} isAdd 2376 // {11-0} imm12/Rm 2377 bits<14> offset; 2378 bits<4> addr; 2379 let Inst{25} = 1; 2380 let Inst{23} = offset{12}; 2381 let Inst{21} = 1; // overwrite 2382 let Inst{19-16} = addr; 2383 let Inst{11-5} = offset{11-5}; 2384 let Inst{4} = 0; 2385 let Inst{3-0} = offset{3-0}; 2386 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2387} 2388 2389def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2390 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2391 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2392 "ldrbt", "\t$Rt, $addr, $offset", 2393 "$addr.base = $Rn_wb", []> { 2394 // {12} isAdd 2395 // {11-0} imm12/Rm 2396 bits<14> offset; 2397 bits<4> addr; 2398 let Inst{25} = 0; 2399 let Inst{23} = offset{12}; 2400 let Inst{21} = 1; // overwrite 2401 let Inst{19-16} = addr; 2402 let Inst{11-0} = offset{11-0}; 2403 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2404} 2405 2406multiclass AI3ldrT<bits<4> op, string opc> { 2407 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2408 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2409 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2410 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2411 bits<9> offset; 2412 let Inst{23} = offset{8}; 2413 let Inst{22} = 1; 2414 let Inst{11-8} = offset{7-4}; 2415 let Inst{3-0} = offset{3-0}; 2416 let AsmMatchConverter = "cvtLdExtTWriteBackImm"; 2417 } 2418 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2419 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2420 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2421 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2422 bits<5> Rm; 2423 let Inst{23} = Rm{4}; 2424 let Inst{22} = 0; 2425 let Inst{11-8} = 0; 2426 let Unpredictable{11-8} = 0b1111; 2427 let Inst{3-0} = Rm{3-0}; 2428 let AsmMatchConverter = "cvtLdExtTWriteBackReg"; 2429 let DecoderMethod = "DecodeLDR"; 2430 } 2431} 2432 2433defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2434defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2435defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2436} 2437 2438// Store 2439 2440// Stores with truncate 2441def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2442 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2443 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2444 2445// Store doubleword 2446let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 2447def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr), 2448 StMiscFrm, IIC_iStore_d_r, 2449 "strd", "\t$Rt, $src2, $addr", []>, 2450 Requires<[IsARM, HasV5TE]> { 2451 let Inst{21} = 0; 2452} 2453 2454// Indexed stores 2455multiclass AI2_stridx<bit isByte, string opc, 2456 InstrItinClass iii, InstrItinClass iir> { 2457 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2458 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre, 2459 StFrm, iii, 2460 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2461 bits<17> addr; 2462 let Inst{25} = 0; 2463 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2464 let Inst{19-16} = addr{16-13}; // Rn 2465 let Inst{11-0} = addr{11-0}; // imm12 2466 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12"; 2467 let DecoderMethod = "DecodeSTRPreImm"; 2468 } 2469 2470 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2471 (ins GPR:$Rt, ldst_so_reg:$addr), 2472 IndexModePre, StFrm, iir, 2473 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2474 bits<17> addr; 2475 let Inst{25} = 1; 2476 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2477 let Inst{19-16} = addr{16-13}; // Rn 2478 let Inst{11-0} = addr{11-0}; 2479 let Inst{4} = 0; // Inst{4} = 0 2480 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2"; 2481 let DecoderMethod = "DecodeSTRPreReg"; 2482 } 2483 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2484 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2485 IndexModePost, StFrm, iir, 2486 opc, "\t$Rt, $addr, $offset", 2487 "$addr.base = $Rn_wb", []> { 2488 // {12} isAdd 2489 // {11-0} imm12/Rm 2490 bits<14> offset; 2491 bits<4> addr; 2492 let Inst{25} = 1; 2493 let Inst{23} = offset{12}; 2494 let Inst{19-16} = addr; 2495 let Inst{11-0} = offset{11-0}; 2496 2497 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2498 } 2499 2500 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2501 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2502 IndexModePost, StFrm, iii, 2503 opc, "\t$Rt, $addr, $offset", 2504 "$addr.base = $Rn_wb", []> { 2505 // {12} isAdd 2506 // {11-0} imm12/Rm 2507 bits<14> offset; 2508 bits<4> addr; 2509 let Inst{25} = 0; 2510 let Inst{23} = offset{12}; 2511 let Inst{19-16} = addr; 2512 let Inst{11-0} = offset{11-0}; 2513 2514 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2515 } 2516} 2517 2518let mayStore = 1, neverHasSideEffects = 1 in { 2519// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 2520// IIC_iStore_siu depending on whether it the offset register is shifted. 2521defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 2522defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 2523} 2524 2525def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2526 am2offset_reg:$offset), 2527 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 2528 am2offset_reg:$offset)>; 2529def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 2530 am2offset_imm:$offset), 2531 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2532 am2offset_imm:$offset)>; 2533def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2534 am2offset_reg:$offset), 2535 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 2536 am2offset_reg:$offset)>; 2537def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 2538 am2offset_imm:$offset), 2539 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 2540 am2offset_imm:$offset)>; 2541 2542// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 2543// put the patterns on the instruction definitions directly as ISel wants 2544// the address base and offset to be separate operands, not a single 2545// complex operand like we represent the instructions themselves. The 2546// pseudos map between the two. 2547let usesCustomInserter = 1, 2548 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 2549def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2550 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2551 4, IIC_iStore_ru, 2552 [(set GPR:$Rn_wb, 2553 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2554def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2555 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2556 4, IIC_iStore_ru, 2557 [(set GPR:$Rn_wb, 2558 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2559def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2560 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 2561 4, IIC_iStore_ru, 2562 [(set GPR:$Rn_wb, 2563 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 2564def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2565 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 2566 4, IIC_iStore_ru, 2567 [(set GPR:$Rn_wb, 2568 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 2569def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 2570 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 2571 4, IIC_iStore_ru, 2572 [(set GPR:$Rn_wb, 2573 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 2574} 2575 2576 2577 2578def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 2579 (ins GPR:$Rt, addrmode3:$addr), IndexModePre, 2580 StMiscFrm, IIC_iStore_bh_ru, 2581 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2582 bits<14> addr; 2583 let Inst{23} = addr{8}; // U bit 2584 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2585 let Inst{19-16} = addr{12-9}; // Rn 2586 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2587 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2588 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3"; 2589 let DecoderMethod = "DecodeAddrMode3Instruction"; 2590} 2591 2592def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 2593 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 2594 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 2595 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2596 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 2597 addr_offset_none:$addr, 2598 am3offset:$offset))]> { 2599 bits<10> offset; 2600 bits<4> addr; 2601 let Inst{23} = offset{8}; // U bit 2602 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2603 let Inst{19-16} = addr; 2604 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2605 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2606 let DecoderMethod = "DecodeAddrMode3Instruction"; 2607} 2608 2609let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2610def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 2611 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2612 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 2613 "strd", "\t$Rt, $Rt2, $addr!", 2614 "$addr.base = $Rn_wb", []> { 2615 bits<14> addr; 2616 let Inst{23} = addr{8}; // U bit 2617 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2618 let Inst{19-16} = addr{12-9}; // Rn 2619 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2620 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2621 let DecoderMethod = "DecodeAddrMode3Instruction"; 2622 let AsmMatchConverter = "cvtStrdPre"; 2623} 2624 2625def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 2626 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 2627 am3offset:$offset), 2628 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 2629 "strd", "\t$Rt, $Rt2, $addr, $offset", 2630 "$addr.base = $Rn_wb", []> { 2631 bits<10> offset; 2632 bits<4> addr; 2633 let Inst{23} = offset{8}; // U bit 2634 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2635 let Inst{19-16} = addr; 2636 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2637 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2638 let DecoderMethod = "DecodeAddrMode3Instruction"; 2639} 2640} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 2641 2642// STRT, STRBT, and STRHT 2643 2644def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2645 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2646 IndexModePost, StFrm, IIC_iStore_bh_ru, 2647 "strbt", "\t$Rt, $addr, $offset", 2648 "$addr.base = $Rn_wb", []> { 2649 // {12} isAdd 2650 // {11-0} imm12/Rm 2651 bits<14> offset; 2652 bits<4> addr; 2653 let Inst{25} = 1; 2654 let Inst{23} = offset{12}; 2655 let Inst{21} = 1; // overwrite 2656 let Inst{19-16} = addr; 2657 let Inst{11-5} = offset{11-5}; 2658 let Inst{4} = 0; 2659 let Inst{3-0} = offset{3-0}; 2660 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2661} 2662 2663def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 2664 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2665 IndexModePost, StFrm, IIC_iStore_bh_ru, 2666 "strbt", "\t$Rt, $addr, $offset", 2667 "$addr.base = $Rn_wb", []> { 2668 // {12} isAdd 2669 // {11-0} imm12/Rm 2670 bits<14> offset; 2671 bits<4> addr; 2672 let Inst{25} = 0; 2673 let Inst{23} = offset{12}; 2674 let Inst{21} = 1; // overwrite 2675 let Inst{19-16} = addr; 2676 let Inst{11-0} = offset{11-0}; 2677 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2678} 2679 2680let mayStore = 1, neverHasSideEffects = 1 in { 2681def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2682 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2683 IndexModePost, StFrm, IIC_iStore_ru, 2684 "strt", "\t$Rt, $addr, $offset", 2685 "$addr.base = $Rn_wb", []> { 2686 // {12} isAdd 2687 // {11-0} imm12/Rm 2688 bits<14> offset; 2689 bits<4> addr; 2690 let Inst{25} = 1; 2691 let Inst{23} = offset{12}; 2692 let Inst{21} = 1; // overwrite 2693 let Inst{19-16} = addr; 2694 let Inst{11-5} = offset{11-5}; 2695 let Inst{4} = 0; 2696 let Inst{3-0} = offset{3-0}; 2697 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2698} 2699 2700def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 2701 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 2702 IndexModePost, StFrm, IIC_iStore_ru, 2703 "strt", "\t$Rt, $addr, $offset", 2704 "$addr.base = $Rn_wb", []> { 2705 // {12} isAdd 2706 // {11-0} imm12/Rm 2707 bits<14> offset; 2708 bits<4> addr; 2709 let Inst{25} = 0; 2710 let Inst{23} = offset{12}; 2711 let Inst{21} = 1; // overwrite 2712 let Inst{19-16} = addr; 2713 let Inst{11-0} = offset{11-0}; 2714 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2715} 2716} 2717 2718 2719multiclass AI3strT<bits<4> op, string opc> { 2720 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2721 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 2722 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2723 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2724 bits<9> offset; 2725 let Inst{23} = offset{8}; 2726 let Inst{22} = 1; 2727 let Inst{11-8} = offset{7-4}; 2728 let Inst{3-0} = offset{3-0}; 2729 let AsmMatchConverter = "cvtStExtTWriteBackImm"; 2730 } 2731 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 2732 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 2733 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 2734 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2735 bits<5> Rm; 2736 let Inst{23} = Rm{4}; 2737 let Inst{22} = 0; 2738 let Inst{11-8} = 0; 2739 let Inst{3-0} = Rm{3-0}; 2740 let AsmMatchConverter = "cvtStExtTWriteBackReg"; 2741 } 2742} 2743 2744 2745defm STRHT : AI3strT<0b1011, "strht">; 2746 2747 2748//===----------------------------------------------------------------------===// 2749// Load / store multiple Instructions. 2750// 2751 2752multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 2753 InstrItinClass itin, InstrItinClass itin_upd> { 2754 // IA is the default, so no need for an explicit suffix on the 2755 // mnemonic here. Without it is the cannonical spelling. 2756 def IA : 2757 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2758 IndexModeNone, f, itin, 2759 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 2760 let Inst{24-23} = 0b01; // Increment After 2761 let Inst{22} = P_bit; 2762 let Inst{21} = 0; // No writeback 2763 let Inst{20} = L_bit; 2764 } 2765 def IA_UPD : 2766 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2767 IndexModeUpd, f, itin_upd, 2768 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2769 let Inst{24-23} = 0b01; // Increment After 2770 let Inst{22} = P_bit; 2771 let Inst{21} = 1; // Writeback 2772 let Inst{20} = L_bit; 2773 2774 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2775 } 2776 def DA : 2777 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2778 IndexModeNone, f, itin, 2779 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 2780 let Inst{24-23} = 0b00; // Decrement After 2781 let Inst{22} = P_bit; 2782 let Inst{21} = 0; // No writeback 2783 let Inst{20} = L_bit; 2784 } 2785 def DA_UPD : 2786 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2787 IndexModeUpd, f, itin_upd, 2788 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2789 let Inst{24-23} = 0b00; // Decrement After 2790 let Inst{22} = P_bit; 2791 let Inst{21} = 1; // Writeback 2792 let Inst{20} = L_bit; 2793 2794 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2795 } 2796 def DB : 2797 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2798 IndexModeNone, f, itin, 2799 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 2800 let Inst{24-23} = 0b10; // Decrement Before 2801 let Inst{22} = P_bit; 2802 let Inst{21} = 0; // No writeback 2803 let Inst{20} = L_bit; 2804 } 2805 def DB_UPD : 2806 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2807 IndexModeUpd, f, itin_upd, 2808 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2809 let Inst{24-23} = 0b10; // Decrement Before 2810 let Inst{22} = P_bit; 2811 let Inst{21} = 1; // Writeback 2812 let Inst{20} = L_bit; 2813 2814 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2815 } 2816 def IB : 2817 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2818 IndexModeNone, f, itin, 2819 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 2820 let Inst{24-23} = 0b11; // Increment Before 2821 let Inst{22} = P_bit; 2822 let Inst{21} = 0; // No writeback 2823 let Inst{20} = L_bit; 2824 } 2825 def IB_UPD : 2826 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 2827 IndexModeUpd, f, itin_upd, 2828 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 2829 let Inst{24-23} = 0b11; // Increment Before 2830 let Inst{22} = P_bit; 2831 let Inst{21} = 1; // Writeback 2832 let Inst{20} = L_bit; 2833 2834 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 2835 } 2836} 2837 2838let neverHasSideEffects = 1 in { 2839 2840let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2841defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 2842 IIC_iLoad_mu>; 2843 2844let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2845defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 2846 IIC_iStore_mu>; 2847 2848} // neverHasSideEffects 2849 2850// FIXME: remove when we have a way to marking a MI with these properties. 2851// FIXME: Should pc be an implicit operand like PICADD, etc? 2852let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2853 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 2854def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 2855 reglist:$regs, variable_ops), 2856 4, IIC_iLoad_mBr, [], 2857 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 2858 RegConstraint<"$Rn = $wb">; 2859 2860let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 2861defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 2862 IIC_iLoad_mu>; 2863 2864let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 2865defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 2866 IIC_iStore_mu>; 2867 2868 2869 2870//===----------------------------------------------------------------------===// 2871// Move Instructions. 2872// 2873 2874let neverHasSideEffects = 1 in 2875def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 2876 "mov", "\t$Rd, $Rm", []>, UnaryDP { 2877 bits<4> Rd; 2878 bits<4> Rm; 2879 2880 let Inst{19-16} = 0b0000; 2881 let Inst{11-4} = 0b00000000; 2882 let Inst{25} = 0; 2883 let Inst{3-0} = Rm; 2884 let Inst{15-12} = Rd; 2885} 2886 2887def : ARMInstAlias<"movs${p} $Rd, $Rm", 2888 (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>; 2889 2890// A version for the smaller set of tail call registers. 2891let neverHasSideEffects = 1 in 2892def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 2893 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP { 2894 bits<4> Rd; 2895 bits<4> Rm; 2896 2897 let Inst{11-4} = 0b00000000; 2898 let Inst{25} = 0; 2899 let Inst{3-0} = Rm; 2900 let Inst{15-12} = Rd; 2901} 2902 2903def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 2904 DPSoRegRegFrm, IIC_iMOVsr, 2905 "mov", "\t$Rd, $src", 2906 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP { 2907 bits<4> Rd; 2908 bits<12> src; 2909 let Inst{15-12} = Rd; 2910 let Inst{19-16} = 0b0000; 2911 let Inst{11-8} = src{11-8}; 2912 let Inst{7} = 0; 2913 let Inst{6-5} = src{6-5}; 2914 let Inst{4} = 1; 2915 let Inst{3-0} = src{3-0}; 2916 let Inst{25} = 0; 2917} 2918 2919def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 2920 DPSoRegImmFrm, IIC_iMOVsr, 2921 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 2922 UnaryDP { 2923 bits<4> Rd; 2924 bits<12> src; 2925 let Inst{15-12} = Rd; 2926 let Inst{19-16} = 0b0000; 2927 let Inst{11-5} = src{11-5}; 2928 let Inst{4} = 0; 2929 let Inst{3-0} = src{3-0}; 2930 let Inst{25} = 0; 2931} 2932 2933let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 2934def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi, 2935 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP { 2936 bits<4> Rd; 2937 bits<12> imm; 2938 let Inst{25} = 1; 2939 let Inst{15-12} = Rd; 2940 let Inst{19-16} = 0b0000; 2941 let Inst{11-0} = imm; 2942} 2943 2944let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 2945def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 2946 DPFrm, IIC_iMOVi, 2947 "movw", "\t$Rd, $imm", 2948 [(set GPR:$Rd, imm0_65535:$imm)]>, 2949 Requires<[IsARM, HasV6T2]>, UnaryDP { 2950 bits<4> Rd; 2951 bits<16> imm; 2952 let Inst{15-12} = Rd; 2953 let Inst{11-0} = imm{11-0}; 2954 let Inst{19-16} = imm{15-12}; 2955 let Inst{20} = 0; 2956 let Inst{25} = 1; 2957 let DecoderMethod = "DecodeArmMOVTWInstruction"; 2958} 2959 2960def : InstAlias<"mov${p} $Rd, $imm", 2961 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>, 2962 Requires<[IsARM]>; 2963 2964def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 2965 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 2966 2967let Constraints = "$src = $Rd" in { 2968def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 2969 (ins GPR:$src, imm0_65535_expr:$imm), 2970 DPFrm, IIC_iMOVi, 2971 "movt", "\t$Rd, $imm", 2972 [(set GPRnopc:$Rd, 2973 (or (and GPR:$src, 0xffff), 2974 lo16AllZero:$imm))]>, UnaryDP, 2975 Requires<[IsARM, HasV6T2]> { 2976 bits<4> Rd; 2977 bits<16> imm; 2978 let Inst{15-12} = Rd; 2979 let Inst{11-0} = imm{11-0}; 2980 let Inst{19-16} = imm{15-12}; 2981 let Inst{20} = 0; 2982 let Inst{25} = 1; 2983 let DecoderMethod = "DecodeArmMOVTWInstruction"; 2984} 2985 2986def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 2987 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 2988 2989} // Constraints 2990 2991def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 2992 Requires<[IsARM, HasV6T2]>; 2993 2994let Uses = [CPSR] in 2995def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 2996 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 2997 Requires<[IsARM]>; 2998 2999// These aren't really mov instructions, but we have to define them this way 3000// due to flag operands. 3001 3002let Defs = [CPSR] in { 3003def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3004 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3005 Requires<[IsARM]>; 3006def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3007 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3008 Requires<[IsARM]>; 3009} 3010 3011//===----------------------------------------------------------------------===// 3012// Extend Instructions. 3013// 3014 3015// Sign extenders 3016 3017def SXTB : AI_ext_rrot<0b01101010, 3018 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3019def SXTH : AI_ext_rrot<0b01101011, 3020 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3021 3022def SXTAB : AI_exta_rrot<0b01101010, 3023 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3024def SXTAH : AI_exta_rrot<0b01101011, 3025 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3026 3027def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3028 3029def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3030 3031// Zero extenders 3032 3033let AddedComplexity = 16 in { 3034def UXTB : AI_ext_rrot<0b01101110, 3035 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3036def UXTH : AI_ext_rrot<0b01101111, 3037 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3038def UXTB16 : AI_ext_rrot<0b01101100, 3039 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3040 3041// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3042// The transformation should probably be done as a combiner action 3043// instead so we can include a check for masking back in the upper 3044// eight bits of the source into the lower eight bits of the result. 3045//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3046// (UXTB16r_rot GPR:$Src, 3)>; 3047def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3048 (UXTB16 GPR:$Src, 1)>; 3049 3050def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3051 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3052def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3053 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3054} 3055 3056// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3057def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3058 3059 3060def SBFX : I<(outs GPRnopc:$Rd), 3061 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3062 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3063 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3064 Requires<[IsARM, HasV6T2]> { 3065 bits<4> Rd; 3066 bits<4> Rn; 3067 bits<5> lsb; 3068 bits<5> width; 3069 let Inst{27-21} = 0b0111101; 3070 let Inst{6-4} = 0b101; 3071 let Inst{20-16} = width; 3072 let Inst{15-12} = Rd; 3073 let Inst{11-7} = lsb; 3074 let Inst{3-0} = Rn; 3075} 3076 3077def UBFX : I<(outs GPR:$Rd), 3078 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width), 3079 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3080 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3081 Requires<[IsARM, HasV6T2]> { 3082 bits<4> Rd; 3083 bits<4> Rn; 3084 bits<5> lsb; 3085 bits<5> width; 3086 let Inst{27-21} = 0b0111111; 3087 let Inst{6-4} = 0b101; 3088 let Inst{20-16} = width; 3089 let Inst{15-12} = Rd; 3090 let Inst{11-7} = lsb; 3091 let Inst{3-0} = Rn; 3092} 3093 3094//===----------------------------------------------------------------------===// 3095// Arithmetic Instructions. 3096// 3097 3098defm ADD : AsI1_bin_irs<0b0100, "add", 3099 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3100 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>; 3101defm SUB : AsI1_bin_irs<0b0010, "sub", 3102 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3103 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">; 3104 3105// ADD and SUB with 's' bit set. 3106// 3107// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3108// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3109// AdjustInstrPostInstrSelection where we determine whether or not to 3110// set the "s" bit based on CPSR liveness. 3111// 3112// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3113// support for an optional CPSR definition that corresponds to the DAG 3114// node's second value. We can then eliminate the implicit def of CPSR. 3115defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3116 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 3117defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3118 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3119 3120defm ADC : AI1_adde_sube_irs<0b0101, "adc", 3121 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 3122 "ADC", 1>; 3123defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 3124 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>, 3125 "SBC">; 3126 3127defm RSB : AsI1_rbin_irs <0b0011, "rsb", 3128 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3129 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">; 3130 3131// FIXME: Eliminate them if we can write def : Pat patterns which defines 3132// CPSR and the implicit def of CPSR is not needed. 3133defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3134 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 3135 3136defm RSC : AI1_rsc_irs<0b0111, "rsc", 3137 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>, 3138 "RSC">; 3139 3140// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3141// The assume-no-carry-in form uses the negation of the input since add/sub 3142// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3143// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3144// details. 3145def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 3146 (SUBri GPR:$src, so_imm_neg:$imm)>; 3147def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm), 3148 (SUBSri GPR:$src, so_imm_neg:$imm)>; 3149 3150// The with-carry-in form matches bitwise not instead of the negation. 3151// Effectively, the inverse interpretation of the carry flag already accounts 3152// for part of the negation. 3153def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR), 3154 (SBCri GPR:$src, so_imm_not:$imm)>; 3155 3156// Note: These are implemented in C++ code, because they have to generate 3157// ADD/SUBrs instructions, which use a complex pattern that a xform function 3158// cannot produce. 3159// (mul X, 2^n+1) -> (add (X << n), X) 3160// (mul X, 2^n-1) -> (rsb X, (X << n)) 3161 3162// ARM Arithmetic Instruction 3163// GPR:$dst = GPR:$a op GPR:$b 3164class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3165 list<dag> pattern = [], 3166 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3167 string asm = "\t$Rd, $Rn, $Rm"> 3168 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> { 3169 bits<4> Rn; 3170 bits<4> Rd; 3171 bits<4> Rm; 3172 let Inst{27-20} = op27_20; 3173 let Inst{11-4} = op11_4; 3174 let Inst{19-16} = Rn; 3175 let Inst{15-12} = Rd; 3176 let Inst{3-0} = Rm; 3177 3178 let Unpredictable{11-8} = 0b1111; 3179} 3180 3181// Saturating add/subtract 3182 3183def QADD : AAI<0b00010000, 0b00000101, "qadd", 3184 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))], 3185 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3186def QSUB : AAI<0b00010010, 0b00000101, "qsub", 3187 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))], 3188 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">; 3189def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], 3190 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3191 "\t$Rd, $Rm, $Rn">; 3192def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], 3193 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3194 "\t$Rd, $Rm, $Rn">; 3195 3196def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">; 3197def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">; 3198def QASX : AAI<0b01100010, 0b11110011, "qasx">; 3199def QSAX : AAI<0b01100010, 0b11110101, "qsax">; 3200def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">; 3201def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">; 3202def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">; 3203def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">; 3204def UQASX : AAI<0b01100110, 0b11110011, "uqasx">; 3205def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">; 3206def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">; 3207def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">; 3208 3209// Signed/Unsigned add/subtract 3210 3211def SASX : AAI<0b01100001, 0b11110011, "sasx">; 3212def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">; 3213def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">; 3214def SSAX : AAI<0b01100001, 0b11110101, "ssax">; 3215def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">; 3216def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">; 3217def UASX : AAI<0b01100101, 0b11110011, "uasx">; 3218def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">; 3219def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">; 3220def USAX : AAI<0b01100101, 0b11110101, "usax">; 3221def USUB16 : AAI<0b01100101, 0b11110111, "usub16">; 3222def USUB8 : AAI<0b01100101, 0b11111111, "usub8">; 3223 3224// Signed/Unsigned halving add/subtract 3225 3226def SHASX : AAI<0b01100011, 0b11110011, "shasx">; 3227def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">; 3228def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">; 3229def SHSAX : AAI<0b01100011, 0b11110101, "shsax">; 3230def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">; 3231def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">; 3232def UHASX : AAI<0b01100111, 0b11110011, "uhasx">; 3233def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">; 3234def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">; 3235def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">; 3236def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">; 3237def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">; 3238 3239// Unsigned Sum of Absolute Differences [and Accumulate]. 3240 3241def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3242 MulFrm /* for convenience */, NoItinerary, "usad8", 3243 "\t$Rd, $Rn, $Rm", []>, 3244 Requires<[IsARM, HasV6]> { 3245 bits<4> Rd; 3246 bits<4> Rn; 3247 bits<4> Rm; 3248 let Inst{27-20} = 0b01111000; 3249 let Inst{15-12} = 0b1111; 3250 let Inst{7-4} = 0b0001; 3251 let Inst{19-16} = Rd; 3252 let Inst{11-8} = Rm; 3253 let Inst{3-0} = Rn; 3254} 3255def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3256 MulFrm /* for convenience */, NoItinerary, "usada8", 3257 "\t$Rd, $Rn, $Rm, $Ra", []>, 3258 Requires<[IsARM, HasV6]> { 3259 bits<4> Rd; 3260 bits<4> Rn; 3261 bits<4> Rm; 3262 bits<4> Ra; 3263 let Inst{27-20} = 0b01111000; 3264 let Inst{7-4} = 0b0001; 3265 let Inst{19-16} = Rd; 3266 let Inst{15-12} = Ra; 3267 let Inst{11-8} = Rm; 3268 let Inst{3-0} = Rn; 3269} 3270 3271// Signed/Unsigned saturate 3272 3273def SSAT : AI<(outs GPRnopc:$Rd), 3274 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3275 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3276 bits<4> Rd; 3277 bits<5> sat_imm; 3278 bits<4> Rn; 3279 bits<8> sh; 3280 let Inst{27-21} = 0b0110101; 3281 let Inst{5-4} = 0b01; 3282 let Inst{20-16} = sat_imm; 3283 let Inst{15-12} = Rd; 3284 let Inst{11-7} = sh{4-0}; 3285 let Inst{6} = sh{5}; 3286 let Inst{3-0} = Rn; 3287} 3288 3289def SSAT16 : AI<(outs GPRnopc:$Rd), 3290 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3291 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> { 3292 bits<4> Rd; 3293 bits<4> sat_imm; 3294 bits<4> Rn; 3295 let Inst{27-20} = 0b01101010; 3296 let Inst{11-4} = 0b11110011; 3297 let Inst{15-12} = Rd; 3298 let Inst{19-16} = sat_imm; 3299 let Inst{3-0} = Rn; 3300} 3301 3302def USAT : AI<(outs GPRnopc:$Rd), 3303 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3304 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 3305 bits<4> Rd; 3306 bits<5> sat_imm; 3307 bits<4> Rn; 3308 bits<8> sh; 3309 let Inst{27-21} = 0b0110111; 3310 let Inst{5-4} = 0b01; 3311 let Inst{15-12} = Rd; 3312 let Inst{11-7} = sh{4-0}; 3313 let Inst{6} = sh{5}; 3314 let Inst{20-16} = sat_imm; 3315 let Inst{3-0} = Rn; 3316} 3317 3318def USAT16 : AI<(outs GPRnopc:$Rd), 3319 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3320 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> { 3321 bits<4> Rd; 3322 bits<4> sat_imm; 3323 bits<4> Rn; 3324 let Inst{27-20} = 0b01101110; 3325 let Inst{11-4} = 0b11110011; 3326 let Inst{15-12} = Rd; 3327 let Inst{19-16} = sat_imm; 3328 let Inst{3-0} = Rn; 3329} 3330 3331def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos), 3332 (SSAT imm:$pos, GPRnopc:$a, 0)>; 3333def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos), 3334 (USAT imm:$pos, GPRnopc:$a, 0)>; 3335 3336//===----------------------------------------------------------------------===// 3337// Bitwise Instructions. 3338// 3339 3340defm AND : AsI1_bin_irs<0b0000, "and", 3341 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3342 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>; 3343defm ORR : AsI1_bin_irs<0b1100, "orr", 3344 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3345 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>; 3346defm EOR : AsI1_bin_irs<0b0001, "eor", 3347 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3348 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>; 3349defm BIC : AsI1_bin_irs<0b1110, "bic", 3350 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3351 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">; 3352 3353// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3354// like in the actual instruction encoding. The complexity of mapping the mask 3355// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3356// instruction description. 3357def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3358 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3359 "bfc", "\t$Rd, $imm", "$src = $Rd", 3360 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3361 Requires<[IsARM, HasV6T2]> { 3362 bits<4> Rd; 3363 bits<10> imm; 3364 let Inst{27-21} = 0b0111110; 3365 let Inst{6-0} = 0b0011111; 3366 let Inst{15-12} = Rd; 3367 let Inst{11-7} = imm{4-0}; // lsb 3368 let Inst{20-16} = imm{9-5}; // msb 3369} 3370 3371// A8.6.18 BFI - Bitfield insert (Encoding A1) 3372def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3373 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3374 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3375 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3376 bf_inv_mask_imm:$imm))]>, 3377 Requires<[IsARM, HasV6T2]> { 3378 bits<4> Rd; 3379 bits<4> Rn; 3380 bits<10> imm; 3381 let Inst{27-21} = 0b0111110; 3382 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3383 let Inst{15-12} = Rd; 3384 let Inst{11-7} = imm{4-0}; // lsb 3385 let Inst{20-16} = imm{9-5}; // width 3386 let Inst{3-0} = Rn; 3387} 3388 3389def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3390 "mvn", "\t$Rd, $Rm", 3391 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP { 3392 bits<4> Rd; 3393 bits<4> Rm; 3394 let Inst{25} = 0; 3395 let Inst{19-16} = 0b0000; 3396 let Inst{11-4} = 0b00000000; 3397 let Inst{15-12} = Rd; 3398 let Inst{3-0} = Rm; 3399} 3400def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3401 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3402 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP { 3403 bits<4> Rd; 3404 bits<12> shift; 3405 let Inst{25} = 0; 3406 let Inst{19-16} = 0b0000; 3407 let Inst{15-12} = Rd; 3408 let Inst{11-5} = shift{11-5}; 3409 let Inst{4} = 0; 3410 let Inst{3-0} = shift{3-0}; 3411} 3412def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift), 3413 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3414 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP { 3415 bits<4> Rd; 3416 bits<12> shift; 3417 let Inst{25} = 0; 3418 let Inst{19-16} = 0b0000; 3419 let Inst{15-12} = Rd; 3420 let Inst{11-8} = shift{11-8}; 3421 let Inst{7} = 0; 3422 let Inst{6-5} = shift{6-5}; 3423 let Inst{4} = 1; 3424 let Inst{3-0} = shift{3-0}; 3425} 3426let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3427def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, 3428 IIC_iMVNi, "mvn", "\t$Rd, $imm", 3429 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP { 3430 bits<4> Rd; 3431 bits<12> imm; 3432 let Inst{25} = 1; 3433 let Inst{19-16} = 0b0000; 3434 let Inst{15-12} = Rd; 3435 let Inst{11-0} = imm; 3436} 3437 3438def : ARMPat<(and GPR:$src, so_imm_not:$imm), 3439 (BICri GPR:$src, so_imm_not:$imm)>; 3440 3441//===----------------------------------------------------------------------===// 3442// Multiply Instructions. 3443// 3444class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3445 string opc, string asm, list<dag> pattern> 3446 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3447 bits<4> Rd; 3448 bits<4> Rm; 3449 bits<4> Rn; 3450 let Inst{19-16} = Rd; 3451 let Inst{11-8} = Rm; 3452 let Inst{3-0} = Rn; 3453} 3454class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 3455 string opc, string asm, list<dag> pattern> 3456 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 3457 bits<4> RdLo; 3458 bits<4> RdHi; 3459 bits<4> Rm; 3460 bits<4> Rn; 3461 let Inst{19-16} = RdHi; 3462 let Inst{15-12} = RdLo; 3463 let Inst{11-8} = Rm; 3464 let Inst{3-0} = Rn; 3465} 3466 3467// FIXME: The v5 pseudos are only necessary for the additional Constraint 3468// property. Remove them when it's possible to add those properties 3469// on an individual MachineInstr, not just an instuction description. 3470let isCommutable = 1 in { 3471def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 3472 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 3473 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 3474 Requires<[IsARM, HasV6]> { 3475 let Inst{15-12} = 0b0000; 3476 let Unpredictable{15-12} = 0b1111; 3477} 3478 3479let Constraints = "@earlyclobber $Rd" in 3480def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 3481 pred:$p, cc_out:$s), 3482 4, IIC_iMUL32, 3483 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 3484 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 3485 Requires<[IsARM, NoV6]>; 3486} 3487 3488def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3489 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 3490 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3491 Requires<[IsARM, HasV6]> { 3492 bits<4> Ra; 3493 let Inst{15-12} = Ra; 3494} 3495 3496let Constraints = "@earlyclobber $Rd" in 3497def MLAv5: ARMPseudoExpand<(outs GPR:$Rd), 3498 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s), 3499 4, IIC_iMAC32, 3500 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))], 3501 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>, 3502 Requires<[IsARM, NoV6]>; 3503 3504def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3505 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 3506 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 3507 Requires<[IsARM, HasV6T2]> { 3508 bits<4> Rd; 3509 bits<4> Rm; 3510 bits<4> Rn; 3511 bits<4> Ra; 3512 let Inst{19-16} = Rd; 3513 let Inst{15-12} = Ra; 3514 let Inst{11-8} = Rm; 3515 let Inst{3-0} = Rn; 3516} 3517 3518// Extra precision multiplies with low / high results 3519let neverHasSideEffects = 1 in { 3520let isCommutable = 1 in { 3521def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 3522 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3523 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3524 Requires<[IsARM, HasV6]>; 3525 3526def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 3527 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 3528 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3529 Requires<[IsARM, HasV6]>; 3530 3531let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3532def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3533 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3534 4, IIC_iMUL64, [], 3535 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3536 Requires<[IsARM, NoV6]>; 3537 3538def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3539 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3540 4, IIC_iMUL64, [], 3541 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3542 Requires<[IsARM, NoV6]>; 3543} 3544} 3545 3546// Multiply + accumulate 3547def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 3548 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3549 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3550 Requires<[IsARM, HasV6]>; 3551def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 3552 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3553 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3554 Requires<[IsARM, HasV6]>; 3555 3556def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 3557 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64, 3558 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3559 Requires<[IsARM, HasV6]> { 3560 bits<4> RdLo; 3561 bits<4> RdHi; 3562 bits<4> Rm; 3563 bits<4> Rn; 3564 let Inst{19-16} = RdHi; 3565 let Inst{15-12} = RdLo; 3566 let Inst{11-8} = Rm; 3567 let Inst{3-0} = Rn; 3568} 3569 3570let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 3571def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3572 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3573 4, IIC_iMAC64, [], 3574 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3575 Requires<[IsARM, NoV6]>; 3576def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3577 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 3578 4, IIC_iMAC64, [], 3579 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 3580 Requires<[IsARM, NoV6]>; 3581def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 3582 (ins GPR:$Rn, GPR:$Rm, pred:$p), 3583 4, IIC_iMAC64, [], 3584 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>, 3585 Requires<[IsARM, NoV6]>; 3586} 3587 3588} // neverHasSideEffects 3589 3590// Most significant word multiply 3591def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3592 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 3593 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 3594 Requires<[IsARM, HasV6]> { 3595 let Inst{15-12} = 0b1111; 3596} 3597 3598def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3599 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>, 3600 Requires<[IsARM, HasV6]> { 3601 let Inst{15-12} = 0b1111; 3602} 3603 3604def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 3605 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3606 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 3607 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 3608 Requires<[IsARM, HasV6]>; 3609 3610def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 3611 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3612 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 3613 Requires<[IsARM, HasV6]>; 3614 3615def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 3616 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3617 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", 3618 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>, 3619 Requires<[IsARM, HasV6]>; 3620 3621def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 3622 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3623 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 3624 Requires<[IsARM, HasV6]>; 3625 3626multiclass AI_smul<string opc, PatFrag opnode> { 3627 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3628 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 3629 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3630 (sext_inreg GPR:$Rm, i16)))]>, 3631 Requires<[IsARM, HasV5TE]>; 3632 3633 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3634 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 3635 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16), 3636 (sra GPR:$Rm, (i32 16))))]>, 3637 Requires<[IsARM, HasV5TE]>; 3638 3639 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3640 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 3641 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3642 (sext_inreg GPR:$Rm, i16)))]>, 3643 Requires<[IsARM, HasV5TE]>; 3644 3645 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3646 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 3647 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)), 3648 (sra GPR:$Rm, (i32 16))))]>, 3649 Requires<[IsARM, HasV5TE]>; 3650 3651 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3652 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 3653 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3654 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>, 3655 Requires<[IsARM, HasV5TE]>; 3656 3657 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3658 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 3659 [(set GPR:$Rd, (sra (opnode GPR:$Rn, 3660 (sra GPR:$Rm, (i32 16))), (i32 16)))]>, 3661 Requires<[IsARM, HasV5TE]>; 3662} 3663 3664 3665multiclass AI_smla<string opc, PatFrag opnode> { 3666 let DecoderMethod = "DecodeSMLAInstruction" in { 3667 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 3668 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3669 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 3670 [(set GPRnopc:$Rd, (add GPR:$Ra, 3671 (opnode (sext_inreg GPRnopc:$Rn, i16), 3672 (sext_inreg GPRnopc:$Rm, i16))))]>, 3673 Requires<[IsARM, HasV5TE]>; 3674 3675 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 3676 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3677 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 3678 [(set GPRnopc:$Rd, 3679 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16), 3680 (sra GPRnopc:$Rm, (i32 16)))))]>, 3681 Requires<[IsARM, HasV5TE]>; 3682 3683 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 3684 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3685 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 3686 [(set GPRnopc:$Rd, 3687 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3688 (sext_inreg GPRnopc:$Rm, i16))))]>, 3689 Requires<[IsARM, HasV5TE]>; 3690 3691 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 3692 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3693 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 3694 [(set GPRnopc:$Rd, 3695 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)), 3696 (sra GPRnopc:$Rm, (i32 16)))))]>, 3697 Requires<[IsARM, HasV5TE]>; 3698 3699 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 3700 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3701 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 3702 [(set GPRnopc:$Rd, 3703 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3704 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>, 3705 Requires<[IsARM, HasV5TE]>; 3706 3707 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 3708 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3709 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 3710 [(set GPRnopc:$Rd, 3711 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn, 3712 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>, 3713 Requires<[IsARM, HasV5TE]>; 3714 } 3715} 3716 3717defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3718defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 3719 3720// Halfword multiply accumulate long: SMLAL<x><y>. 3721def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3722 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3723 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3724 Requires<[IsARM, HasV5TE]>; 3725 3726def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3727 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3728 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3729 Requires<[IsARM, HasV5TE]>; 3730 3731def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3732 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3733 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3734 Requires<[IsARM, HasV5TE]>; 3735 3736def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3737 (ins GPRnopc:$Rn, GPRnopc:$Rm), 3738 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 3739 Requires<[IsARM, HasV5TE]>; 3740 3741// Helper class for AI_smld. 3742class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 3743 InstrItinClass itin, string opc, string asm> 3744 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 3745 bits<4> Rn; 3746 bits<4> Rm; 3747 let Inst{27-23} = 0b01110; 3748 let Inst{22} = long; 3749 let Inst{21-20} = 0b00; 3750 let Inst{11-8} = Rm; 3751 let Inst{7} = 0; 3752 let Inst{6} = sub; 3753 let Inst{5} = swap; 3754 let Inst{4} = 1; 3755 let Inst{3-0} = Rn; 3756} 3757class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 3758 InstrItinClass itin, string opc, string asm> 3759 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3760 bits<4> Rd; 3761 let Inst{15-12} = 0b1111; 3762 let Inst{19-16} = Rd; 3763} 3764class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 3765 InstrItinClass itin, string opc, string asm> 3766 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3767 bits<4> Ra; 3768 bits<4> Rd; 3769 let Inst{19-16} = Rd; 3770 let Inst{15-12} = Ra; 3771} 3772class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 3773 InstrItinClass itin, string opc, string asm> 3774 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 3775 bits<4> RdLo; 3776 bits<4> RdHi; 3777 let Inst{19-16} = RdHi; 3778 let Inst{15-12} = RdLo; 3779} 3780 3781multiclass AI_smld<bit sub, string opc> { 3782 3783 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 3784 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3785 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">; 3786 3787 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 3788 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 3789 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">; 3790 3791 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3792 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3793 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">; 3794 3795 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 3796 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary, 3797 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">; 3798 3799} 3800 3801defm SMLA : AI_smld<0, "smla">; 3802defm SMLS : AI_smld<1, "smls">; 3803 3804multiclass AI_sdml<bit sub, string opc> { 3805 3806 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 3807 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">; 3808 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 3809 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">; 3810} 3811 3812defm SMUA : AI_sdml<0, "smua">; 3813defm SMUS : AI_sdml<1, "smus">; 3814 3815//===----------------------------------------------------------------------===// 3816// Misc. Arithmetic Instructions. 3817// 3818 3819def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 3820 IIC_iUNAr, "clz", "\t$Rd, $Rm", 3821 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>; 3822 3823def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3824 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 3825 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>, 3826 Requires<[IsARM, HasV6T2]>; 3827 3828def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 3829 IIC_iUNAr, "rev", "\t$Rd, $Rm", 3830 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>; 3831 3832let AddedComplexity = 5 in 3833def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 3834 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 3835 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 3836 Requires<[IsARM, HasV6]>; 3837 3838let AddedComplexity = 5 in 3839def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 3840 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 3841 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 3842 Requires<[IsARM, HasV6]>; 3843 3844def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 3845 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 3846 (REVSH GPR:$Rm)>; 3847 3848def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 3849 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 3850 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 3851 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 3852 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 3853 0xFFFF0000)))]>, 3854 Requires<[IsARM, HasV6]>; 3855 3856// Alternate cases for PKHBT where identities eliminate some nodes. 3857def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 3858 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 3859def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 3860 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 3861 3862// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 3863// will match the pattern below. 3864def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 3865 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 3866 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 3867 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 3868 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 3869 0xFFFF)))]>, 3870 Requires<[IsARM, HasV6]>; 3871 3872// Alternate cases for PKHTB where identities eliminate some nodes. Note that 3873// a shift amount of 0 is *not legal* here, it is PKHBT instead. 3874def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 3875 (srl GPRnopc:$src2, imm16_31:$sh)), 3876 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 3877def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 3878 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 3879 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 3880 3881//===----------------------------------------------------------------------===// 3882// Comparison Instructions... 3883// 3884 3885defm CMP : AI1_cmp_irs<0b1010, "cmp", 3886 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 3887 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 3888 3889// ARMcmpZ can re-use the above instruction definitions. 3890def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm), 3891 (CMPri GPR:$src, so_imm:$imm)>; 3892def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 3893 (CMPrr GPR:$src, GPR:$rhs)>; 3894def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 3895 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 3896def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 3897 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 3898 3899// FIXME: We have to be careful when using the CMN instruction and comparison 3900// with 0. One would expect these two pieces of code should give identical 3901// results: 3902// 3903// rsbs r1, r1, 0 3904// cmp r0, r1 3905// mov r0, #0 3906// it ls 3907// mov r0, #1 3908// 3909// and: 3910// 3911// cmn r0, r1 3912// mov r0, #0 3913// it ls 3914// mov r0, #1 3915// 3916// However, the CMN gives the *opposite* result when r1 is 0. This is because 3917// the carry flag is set in the CMP case but not in the CMN case. In short, the 3918// CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the 3919// value of r0 and the carry bit (because the "carry bit" parameter to 3920// AddWithCarry is defined as 1 in this case, the carry flag will always be set 3921// when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is 3922// never a "carry" when this AddWithCarry is performed (because the "carry bit" 3923// parameter to AddWithCarry is defined as 0). 3924// 3925// When x is 0 and unsigned: 3926// 3927// x = 0 3928// ~x = 0xFFFF FFFF 3929// ~x + 1 = 0x1 0000 0000 3930// (-x = 0) != (0x1 0000 0000 = ~x + 1) 3931// 3932// Therefore, we should disable CMN when comparing against zero, until we can 3933// limit when the CMN instruction is used (when we know that the RHS is not 0 or 3934// when it's a comparison which doesn't look at the 'carry' flag). 3935// 3936// (See the ARM docs for the "AddWithCarry" pseudo-code.) 3937// 3938// This is related to <rdar://problem/7569620>. 3939// 3940//defm CMN : AI1_cmp_irs<0b1011, "cmn", 3941// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 3942 3943// Note that TST/TEQ don't set all the same flags that CMP does! 3944defm TST : AI1_cmp_irs<0b1000, "tst", 3945 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 3946 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>; 3947defm TEQ : AI1_cmp_irs<0b1001, "teq", 3948 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 3949 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 3950 3951defm CMNz : AI1_cmp_irs<0b1011, "cmn", 3952 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, 3953 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 3954 3955//def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 3956// (CMNri GPR:$src, so_imm_neg:$imm)>; 3957 3958def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 3959 (CMNzri GPR:$src, so_imm_neg:$imm)>; 3960 3961// Pseudo i64 compares for some floating point compares. 3962let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 3963 Defs = [CPSR] in { 3964def BCCi64 : PseudoInst<(outs), 3965 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 3966 IIC_Br, 3967 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>; 3968 3969def BCCZi64 : PseudoInst<(outs), 3970 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 3971 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>; 3972} // usesCustomInserter 3973 3974 3975// Conditional moves 3976// FIXME: should be able to write a pattern for ARMcmov, but can't use 3977// a two-value operand where a dag node expects two operands. :( 3978let neverHasSideEffects = 1 in { 3979 3980let isCommutable = 1 in 3981def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p), 3982 4, IIC_iCMOVr, 3983 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, 3984 RegConstraint<"$false = $Rd">; 3985 3986def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 3987 (ins GPR:$false, so_reg_imm:$shift, pred:$p), 3988 4, IIC_iCMOVsr, 3989 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift, 3990 imm:$cc, CCR:$ccr))*/]>, 3991 RegConstraint<"$false = $Rd">; 3992def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 3993 (ins GPR:$false, so_reg_reg:$shift, pred:$p), 3994 4, IIC_iCMOVsr, 3995 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 3996 imm:$cc, CCR:$ccr))*/]>, 3997 RegConstraint<"$false = $Rd">; 3998 3999 4000let isMoveImm = 1 in 4001def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd), 4002 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p), 4003 4, IIC_iMOVi, 4004 []>, 4005 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4006 4007let isMoveImm = 1 in 4008def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4009 (ins GPR:$false, so_imm:$imm, pred:$p), 4010 4, IIC_iCMOVi, 4011 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>, 4012 RegConstraint<"$false = $Rd">; 4013 4014// Two instruction predicate mov immediate. 4015let isMoveImm = 1 in 4016def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd), 4017 (ins GPR:$false, i32imm:$src, pred:$p), 4018 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">; 4019 4020let isMoveImm = 1 in 4021def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4022 (ins GPR:$false, so_imm:$imm, pred:$p), 4023 4, IIC_iCMOVi, 4024 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>, 4025 RegConstraint<"$false = $Rd">; 4026 4027// Conditional instructions 4028multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi, 4029 Instruction irsr, 4030 InstrItinClass iii, InstrItinClass iir, 4031 InstrItinClass iis> { 4032 def ri : ARMPseudoExpand<(outs GPR:$Rd), 4033 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s), 4034 4, iii, [], 4035 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>, 4036 RegConstraint<"$Rn = $Rd">; 4037 def rr : ARMPseudoExpand<(outs GPR:$Rd), 4038 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4039 4, iir, [], 4040 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4041 RegConstraint<"$Rn = $Rd">; 4042 def rsi : ARMPseudoExpand<(outs GPR:$Rd), 4043 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s), 4044 4, iis, [], 4045 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>, 4046 RegConstraint<"$Rn = $Rd">; 4047 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd), 4048 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s), 4049 4, iis, [], 4050 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>, 4051 RegConstraint<"$Rn = $Rd">; 4052} 4053 4054defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr, 4055 IIC_iBITi, IIC_iBITr, IIC_iBITsr>; 4056defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr, 4057 IIC_iBITi, IIC_iBITr, IIC_iBITsr>; 4058defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr, 4059 IIC_iBITi, IIC_iBITr, IIC_iBITsr>; 4060 4061} // neverHasSideEffects 4062 4063 4064//===----------------------------------------------------------------------===// 4065// Atomic operations intrinsics 4066// 4067 4068def MemBarrierOptOperand : AsmOperandClass { 4069 let Name = "MemBarrierOpt"; 4070 let ParserMethod = "parseMemBarrierOptOperand"; 4071} 4072def memb_opt : Operand<i32> { 4073 let PrintMethod = "printMemBOption"; 4074 let ParserMatchClass = MemBarrierOptOperand; 4075 let DecoderMethod = "DecodeMemBarrierOption"; 4076} 4077 4078// memory barriers protect the atomic sequences 4079let hasSideEffects = 1 in { 4080def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4081 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>, 4082 Requires<[IsARM, HasDB]> { 4083 bits<4> opt; 4084 let Inst{31-4} = 0xf57ff05; 4085 let Inst{3-0} = opt; 4086} 4087} 4088 4089def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4090 "dsb", "\t$opt", []>, 4091 Requires<[IsARM, HasDB]> { 4092 bits<4> opt; 4093 let Inst{31-4} = 0xf57ff04; 4094 let Inst{3-0} = opt; 4095} 4096 4097// ISB has only full system option 4098def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4099 "isb", "\t$opt", []>, 4100 Requires<[IsARM, HasDB]> { 4101 bits<4> opt; 4102 let Inst{31-4} = 0xf57ff06; 4103 let Inst{3-0} = opt; 4104} 4105 4106// Pseudo isntruction that combines movs + predicated rsbmi 4107// to implement integer ABS 4108let usesCustomInserter = 1, Defs = [CPSR] in { 4109def ABS : ARMPseudoInst< 4110 (outs GPR:$dst), (ins GPR:$src), 4111 8, NoItinerary, []>; 4112} 4113 4114let usesCustomInserter = 1 in { 4115 let Defs = [CPSR] in { 4116 def ATOMIC_LOAD_ADD_I8 : PseudoInst< 4117 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4118 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>; 4119 def ATOMIC_LOAD_SUB_I8 : PseudoInst< 4120 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4121 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>; 4122 def ATOMIC_LOAD_AND_I8 : PseudoInst< 4123 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4124 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>; 4125 def ATOMIC_LOAD_OR_I8 : PseudoInst< 4126 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4127 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>; 4128 def ATOMIC_LOAD_XOR_I8 : PseudoInst< 4129 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4130 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>; 4131 def ATOMIC_LOAD_NAND_I8 : PseudoInst< 4132 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4133 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>; 4134 def ATOMIC_LOAD_MIN_I8 : PseudoInst< 4135 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4136 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>; 4137 def ATOMIC_LOAD_MAX_I8 : PseudoInst< 4138 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4139 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>; 4140 def ATOMIC_LOAD_UMIN_I8 : PseudoInst< 4141 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4142 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>; 4143 def ATOMIC_LOAD_UMAX_I8 : PseudoInst< 4144 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4145 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>; 4146 def ATOMIC_LOAD_ADD_I16 : PseudoInst< 4147 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4148 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>; 4149 def ATOMIC_LOAD_SUB_I16 : PseudoInst< 4150 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4151 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>; 4152 def ATOMIC_LOAD_AND_I16 : PseudoInst< 4153 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4154 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>; 4155 def ATOMIC_LOAD_OR_I16 : PseudoInst< 4156 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4157 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>; 4158 def ATOMIC_LOAD_XOR_I16 : PseudoInst< 4159 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4160 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>; 4161 def ATOMIC_LOAD_NAND_I16 : PseudoInst< 4162 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4163 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>; 4164 def ATOMIC_LOAD_MIN_I16 : PseudoInst< 4165 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4166 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>; 4167 def ATOMIC_LOAD_MAX_I16 : PseudoInst< 4168 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4169 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>; 4170 def ATOMIC_LOAD_UMIN_I16 : PseudoInst< 4171 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4172 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>; 4173 def ATOMIC_LOAD_UMAX_I16 : PseudoInst< 4174 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4175 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>; 4176 def ATOMIC_LOAD_ADD_I32 : PseudoInst< 4177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4178 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>; 4179 def ATOMIC_LOAD_SUB_I32 : PseudoInst< 4180 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4181 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>; 4182 def ATOMIC_LOAD_AND_I32 : PseudoInst< 4183 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4184 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>; 4185 def ATOMIC_LOAD_OR_I32 : PseudoInst< 4186 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4187 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>; 4188 def ATOMIC_LOAD_XOR_I32 : PseudoInst< 4189 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4190 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>; 4191 def ATOMIC_LOAD_NAND_I32 : PseudoInst< 4192 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 4193 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>; 4194 def ATOMIC_LOAD_MIN_I32 : PseudoInst< 4195 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4196 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>; 4197 def ATOMIC_LOAD_MAX_I32 : PseudoInst< 4198 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4199 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>; 4200 def ATOMIC_LOAD_UMIN_I32 : PseudoInst< 4201 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4202 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>; 4203 def ATOMIC_LOAD_UMAX_I32 : PseudoInst< 4204 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary, 4205 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>; 4206 4207 def ATOMIC_SWAP_I8 : PseudoInst< 4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 4209 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>; 4210 def ATOMIC_SWAP_I16 : PseudoInst< 4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 4212 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>; 4213 def ATOMIC_SWAP_I32 : PseudoInst< 4214 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 4215 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>; 4216 4217 def ATOMIC_CMP_SWAP_I8 : PseudoInst< 4218 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 4219 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>; 4220 def ATOMIC_CMP_SWAP_I16 : PseudoInst< 4221 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 4222 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>; 4223 def ATOMIC_CMP_SWAP_I32 : PseudoInst< 4224 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 4225 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>; 4226} 4227} 4228 4229let mayLoad = 1 in { 4230def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4231 NoItinerary, 4232 "ldrexb", "\t$Rt, $addr", []>; 4233def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4234 NoItinerary, "ldrexh", "\t$Rt, $addr", []>; 4235def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4236 NoItinerary, "ldrex", "\t$Rt, $addr", []>; 4237let hasExtraDefRegAllocReq = 1 in 4238def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr), 4239 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> { 4240 let DecoderMethod = "DecodeDoubleRegLoad"; 4241} 4242} 4243 4244let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 4245def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4246 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>; 4247def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4248 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>; 4249def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 4250 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>; 4251let hasExtraSrcRegAllocReq = 1 in 4252def STREXD : AIstrex<0b01, (outs GPR:$Rd), 4253 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr), 4254 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> { 4255 let DecoderMethod = "DecodeDoubleRegStore"; 4256} 4257} 4258 4259 4260def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>, 4261 Requires<[IsARM, HasV7]> { 4262 let Inst{31-0} = 0b11110101011111111111000000011111; 4263} 4264 4265// SWP/SWPB are deprecated in V6/V7. 4266let mayLoad = 1, mayStore = 1 in { 4267def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr), 4268 "swp", []>; 4269def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr), 4270 "swpb", []>; 4271} 4272 4273//===----------------------------------------------------------------------===// 4274// Coprocessor Instructions. 4275// 4276 4277def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4278 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4279 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4280 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4281 imm:$CRm, imm:$opc2)]> { 4282 bits<4> opc1; 4283 bits<4> CRn; 4284 bits<4> CRd; 4285 bits<4> cop; 4286 bits<3> opc2; 4287 bits<4> CRm; 4288 4289 let Inst{3-0} = CRm; 4290 let Inst{4} = 0; 4291 let Inst{7-5} = opc2; 4292 let Inst{11-8} = cop; 4293 let Inst{15-12} = CRd; 4294 let Inst{19-16} = CRn; 4295 let Inst{23-20} = opc1; 4296} 4297 4298def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4299 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4300 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4301 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4302 imm:$CRm, imm:$opc2)]> { 4303 let Inst{31-28} = 0b1111; 4304 bits<4> opc1; 4305 bits<4> CRn; 4306 bits<4> CRd; 4307 bits<4> cop; 4308 bits<3> opc2; 4309 bits<4> CRm; 4310 4311 let Inst{3-0} = CRm; 4312 let Inst{4} = 0; 4313 let Inst{7-5} = opc2; 4314 let Inst{11-8} = cop; 4315 let Inst{15-12} = CRd; 4316 let Inst{19-16} = CRn; 4317 let Inst{23-20} = opc1; 4318} 4319 4320class ACI<dag oops, dag iops, string opc, string asm, 4321 IndexMode im = IndexModeNone> 4322 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4323 opc, asm, "", []> { 4324 let Inst{27-25} = 0b110; 4325} 4326class ACInoP<dag oops, dag iops, string opc, string asm, 4327 IndexMode im = IndexModeNone> 4328 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 4329 opc, asm, "", []> { 4330 let Inst{31-28} = 0b1111; 4331 let Inst{27-25} = 0b110; 4332} 4333multiclass LdStCop<bit load, bit Dbit, string asm> { 4334 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4335 asm, "\t$cop, $CRd, $addr"> { 4336 bits<13> addr; 4337 bits<4> cop; 4338 bits<4> CRd; 4339 let Inst{24} = 1; // P = 1 4340 let Inst{23} = addr{8}; 4341 let Inst{22} = Dbit; 4342 let Inst{21} = 0; // W = 0 4343 let Inst{20} = load; 4344 let Inst{19-16} = addr{12-9}; 4345 let Inst{15-12} = CRd; 4346 let Inst{11-8} = cop; 4347 let Inst{7-0} = addr{7-0}; 4348 let DecoderMethod = "DecodeCopMemInstruction"; 4349 } 4350 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4351 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4352 bits<13> addr; 4353 bits<4> cop; 4354 bits<4> CRd; 4355 let Inst{24} = 1; // P = 1 4356 let Inst{23} = addr{8}; 4357 let Inst{22} = Dbit; 4358 let Inst{21} = 1; // W = 1 4359 let Inst{20} = load; 4360 let Inst{19-16} = addr{12-9}; 4361 let Inst{15-12} = CRd; 4362 let Inst{11-8} = cop; 4363 let Inst{7-0} = addr{7-0}; 4364 let DecoderMethod = "DecodeCopMemInstruction"; 4365 } 4366 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4367 postidx_imm8s4:$offset), 4368 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4369 bits<9> offset; 4370 bits<4> addr; 4371 bits<4> cop; 4372 bits<4> CRd; 4373 let Inst{24} = 0; // P = 0 4374 let Inst{23} = offset{8}; 4375 let Inst{22} = Dbit; 4376 let Inst{21} = 1; // W = 1 4377 let Inst{20} = load; 4378 let Inst{19-16} = addr; 4379 let Inst{15-12} = CRd; 4380 let Inst{11-8} = cop; 4381 let Inst{7-0} = offset{7-0}; 4382 let DecoderMethod = "DecodeCopMemInstruction"; 4383 } 4384 def _OPTION : ACI<(outs), 4385 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4386 coproc_option_imm:$option), 4387 asm, "\t$cop, $CRd, $addr, $option"> { 4388 bits<8> option; 4389 bits<4> addr; 4390 bits<4> cop; 4391 bits<4> CRd; 4392 let Inst{24} = 0; // P = 0 4393 let Inst{23} = 1; // U = 1 4394 let Inst{22} = Dbit; 4395 let Inst{21} = 0; // W = 0 4396 let Inst{20} = load; 4397 let Inst{19-16} = addr; 4398 let Inst{15-12} = CRd; 4399 let Inst{11-8} = cop; 4400 let Inst{7-0} = option; 4401 let DecoderMethod = "DecodeCopMemInstruction"; 4402 } 4403} 4404multiclass LdSt2Cop<bit load, bit Dbit, string asm> { 4405 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4406 asm, "\t$cop, $CRd, $addr"> { 4407 bits<13> addr; 4408 bits<4> cop; 4409 bits<4> CRd; 4410 let Inst{24} = 1; // P = 1 4411 let Inst{23} = addr{8}; 4412 let Inst{22} = Dbit; 4413 let Inst{21} = 0; // W = 0 4414 let Inst{20} = load; 4415 let Inst{19-16} = addr{12-9}; 4416 let Inst{15-12} = CRd; 4417 let Inst{11-8} = cop; 4418 let Inst{7-0} = addr{7-0}; 4419 let DecoderMethod = "DecodeCopMemInstruction"; 4420 } 4421 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 4422 asm, "\t$cop, $CRd, $addr!", IndexModePre> { 4423 bits<13> addr; 4424 bits<4> cop; 4425 bits<4> CRd; 4426 let Inst{24} = 1; // P = 1 4427 let Inst{23} = addr{8}; 4428 let Inst{22} = Dbit; 4429 let Inst{21} = 1; // W = 1 4430 let Inst{20} = load; 4431 let Inst{19-16} = addr{12-9}; 4432 let Inst{15-12} = CRd; 4433 let Inst{11-8} = cop; 4434 let Inst{7-0} = addr{7-0}; 4435 let DecoderMethod = "DecodeCopMemInstruction"; 4436 } 4437 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4438 postidx_imm8s4:$offset), 4439 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> { 4440 bits<9> offset; 4441 bits<4> addr; 4442 bits<4> cop; 4443 bits<4> CRd; 4444 let Inst{24} = 0; // P = 0 4445 let Inst{23} = offset{8}; 4446 let Inst{22} = Dbit; 4447 let Inst{21} = 1; // W = 1 4448 let Inst{20} = load; 4449 let Inst{19-16} = addr; 4450 let Inst{15-12} = CRd; 4451 let Inst{11-8} = cop; 4452 let Inst{7-0} = offset{7-0}; 4453 let DecoderMethod = "DecodeCopMemInstruction"; 4454 } 4455 def _OPTION : ACInoP<(outs), 4456 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 4457 coproc_option_imm:$option), 4458 asm, "\t$cop, $CRd, $addr, $option"> { 4459 bits<8> option; 4460 bits<4> addr; 4461 bits<4> cop; 4462 bits<4> CRd; 4463 let Inst{24} = 0; // P = 0 4464 let Inst{23} = 1; // U = 1 4465 let Inst{22} = Dbit; 4466 let Inst{21} = 0; // W = 0 4467 let Inst{20} = load; 4468 let Inst{19-16} = addr; 4469 let Inst{15-12} = CRd; 4470 let Inst{11-8} = cop; 4471 let Inst{7-0} = option; 4472 let DecoderMethod = "DecodeCopMemInstruction"; 4473 } 4474} 4475 4476defm LDC : LdStCop <1, 0, "ldc">; 4477defm LDCL : LdStCop <1, 1, "ldcl">; 4478defm STC : LdStCop <0, 0, "stc">; 4479defm STCL : LdStCop <0, 1, "stcl">; 4480defm LDC2 : LdSt2Cop<1, 0, "ldc2">; 4481defm LDC2L : LdSt2Cop<1, 1, "ldc2l">; 4482defm STC2 : LdSt2Cop<0, 0, "stc2">; 4483defm STC2L : LdSt2Cop<0, 1, "stc2l">; 4484 4485//===----------------------------------------------------------------------===// 4486// Move between coprocessor and ARM core register. 4487// 4488 4489class MovRCopro<string opc, bit direction, dag oops, dag iops, 4490 list<dag> pattern> 4491 : ABI<0b1110, oops, iops, NoItinerary, opc, 4492 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 4493 let Inst{20} = direction; 4494 let Inst{4} = 1; 4495 4496 bits<4> Rt; 4497 bits<4> cop; 4498 bits<3> opc1; 4499 bits<3> opc2; 4500 bits<4> CRm; 4501 bits<4> CRn; 4502 4503 let Inst{15-12} = Rt; 4504 let Inst{11-8} = cop; 4505 let Inst{23-21} = opc1; 4506 let Inst{7-5} = opc2; 4507 let Inst{3-0} = CRm; 4508 let Inst{19-16} = CRn; 4509} 4510 4511def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 4512 (outs), 4513 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4514 c_imm:$CRm, imm0_7:$opc2), 4515 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4516 imm:$CRm, imm:$opc2)]>; 4517def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4518 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4519 c_imm:$CRm, 0, pred:$p)>; 4520def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 4521 (outs GPR:$Rt), 4522 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4523 imm0_7:$opc2), []>; 4524def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4525 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4526 c_imm:$CRm, 0, pred:$p)>; 4527 4528def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4529 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4530 4531class MovRCopro2<string opc, bit direction, dag oops, dag iops, 4532 list<dag> pattern> 4533 : ABXI<0b1110, oops, iops, NoItinerary, 4534 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 4535 let Inst{31-28} = 0b1111; 4536 let Inst{20} = direction; 4537 let Inst{4} = 1; 4538 4539 bits<4> Rt; 4540 bits<4> cop; 4541 bits<3> opc1; 4542 bits<3> opc2; 4543 bits<4> CRm; 4544 bits<4> CRn; 4545 4546 let Inst{15-12} = Rt; 4547 let Inst{11-8} = cop; 4548 let Inst{23-21} = opc1; 4549 let Inst{7-5} = opc2; 4550 let Inst{3-0} = CRm; 4551 let Inst{19-16} = CRn; 4552} 4553 4554def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 4555 (outs), 4556 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4557 c_imm:$CRm, imm0_7:$opc2), 4558 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4559 imm:$CRm, imm:$opc2)]>; 4560def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm", 4561 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4562 c_imm:$CRm, 0)>; 4563def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 4564 (outs GPR:$Rt), 4565 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 4566 imm0_7:$opc2), []>; 4567def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm", 4568 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4569 c_imm:$CRm, 0)>; 4570 4571def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 4572 imm:$CRm, imm:$opc2), 4573 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4574 4575class MovRRCopro<string opc, bit direction, list<dag> pattern = []> 4576 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4577 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), 4578 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4579 let Inst{23-21} = 0b010; 4580 let Inst{20} = direction; 4581 4582 bits<4> Rt; 4583 bits<4> Rt2; 4584 bits<4> cop; 4585 bits<4> opc1; 4586 bits<4> CRm; 4587 4588 let Inst{15-12} = Rt; 4589 let Inst{19-16} = Rt2; 4590 let Inst{11-8} = cop; 4591 let Inst{7-4} = opc1; 4592 let Inst{3-0} = CRm; 4593} 4594 4595def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 4596 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, 4597 imm:$CRm)]>; 4598def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; 4599 4600class MovRRCopro2<string opc, bit direction, list<dag> pattern = []> 4601 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4602 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary, 4603 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { 4604 let Inst{31-28} = 0b1111; 4605 let Inst{23-21} = 0b010; 4606 let Inst{20} = direction; 4607 4608 bits<4> Rt; 4609 bits<4> Rt2; 4610 bits<4> cop; 4611 bits<4> opc1; 4612 bits<4> CRm; 4613 4614 let Inst{15-12} = Rt; 4615 let Inst{19-16} = Rt2; 4616 let Inst{11-8} = cop; 4617 let Inst{7-4} = opc1; 4618 let Inst{3-0} = CRm; 4619} 4620 4621def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 4622 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, 4623 imm:$CRm)]>; 4624def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; 4625 4626//===----------------------------------------------------------------------===// 4627// Move between special register and ARM core register 4628// 4629 4630// Move to ARM core register from Special Register 4631def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, 4632 "mrs", "\t$Rd, apsr", []> { 4633 bits<4> Rd; 4634 let Inst{23-16} = 0b00001111; 4635 let Inst{15-12} = Rd; 4636 let Inst{7-4} = 0b0000; 4637} 4638 4639def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>; 4640 4641def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, 4642 "mrs", "\t$Rd, spsr", []> { 4643 bits<4> Rd; 4644 let Inst{23-16} = 0b01001111; 4645 let Inst{15-12} = Rd; 4646 let Inst{7-4} = 0b0000; 4647} 4648 4649// Move from ARM core register to Special Register 4650// 4651// No need to have both system and application versions, the encodings are the 4652// same and the assembly parser has no way to distinguish between them. The mask 4653// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 4654// the mask with the fields to be accessed in the special register. 4655def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 4656 "msr", "\t$mask, $Rn", []> { 4657 bits<5> mask; 4658 bits<4> Rn; 4659 4660 let Inst{23} = 0; 4661 let Inst{22} = mask{4}; // R bit 4662 let Inst{21-20} = 0b10; 4663 let Inst{19-16} = mask{3-0}; 4664 let Inst{15-12} = 0b1111; 4665 let Inst{11-4} = 0b00000000; 4666 let Inst{3-0} = Rn; 4667} 4668 4669def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, 4670 "msr", "\t$mask, $a", []> { 4671 bits<5> mask; 4672 bits<12> a; 4673 4674 let Inst{23} = 0; 4675 let Inst{22} = mask{4}; // R bit 4676 let Inst{21-20} = 0b10; 4677 let Inst{19-16} = mask{3-0}; 4678 let Inst{15-12} = 0b1111; 4679 let Inst{11-0} = a; 4680} 4681 4682//===----------------------------------------------------------------------===// 4683// TLS Instructions 4684// 4685 4686// __aeabi_read_tp preserves the registers r1-r3. 4687// This is a pseudo inst so that we can get the encoding right, 4688// complete with fixup for the aeabi_read_tp function. 4689let isCall = 1, 4690 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 4691 def TPsoft : PseudoInst<(outs), (ins), IIC_Br, 4692 [(set R0, ARMthread_pointer)]>; 4693} 4694 4695//===----------------------------------------------------------------------===// 4696// SJLJ Exception handling intrinsics 4697// eh_sjlj_setjmp() is an instruction sequence to store the return 4698// address and save #0 in R0 for the non-longjmp case. 4699// Since by its nature we may be coming from some other function to get 4700// here, and we're using the stack frame for the containing function to 4701// save/restore registers, we can't keep anything live in regs across 4702// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 4703// when we get here from a longjmp(). We force everything out of registers 4704// except for our own input by listing the relevant registers in Defs. By 4705// doing so, we also cause the prologue/epilogue code to actively preserve 4706// all of the callee-saved resgisters, which is exactly what we want. 4707// A constant value is passed in $val, and we use the location as a scratch. 4708// 4709// These are pseudo-instructions and are lowered to individual MC-insts, so 4710// no encoding information is necessary. 4711let Defs = 4712 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 4713 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 4714 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 4715 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 4716 NoItinerary, 4717 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 4718 Requires<[IsARM, HasVFP2]>; 4719} 4720 4721let Defs = 4722 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 4723 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 4724 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 4725 NoItinerary, 4726 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 4727 Requires<[IsARM, NoVFP]>; 4728} 4729 4730// FIXME: Non-IOS version(s) 4731let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 4732 Defs = [ R7, LR, SP ] in { 4733def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 4734 NoItinerary, 4735 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 4736 Requires<[IsARM, IsIOS]>; 4737} 4738 4739// eh.sjlj.dispatchsetup pseudo-instructions. 4740// These pseudos are used for both ARM and Thumb2. Any differences are 4741// handled when the pseudo is expanded (which happens before any passes 4742// that need the instruction size). 4743let Defs = 4744 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 4745 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 4746 isBarrier = 1 in 4747def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 4748 4749let Defs = 4750 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 4751 isBarrier = 1 in 4752def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>; 4753 4754 4755//===----------------------------------------------------------------------===// 4756// Non-Instruction Patterns 4757// 4758 4759// ARMv4 indirect branch using (MOVr PC, dst) 4760let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 4761 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 4762 4, IIC_Br, [(brind GPR:$dst)], 4763 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 4764 Requires<[IsARM, NoV4T]>; 4765 4766// Large immediate handling. 4767 4768// 32-bit immediate using two piece so_imms or movw + movt. 4769// This is a single pseudo instruction, the benefit is that it can be remat'd 4770// as a single unit instead of having to handle reg inputs. 4771// FIXME: Remove this when we can do generalized remat. 4772let isReMaterializable = 1, isMoveImm = 1 in 4773def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 4774 [(set GPR:$dst, (arm_i32imm:$src))]>, 4775 Requires<[IsARM]>; 4776 4777// Pseudo instruction that combines movw + movt + add pc (if PIC). 4778// It also makes it possible to rematerialize the instructions. 4779// FIXME: Remove this when we can do generalized remat and when machine licm 4780// can properly the instructions. 4781let isReMaterializable = 1 in { 4782def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 4783 IIC_iMOVix2addpc, 4784 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 4785 Requires<[IsARM, UseMovt]>; 4786 4787def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 4788 IIC_iMOVix2, 4789 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>, 4790 Requires<[IsARM, UseMovt]>; 4791 4792let AddedComplexity = 10 in 4793def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 4794 IIC_iMOVix2ld, 4795 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 4796 Requires<[IsARM, UseMovt]>; 4797} // isReMaterializable 4798 4799// ConstantPool, GlobalAddress, and JumpTable 4800def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>, 4801 Requires<[IsARM, DontUseMovt]>; 4802def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 4803def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 4804 Requires<[IsARM, UseMovt]>; 4805def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 4806 (LEApcrelJT tjumptable:$dst, imm:$id)>; 4807 4808// TODO: add,sub,and, 3-instr forms? 4809 4810// Tail calls. These patterns also apply to Thumb mode. 4811def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 4812def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 4813def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 4814 4815// Direct calls 4816def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 4817def : ARMPat<(ARMcall_nolink texternalsym:$func), 4818 (BMOVPCB_CALL texternalsym:$func)>; 4819 4820// zextload i1 -> zextload i8 4821def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 4822def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 4823 4824// extload -> zextload 4825def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 4826def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 4827def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 4828def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 4829 4830def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 4831 4832def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 4833def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 4834 4835// smul* and smla* 4836def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4837 (sra (shl GPR:$b, (i32 16)), (i32 16))), 4838 (SMULBB GPR:$a, GPR:$b)>; 4839def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 4840 (SMULBB GPR:$a, GPR:$b)>; 4841def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4842 (sra GPR:$b, (i32 16))), 4843 (SMULBT GPR:$a, GPR:$b)>; 4844def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 4845 (SMULBT GPR:$a, GPR:$b)>; 4846def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 4847 (sra (shl GPR:$b, (i32 16)), (i32 16))), 4848 (SMULTB GPR:$a, GPR:$b)>; 4849def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 4850 (SMULTB GPR:$a, GPR:$b)>; 4851def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 4852 (i32 16)), 4853 (SMULWB GPR:$a, GPR:$b)>; 4854def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 4855 (SMULWB GPR:$a, GPR:$b)>; 4856 4857def : ARMV5TEPat<(add GPR:$acc, 4858 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4859 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 4860 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 4861def : ARMV5TEPat<(add GPR:$acc, 4862 (mul sext_16_node:$a, sext_16_node:$b)), 4863 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 4864def : ARMV5TEPat<(add GPR:$acc, 4865 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 4866 (sra GPR:$b, (i32 16)))), 4867 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 4868def : ARMV5TEPat<(add GPR:$acc, 4869 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 4870 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 4871def : ARMV5TEPat<(add GPR:$acc, 4872 (mul (sra GPR:$a, (i32 16)), 4873 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 4874 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 4875def : ARMV5TEPat<(add GPR:$acc, 4876 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 4877 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 4878def : ARMV5TEPat<(add GPR:$acc, 4879 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 4880 (i32 16))), 4881 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 4882def : ARMV5TEPat<(add GPR:$acc, 4883 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 4884 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 4885 4886 4887// Pre-v7 uses MCR for synchronization barriers. 4888def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 4889 Requires<[IsARM, HasV6]>; 4890 4891// SXT/UXT with no rotate 4892let AddedComplexity = 16 in { 4893def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 4894def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 4895def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 4896def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 4897 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 4898def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 4899 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 4900} 4901 4902def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 4903def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 4904 4905def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 4906 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 4907def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 4908 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 4909 4910// Atomic load/store patterns 4911def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 4912 (LDRBrs ldst_so_reg:$src)>; 4913def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 4914 (LDRBi12 addrmode_imm12:$src)>; 4915def : ARMPat<(atomic_load_16 addrmode3:$src), 4916 (LDRH addrmode3:$src)>; 4917def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 4918 (LDRrs ldst_so_reg:$src)>; 4919def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 4920 (LDRi12 addrmode_imm12:$src)>; 4921def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 4922 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 4923def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 4924 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 4925def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 4926 (STRH GPR:$val, addrmode3:$ptr)>; 4927def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 4928 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 4929def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 4930 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 4931 4932 4933//===----------------------------------------------------------------------===// 4934// Thumb Support 4935// 4936 4937include "ARMInstrThumb.td" 4938 4939//===----------------------------------------------------------------------===// 4940// Thumb2 Support 4941// 4942 4943include "ARMInstrThumb2.td" 4944 4945//===----------------------------------------------------------------------===// 4946// Floating Point Support 4947// 4948 4949include "ARMInstrVFP.td" 4950 4951//===----------------------------------------------------------------------===// 4952// Advanced SIMD (NEON) Support 4953// 4954 4955include "ARMInstrNEON.td" 4956 4957//===----------------------------------------------------------------------===// 4958// Assembler aliases 4959// 4960 4961// Memory barriers 4962def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; 4963def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; 4964def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; 4965 4966// System instructions 4967def : MnemonicAlias<"swi", "svc">; 4968 4969// Load / Store Multiple 4970def : MnemonicAlias<"ldmfd", "ldm">; 4971def : MnemonicAlias<"ldmia", "ldm">; 4972def : MnemonicAlias<"ldmea", "ldmdb">; 4973def : MnemonicAlias<"stmfd", "stmdb">; 4974def : MnemonicAlias<"stmia", "stm">; 4975def : MnemonicAlias<"stmea", "stm">; 4976 4977// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 4978// shift amount is zero (i.e., unspecified). 4979def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 4980 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 4981 Requires<[IsARM, HasV6]>; 4982def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 4983 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>, 4984 Requires<[IsARM, HasV6]>; 4985 4986// PUSH/POP aliases for STM/LDM 4987def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 4988def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4989 4990// SSAT/USAT optional shift operand. 4991def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 4992 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 4993def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 4994 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 4995 4996 4997// Extend instruction optional rotate operand. 4998def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 4999 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5000def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5001 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5002def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5003 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5004def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5005 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5006def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5007 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5008def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5009 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5010 5011def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5012 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5013def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5014 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5015def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5016 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5017def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5018 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5019def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 5020 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5021def : ARMInstAlias<"uxth${p} $Rd, $Rm", 5022 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5023 5024 5025// RFE aliases 5026def : MnemonicAlias<"rfefa", "rfeda">; 5027def : MnemonicAlias<"rfeea", "rfedb">; 5028def : MnemonicAlias<"rfefd", "rfeia">; 5029def : MnemonicAlias<"rfeed", "rfeib">; 5030def : MnemonicAlias<"rfe", "rfeia">; 5031 5032// SRS aliases 5033def : MnemonicAlias<"srsfa", "srsda">; 5034def : MnemonicAlias<"srsea", "srsdb">; 5035def : MnemonicAlias<"srsfd", "srsia">; 5036def : MnemonicAlias<"srsed", "srsib">; 5037def : MnemonicAlias<"srs", "srsia">; 5038 5039// QSAX == QSUBADDX 5040def : MnemonicAlias<"qsubaddx", "qsax">; 5041// SASX == SADDSUBX 5042def : MnemonicAlias<"saddsubx", "sasx">; 5043// SHASX == SHADDSUBX 5044def : MnemonicAlias<"shaddsubx", "shasx">; 5045// SHSAX == SHSUBADDX 5046def : MnemonicAlias<"shsubaddx", "shsax">; 5047// SSAX == SSUBADDX 5048def : MnemonicAlias<"ssubaddx", "ssax">; 5049// UASX == UADDSUBX 5050def : MnemonicAlias<"uaddsubx", "uasx">; 5051// UHASX == UHADDSUBX 5052def : MnemonicAlias<"uhaddsubx", "uhasx">; 5053// UHSAX == UHSUBADDX 5054def : MnemonicAlias<"uhsubaddx", "uhsax">; 5055// UQASX == UQADDSUBX 5056def : MnemonicAlias<"uqaddsubx", "uqasx">; 5057// UQSAX == UQSUBADDX 5058def : MnemonicAlias<"uqsubaddx", "uqsax">; 5059// USAX == USUBADDX 5060def : MnemonicAlias<"usubaddx", "usax">; 5061 5062// "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like 5063// for isel. 5064def : ARMInstAlias<"mov${s}${p} $Rd, $imm", 5065 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5066def : ARMInstAlias<"mvn${s}${p} $Rd, $imm", 5067 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; 5068// Same for AND <--> BIC 5069def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm", 5070 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5071 pred:$p, cc_out:$s)>; 5072def : ARMInstAlias<"bic${s}${p} $Rdn, $imm", 5073 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5074 pred:$p, cc_out:$s)>; 5075def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm", 5076 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm, 5077 pred:$p, cc_out:$s)>; 5078def : ARMInstAlias<"and${s}${p} $Rdn, $imm", 5079 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm, 5080 pred:$p, cc_out:$s)>; 5081 5082// Likewise, "add Rd, so_imm_neg" -> sub 5083def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm", 5084 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5085def : ARMInstAlias<"add${s}${p} $Rd, $imm", 5086 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>; 5087// Same for CMP <--> CMN via so_imm_neg 5088def : ARMInstAlias<"cmp${p} $Rd, $imm", 5089 (CMNzri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5090def : ARMInstAlias<"cmn${p} $Rd, $imm", 5091 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>; 5092 5093// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 5094// LSR, ROR, and RRX instructions. 5095// FIXME: We need C++ parser hooks to map the alias to the MOV 5096// encoding. It seems we should be able to do that sort of thing 5097// in tblgen, but it could get ugly. 5098def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 5099 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5100 cc_out:$s)>; 5101def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 5102 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 5103 cc_out:$s)>; 5104def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 5105 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5106 cc_out:$s)>; 5107def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 5108 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 5109 cc_out:$s)>; 5110def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 5111 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>; 5112def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 5113 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5114 cc_out:$s)>; 5115def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 5116 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5117 cc_out:$s)>; 5118def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 5119 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5120 cc_out:$s)>; 5121def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 5122 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5123 cc_out:$s)>; 5124// shifter instructions also support a two-operand form. 5125def : ARMInstAlias<"asr${s}${p} $Rm, $imm", 5126 (ASRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>; 5127def : ARMInstAlias<"lsr${s}${p} $Rm, $imm", 5128 (LSRi GPR:$Rm, GPR:$Rm, imm0_32:$imm, pred:$p, cc_out:$s)>; 5129def : ARMInstAlias<"lsl${s}${p} $Rm, $imm", 5130 (LSLi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>; 5131def : ARMInstAlias<"ror${s}${p} $Rm, $imm", 5132 (RORi GPR:$Rm, GPR:$Rm, imm0_31:$imm, pred:$p, cc_out:$s)>; 5133def : ARMInstAlias<"asr${s}${p} $Rn, $Rm", 5134 (ASRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5135 cc_out:$s)>; 5136def : ARMInstAlias<"lsr${s}${p} $Rn, $Rm", 5137 (LSRr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5138 cc_out:$s)>; 5139def : ARMInstAlias<"lsl${s}${p} $Rn, $Rm", 5140 (LSLr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5141 cc_out:$s)>; 5142def : ARMInstAlias<"ror${s}${p} $Rn, $Rm", 5143 (RORr GPRnopc:$Rn, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 5144 cc_out:$s)>; 5145 5146 5147// 'mul' instruction can be specified with only two operands. 5148def : ARMInstAlias<"mul${s}${p} $Rn, $Rm", 5149 (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>; 5150 5151// "neg" is and alias for "rsb rd, rn, #0" 5152def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 5153 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 5154 5155// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 5156def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 5157 Requires<[IsARM, NoV6]>; 5158 5159// UMULL/SMULL are available on all arches, but the instruction definitions 5160// need difference constraints pre-v6. Use these aliases for the assembly 5161// parsing on pre-v6. 5162def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5163 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5164 Requires<[IsARM, NoV6]>; 5165def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 5166 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 5167 Requires<[IsARM, NoV6]>; 5168 5169// 'it' blocks in ARM mode just validate the predicates. The IT itself 5170// is discarded. 5171def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>; 5172