ARMInstrInfo.td revision 207618
1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21 22def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 23 24def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 25 26def SDT_ARMCMov : SDTypeProfile<1, 3, 27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 28 SDTCisVT<3, i32>]>; 29 30def SDT_ARMBrcond : SDTypeProfile<0, 2, 31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 32 33def SDT_ARMBrJT : SDTypeProfile<0, 3, 34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 35 SDTCisVT<2, i32>]>; 36 37def SDT_ARMBr2JT : SDTypeProfile<0, 4, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 40 41def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 42 43def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 45 46def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 47def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisInt<2>]>; 49 50def SDT_ARMMEMBARRIERV7 : SDTypeProfile<0, 0, []>; 51def SDT_ARMSYNCBARRIERV7 : SDTypeProfile<0, 0, []>; 52def SDT_ARMMEMBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 53def SDT_ARMSYNCBARRIERV6 : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 54 55// Node definitions. 56def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 57def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 58 59def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 60 [SDNPHasChain, SDNPOutFlag]>; 61def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 62 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 63 64def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 65 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 66 SDNPVariadic]>; 67def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 68 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 69 SDNPVariadic]>; 70def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 71 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, 72 SDNPVariadic]>; 73 74def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 75 [SDNPHasChain, SDNPOptInFlag]>; 76 77def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 78 [SDNPInFlag]>; 79def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, 80 [SDNPInFlag]>; 81 82def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 83 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; 84 85def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 86 [SDNPHasChain]>; 87def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 88 [SDNPHasChain]>; 89 90def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 91 [SDNPOutFlag]>; 92 93def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 94 [SDNPOutFlag,SDNPCommutative]>; 95 96def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 97 98def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 99def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 100def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; 101 102def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 103def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>; 104 105def ARMMemBarrierV7 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV7, 106 [SDNPHasChain]>; 107def ARMSyncBarrierV7 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV7, 108 [SDNPHasChain]>; 109def ARMMemBarrierV6 : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIERV6, 110 [SDNPHasChain]>; 111def ARMSyncBarrierV6 : SDNode<"ARMISD::SYNCBARRIER", SDT_ARMMEMBARRIERV6, 112 [SDNPHasChain]>; 113 114def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>; 115 116//===----------------------------------------------------------------------===// 117// ARM Instruction Predicate Definitions. 118// 119def HasV4T : Predicate<"Subtarget->hasV4TOps()">; 120def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 121def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 122def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; 123def HasV6 : Predicate<"Subtarget->hasV6Ops()">; 124def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">; 125def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 126def HasV7 : Predicate<"Subtarget->hasV7Ops()">; 127def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 128def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; 129def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; 130def HasNEON : Predicate<"Subtarget->hasNEON()">; 131def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 132def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 133def IsThumb : Predicate<"Subtarget->isThumb()">; 134def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 135def IsThumb2 : Predicate<"Subtarget->isThumb2()">; 136def IsARM : Predicate<"!Subtarget->isThumb()">; 137def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; 138def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; 139 140// FIXME: Eventually this will be just "hasV6T2Ops". 141def UseMovt : Predicate<"Subtarget->useMovt()">; 142def DontUseMovt : Predicate<"!Subtarget->useMovt()">; 143 144def UseVMLx : Predicate<"Subtarget->useVMLx()">; 145 146//===----------------------------------------------------------------------===// 147// ARM Flag Definitions. 148 149class RegConstraint<string C> { 150 string Constraints = C; 151} 152 153//===----------------------------------------------------------------------===// 154// ARM specific transformation functions and pattern fragments. 155// 156 157// so_imm_neg_XFORM - Return a so_imm value packed into the format described for 158// so_imm_neg def below. 159def so_imm_neg_XFORM : SDNodeXForm<imm, [{ 160 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 161}]>; 162 163// so_imm_not_XFORM - Return a so_imm value packed into the format described for 164// so_imm_not def below. 165def so_imm_not_XFORM : SDNodeXForm<imm, [{ 166 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); 167}]>; 168 169// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. 170def rot_imm : PatLeaf<(i32 imm), [{ 171 int32_t v = (int32_t)N->getZExtValue(); 172 return v == 8 || v == 16 || v == 24; 173}]>; 174 175/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. 176def imm1_15 : PatLeaf<(i32 imm), [{ 177 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16; 178}]>; 179 180/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 181def imm16_31 : PatLeaf<(i32 imm), [{ 182 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32; 183}]>; 184 185def so_imm_neg : 186 PatLeaf<(imm), [{ 187 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1; 188 }], so_imm_neg_XFORM>; 189 190def so_imm_not : 191 PatLeaf<(imm), [{ 192 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1; 193 }], so_imm_not_XFORM>; 194 195// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 196def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 197 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 198}]>; 199 200/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 201/// e.g., 0xf000ffff 202def bf_inv_mask_imm : Operand<i32>, 203 PatLeaf<(imm), [{ 204 uint32_t v = (uint32_t)N->getZExtValue(); 205 if (v == 0xffffffff) 206 return 0; 207 // there can be 1's on either or both "outsides", all the "inside" 208 // bits must be 0's 209 unsigned int lsb = 0, msb = 31; 210 while (v & (1 << msb)) --msb; 211 while (v & (1 << lsb)) ++lsb; 212 for (unsigned int i = lsb; i <= msb; ++i) { 213 if (v & (1 << i)) 214 return 0; 215 } 216 return 1; 217}] > { 218 let PrintMethod = "printBitfieldInvMaskImmOperand"; 219} 220 221/// Split a 32-bit immediate into two 16 bit parts. 222def lo16 : SDNodeXForm<imm, [{ 223 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff, 224 MVT::i32); 225}]>; 226 227def hi16 : SDNodeXForm<imm, [{ 228 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 229}]>; 230 231def lo16AllZero : PatLeaf<(i32 imm), [{ 232 // Returns true if all low 16-bits are 0. 233 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 234}], hi16>; 235 236/// imm0_65535 predicate - True if the 32-bit immediate is in the range 237/// [0.65535]. 238def imm0_65535 : PatLeaf<(i32 imm), [{ 239 return (uint32_t)N->getZExtValue() < 65536; 240}]>; 241 242class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 243class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 244 245/// adde and sube predicates - True based on whether the carry flag output 246/// will be needed or not. 247def adde_dead_carry : 248 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), 249 [{return !N->hasAnyUseOfValue(1);}]>; 250def sube_dead_carry : 251 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), 252 [{return !N->hasAnyUseOfValue(1);}]>; 253def adde_live_carry : 254 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS), 255 [{return N->hasAnyUseOfValue(1);}]>; 256def sube_live_carry : 257 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS), 258 [{return N->hasAnyUseOfValue(1);}]>; 259 260//===----------------------------------------------------------------------===// 261// Operand Definitions. 262// 263 264// Branch target. 265def brtarget : Operand<OtherVT>; 266 267// A list of registers separated by comma. Used by load/store multiple. 268def reglist : Operand<i32> { 269 let PrintMethod = "printRegisterList"; 270} 271 272// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 273def cpinst_operand : Operand<i32> { 274 let PrintMethod = "printCPInstOperand"; 275} 276 277def jtblock_operand : Operand<i32> { 278 let PrintMethod = "printJTBlockOperand"; 279} 280def jt2block_operand : Operand<i32> { 281 let PrintMethod = "printJT2BlockOperand"; 282} 283 284// Local PC labels. 285def pclabel : Operand<i32> { 286 let PrintMethod = "printPCLabel"; 287} 288 289// shifter_operand operands: so_reg and so_imm. 290def so_reg : Operand<i32>, // reg reg imm 291 ComplexPattern<i32, 3, "SelectShifterOperandReg", 292 [shl,srl,sra,rotr]> { 293 let PrintMethod = "printSORegOperand"; 294 let MIOperandInfo = (ops GPR, GPR, i32imm); 295} 296 297// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 298// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are 299// represented in the imm field in the same 12-bit form that they are encoded 300// into so_imm instructions: the 8-bit immediate is the least significant bits 301// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. 302def so_imm : Operand<i32>, 303 PatLeaf<(imm), [{ 304 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; 305 }]> { 306 let PrintMethod = "printSOImmOperand"; 307} 308 309// Break so_imm's up into two pieces. This handles immediates with up to 16 310// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 311// get the first/second pieces. 312def so_imm2part : Operand<i32>, 313 PatLeaf<(imm), [{ 314 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 315 }]> { 316 let PrintMethod = "printSOImm2PartOperand"; 317} 318 319def so_imm2part_1 : SDNodeXForm<imm, [{ 320 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue()); 321 return CurDAG->getTargetConstant(V, MVT::i32); 322}]>; 323 324def so_imm2part_2 : SDNodeXForm<imm, [{ 325 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue()); 326 return CurDAG->getTargetConstant(V, MVT::i32); 327}]>; 328 329def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{ 330 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue()); 331 }]> { 332 let PrintMethod = "printSOImm2PartOperand"; 333} 334 335def so_neg_imm2part_1 : SDNodeXForm<imm, [{ 336 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue()); 337 return CurDAG->getTargetConstant(V, MVT::i32); 338}]>; 339 340def so_neg_imm2part_2 : SDNodeXForm<imm, [{ 341 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue()); 342 return CurDAG->getTargetConstant(V, MVT::i32); 343}]>; 344 345/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 346def imm0_31 : Operand<i32>, PatLeaf<(imm), [{ 347 return (int32_t)N->getZExtValue() < 32; 348}]>; 349 350// Define ARM specific addressing modes. 351 352// addrmode2 := reg +/- reg shop imm 353// addrmode2 := reg +/- imm12 354// 355def addrmode2 : Operand<i32>, 356 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 357 let PrintMethod = "printAddrMode2Operand"; 358 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 359} 360 361def am2offset : Operand<i32>, 362 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> { 363 let PrintMethod = "printAddrMode2OffsetOperand"; 364 let MIOperandInfo = (ops GPR, i32imm); 365} 366 367// addrmode3 := reg +/- reg 368// addrmode3 := reg +/- imm8 369// 370def addrmode3 : Operand<i32>, 371 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 372 let PrintMethod = "printAddrMode3Operand"; 373 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 374} 375 376def am3offset : Operand<i32>, 377 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> { 378 let PrintMethod = "printAddrMode3OffsetOperand"; 379 let MIOperandInfo = (ops GPR, i32imm); 380} 381 382// addrmode4 := reg, <mode|W> 383// 384def addrmode4 : Operand<i32>, 385 ComplexPattern<i32, 2, "SelectAddrMode4", []> { 386 let PrintMethod = "printAddrMode4Operand"; 387 let MIOperandInfo = (ops GPR:$addr, i32imm); 388} 389 390// addrmode5 := reg +/- imm8*4 391// 392def addrmode5 : Operand<i32>, 393 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 394 let PrintMethod = "printAddrMode5Operand"; 395 let MIOperandInfo = (ops GPR:$base, i32imm); 396} 397 398// addrmode6 := reg with optional writeback 399// 400def addrmode6 : Operand<i32>, 401 ComplexPattern<i32, 2, "SelectAddrMode6", []> { 402 let PrintMethod = "printAddrMode6Operand"; 403 let MIOperandInfo = (ops GPR:$addr, i32imm); 404} 405 406def am6offset : Operand<i32> { 407 let PrintMethod = "printAddrMode6OffsetOperand"; 408 let MIOperandInfo = (ops GPR); 409} 410 411// addrmodepc := pc + reg 412// 413def addrmodepc : Operand<i32>, 414 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 415 let PrintMethod = "printAddrModePCOperand"; 416 let MIOperandInfo = (ops GPR, i32imm); 417} 418 419def nohash_imm : Operand<i32> { 420 let PrintMethod = "printNoHashImmediate"; 421} 422 423//===----------------------------------------------------------------------===// 424 425include "ARMInstrFormats.td" 426 427//===----------------------------------------------------------------------===// 428// Multiclass helpers... 429// 430 431/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 432/// binop that produces a value. 433multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode, 434 bit Commutable = 0> { 435 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 436 IIC_iALUi, opc, "\t$dst, $a, $b", 437 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> { 438 let Inst{25} = 1; 439 } 440 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, 441 IIC_iALUr, opc, "\t$dst, $a, $b", 442 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> { 443 let Inst{11-4} = 0b00000000; 444 let Inst{25} = 0; 445 let isCommutable = Commutable; 446 } 447 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 448 IIC_iALUsr, opc, "\t$dst, $a, $b", 449 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> { 450 let Inst{25} = 0; 451 } 452} 453 454/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the 455/// instruction modifies the CPSR register. 456let Defs = [CPSR] in { 457multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode, 458 bit Commutable = 0> { 459 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 460 IIC_iALUi, opc, "\t$dst, $a, $b", 461 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> { 462 let Inst{20} = 1; 463 let Inst{25} = 1; 464 } 465 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, 466 IIC_iALUr, opc, "\t$dst, $a, $b", 467 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> { 468 let isCommutable = Commutable; 469 let Inst{11-4} = 0b00000000; 470 let Inst{20} = 1; 471 let Inst{25} = 0; 472 } 473 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 474 IIC_iALUsr, opc, "\t$dst, $a, $b", 475 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> { 476 let Inst{20} = 1; 477 let Inst{25} = 0; 478 } 479} 480} 481 482/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 483/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 484/// a explicit result, only implicitly set CPSR. 485let Defs = [CPSR] in { 486multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode, 487 bit Commutable = 0> { 488 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi, 489 opc, "\t$a, $b", 490 [(opnode GPR:$a, so_imm:$b)]> { 491 let Inst{20} = 1; 492 let Inst{25} = 1; 493 } 494 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr, 495 opc, "\t$a, $b", 496 [(opnode GPR:$a, GPR:$b)]> { 497 let Inst{11-4} = 0b00000000; 498 let Inst{20} = 1; 499 let Inst{25} = 0; 500 let isCommutable = Commutable; 501 } 502 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr, 503 opc, "\t$a, $b", 504 [(opnode GPR:$a, so_reg:$b)]> { 505 let Inst{20} = 1; 506 let Inst{25} = 0; 507 } 508} 509} 510 511/// AI_unary_rrot - A unary operation with two forms: one whose operand is a 512/// register and one whose operand is a register rotated by 8/16/24. 513/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 514multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> { 515 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src), 516 IIC_iUNAr, opc, "\t$dst, $src", 517 [(set GPR:$dst, (opnode GPR:$src))]>, 518 Requires<[IsARM, HasV6]> { 519 let Inst{11-10} = 0b00; 520 let Inst{19-16} = 0b1111; 521 } 522 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot), 523 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot", 524 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>, 525 Requires<[IsARM, HasV6]> { 526 let Inst{19-16} = 0b1111; 527 } 528} 529 530multiclass AI_unary_rrot_np<bits<8> opcod, string opc> { 531 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src), 532 IIC_iUNAr, opc, "\t$dst, $src", 533 [/* For disassembly only; pattern left blank */]>, 534 Requires<[IsARM, HasV6]> { 535 let Inst{11-10} = 0b00; 536 let Inst{19-16} = 0b1111; 537 } 538 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot), 539 IIC_iUNAsi, opc, "\t$dst, $src, ror $rot", 540 [/* For disassembly only; pattern left blank */]>, 541 Requires<[IsARM, HasV6]> { 542 let Inst{19-16} = 0b1111; 543 } 544} 545 546/// AI_bin_rrot - A binary operation with two forms: one whose operand is a 547/// register and one whose operand is a register rotated by 8/16/24. 548multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> { 549 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 550 IIC_iALUr, opc, "\t$dst, $LHS, $RHS", 551 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, 552 Requires<[IsARM, HasV6]> { 553 let Inst{11-10} = 0b00; 554 } 555 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, 556 i32imm:$rot), 557 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot", 558 [(set GPR:$dst, (opnode GPR:$LHS, 559 (rotr GPR:$RHS, rot_imm:$rot)))]>, 560 Requires<[IsARM, HasV6]>; 561} 562 563// For disassembly only. 564multiclass AI_bin_rrot_np<bits<8> opcod, string opc> { 565 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 566 IIC_iALUr, opc, "\t$dst, $LHS, $RHS", 567 [/* For disassembly only; pattern left blank */]>, 568 Requires<[IsARM, HasV6]> { 569 let Inst{11-10} = 0b00; 570 } 571 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, 572 i32imm:$rot), 573 IIC_iALUsi, opc, "\t$dst, $LHS, $RHS, ror $rot", 574 [/* For disassembly only; pattern left blank */]>, 575 Requires<[IsARM, HasV6]>; 576} 577 578/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 579let Uses = [CPSR] in { 580multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 581 bit Commutable = 0> { 582 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 583 DPFrm, IIC_iALUi, opc, "\t$dst, $a, $b", 584 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, 585 Requires<[IsARM]> { 586 let Inst{25} = 1; 587 } 588 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 589 DPFrm, IIC_iALUr, opc, "\t$dst, $a, $b", 590 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, 591 Requires<[IsARM]> { 592 let isCommutable = Commutable; 593 let Inst{11-4} = 0b00000000; 594 let Inst{25} = 0; 595 } 596 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 597 DPSoRegFrm, IIC_iALUsr, opc, "\t$dst, $a, $b", 598 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, 599 Requires<[IsARM]> { 600 let Inst{25} = 0; 601 } 602} 603// Carry setting variants 604let Defs = [CPSR] in { 605multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, 606 bit Commutable = 0> { 607 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 608 DPFrm, IIC_iALUi, !strconcat(opc, "\t$dst, $a, $b"), 609 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, 610 Requires<[IsARM]> { 611 let Inst{20} = 1; 612 let Inst{25} = 1; 613 } 614 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 615 DPFrm, IIC_iALUr, !strconcat(opc, "\t$dst, $a, $b"), 616 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, 617 Requires<[IsARM]> { 618 let Inst{11-4} = 0b00000000; 619 let Inst{20} = 1; 620 let Inst{25} = 0; 621 } 622 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 623 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$dst, $a, $b"), 624 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, 625 Requires<[IsARM]> { 626 let Inst{20} = 1; 627 let Inst{25} = 0; 628 } 629} 630} 631} 632 633//===----------------------------------------------------------------------===// 634// Instructions 635//===----------------------------------------------------------------------===// 636 637//===----------------------------------------------------------------------===// 638// Miscellaneous Instructions. 639// 640 641/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 642/// the function. The first operand is the ID# for this instruction, the second 643/// is the index into the MachineConstantPool that this is, the third is the 644/// size in bytes of this constant pool entry. 645let neverHasSideEffects = 1, isNotDuplicable = 1 in 646def CONSTPOOL_ENTRY : 647PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 648 i32imm:$size), NoItinerary, 649 "${instid:label} ${cpidx:cpentry}", []>; 650 651// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 652// from removing one half of the matched pairs. That breaks PEI, which assumes 653// these will always be in pairs, and asserts if it finds otherwise. Better way? 654let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 655def ADJCALLSTACKUP : 656PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 657 "@ ADJCALLSTACKUP $amt1", 658 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 659 660def ADJCALLSTACKDOWN : 661PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary, 662 "@ ADJCALLSTACKDOWN $amt", 663 [(ARMcallseq_start timm:$amt)]>; 664} 665 666def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", 667 [/* For disassembly only; pattern left blank */]>, 668 Requires<[IsARM, HasV6T2]> { 669 let Inst{27-16} = 0b001100100000; 670 let Inst{7-0} = 0b00000000; 671} 672 673def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", 674 [/* For disassembly only; pattern left blank */]>, 675 Requires<[IsARM, HasV6T2]> { 676 let Inst{27-16} = 0b001100100000; 677 let Inst{7-0} = 0b00000001; 678} 679 680def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", 681 [/* For disassembly only; pattern left blank */]>, 682 Requires<[IsARM, HasV6T2]> { 683 let Inst{27-16} = 0b001100100000; 684 let Inst{7-0} = 0b00000010; 685} 686 687def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", 688 [/* For disassembly only; pattern left blank */]>, 689 Requires<[IsARM, HasV6T2]> { 690 let Inst{27-16} = 0b001100100000; 691 let Inst{7-0} = 0b00000011; 692} 693 694def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel", 695 "\t$dst, $a, $b", 696 [/* For disassembly only; pattern left blank */]>, 697 Requires<[IsARM, HasV6]> { 698 let Inst{27-20} = 0b01101000; 699 let Inst{7-4} = 0b1011; 700} 701 702def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "", 703 [/* For disassembly only; pattern left blank */]>, 704 Requires<[IsARM, HasV6T2]> { 705 let Inst{27-16} = 0b001100100000; 706 let Inst{7-0} = 0b00000100; 707} 708 709// The i32imm operand $val can be used by a debugger to store more information 710// about the breakpoint. 711def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val", 712 [/* For disassembly only; pattern left blank */]>, 713 Requires<[IsARM]> { 714 let Inst{27-20} = 0b00010010; 715 let Inst{7-4} = 0b0111; 716} 717 718// Change Processor State is a system instruction -- for disassembly only. 719// The singleton $opt operand contains the following information: 720// opt{4-0} = mode from Inst{4-0} 721// opt{5} = changemode from Inst{17} 722// opt{8-6} = AIF from Inst{8-6} 723// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable 724def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt", 725 [/* For disassembly only; pattern left blank */]>, 726 Requires<[IsARM]> { 727 let Inst{31-28} = 0b1111; 728 let Inst{27-20} = 0b00010000; 729 let Inst{16} = 0; 730 let Inst{5} = 0; 731} 732 733// Preload signals the memory system of possible future data/instruction access. 734// These are for disassembly only. 735// 736// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 737// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 738multiclass APreLoad<bit data, bit read, string opc> { 739 740 def i : AXI<(outs), (ins GPR:$base, neg_zero:$imm), MiscFrm, NoItinerary, 741 !strconcat(opc, "\t[$base, $imm]"), []> { 742 let Inst{31-26} = 0b111101; 743 let Inst{25} = 0; // 0 for immediate form 744 let Inst{24} = data; 745 let Inst{22} = read; 746 let Inst{21-20} = 0b01; 747 } 748 749 def r : AXI<(outs), (ins addrmode2:$addr), MiscFrm, NoItinerary, 750 !strconcat(opc, "\t$addr"), []> { 751 let Inst{31-26} = 0b111101; 752 let Inst{25} = 1; // 1 for register form 753 let Inst{24} = data; 754 let Inst{22} = read; 755 let Inst{21-20} = 0b01; 756 let Inst{4} = 0; 757 } 758} 759 760defm PLD : APreLoad<1, 1, "pld">; 761defm PLDW : APreLoad<1, 0, "pldw">; 762defm PLI : APreLoad<0, 1, "pli">; 763 764def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe", 765 [/* For disassembly only; pattern left blank */]>, 766 Requires<[IsARM]> { 767 let Inst{31-28} = 0b1111; 768 let Inst{27-20} = 0b00010000; 769 let Inst{16} = 1; 770 let Inst{9} = 1; 771 let Inst{7-4} = 0b0000; 772} 773 774def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle", 775 [/* For disassembly only; pattern left blank */]>, 776 Requires<[IsARM]> { 777 let Inst{31-28} = 0b1111; 778 let Inst{27-20} = 0b00010000; 779 let Inst{16} = 1; 780 let Inst{9} = 0; 781 let Inst{7-4} = 0b0000; 782} 783 784def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 785 [/* For disassembly only; pattern left blank */]>, 786 Requires<[IsARM, HasV7]> { 787 let Inst{27-16} = 0b001100100000; 788 let Inst{7-4} = 0b1111; 789} 790 791// A5.4 Permanently UNDEFINED instructions. 792def TRAP : AI<(outs), (ins), MiscFrm, NoItinerary, "trap", "", 793 [/* For disassembly only; pattern left blank */]>, 794 Requires<[IsARM]> { 795 let Inst{27-25} = 0b011; 796 let Inst{24-20} = 0b11111; 797 let Inst{7-5} = 0b111; 798 let Inst{4} = 0b1; 799} 800 801// Address computation and loads and stores in PIC mode. 802let isNotDuplicable = 1 in { 803def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 804 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p\t$dst, pc, $a", 805 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; 806 807let AddedComplexity = 10 in { 808def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 809 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr", 810 [(set GPR:$dst, (load addrmodepc:$addr))]>; 811 812def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 813 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrh${p}\t$dst, $addr", 814 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; 815 816def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 817 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrb${p}\t$dst, $addr", 818 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; 819 820def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 821 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsh${p}\t$dst, $addr", 822 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; 823 824def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 825 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldrsb${p}\t$dst, $addr", 826 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; 827} 828let AddedComplexity = 10 in { 829def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 830 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p\t$src, $addr", 831 [(store GPR:$src, addrmodepc:$addr)]>; 832 833def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 834 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrh${p}\t$src, $addr", 835 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; 836 837def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 838 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstrb${p}\t$src, $addr", 839 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 840} 841} // isNotDuplicable = 1 842 843 844// LEApcrel - Load a pc-relative address into a register without offending the 845// assembler. 846def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), 847 Pseudo, IIC_iALUi, 848 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(", 849 "${:private}PCRELL${:uid}+8))\n"), 850 !strconcat("${:private}PCRELL${:uid}:\n\t", 851 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")), 852 []>; 853 854def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), 855 (ins i32imm:$label, nohash_imm:$id, pred:$p), 856 Pseudo, IIC_iALUi, 857 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, " 858 "(${label}_${id}-(", 859 "${:private}PCRELL${:uid}+8))\n"), 860 !strconcat("${:private}PCRELL${:uid}:\n\t", 861 "add$p\t$dst, pc, #${:private}PCRELV${:uid}")), 862 []> { 863 let Inst{25} = 1; 864} 865 866//===----------------------------------------------------------------------===// 867// Control Flow Instructions. 868// 869 870let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 871 // ARMV4T and above 872 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 873 "bx", "\tlr", [(ARMretflag)]>, 874 Requires<[IsARM, HasV4T]> { 875 let Inst{3-0} = 0b1110; 876 let Inst{7-4} = 0b0001; 877 let Inst{19-8} = 0b111111111111; 878 let Inst{27-20} = 0b00010010; 879 } 880 881 // ARMV4 only 882 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 883 "mov", "\tpc, lr", [(ARMretflag)]>, 884 Requires<[IsARM, NoV4T]> { 885 let Inst{11-0} = 0b000000001110; 886 let Inst{15-12} = 0b1111; 887 let Inst{19-16} = 0b0000; 888 let Inst{27-20} = 0b00011010; 889 } 890} 891 892// Indirect branches 893let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 894 // ARMV4T and above 895 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 896 [(brind GPR:$dst)]>, 897 Requires<[IsARM, HasV4T]> { 898 let Inst{7-4} = 0b0001; 899 let Inst{19-8} = 0b111111111111; 900 let Inst{27-20} = 0b00010010; 901 let Inst{31-28} = 0b1110; 902 } 903 904 // ARMV4 only 905 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst", 906 [(brind GPR:$dst)]>, 907 Requires<[IsARM, NoV4T]> { 908 let Inst{11-4} = 0b00000000; 909 let Inst{15-12} = 0b1111; 910 let Inst{19-16} = 0b0000; 911 let Inst{27-20} = 0b00011010; 912 let Inst{31-28} = 0b1110; 913 } 914} 915 916// FIXME: remove when we have a way to marking a MI with these properties. 917// FIXME: Should pc be an implicit operand like PICADD, etc? 918let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 919 hasExtraDefRegAllocReq = 1 in 920 def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 921 reglist:$dsts, variable_ops), 922 IndexModeUpd, LdStMulFrm, IIC_Br, 923 "ldm${addr:submode}${p}\t$addr!, $dsts", 924 "$addr.addr = $wb", []>; 925 926// On non-Darwin platforms R9 is callee-saved. 927let isCall = 1, 928 Defs = [R0, R1, R2, R3, R12, LR, 929 D0, D1, D2, D3, D4, D5, D6, D7, 930 D16, D17, D18, D19, D20, D21, D22, D23, 931 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 932 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), 933 IIC_Br, "bl\t${func:call}", 934 [(ARMcall tglobaladdr:$func)]>, 935 Requires<[IsARM, IsNotDarwin]> { 936 let Inst{31-28} = 0b1110; 937 } 938 939 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), 940 IIC_Br, "bl", "\t${func:call}", 941 [(ARMcall_pred tglobaladdr:$func)]>, 942 Requires<[IsARM, IsNotDarwin]>; 943 944 // ARMv5T and above 945 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 946 IIC_Br, "blx\t$func", 947 [(ARMcall GPR:$func)]>, 948 Requires<[IsARM, HasV5T, IsNotDarwin]> { 949 let Inst{7-4} = 0b0011; 950 let Inst{19-8} = 0b111111111111; 951 let Inst{27-20} = 0b00010010; 952 } 953 954 // ARMv4T 955 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 956 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 957 IIC_Br, "mov\tlr, pc\n\tbx\t$func", 958 [(ARMcall_nolink tGPR:$func)]>, 959 Requires<[IsARM, HasV4T, IsNotDarwin]> { 960 let Inst{7-4} = 0b0001; 961 let Inst{19-8} = 0b111111111111; 962 let Inst{27-20} = 0b00010010; 963 } 964 965 // ARMv4 966 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 967 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", 968 [(ARMcall_nolink tGPR:$func)]>, 969 Requires<[IsARM, NoV4T, IsNotDarwin]> { 970 let Inst{11-4} = 0b00000000; 971 let Inst{15-12} = 0b1111; 972 let Inst{19-16} = 0b0000; 973 let Inst{27-20} = 0b00011010; 974 } 975} 976 977// On Darwin R9 is call-clobbered. 978let isCall = 1, 979 Defs = [R0, R1, R2, R3, R9, R12, LR, 980 D0, D1, D2, D3, D4, D5, D6, D7, 981 D16, D17, D18, D19, D20, D21, D22, D23, 982 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 983 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), 984 IIC_Br, "bl\t${func:call}", 985 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> { 986 let Inst{31-28} = 0b1110; 987 } 988 989 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), 990 IIC_Br, "bl", "\t${func:call}", 991 [(ARMcall_pred tglobaladdr:$func)]>, 992 Requires<[IsARM, IsDarwin]>; 993 994 // ARMv5T and above 995 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 996 IIC_Br, "blx\t$func", 997 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> { 998 let Inst{7-4} = 0b0011; 999 let Inst{19-8} = 0b111111111111; 1000 let Inst{27-20} = 0b00010010; 1001 } 1002 1003 // ARMv4T 1004 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 1005 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 1006 IIC_Br, "mov\tlr, pc\n\tbx\t$func", 1007 [(ARMcall_nolink tGPR:$func)]>, 1008 Requires<[IsARM, HasV4T, IsDarwin]> { 1009 let Inst{7-4} = 0b0001; 1010 let Inst{19-8} = 0b111111111111; 1011 let Inst{27-20} = 0b00010010; 1012 } 1013 1014 // ARMv4 1015 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), 1016 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", 1017 [(ARMcall_nolink tGPR:$func)]>, 1018 Requires<[IsARM, NoV4T, IsDarwin]> { 1019 let Inst{11-4} = 0b00000000; 1020 let Inst{15-12} = 0b1111; 1021 let Inst{19-16} = 0b0000; 1022 let Inst{27-20} = 0b00011010; 1023 } 1024} 1025 1026let isBranch = 1, isTerminator = 1 in { 1027 // B is "predicable" since it can be xformed into a Bcc. 1028 let isBarrier = 1 in { 1029 let isPredicable = 1 in 1030 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br, 1031 "b\t$target", [(br bb:$target)]>; 1032 1033 let isNotDuplicable = 1, isIndirectBranch = 1 in { 1034 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), 1035 IIC_Br, "mov\tpc, $target \n$jt", 1036 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { 1037 let Inst{11-4} = 0b00000000; 1038 let Inst{15-12} = 0b1111; 1039 let Inst{20} = 0; // S Bit 1040 let Inst{24-21} = 0b1101; 1041 let Inst{27-25} = 0b000; 1042 } 1043 def BR_JTm : JTI<(outs), 1044 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), 1045 IIC_Br, "ldr\tpc, $target \n$jt", 1046 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 1047 imm:$id)]> { 1048 let Inst{15-12} = 0b1111; 1049 let Inst{20} = 1; // L bit 1050 let Inst{21} = 0; // W bit 1051 let Inst{22} = 0; // B bit 1052 let Inst{24} = 1; // P bit 1053 let Inst{27-25} = 0b011; 1054 } 1055 def BR_JTadd : JTI<(outs), 1056 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), 1057 IIC_Br, "add\tpc, $target, $idx \n$jt", 1058 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 1059 imm:$id)]> { 1060 let Inst{15-12} = 0b1111; 1061 let Inst{20} = 0; // S bit 1062 let Inst{24-21} = 0b0100; 1063 let Inst{27-25} = 0b000; 1064 } 1065 } // isNotDuplicable = 1, isIndirectBranch = 1 1066 } // isBarrier = 1 1067 1068 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 1069 // a two-value operand where a dag node expects two operands. :( 1070 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target), 1071 IIC_Br, "b", "\t$target", 1072 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; 1073} 1074 1075// Branch and Exchange Jazelle -- for disassembly only 1076def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 1077 [/* For disassembly only; pattern left blank */]> { 1078 let Inst{23-20} = 0b0010; 1079 //let Inst{19-8} = 0xfff; 1080 let Inst{7-4} = 0b0010; 1081} 1082 1083// Secure Monitor Call is a system instruction -- for disassembly only 1084def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", 1085 [/* For disassembly only; pattern left blank */]> { 1086 let Inst{23-20} = 0b0110; 1087 let Inst{7-4} = 0b0111; 1088} 1089 1090// Supervisor Call (Software Interrupt) -- for disassembly only 1091let isCall = 1 in { 1092def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", 1093 [/* For disassembly only; pattern left blank */]>; 1094} 1095 1096// Store Return State is a system instruction -- for disassembly only 1097def SRSW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), 1098 NoItinerary, "srs${addr:submode}\tsp!, $mode", 1099 [/* For disassembly only; pattern left blank */]> { 1100 let Inst{31-28} = 0b1111; 1101 let Inst{22-20} = 0b110; // W = 1 1102} 1103 1104def SRS : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, i32imm:$mode), 1105 NoItinerary, "srs${addr:submode}\tsp, $mode", 1106 [/* For disassembly only; pattern left blank */]> { 1107 let Inst{31-28} = 0b1111; 1108 let Inst{22-20} = 0b100; // W = 0 1109} 1110 1111// Return From Exception is a system instruction -- for disassembly only 1112def RFEW : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), 1113 NoItinerary, "rfe${addr:submode}\t$base!", 1114 [/* For disassembly only; pattern left blank */]> { 1115 let Inst{31-28} = 0b1111; 1116 let Inst{22-20} = 0b011; // W = 1 1117} 1118 1119def RFE : ABXI<{1,0,0,?}, (outs), (ins addrmode4:$addr, GPR:$base), 1120 NoItinerary, "rfe${addr:submode}\t$base", 1121 [/* For disassembly only; pattern left blank */]> { 1122 let Inst{31-28} = 0b1111; 1123 let Inst{22-20} = 0b001; // W = 0 1124} 1125 1126//===----------------------------------------------------------------------===// 1127// Load / store Instructions. 1128// 1129 1130// Load 1131let canFoldAsLoad = 1, isReMaterializable = 1 in 1132def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr, 1133 "ldr", "\t$dst, $addr", 1134 [(set GPR:$dst, (load addrmode2:$addr))]>; 1135 1136// Special LDR for loads from non-pc-relative constpools. 1137let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in 1138def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr, 1139 "ldr", "\t$dst, $addr", []>; 1140 1141// Loads with zero extension 1142def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 1143 IIC_iLoadr, "ldrh", "\t$dst, $addr", 1144 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; 1145 1146def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 1147 IIC_iLoadr, "ldrb", "\t$dst, $addr", 1148 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; 1149 1150// Loads with sign extension 1151def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 1152 IIC_iLoadr, "ldrsh", "\t$dst, $addr", 1153 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; 1154 1155def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 1156 IIC_iLoadr, "ldrsb", "\t$dst, $addr", 1157 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; 1158 1159let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 1160// Load doubleword 1161def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, 1162 IIC_iLoadr, "ldrd", "\t$dst1, $addr", 1163 []>, Requires<[IsARM, HasV5TE]>; 1164 1165// Indexed loads 1166def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), 1167 (ins addrmode2:$addr), LdFrm, IIC_iLoadru, 1168 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1169 1170def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), 1171 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru, 1172 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1173 1174def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), 1175 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru, 1176 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1177 1178def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), 1179 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru, 1180 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1181 1182def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), 1183 (ins addrmode2:$addr), LdFrm, IIC_iLoadru, 1184 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1185 1186def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), 1187 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru, 1188 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1189 1190def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), 1191 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru, 1192 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1193 1194def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), 1195 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru, 1196 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1197 1198def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), 1199 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru, 1200 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>; 1201 1202def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), 1203 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru, 1204 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>; 1205 1206// For disassembly only 1207def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb), 1208 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadr, 1209 "ldrd", "\t$dst1, $dst2, $addr!", "$addr.base = $base_wb", []>, 1210 Requires<[IsARM, HasV5TE]>; 1211 1212// For disassembly only 1213def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb), 1214 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadr, 1215 "ldrd", "\t$dst1, $dst2, [$base], $offset", "$base = $base_wb", []>, 1216 Requires<[IsARM, HasV5TE]>; 1217 1218} 1219 1220// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only. 1221 1222def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), 1223 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru, 1224 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1225 let Inst{21} = 1; // overwrite 1226} 1227 1228def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), 1229 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru, 1230 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1231 let Inst{21} = 1; // overwrite 1232} 1233 1234def LDRSBT : AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), 1235 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru, 1236 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1237 let Inst{21} = 1; // overwrite 1238} 1239 1240def LDRHT : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), 1241 (ins GPR:$base, am3offset:$offset), LdMiscFrm, IIC_iLoadru, 1242 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1243 let Inst{21} = 1; // overwrite 1244} 1245 1246def LDRSHT : AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), 1247 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru, 1248 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> { 1249 let Inst{21} = 1; // overwrite 1250} 1251 1252// Store 1253def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer, 1254 "str", "\t$src, $addr", 1255 [(store GPR:$src, addrmode2:$addr)]>; 1256 1257// Stores with truncate 1258def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, 1259 IIC_iStorer, "strh", "\t$src, $addr", 1260 [(truncstorei16 GPR:$src, addrmode3:$addr)]>; 1261 1262def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer, 1263 "strb", "\t$src, $addr", 1264 [(truncstorei8 GPR:$src, addrmode2:$addr)]>; 1265 1266// Store doubleword 1267let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 1268def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr), 1269 StMiscFrm, IIC_iStorer, 1270 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>; 1271 1272// Indexed stores 1273def STR_PRE : AI2stwpr<(outs GPR:$base_wb), 1274 (ins GPR:$src, GPR:$base, am2offset:$offset), 1275 StFrm, IIC_iStoreru, 1276 "str", "\t$src, [$base, $offset]!", "$base = $base_wb", 1277 [(set GPR:$base_wb, 1278 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; 1279 1280def STR_POST : AI2stwpo<(outs GPR:$base_wb), 1281 (ins GPR:$src, GPR:$base,am2offset:$offset), 1282 StFrm, IIC_iStoreru, 1283 "str", "\t$src, [$base], $offset", "$base = $base_wb", 1284 [(set GPR:$base_wb, 1285 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; 1286 1287def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), 1288 (ins GPR:$src, GPR:$base,am3offset:$offset), 1289 StMiscFrm, IIC_iStoreru, 1290 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb", 1291 [(set GPR:$base_wb, 1292 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; 1293 1294def STRH_POST: AI3sthpo<(outs GPR:$base_wb), 1295 (ins GPR:$src, GPR:$base,am3offset:$offset), 1296 StMiscFrm, IIC_iStoreru, 1297 "strh", "\t$src, [$base], $offset", "$base = $base_wb", 1298 [(set GPR:$base_wb, (post_truncsti16 GPR:$src, 1299 GPR:$base, am3offset:$offset))]>; 1300 1301def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), 1302 (ins GPR:$src, GPR:$base,am2offset:$offset), 1303 StFrm, IIC_iStoreru, 1304 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", 1305 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, 1306 GPR:$base, am2offset:$offset))]>; 1307 1308def STRB_POST: AI2stbpo<(outs GPR:$base_wb), 1309 (ins GPR:$src, GPR:$base,am2offset:$offset), 1310 StFrm, IIC_iStoreru, 1311 "strb", "\t$src, [$base], $offset", "$base = $base_wb", 1312 [(set GPR:$base_wb, (post_truncsti8 GPR:$src, 1313 GPR:$base, am2offset:$offset))]>; 1314 1315// For disassembly only 1316def STRD_PRE : AI3stdpr<(outs GPR:$base_wb), 1317 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), 1318 StMiscFrm, IIC_iStoreru, 1319 "strd", "\t$src1, $src2, [$base, $offset]!", 1320 "$base = $base_wb", []>; 1321 1322// For disassembly only 1323def STRD_POST: AI3stdpo<(outs GPR:$base_wb), 1324 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset), 1325 StMiscFrm, IIC_iStoreru, 1326 "strd", "\t$src1, $src2, [$base], $offset", 1327 "$base = $base_wb", []>; 1328 1329// STRT, STRBT, and STRHT are for disassembly only. 1330 1331def STRT : AI2stwpo<(outs GPR:$base_wb), 1332 (ins GPR:$src, GPR:$base,am2offset:$offset), 1333 StFrm, IIC_iStoreru, 1334 "strt", "\t$src, [$base], $offset", "$base = $base_wb", 1335 [/* For disassembly only; pattern left blank */]> { 1336 let Inst{21} = 1; // overwrite 1337} 1338 1339def STRBT : AI2stbpo<(outs GPR:$base_wb), 1340 (ins GPR:$src, GPR:$base,am2offset:$offset), 1341 StFrm, IIC_iStoreru, 1342 "strbt", "\t$src, [$base], $offset", "$base = $base_wb", 1343 [/* For disassembly only; pattern left blank */]> { 1344 let Inst{21} = 1; // overwrite 1345} 1346 1347def STRHT: AI3sthpo<(outs GPR:$base_wb), 1348 (ins GPR:$src, GPR:$base,am3offset:$offset), 1349 StMiscFrm, IIC_iStoreru, 1350 "strht", "\t$src, [$base], $offset", "$base = $base_wb", 1351 [/* For disassembly only; pattern left blank */]> { 1352 let Inst{21} = 1; // overwrite 1353} 1354 1355//===----------------------------------------------------------------------===// 1356// Load / store multiple Instructions. 1357// 1358 1359let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 1360def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, 1361 reglist:$dsts, variable_ops), 1362 IndexModeNone, LdStMulFrm, IIC_iLoadm, 1363 "ldm${addr:submode}${p}\t$addr, $dsts", "", []>; 1364 1365def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1366 reglist:$dsts, variable_ops), 1367 IndexModeUpd, LdStMulFrm, IIC_iLoadm, 1368 "ldm${addr:submode}${p}\t$addr!, $dsts", 1369 "$addr.addr = $wb", []>; 1370} // mayLoad, hasExtraDefRegAllocReq 1371 1372let mayStore = 1, hasExtraSrcRegAllocReq = 1 in { 1373def STM : AXI4st<(outs), (ins addrmode4:$addr, pred:$p, 1374 reglist:$srcs, variable_ops), 1375 IndexModeNone, LdStMulFrm, IIC_iStorem, 1376 "stm${addr:submode}${p}\t$addr, $srcs", "", []>; 1377 1378def STM_UPD : AXI4st<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1379 reglist:$srcs, variable_ops), 1380 IndexModeUpd, LdStMulFrm, IIC_iStorem, 1381 "stm${addr:submode}${p}\t$addr!, $srcs", 1382 "$addr.addr = $wb", []>; 1383} // mayStore, hasExtraSrcRegAllocReq 1384 1385//===----------------------------------------------------------------------===// 1386// Move Instructions. 1387// 1388 1389let neverHasSideEffects = 1 in 1390def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr, 1391 "mov", "\t$dst, $src", []>, UnaryDP { 1392 let Inst{11-4} = 0b00000000; 1393 let Inst{25} = 0; 1394} 1395 1396def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), 1397 DPSoRegFrm, IIC_iMOVsr, 1398 "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP { 1399 let Inst{25} = 0; 1400} 1401 1402let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1403def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi, 1404 "mov", "\t$dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP { 1405 let Inst{25} = 1; 1406} 1407 1408let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1409def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src), 1410 DPFrm, IIC_iMOVi, 1411 "movw", "\t$dst, $src", 1412 [(set GPR:$dst, imm0_65535:$src)]>, 1413 Requires<[IsARM, HasV6T2]>, UnaryDP { 1414 let Inst{20} = 0; 1415 let Inst{25} = 1; 1416} 1417 1418let Constraints = "$src = $dst" in 1419def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm), 1420 DPFrm, IIC_iMOVi, 1421 "movt", "\t$dst, $imm", 1422 [(set GPR:$dst, 1423 (or (and GPR:$src, 0xffff), 1424 lo16AllZero:$imm))]>, UnaryDP, 1425 Requires<[IsARM, HasV6T2]> { 1426 let Inst{20} = 0; 1427 let Inst{25} = 1; 1428} 1429 1430def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 1431 Requires<[IsARM, HasV6T2]>; 1432 1433let Uses = [CPSR] in 1434def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi, 1435 "mov", "\t$dst, $src, rrx", 1436 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP; 1437 1438// These aren't really mov instructions, but we have to define them this way 1439// due to flag operands. 1440 1441let Defs = [CPSR] in { 1442def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 1443 IIC_iMOVsi, "movs", "\t$dst, $src, lsr #1", 1444 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP; 1445def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 1446 IIC_iMOVsi, "movs", "\t$dst, $src, asr #1", 1447 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP; 1448} 1449 1450//===----------------------------------------------------------------------===// 1451// Extend Instructions. 1452// 1453 1454// Sign extenders 1455 1456defm SXTB : AI_unary_rrot<0b01101010, 1457 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 1458defm SXTH : AI_unary_rrot<0b01101011, 1459 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 1460 1461defm SXTAB : AI_bin_rrot<0b01101010, 1462 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1463defm SXTAH : AI_bin_rrot<0b01101011, 1464 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1465 1466// For disassembly only 1467defm SXTB16 : AI_unary_rrot_np<0b01101000, "sxtb16">; 1468 1469// For disassembly only 1470defm SXTAB16 : AI_bin_rrot_np<0b01101000, "sxtab16">; 1471 1472// Zero extenders 1473 1474let AddedComplexity = 16 in { 1475defm UXTB : AI_unary_rrot<0b01101110, 1476 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 1477defm UXTH : AI_unary_rrot<0b01101111, 1478 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1479defm UXTB16 : AI_unary_rrot<0b01101100, 1480 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1481 1482def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 1483 (UXTB16r_rot GPR:$Src, 24)>; 1484def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 1485 (UXTB16r_rot GPR:$Src, 8)>; 1486 1487defm UXTAB : AI_bin_rrot<0b01101110, "uxtab", 1488 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1489defm UXTAH : AI_bin_rrot<0b01101111, "uxtah", 1490 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1491} 1492 1493// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 1494// For disassembly only 1495defm UXTAB16 : AI_bin_rrot_np<0b01101100, "uxtab16">; 1496 1497 1498def SBFX : I<(outs GPR:$dst), 1499 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1500 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi, 1501 "sbfx", "\t$dst, $src, $lsb, $width", "", []>, 1502 Requires<[IsARM, HasV6T2]> { 1503 let Inst{27-21} = 0b0111101; 1504 let Inst{6-4} = 0b101; 1505} 1506 1507def UBFX : I<(outs GPR:$dst), 1508 (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1509 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi, 1510 "ubfx", "\t$dst, $src, $lsb, $width", "", []>, 1511 Requires<[IsARM, HasV6T2]> { 1512 let Inst{27-21} = 0b0111111; 1513 let Inst{6-4} = 0b101; 1514} 1515 1516//===----------------------------------------------------------------------===// 1517// Arithmetic Instructions. 1518// 1519 1520defm ADD : AsI1_bin_irs<0b0100, "add", 1521 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1522defm SUB : AsI1_bin_irs<0b0010, "sub", 1523 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1524 1525// ADD and SUB with 's' bit set. 1526defm ADDS : AI1_bin_s_irs<0b0100, "adds", 1527 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 1528defm SUBS : AI1_bin_s_irs<0b0010, "subs", 1529 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1530 1531defm ADC : AI1_adde_sube_irs<0b0101, "adc", 1532 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; 1533defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 1534 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; 1535defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs", 1536 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; 1537defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs", 1538 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>; 1539 1540// These don't define reg/reg forms, because they are handled above. 1541def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 1542 IIC_iALUi, "rsb", "\t$dst, $a, $b", 1543 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> { 1544 let Inst{25} = 1; 1545} 1546 1547def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 1548 IIC_iALUsr, "rsb", "\t$dst, $a, $b", 1549 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> { 1550 let Inst{25} = 0; 1551} 1552 1553// RSB with 's' bit set. 1554let Defs = [CPSR] in { 1555def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 1556 IIC_iALUi, "rsbs", "\t$dst, $a, $b", 1557 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> { 1558 let Inst{20} = 1; 1559 let Inst{25} = 1; 1560} 1561def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 1562 IIC_iALUsr, "rsbs", "\t$dst, $a, $b", 1563 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]> { 1564 let Inst{20} = 1; 1565 let Inst{25} = 0; 1566} 1567} 1568 1569let Uses = [CPSR] in { 1570def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 1571 DPFrm, IIC_iALUi, "rsc", "\t$dst, $a, $b", 1572 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>, 1573 Requires<[IsARM]> { 1574 let Inst{25} = 1; 1575} 1576def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 1577 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b", 1578 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>, 1579 Requires<[IsARM]> { 1580 let Inst{25} = 0; 1581} 1582} 1583 1584// FIXME: Allow these to be predicated. 1585let Defs = [CPSR], Uses = [CPSR] in { 1586def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 1587 DPFrm, IIC_iALUi, "rscs\t$dst, $a, $b", 1588 [(set GPR:$dst, (sube_dead_carry so_imm:$b, GPR:$a))]>, 1589 Requires<[IsARM]> { 1590 let Inst{20} = 1; 1591 let Inst{25} = 1; 1592} 1593def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 1594 DPSoRegFrm, IIC_iALUsr, "rscs\t$dst, $a, $b", 1595 [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>, 1596 Requires<[IsARM]> { 1597 let Inst{20} = 1; 1598 let Inst{25} = 0; 1599} 1600} 1601 1602// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1603def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 1604 (SUBri GPR:$src, so_imm_neg:$imm)>; 1605 1606//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), 1607// (SUBSri GPR:$src, so_imm_neg:$imm)>; 1608//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), 1609// (SBCri GPR:$src, so_imm_neg:$imm)>; 1610 1611// Note: These are implemented in C++ code, because they have to generate 1612// ADD/SUBrs instructions, which use a complex pattern that a xform function 1613// cannot produce. 1614// (mul X, 2^n+1) -> (add (X << n), X) 1615// (mul X, 2^n-1) -> (rsb X, (X << n)) 1616 1617// ARM Arithmetic Instruction -- for disassembly only 1618// GPR:$dst = GPR:$a op GPR:$b 1619class AAI<bits<8> op27_20, bits<4> op7_4, string opc> 1620 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, IIC_iALUr, 1621 opc, "\t$dst, $a, $b", 1622 [/* For disassembly only; pattern left blank */]> { 1623 let Inst{27-20} = op27_20; 1624 let Inst{7-4} = op7_4; 1625} 1626 1627// Saturating add/subtract -- for disassembly only 1628 1629def QADD : AAI<0b00010000, 0b0101, "qadd">; 1630def QADD16 : AAI<0b01100010, 0b0001, "qadd16">; 1631def QADD8 : AAI<0b01100010, 0b1001, "qadd8">; 1632def QASX : AAI<0b01100010, 0b0011, "qasx">; 1633def QDADD : AAI<0b00010100, 0b0101, "qdadd">; 1634def QDSUB : AAI<0b00010110, 0b0101, "qdsub">; 1635def QSAX : AAI<0b01100010, 0b0101, "qsax">; 1636def QSUB : AAI<0b00010010, 0b0101, "qsub">; 1637def QSUB16 : AAI<0b01100010, 0b0111, "qsub16">; 1638def QSUB8 : AAI<0b01100010, 0b1111, "qsub8">; 1639def UQADD16 : AAI<0b01100110, 0b0001, "uqadd16">; 1640def UQADD8 : AAI<0b01100110, 0b1001, "uqadd8">; 1641def UQASX : AAI<0b01100110, 0b0011, "uqasx">; 1642def UQSAX : AAI<0b01100110, 0b0101, "uqsax">; 1643def UQSUB16 : AAI<0b01100110, 0b0111, "uqsub16">; 1644def UQSUB8 : AAI<0b01100110, 0b1111, "uqsub8">; 1645 1646// Signed/Unsigned add/subtract -- for disassembly only 1647 1648def SASX : AAI<0b01100001, 0b0011, "sasx">; 1649def SADD16 : AAI<0b01100001, 0b0001, "sadd16">; 1650def SADD8 : AAI<0b01100001, 0b1001, "sadd8">; 1651def SSAX : AAI<0b01100001, 0b0101, "ssax">; 1652def SSUB16 : AAI<0b01100001, 0b0111, "ssub16">; 1653def SSUB8 : AAI<0b01100001, 0b1111, "ssub8">; 1654def UASX : AAI<0b01100101, 0b0011, "uasx">; 1655def UADD16 : AAI<0b01100101, 0b0001, "uadd16">; 1656def UADD8 : AAI<0b01100101, 0b1001, "uadd8">; 1657def USAX : AAI<0b01100101, 0b0101, "usax">; 1658def USUB16 : AAI<0b01100101, 0b0111, "usub16">; 1659def USUB8 : AAI<0b01100101, 0b1111, "usub8">; 1660 1661// Signed/Unsigned halving add/subtract -- for disassembly only 1662 1663def SHASX : AAI<0b01100011, 0b0011, "shasx">; 1664def SHADD16 : AAI<0b01100011, 0b0001, "shadd16">; 1665def SHADD8 : AAI<0b01100011, 0b1001, "shadd8">; 1666def SHSAX : AAI<0b01100011, 0b0101, "shsax">; 1667def SHSUB16 : AAI<0b01100011, 0b0111, "shsub16">; 1668def SHSUB8 : AAI<0b01100011, 0b1111, "shsub8">; 1669def UHASX : AAI<0b01100111, 0b0011, "uhasx">; 1670def UHADD16 : AAI<0b01100111, 0b0001, "uhadd16">; 1671def UHADD8 : AAI<0b01100111, 0b1001, "uhadd8">; 1672def UHSAX : AAI<0b01100111, 0b0101, "uhsax">; 1673def UHSUB16 : AAI<0b01100111, 0b0111, "uhsub16">; 1674def UHSUB8 : AAI<0b01100111, 0b1111, "uhsub8">; 1675 1676// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only 1677 1678def USAD8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 1679 MulFrm /* for convenience */, NoItinerary, "usad8", 1680 "\t$dst, $a, $b", []>, 1681 Requires<[IsARM, HasV6]> { 1682 let Inst{27-20} = 0b01111000; 1683 let Inst{15-12} = 0b1111; 1684 let Inst{7-4} = 0b0001; 1685} 1686def USADA8 : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1687 MulFrm /* for convenience */, NoItinerary, "usada8", 1688 "\t$dst, $a, $b, $acc", []>, 1689 Requires<[IsARM, HasV6]> { 1690 let Inst{27-20} = 0b01111000; 1691 let Inst{7-4} = 0b0001; 1692} 1693 1694// Signed/Unsigned saturate -- for disassembly only 1695 1696def SSATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt), 1697 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt", 1698 [/* For disassembly only; pattern left blank */]> { 1699 let Inst{27-21} = 0b0110101; 1700 let Inst{6-4} = 0b001; 1701} 1702 1703def SSATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt), 1704 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt", 1705 [/* For disassembly only; pattern left blank */]> { 1706 let Inst{27-21} = 0b0110101; 1707 let Inst{6-4} = 0b101; 1708} 1709 1710def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm, 1711 NoItinerary, "ssat16", "\t$dst, $bit_pos, $a", 1712 [/* For disassembly only; pattern left blank */]> { 1713 let Inst{27-20} = 0b01101010; 1714 let Inst{7-4} = 0b0011; 1715} 1716 1717def USATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt), 1718 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt", 1719 [/* For disassembly only; pattern left blank */]> { 1720 let Inst{27-21} = 0b0110111; 1721 let Inst{6-4} = 0b001; 1722} 1723 1724def USATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt), 1725 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt", 1726 [/* For disassembly only; pattern left blank */]> { 1727 let Inst{27-21} = 0b0110111; 1728 let Inst{6-4} = 0b101; 1729} 1730 1731def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm, 1732 NoItinerary, "usat16", "\t$dst, $bit_pos, $a", 1733 [/* For disassembly only; pattern left blank */]> { 1734 let Inst{27-20} = 0b01101110; 1735 let Inst{7-4} = 0b0011; 1736} 1737 1738//===----------------------------------------------------------------------===// 1739// Bitwise Instructions. 1740// 1741 1742defm AND : AsI1_bin_irs<0b0000, "and", 1743 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 1744defm ORR : AsI1_bin_irs<0b1100, "orr", 1745 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 1746defm EOR : AsI1_bin_irs<0b0001, "eor", 1747 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 1748defm BIC : AsI1_bin_irs<0b1110, "bic", 1749 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1750 1751def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 1752 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, 1753 "bfc", "\t$dst, $imm", "$src = $dst", 1754 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 1755 Requires<[IsARM, HasV6T2]> { 1756 let Inst{27-21} = 0b0111110; 1757 let Inst{6-0} = 0b0011111; 1758} 1759 1760// A8.6.18 BFI - Bitfield insert (Encoding A1) 1761// Added for disassembler with the pattern field purposely left blank. 1762def BFI : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 1763 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, 1764 "bfi", "\t$dst, $src, $imm", "", 1765 [/* For disassembly only; pattern left blank */]>, 1766 Requires<[IsARM, HasV6T2]> { 1767 let Inst{27-21} = 0b0111110; 1768 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 1769} 1770 1771def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr, 1772 "mvn", "\t$dst, $src", 1773 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP { 1774 let Inst{25} = 0; 1775 let Inst{11-4} = 0b00000000; 1776} 1777def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, 1778 IIC_iMOVsr, "mvn", "\t$dst, $src", 1779 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP { 1780 let Inst{25} = 0; 1781} 1782let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1783def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, 1784 IIC_iMOVi, "mvn", "\t$dst, $imm", 1785 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP { 1786 let Inst{25} = 1; 1787} 1788 1789def : ARMPat<(and GPR:$src, so_imm_not:$imm), 1790 (BICri GPR:$src, so_imm_not:$imm)>; 1791 1792//===----------------------------------------------------------------------===// 1793// Multiply Instructions. 1794// 1795 1796let isCommutable = 1 in 1797def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1798 IIC_iMUL32, "mul", "\t$dst, $a, $b", 1799 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 1800 1801def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1802 IIC_iMAC32, "mla", "\t$dst, $a, $b, $c", 1803 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 1804 1805def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1806 IIC_iMAC32, "mls", "\t$dst, $a, $b, $c", 1807 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>, 1808 Requires<[IsARM, HasV6T2]>; 1809 1810// Extra precision multiplies with low / high results 1811let neverHasSideEffects = 1 in { 1812let isCommutable = 1 in { 1813def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst), 1814 (ins GPR:$a, GPR:$b), IIC_iMUL64, 1815 "smull", "\t$ldst, $hdst, $a, $b", []>; 1816 1817def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst), 1818 (ins GPR:$a, GPR:$b), IIC_iMUL64, 1819 "umull", "\t$ldst, $hdst, $a, $b", []>; 1820} 1821 1822// Multiply + accumulate 1823def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst), 1824 (ins GPR:$a, GPR:$b), IIC_iMAC64, 1825 "smlal", "\t$ldst, $hdst, $a, $b", []>; 1826 1827def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst), 1828 (ins GPR:$a, GPR:$b), IIC_iMAC64, 1829 "umlal", "\t$ldst, $hdst, $a, $b", []>; 1830 1831def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst), 1832 (ins GPR:$a, GPR:$b), IIC_iMAC64, 1833 "umaal", "\t$ldst, $hdst, $a, $b", []>, 1834 Requires<[IsARM, HasV6]>; 1835} // neverHasSideEffects 1836 1837// Most significant word multiply 1838def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1839 IIC_iMUL32, "smmul", "\t$dst, $a, $b", 1840 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, 1841 Requires<[IsARM, HasV6]> { 1842 let Inst{7-4} = 0b0001; 1843 let Inst{15-12} = 0b1111; 1844} 1845 1846def SMMULR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1847 IIC_iMUL32, "smmulr", "\t$dst, $a, $b", 1848 [/* For disassembly only; pattern left blank */]>, 1849 Requires<[IsARM, HasV6]> { 1850 let Inst{7-4} = 0b0011; // R = 1 1851 let Inst{15-12} = 0b1111; 1852} 1853 1854def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1855 IIC_iMAC32, "smmla", "\t$dst, $a, $b, $c", 1856 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, 1857 Requires<[IsARM, HasV6]> { 1858 let Inst{7-4} = 0b0001; 1859} 1860 1861def SMMLAR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1862 IIC_iMAC32, "smmlar", "\t$dst, $a, $b, $c", 1863 [/* For disassembly only; pattern left blank */]>, 1864 Requires<[IsARM, HasV6]> { 1865 let Inst{7-4} = 0b0011; // R = 1 1866} 1867 1868def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1869 IIC_iMAC32, "smmls", "\t$dst, $a, $b, $c", 1870 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, 1871 Requires<[IsARM, HasV6]> { 1872 let Inst{7-4} = 0b1101; 1873} 1874 1875def SMMLSR : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1876 IIC_iMAC32, "smmlsr", "\t$dst, $a, $b, $c", 1877 [/* For disassembly only; pattern left blank */]>, 1878 Requires<[IsARM, HasV6]> { 1879 let Inst{7-4} = 0b1111; // R = 1 1880} 1881 1882multiclass AI_smul<string opc, PatFrag opnode> { 1883 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1884 IIC_iMUL32, !strconcat(opc, "bb"), "\t$dst, $a, $b", 1885 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1886 (sext_inreg GPR:$b, i16)))]>, 1887 Requires<[IsARM, HasV5TE]> { 1888 let Inst{5} = 0; 1889 let Inst{6} = 0; 1890 } 1891 1892 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1893 IIC_iMUL32, !strconcat(opc, "bt"), "\t$dst, $a, $b", 1894 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1895 (sra GPR:$b, (i32 16))))]>, 1896 Requires<[IsARM, HasV5TE]> { 1897 let Inst{5} = 0; 1898 let Inst{6} = 1; 1899 } 1900 1901 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1902 IIC_iMUL32, !strconcat(opc, "tb"), "\t$dst, $a, $b", 1903 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1904 (sext_inreg GPR:$b, i16)))]>, 1905 Requires<[IsARM, HasV5TE]> { 1906 let Inst{5} = 1; 1907 let Inst{6} = 0; 1908 } 1909 1910 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1911 IIC_iMUL32, !strconcat(opc, "tt"), "\t$dst, $a, $b", 1912 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1913 (sra GPR:$b, (i32 16))))]>, 1914 Requires<[IsARM, HasV5TE]> { 1915 let Inst{5} = 1; 1916 let Inst{6} = 1; 1917 } 1918 1919 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1920 IIC_iMUL16, !strconcat(opc, "wb"), "\t$dst, $a, $b", 1921 [(set GPR:$dst, (sra (opnode GPR:$a, 1922 (sext_inreg GPR:$b, i16)), (i32 16)))]>, 1923 Requires<[IsARM, HasV5TE]> { 1924 let Inst{5} = 1; 1925 let Inst{6} = 0; 1926 } 1927 1928 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1929 IIC_iMUL16, !strconcat(opc, "wt"), "\t$dst, $a, $b", 1930 [(set GPR:$dst, (sra (opnode GPR:$a, 1931 (sra GPR:$b, (i32 16))), (i32 16)))]>, 1932 Requires<[IsARM, HasV5TE]> { 1933 let Inst{5} = 1; 1934 let Inst{6} = 1; 1935 } 1936} 1937 1938 1939multiclass AI_smla<string opc, PatFrag opnode> { 1940 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1941 IIC_iMAC16, !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc", 1942 [(set GPR:$dst, (add GPR:$acc, 1943 (opnode (sext_inreg GPR:$a, i16), 1944 (sext_inreg GPR:$b, i16))))]>, 1945 Requires<[IsARM, HasV5TE]> { 1946 let Inst{5} = 0; 1947 let Inst{6} = 0; 1948 } 1949 1950 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1951 IIC_iMAC16, !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc", 1952 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 1953 (sra GPR:$b, (i32 16)))))]>, 1954 Requires<[IsARM, HasV5TE]> { 1955 let Inst{5} = 0; 1956 let Inst{6} = 1; 1957 } 1958 1959 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1960 IIC_iMAC16, !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc", 1961 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1962 (sext_inreg GPR:$b, i16))))]>, 1963 Requires<[IsARM, HasV5TE]> { 1964 let Inst{5} = 1; 1965 let Inst{6} = 0; 1966 } 1967 1968 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1969 IIC_iMAC16, !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc", 1970 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1971 (sra GPR:$b, (i32 16)))))]>, 1972 Requires<[IsARM, HasV5TE]> { 1973 let Inst{5} = 1; 1974 let Inst{6} = 1; 1975 } 1976 1977 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1978 IIC_iMAC16, !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc", 1979 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1980 (sext_inreg GPR:$b, i16)), (i32 16))))]>, 1981 Requires<[IsARM, HasV5TE]> { 1982 let Inst{5} = 0; 1983 let Inst{6} = 0; 1984 } 1985 1986 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1987 IIC_iMAC16, !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc", 1988 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1989 (sra GPR:$b, (i32 16))), (i32 16))))]>, 1990 Requires<[IsARM, HasV5TE]> { 1991 let Inst{5} = 0; 1992 let Inst{6} = 1; 1993 } 1994} 1995 1996defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1997defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1998 1999// Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only 2000def SMLALBB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), 2001 IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b", 2002 [/* For disassembly only; pattern left blank */]>, 2003 Requires<[IsARM, HasV5TE]> { 2004 let Inst{5} = 0; 2005 let Inst{6} = 0; 2006} 2007 2008def SMLALBT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), 2009 IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b", 2010 [/* For disassembly only; pattern left blank */]>, 2011 Requires<[IsARM, HasV5TE]> { 2012 let Inst{5} = 0; 2013 let Inst{6} = 1; 2014} 2015 2016def SMLALTB : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), 2017 IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b", 2018 [/* For disassembly only; pattern left blank */]>, 2019 Requires<[IsARM, HasV5TE]> { 2020 let Inst{5} = 1; 2021 let Inst{6} = 0; 2022} 2023 2024def SMLALTT : AMulxyI<0b0001010,(outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), 2025 IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b", 2026 [/* For disassembly only; pattern left blank */]>, 2027 Requires<[IsARM, HasV5TE]> { 2028 let Inst{5} = 1; 2029 let Inst{6} = 1; 2030} 2031 2032// Helper class for AI_smld -- for disassembly only 2033class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 2034 InstrItinClass itin, string opc, string asm> 2035 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { 2036 let Inst{4} = 1; 2037 let Inst{5} = swap; 2038 let Inst{6} = sub; 2039 let Inst{7} = 0; 2040 let Inst{21-20} = 0b00; 2041 let Inst{22} = long; 2042 let Inst{27-23} = 0b01110; 2043} 2044 2045multiclass AI_smld<bit sub, string opc> { 2046 2047 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 2048 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b, $acc">; 2049 2050 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 2051 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b, $acc">; 2052 2053 def LD : AMulDualI<1, sub, 0, (outs GPR:$ldst,GPR:$hdst), (ins GPR:$a,GPR:$b), 2054 NoItinerary, !strconcat(opc, "ld"), "\t$ldst, $hdst, $a, $b">; 2055 2056 def LDX : AMulDualI<1, sub, 1, (outs GPR:$ldst,GPR:$hdst),(ins GPR:$a,GPR:$b), 2057 NoItinerary, !strconcat(opc, "ldx"),"\t$ldst, $hdst, $a, $b">; 2058 2059} 2060 2061defm SMLA : AI_smld<0, "smla">; 2062defm SMLS : AI_smld<1, "smls">; 2063 2064multiclass AI_sdml<bit sub, string opc> { 2065 2066 def D : AMulDualI<0, sub, 0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 2067 NoItinerary, !strconcat(opc, "d"), "\t$dst, $a, $b"> { 2068 let Inst{15-12} = 0b1111; 2069 } 2070 2071 def DX : AMulDualI<0, sub, 1, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 2072 NoItinerary, !strconcat(opc, "dx"), "\t$dst, $a, $b"> { 2073 let Inst{15-12} = 0b1111; 2074 } 2075 2076} 2077 2078defm SMUA : AI_sdml<0, "smua">; 2079defm SMUS : AI_sdml<1, "smus">; 2080 2081//===----------------------------------------------------------------------===// 2082// Misc. Arithmetic Instructions. 2083// 2084 2085def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2086 "clz", "\t$dst, $src", 2087 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> { 2088 let Inst{7-4} = 0b0001; 2089 let Inst{11-8} = 0b1111; 2090 let Inst{19-16} = 0b1111; 2091} 2092 2093def RBIT : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2094 "rbit", "\t$dst, $src", 2095 [(set GPR:$dst, (ARMrbit GPR:$src))]>, 2096 Requires<[IsARM, HasV6T2]> { 2097 let Inst{7-4} = 0b0011; 2098 let Inst{11-8} = 0b1111; 2099 let Inst{19-16} = 0b1111; 2100} 2101 2102def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2103 "rev", "\t$dst, $src", 2104 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> { 2105 let Inst{7-4} = 0b0011; 2106 let Inst{11-8} = 0b1111; 2107 let Inst{19-16} = 0b1111; 2108} 2109 2110def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2111 "rev16", "\t$dst, $src", 2112 [(set GPR:$dst, 2113 (or (and (srl GPR:$src, (i32 8)), 0xFF), 2114 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 2115 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 2116 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>, 2117 Requires<[IsARM, HasV6]> { 2118 let Inst{7-4} = 0b1011; 2119 let Inst{11-8} = 0b1111; 2120 let Inst{19-16} = 0b1111; 2121} 2122 2123def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2124 "revsh", "\t$dst, $src", 2125 [(set GPR:$dst, 2126 (sext_inreg 2127 (or (srl (and GPR:$src, 0xFF00), (i32 8)), 2128 (shl GPR:$src, (i32 8))), i16))]>, 2129 Requires<[IsARM, HasV6]> { 2130 let Inst{7-4} = 0b1011; 2131 let Inst{11-8} = 0b1111; 2132 let Inst{19-16} = 0b1111; 2133} 2134 2135def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst), 2136 (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 2137 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt", 2138 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 2139 (and (shl GPR:$src2, (i32 imm:$shamt)), 2140 0xFFFF0000)))]>, 2141 Requires<[IsARM, HasV6]> { 2142 let Inst{6-4} = 0b001; 2143} 2144 2145// Alternate cases for PKHBT where identities eliminate some nodes. 2146def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 2147 (PKHBT GPR:$src1, GPR:$src2, 0)>; 2148def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 2149 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 2150 2151 2152def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst), 2153 (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 2154 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt", 2155 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 2156 (and (sra GPR:$src2, imm16_31:$shamt), 2157 0xFFFF)))]>, Requires<[IsARM, HasV6]> { 2158 let Inst{6-4} = 0b101; 2159} 2160 2161// Alternate cases for PKHTB where identities eliminate some nodes. Note that 2162// a shift amount of 0 is *not legal* here, it is PKHBT instead. 2163def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 2164 (PKHTB GPR:$src1, GPR:$src2, 16)>; 2165def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), 2166 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 2167 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 2168 2169//===----------------------------------------------------------------------===// 2170// Comparison Instructions... 2171// 2172 2173defm CMP : AI1_cmp_irs<0b1010, "cmp", 2174 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 2175//FIXME: Disable CMN, as CCodes are backwards from compare expectations 2176// Compare-to-zero still works out, just not the relationals 2177//defm CMN : AI1_cmp_irs<0b1011, "cmn", 2178// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 2179 2180// Note that TST/TEQ don't set all the same flags that CMP does! 2181defm TST : AI1_cmp_irs<0b1000, "tst", 2182 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>; 2183defm TEQ : AI1_cmp_irs<0b1001, "teq", 2184 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>; 2185 2186defm CMPz : AI1_cmp_irs<0b1010, "cmp", 2187 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 2188defm CMNz : AI1_cmp_irs<0b1011, "cmn", 2189 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 2190 2191//def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 2192// (CMNri GPR:$src, so_imm_neg:$imm)>; 2193 2194def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), 2195 (CMNzri GPR:$src, so_imm_neg:$imm)>; 2196 2197 2198// Conditional moves 2199// FIXME: should be able to write a pattern for ARMcmov, but can't use 2200// a two-value operand where a dag node expects two operands. :( 2201def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, 2202 IIC_iCMOVr, "mov", "\t$dst, $true", 2203 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 2204 RegConstraint<"$false = $dst">, UnaryDP { 2205 let Inst{11-4} = 0b00000000; 2206 let Inst{25} = 0; 2207} 2208 2209def MOVCCs : AI1<0b1101, (outs GPR:$dst), 2210 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr, 2211 "mov", "\t$dst, $true", 2212 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 2213 RegConstraint<"$false = $dst">, UnaryDP { 2214 let Inst{25} = 0; 2215} 2216 2217def MOVCCi : AI1<0b1101, (outs GPR:$dst), 2218 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi, 2219 "mov", "\t$dst, $true", 2220 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 2221 RegConstraint<"$false = $dst">, UnaryDP { 2222 let Inst{25} = 1; 2223} 2224 2225//===----------------------------------------------------------------------===// 2226// Atomic operations intrinsics 2227// 2228 2229// memory barriers protect the atomic sequences 2230let hasSideEffects = 1 in { 2231def Int_MemBarrierV7 : AInoP<(outs), (ins), 2232 Pseudo, NoItinerary, 2233 "dmb", "", 2234 [(ARMMemBarrierV7)]>, 2235 Requires<[IsARM, HasV7]> { 2236 let Inst{31-4} = 0xf57ff05; 2237 // FIXME: add support for options other than a full system DMB 2238 // See DMB disassembly-only variants below. 2239 let Inst{3-0} = 0b1111; 2240} 2241 2242def Int_SyncBarrierV7 : AInoP<(outs), (ins), 2243 Pseudo, NoItinerary, 2244 "dsb", "", 2245 [(ARMSyncBarrierV7)]>, 2246 Requires<[IsARM, HasV7]> { 2247 let Inst{31-4} = 0xf57ff04; 2248 // FIXME: add support for options other than a full system DSB 2249 // See DSB disassembly-only variants below. 2250 let Inst{3-0} = 0b1111; 2251} 2252 2253def Int_MemBarrierV6 : AInoP<(outs), (ins GPR:$zero), 2254 Pseudo, NoItinerary, 2255 "mcr", "\tp15, 0, $zero, c7, c10, 5", 2256 [(ARMMemBarrierV6 GPR:$zero)]>, 2257 Requires<[IsARM, HasV6]> { 2258 // FIXME: add support for options other than a full system DMB 2259 // FIXME: add encoding 2260} 2261 2262def Int_SyncBarrierV6 : AInoP<(outs), (ins GPR:$zero), 2263 Pseudo, NoItinerary, 2264 "mcr", "\tp15, 0, $zero, c7, c10, 4", 2265 [(ARMSyncBarrierV6 GPR:$zero)]>, 2266 Requires<[IsARM, HasV6]> { 2267 // FIXME: add support for options other than a full system DSB 2268 // FIXME: add encoding 2269} 2270} 2271 2272// Helper class for multiclass MemB -- for disassembly only 2273class AMBI<string opc, string asm> 2274 : AInoP<(outs), (ins), MiscFrm, NoItinerary, opc, asm, 2275 [/* For disassembly only; pattern left blank */]>, 2276 Requires<[IsARM, HasV7]> { 2277 let Inst{31-20} = 0xf57; 2278} 2279 2280multiclass MemB<bits<4> op7_4, string opc> { 2281 2282 def st : AMBI<opc, "\tst"> { 2283 let Inst{7-4} = op7_4; 2284 let Inst{3-0} = 0b1110; 2285 } 2286 2287 def ish : AMBI<opc, "\tish"> { 2288 let Inst{7-4} = op7_4; 2289 let Inst{3-0} = 0b1011; 2290 } 2291 2292 def ishst : AMBI<opc, "\tishst"> { 2293 let Inst{7-4} = op7_4; 2294 let Inst{3-0} = 0b1010; 2295 } 2296 2297 def nsh : AMBI<opc, "\tnsh"> { 2298 let Inst{7-4} = op7_4; 2299 let Inst{3-0} = 0b0111; 2300 } 2301 2302 def nshst : AMBI<opc, "\tnshst"> { 2303 let Inst{7-4} = op7_4; 2304 let Inst{3-0} = 0b0110; 2305 } 2306 2307 def osh : AMBI<opc, "\tosh"> { 2308 let Inst{7-4} = op7_4; 2309 let Inst{3-0} = 0b0011; 2310 } 2311 2312 def oshst : AMBI<opc, "\toshst"> { 2313 let Inst{7-4} = op7_4; 2314 let Inst{3-0} = 0b0010; 2315 } 2316} 2317 2318// These DMB variants are for disassembly only. 2319defm DMB : MemB<0b0101, "dmb">; 2320 2321// These DSB variants are for disassembly only. 2322defm DSB : MemB<0b0100, "dsb">; 2323 2324// ISB has only full system option -- for disassembly only 2325def ISBsy : AMBI<"isb", ""> { 2326 let Inst{7-4} = 0b0110; 2327 let Inst{3-0} = 0b1111; 2328} 2329 2330let usesCustomInserter = 1 in { 2331 let Uses = [CPSR] in { 2332 def ATOMIC_LOAD_ADD_I8 : PseudoInst< 2333 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2334 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!", 2335 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>; 2336 def ATOMIC_LOAD_SUB_I8 : PseudoInst< 2337 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2338 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!", 2339 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>; 2340 def ATOMIC_LOAD_AND_I8 : PseudoInst< 2341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2342 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!", 2343 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>; 2344 def ATOMIC_LOAD_OR_I8 : PseudoInst< 2345 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2346 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!", 2347 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>; 2348 def ATOMIC_LOAD_XOR_I8 : PseudoInst< 2349 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2350 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!", 2351 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>; 2352 def ATOMIC_LOAD_NAND_I8 : PseudoInst< 2353 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2354 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!", 2355 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>; 2356 def ATOMIC_LOAD_ADD_I16 : PseudoInst< 2357 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2358 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!", 2359 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>; 2360 def ATOMIC_LOAD_SUB_I16 : PseudoInst< 2361 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2362 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!", 2363 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>; 2364 def ATOMIC_LOAD_AND_I16 : PseudoInst< 2365 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2366 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!", 2367 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>; 2368 def ATOMIC_LOAD_OR_I16 : PseudoInst< 2369 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2370 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!", 2371 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>; 2372 def ATOMIC_LOAD_XOR_I16 : PseudoInst< 2373 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2374 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!", 2375 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>; 2376 def ATOMIC_LOAD_NAND_I16 : PseudoInst< 2377 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2378 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!", 2379 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>; 2380 def ATOMIC_LOAD_ADD_I32 : PseudoInst< 2381 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2382 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!", 2383 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>; 2384 def ATOMIC_LOAD_SUB_I32 : PseudoInst< 2385 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2386 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!", 2387 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>; 2388 def ATOMIC_LOAD_AND_I32 : PseudoInst< 2389 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2390 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!", 2391 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>; 2392 def ATOMIC_LOAD_OR_I32 : PseudoInst< 2393 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2394 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!", 2395 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>; 2396 def ATOMIC_LOAD_XOR_I32 : PseudoInst< 2397 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2398 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!", 2399 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>; 2400 def ATOMIC_LOAD_NAND_I32 : PseudoInst< 2401 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary, 2402 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!", 2403 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>; 2404 2405 def ATOMIC_SWAP_I8 : PseudoInst< 2406 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 2407 "${:comment} ATOMIC_SWAP_I8 PSEUDO!", 2408 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>; 2409 def ATOMIC_SWAP_I16 : PseudoInst< 2410 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 2411 "${:comment} ATOMIC_SWAP_I16 PSEUDO!", 2412 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>; 2413 def ATOMIC_SWAP_I32 : PseudoInst< 2414 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary, 2415 "${:comment} ATOMIC_SWAP_I32 PSEUDO!", 2416 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>; 2417 2418 def ATOMIC_CMP_SWAP_I8 : PseudoInst< 2419 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 2420 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!", 2421 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>; 2422 def ATOMIC_CMP_SWAP_I16 : PseudoInst< 2423 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 2424 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!", 2425 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>; 2426 def ATOMIC_CMP_SWAP_I32 : PseudoInst< 2427 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary, 2428 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!", 2429 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>; 2430} 2431} 2432 2433let mayLoad = 1 in { 2434def LDREXB : AIldrex<0b10, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, 2435 "ldrexb", "\t$dest, [$ptr]", 2436 []>; 2437def LDREXH : AIldrex<0b11, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, 2438 "ldrexh", "\t$dest, [$ptr]", 2439 []>; 2440def LDREX : AIldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), NoItinerary, 2441 "ldrex", "\t$dest, [$ptr]", 2442 []>; 2443def LDREXD : AIldrex<0b01, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr), 2444 NoItinerary, 2445 "ldrexd", "\t$dest, $dest2, [$ptr]", 2446 []>; 2447} 2448 2449let mayStore = 1, Constraints = "@earlyclobber $success" in { 2450def STREXB : AIstrex<0b10, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2451 NoItinerary, 2452 "strexb", "\t$success, $src, [$ptr]", 2453 []>; 2454def STREXH : AIstrex<0b11, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2455 NoItinerary, 2456 "strexh", "\t$success, $src, [$ptr]", 2457 []>; 2458def STREX : AIstrex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2459 NoItinerary, 2460 "strex", "\t$success, $src, [$ptr]", 2461 []>; 2462def STREXD : AIstrex<0b01, (outs GPR:$success), 2463 (ins GPR:$src, GPR:$src2, GPR:$ptr), 2464 NoItinerary, 2465 "strexd", "\t$success, $src, $src2, [$ptr]", 2466 []>; 2467} 2468 2469// Clear-Exclusive is for disassembly only. 2470def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 2471 [/* For disassembly only; pattern left blank */]>, 2472 Requires<[IsARM, HasV7]> { 2473 let Inst{31-20} = 0xf57; 2474 let Inst{7-4} = 0b0001; 2475} 2476 2477// SWP/SWPB are deprecated in V6/V7 and for disassembly only. 2478let mayLoad = 1 in { 2479def SWP : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary, 2480 "swp", "\t$dst, $src, [$ptr]", 2481 [/* For disassembly only; pattern left blank */]> { 2482 let Inst{27-23} = 0b00010; 2483 let Inst{22} = 0; // B = 0 2484 let Inst{21-20} = 0b00; 2485 let Inst{7-4} = 0b1001; 2486} 2487 2488def SWPB : AI<(outs GPR:$dst), (ins GPR:$src, GPR:$ptr), LdStExFrm, NoItinerary, 2489 "swpb", "\t$dst, $src, [$ptr]", 2490 [/* For disassembly only; pattern left blank */]> { 2491 let Inst{27-23} = 0b00010; 2492 let Inst{22} = 1; // B = 1 2493 let Inst{21-20} = 0b00; 2494 let Inst{7-4} = 0b1001; 2495} 2496} 2497 2498//===----------------------------------------------------------------------===// 2499// TLS Instructions 2500// 2501 2502// __aeabi_read_tp preserves the registers r1-r3. 2503let isCall = 1, 2504 Defs = [R0, R12, LR, CPSR] in { 2505 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br, 2506 "bl\t__aeabi_read_tp", 2507 [(set R0, ARMthread_pointer)]>; 2508} 2509 2510//===----------------------------------------------------------------------===// 2511// SJLJ Exception handling intrinsics 2512// eh_sjlj_setjmp() is an instruction sequence to store the return 2513// address and save #0 in R0 for the non-longjmp case. 2514// Since by its nature we may be coming from some other function to get 2515// here, and we're using the stack frame for the containing function to 2516// save/restore registers, we can't keep anything live in regs across 2517// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 2518// when we get here from a longjmp(). We force everthing out of registers 2519// except for our own input by listing the relevant registers in Defs. By 2520// doing so, we also cause the prologue/epilogue code to actively preserve 2521// all of the callee-saved resgisters, which is exactly what we want. 2522// A constant value is passed in $val, and we use the location as a scratch. 2523let Defs = 2524 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, 2525 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 2526 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, 2527 D31 ] in { 2528 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val), 2529 AddrModeNone, SizeSpecial, IndexModeNone, 2530 Pseudo, NoItinerary, 2531 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t" 2532 "add\t$val, pc, #8\n\t" 2533 "str\t$val, [$src, #+4]\n\t" 2534 "mov\tr0, #0\n\t" 2535 "add\tpc, pc, #0\n\t" 2536 "mov\tr0, #1 @ eh_setjmp end", "", 2537 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 2538 Requires<[IsARM, HasVFP2]>; 2539} 2540 2541let Defs = 2542 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ] in { 2543 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val), 2544 AddrModeNone, SizeSpecial, IndexModeNone, 2545 Pseudo, NoItinerary, 2546 "str\tsp, [$src, #+8] @ eh_setjmp begin\n\t" 2547 "add\t$val, pc, #8\n\t" 2548 "str\t$val, [$src, #+4]\n\t" 2549 "mov\tr0, #0\n\t" 2550 "add\tpc, pc, #0\n\t" 2551 "mov\tr0, #1 @ eh_setjmp end", "", 2552 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 2553 Requires<[IsARM, NoVFP]>; 2554} 2555 2556//===----------------------------------------------------------------------===// 2557// Non-Instruction Patterns 2558// 2559 2560// Large immediate handling. 2561 2562// Two piece so_imms. 2563let isReMaterializable = 1 in 2564def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), 2565 Pseudo, IIC_iMOVi, 2566 "mov", "\t$dst, $src", 2567 [(set GPR:$dst, so_imm2part:$src)]>, 2568 Requires<[IsARM, NoV6T2]>; 2569 2570def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), 2571 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 2572 (so_imm2part_2 imm:$RHS))>; 2573def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), 2574 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 2575 (so_imm2part_2 imm:$RHS))>; 2576def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS), 2577 (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 2578 (so_imm2part_2 imm:$RHS))>; 2579def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS), 2580 (SUBri (SUBri GPR:$LHS, (so_neg_imm2part_1 imm:$RHS)), 2581 (so_neg_imm2part_2 imm:$RHS))>; 2582 2583// 32-bit immediate using movw + movt. 2584// This is a single pseudo instruction, the benefit is that it can be remat'd 2585// as a single unit instead of having to handle reg inputs. 2586// FIXME: Remove this when we can do generalized remat. 2587let isReMaterializable = 1 in 2588def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi, 2589 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}", 2590 [(set GPR:$dst, (i32 imm:$src))]>, 2591 Requires<[IsARM, HasV6T2]>; 2592 2593// ConstantPool, GlobalAddress, and JumpTable 2594def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>, 2595 Requires<[IsARM, DontUseMovt]>; 2596def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 2597def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 2598 Requires<[IsARM, UseMovt]>; 2599def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 2600 (LEApcrelJT tjumptable:$dst, imm:$id)>; 2601 2602// TODO: add,sub,and, 3-instr forms? 2603 2604 2605// Direct calls 2606def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>, 2607 Requires<[IsARM, IsNotDarwin]>; 2608def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>, 2609 Requires<[IsARM, IsDarwin]>; 2610 2611// zextload i1 -> zextload i8 2612def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 2613 2614// extload -> zextload 2615def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 2616def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; 2617def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 2618 2619def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 2620def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 2621 2622// smul* and smla* 2623def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 2624 (sra (shl GPR:$b, (i32 16)), (i32 16))), 2625 (SMULBB GPR:$a, GPR:$b)>; 2626def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 2627 (SMULBB GPR:$a, GPR:$b)>; 2628def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 2629 (sra GPR:$b, (i32 16))), 2630 (SMULBT GPR:$a, GPR:$b)>; 2631def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 2632 (SMULBT GPR:$a, GPR:$b)>; 2633def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 2634 (sra (shl GPR:$b, (i32 16)), (i32 16))), 2635 (SMULTB GPR:$a, GPR:$b)>; 2636def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 2637 (SMULTB GPR:$a, GPR:$b)>; 2638def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 2639 (i32 16)), 2640 (SMULWB GPR:$a, GPR:$b)>; 2641def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 2642 (SMULWB GPR:$a, GPR:$b)>; 2643 2644def : ARMV5TEPat<(add GPR:$acc, 2645 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 2646 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 2647 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 2648def : ARMV5TEPat<(add GPR:$acc, 2649 (mul sext_16_node:$a, sext_16_node:$b)), 2650 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 2651def : ARMV5TEPat<(add GPR:$acc, 2652 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 2653 (sra GPR:$b, (i32 16)))), 2654 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 2655def : ARMV5TEPat<(add GPR:$acc, 2656 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 2657 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 2658def : ARMV5TEPat<(add GPR:$acc, 2659 (mul (sra GPR:$a, (i32 16)), 2660 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 2661 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 2662def : ARMV5TEPat<(add GPR:$acc, 2663 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 2664 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 2665def : ARMV5TEPat<(add GPR:$acc, 2666 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 2667 (i32 16))), 2668 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 2669def : ARMV5TEPat<(add GPR:$acc, 2670 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 2671 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 2672 2673//===----------------------------------------------------------------------===// 2674// Thumb Support 2675// 2676 2677include "ARMInstrThumb.td" 2678 2679//===----------------------------------------------------------------------===// 2680// Thumb2 Support 2681// 2682 2683include "ARMInstrThumb2.td" 2684 2685//===----------------------------------------------------------------------===// 2686// Floating Point Support 2687// 2688 2689include "ARMInstrVFP.td" 2690 2691//===----------------------------------------------------------------------===// 2692// Advanced SIMD (NEON) Support 2693// 2694 2695include "ARMInstrNEON.td" 2696 2697//===----------------------------------------------------------------------===// 2698// Coprocessor Instructions. For disassembly only. 2699// 2700 2701def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 2702 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 2703 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2", 2704 [/* For disassembly only; pattern left blank */]> { 2705 let Inst{4} = 0; 2706} 2707 2708def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 2709 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 2710 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2", 2711 [/* For disassembly only; pattern left blank */]> { 2712 let Inst{31-28} = 0b1111; 2713 let Inst{4} = 0; 2714} 2715 2716class ACI<dag oops, dag iops, string opc, string asm> 2717 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary, 2718 opc, asm, "", [/* For disassembly only; pattern left blank */]> { 2719 let Inst{27-25} = 0b110; 2720} 2721 2722multiclass LdStCop<bits<4> op31_28, bit load, string opc> { 2723 2724 def _OFFSET : ACI<(outs), 2725 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 2726 opc, "\tp$cop, cr$CRd, $addr"> { 2727 let Inst{31-28} = op31_28; 2728 let Inst{24} = 1; // P = 1 2729 let Inst{21} = 0; // W = 0 2730 let Inst{22} = 0; // D = 0 2731 let Inst{20} = load; 2732 } 2733 2734 def _PRE : ACI<(outs), 2735 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 2736 opc, "\tp$cop, cr$CRd, $addr!"> { 2737 let Inst{31-28} = op31_28; 2738 let Inst{24} = 1; // P = 1 2739 let Inst{21} = 1; // W = 1 2740 let Inst{22} = 0; // D = 0 2741 let Inst{20} = load; 2742 } 2743 2744 def _POST : ACI<(outs), 2745 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset), 2746 opc, "\tp$cop, cr$CRd, [$base], $offset"> { 2747 let Inst{31-28} = op31_28; 2748 let Inst{24} = 0; // P = 0 2749 let Inst{21} = 1; // W = 1 2750 let Inst{22} = 0; // D = 0 2751 let Inst{20} = load; 2752 } 2753 2754 def _OPTION : ACI<(outs), 2755 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option), 2756 opc, "\tp$cop, cr$CRd, [$base], $option"> { 2757 let Inst{31-28} = op31_28; 2758 let Inst{24} = 0; // P = 0 2759 let Inst{23} = 1; // U = 1 2760 let Inst{21} = 0; // W = 0 2761 let Inst{22} = 0; // D = 0 2762 let Inst{20} = load; 2763 } 2764 2765 def L_OFFSET : ACI<(outs), 2766 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 2767 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> { 2768 let Inst{31-28} = op31_28; 2769 let Inst{24} = 1; // P = 1 2770 let Inst{21} = 0; // W = 0 2771 let Inst{22} = 1; // D = 1 2772 let Inst{20} = load; 2773 } 2774 2775 def L_PRE : ACI<(outs), 2776 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 2777 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> { 2778 let Inst{31-28} = op31_28; 2779 let Inst{24} = 1; // P = 1 2780 let Inst{21} = 1; // W = 1 2781 let Inst{22} = 1; // D = 1 2782 let Inst{20} = load; 2783 } 2784 2785 def L_POST : ACI<(outs), 2786 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset), 2787 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> { 2788 let Inst{31-28} = op31_28; 2789 let Inst{24} = 0; // P = 0 2790 let Inst{21} = 1; // W = 1 2791 let Inst{22} = 1; // D = 1 2792 let Inst{20} = load; 2793 } 2794 2795 def L_OPTION : ACI<(outs), 2796 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option), 2797 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> { 2798 let Inst{31-28} = op31_28; 2799 let Inst{24} = 0; // P = 0 2800 let Inst{23} = 1; // U = 1 2801 let Inst{21} = 0; // W = 0 2802 let Inst{22} = 1; // D = 1 2803 let Inst{20} = load; 2804 } 2805} 2806 2807defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">; 2808defm LDC2 : LdStCop<0b1111, 1, "ldc2">; 2809defm STC : LdStCop<{?,?,?,?}, 0, "stc">; 2810defm STC2 : LdStCop<0b1111, 0, "stc2">; 2811 2812def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 2813 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 2814 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 2815 [/* For disassembly only; pattern left blank */]> { 2816 let Inst{20} = 0; 2817 let Inst{4} = 1; 2818} 2819 2820def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 2821 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 2822 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 2823 [/* For disassembly only; pattern left blank */]> { 2824 let Inst{31-28} = 0b1111; 2825 let Inst{20} = 0; 2826 let Inst{4} = 1; 2827} 2828 2829def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 2830 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 2831 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 2832 [/* For disassembly only; pattern left blank */]> { 2833 let Inst{20} = 1; 2834 let Inst{4} = 1; 2835} 2836 2837def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, 2838 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), 2839 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", 2840 [/* For disassembly only; pattern left blank */]> { 2841 let Inst{31-28} = 0b1111; 2842 let Inst{20} = 1; 2843 let Inst{4} = 1; 2844} 2845 2846def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 2847 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 2848 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 2849 [/* For disassembly only; pattern left blank */]> { 2850 let Inst{23-20} = 0b0100; 2851} 2852 2853def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 2854 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 2855 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 2856 [/* For disassembly only; pattern left blank */]> { 2857 let Inst{31-28} = 0b1111; 2858 let Inst{23-20} = 0b0100; 2859} 2860 2861def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 2862 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 2863 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 2864 [/* For disassembly only; pattern left blank */]> { 2865 let Inst{23-20} = 0b0101; 2866} 2867 2868def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, 2869 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), 2870 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", 2871 [/* For disassembly only; pattern left blank */]> { 2872 let Inst{31-28} = 0b1111; 2873 let Inst{23-20} = 0b0101; 2874} 2875 2876//===----------------------------------------------------------------------===// 2877// Move between special register and ARM core register -- for disassembly only 2878// 2879 2880def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr", 2881 [/* For disassembly only; pattern left blank */]> { 2882 let Inst{23-20} = 0b0000; 2883 let Inst{7-4} = 0b0000; 2884} 2885 2886def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr", 2887 [/* For disassembly only; pattern left blank */]> { 2888 let Inst{23-20} = 0b0100; 2889 let Inst{7-4} = 0b0000; 2890} 2891 2892def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, 2893 "msr", "\tcpsr$mask, $src", 2894 [/* For disassembly only; pattern left blank */]> { 2895 let Inst{23-20} = 0b0010; 2896 let Inst{7-4} = 0b0000; 2897} 2898 2899def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary, 2900 "msr", "\tcpsr$mask, $a", 2901 [/* For disassembly only; pattern left blank */]> { 2902 let Inst{23-20} = 0b0010; 2903 let Inst{7-4} = 0b0000; 2904} 2905 2906def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, 2907 "msr", "\tspsr$mask, $src", 2908 [/* For disassembly only; pattern left blank */]> { 2909 let Inst{23-20} = 0b0110; 2910 let Inst{7-4} = 0b0000; 2911} 2912 2913def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary, 2914 "msr", "\tspsr$mask, $a", 2915 [/* For disassembly only; pattern left blank */]> { 2916 let Inst{23-20} = 0b0110; 2917 let Inst{7-4} = 0b0000; 2918} 2919