ARMInstrInfo.td revision 195098
1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21 22def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 23 24def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 25 26def SDT_ARMCMov : SDTypeProfile<1, 3, 27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 28 SDTCisVT<3, i32>]>; 29 30def SDT_ARMBrcond : SDTypeProfile<0, 2, 31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 32 33def SDT_ARMBrJT : SDTypeProfile<0, 3, 34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 35 SDTCisVT<2, i32>]>; 36 37def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 38 39def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 41 42def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 43def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 44 45// Node definitions. 46def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 47def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 48 49def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 50 [SDNPHasChain, SDNPOutFlag]>; 51def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 53 54def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 56def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 58def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 60 61def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 62 [SDNPHasChain, SDNPOptInFlag]>; 63 64def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 65 [SDNPInFlag]>; 66def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, 67 [SDNPInFlag]>; 68 69def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; 71 72def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 73 [SDNPHasChain]>; 74 75def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 76 [SDNPOutFlag]>; 77 78def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp, 79 [SDNPOutFlag]>; 80 81def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 82 83def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 84def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 85def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; 86 87def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 88def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>; 89 90//===----------------------------------------------------------------------===// 91// ARM Instruction Predicate Definitions. 92// 93def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 94def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; 95def HasV6 : Predicate<"Subtarget->hasV6Ops()">; 96def HasV7 : Predicate<"Subtarget->hasV7Ops()">; 97def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; 98def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; 99def HasNEON : Predicate<"Subtarget->hasNEON()">; 100def IsThumb : Predicate<"Subtarget->isThumb()">; 101def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 102def HasThumb2 : Predicate<"Subtarget->hasThumb2()">; 103def IsARM : Predicate<"!Subtarget->isThumb()">; 104def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">; 105def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">; 106def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">; 107def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">; 108 109//===----------------------------------------------------------------------===// 110// ARM Flag Definitions. 111 112class RegConstraint<string C> { 113 string Constraints = C; 114} 115 116//===----------------------------------------------------------------------===// 117// ARM specific transformation functions and pattern fragments. 118// 119 120// so_imm_XFORM - Return a so_imm value packed into the format described for 121// so_imm def below. 122def so_imm_XFORM : SDNodeXForm<imm, [{ 123 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()), 124 MVT::i32); 125}]>; 126 127// so_imm_neg_XFORM - Return a so_imm value packed into the format described for 128// so_imm_neg def below. 129def so_imm_neg_XFORM : SDNodeXForm<imm, [{ 130 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()), 131 MVT::i32); 132}]>; 133 134// so_imm_not_XFORM - Return a so_imm value packed into the format described for 135// so_imm_not def below. 136def so_imm_not_XFORM : SDNodeXForm<imm, [{ 137 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()), 138 MVT::i32); 139}]>; 140 141// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. 142def rot_imm : PatLeaf<(i32 imm), [{ 143 int32_t v = (int32_t)N->getZExtValue(); 144 return v == 8 || v == 16 || v == 24; 145}]>; 146 147/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. 148def imm1_15 : PatLeaf<(i32 imm), [{ 149 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16; 150}]>; 151 152/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 153def imm16_31 : PatLeaf<(i32 imm), [{ 154 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32; 155}]>; 156 157def so_imm_neg : 158 PatLeaf<(imm), [{ 159 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1; 160 }], so_imm_neg_XFORM>; 161 162def so_imm_not : 163 PatLeaf<(imm), [{ 164 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1; 165 }], so_imm_not_XFORM>; 166 167// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 168def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 169 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 170}]>; 171 172class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 173class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 174 175//===----------------------------------------------------------------------===// 176// Operand Definitions. 177// 178 179// Branch target. 180def brtarget : Operand<OtherVT>; 181 182// A list of registers separated by comma. Used by load/store multiple. 183def reglist : Operand<i32> { 184 let PrintMethod = "printRegisterList"; 185} 186 187// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 188def cpinst_operand : Operand<i32> { 189 let PrintMethod = "printCPInstOperand"; 190} 191 192def jtblock_operand : Operand<i32> { 193 let PrintMethod = "printJTBlockOperand"; 194} 195 196// Local PC labels. 197def pclabel : Operand<i32> { 198 let PrintMethod = "printPCLabel"; 199} 200 201// shifter_operand operands: so_reg and so_imm. 202def so_reg : Operand<i32>, // reg reg imm 203 ComplexPattern<i32, 3, "SelectShifterOperandReg", 204 [shl,srl,sra,rotr]> { 205 let PrintMethod = "printSORegOperand"; 206 let MIOperandInfo = (ops GPR, GPR, i32imm); 207} 208 209// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 210// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are 211// represented in the imm field in the same 12-bit form that they are encoded 212// into so_imm instructions: the 8-bit immediate is the least significant bits 213// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. 214def so_imm : Operand<i32>, 215 PatLeaf<(imm), 216 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }], 217 so_imm_XFORM> { 218 let PrintMethod = "printSOImmOperand"; 219} 220 221// Break so_imm's up into two pieces. This handles immediates with up to 16 222// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 223// get the first/second pieces. 224def so_imm2part : Operand<i32>, 225 PatLeaf<(imm), [{ 226 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 227 }]> { 228 let PrintMethod = "printSOImm2PartOperand"; 229} 230 231def so_imm2part_1 : SDNodeXForm<imm, [{ 232 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue()); 233 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); 234}]>; 235 236def so_imm2part_2 : SDNodeXForm<imm, [{ 237 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue()); 238 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); 239}]>; 240 241 242// Define ARM specific addressing modes. 243 244// addrmode2 := reg +/- reg shop imm 245// addrmode2 := reg +/- imm12 246// 247def addrmode2 : Operand<i32>, 248 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 249 let PrintMethod = "printAddrMode2Operand"; 250 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 251} 252 253def am2offset : Operand<i32>, 254 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> { 255 let PrintMethod = "printAddrMode2OffsetOperand"; 256 let MIOperandInfo = (ops GPR, i32imm); 257} 258 259// addrmode3 := reg +/- reg 260// addrmode3 := reg +/- imm8 261// 262def addrmode3 : Operand<i32>, 263 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 264 let PrintMethod = "printAddrMode3Operand"; 265 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 266} 267 268def am3offset : Operand<i32>, 269 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> { 270 let PrintMethod = "printAddrMode3OffsetOperand"; 271 let MIOperandInfo = (ops GPR, i32imm); 272} 273 274// addrmode4 := reg, <mode|W> 275// 276def addrmode4 : Operand<i32>, 277 ComplexPattern<i32, 2, "", []> { 278 let PrintMethod = "printAddrMode4Operand"; 279 let MIOperandInfo = (ops GPR, i32imm); 280} 281 282// addrmode5 := reg +/- imm8*4 283// 284def addrmode5 : Operand<i32>, 285 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 286 let PrintMethod = "printAddrMode5Operand"; 287 let MIOperandInfo = (ops GPR, i32imm); 288} 289 290// addrmodepc := pc + reg 291// 292def addrmodepc : Operand<i32>, 293 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 294 let PrintMethod = "printAddrModePCOperand"; 295 let MIOperandInfo = (ops GPR, i32imm); 296} 297 298// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 299// register whose default is 0 (no register). 300def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 301 (ops (i32 14), (i32 zero_reg))> { 302 let PrintMethod = "printPredicateOperand"; 303} 304 305// Conditional code result for instructions whose 's' bit is set, e.g. subs. 306// 307def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 308 let PrintMethod = "printSBitModifierOperand"; 309} 310 311//===----------------------------------------------------------------------===// 312// ARM Instruction flags. These need to match ARMInstrInfo.h. 313// 314 315// Addressing mode. 316class AddrMode<bits<4> val> { 317 bits<4> Value = val; 318} 319def AddrModeNone : AddrMode<0>; 320def AddrMode1 : AddrMode<1>; 321def AddrMode2 : AddrMode<2>; 322def AddrMode3 : AddrMode<3>; 323def AddrMode4 : AddrMode<4>; 324def AddrMode5 : AddrMode<5>; 325def AddrModeT1 : AddrMode<6>; 326def AddrModeT2 : AddrMode<7>; 327def AddrModeT4 : AddrMode<8>; 328def AddrModeTs : AddrMode<9>; 329 330// Instruction size. 331class SizeFlagVal<bits<3> val> { 332 bits<3> Value = val; 333} 334def SizeInvalid : SizeFlagVal<0>; // Unset. 335def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 336def Size8Bytes : SizeFlagVal<2>; 337def Size4Bytes : SizeFlagVal<3>; 338def Size2Bytes : SizeFlagVal<4>; 339 340// Load / store index mode. 341class IndexMode<bits<2> val> { 342 bits<2> Value = val; 343} 344def IndexModeNone : IndexMode<0>; 345def IndexModePre : IndexMode<1>; 346def IndexModePost : IndexMode<2>; 347 348//===----------------------------------------------------------------------===// 349 350include "ARMInstrFormats.td" 351 352//===----------------------------------------------------------------------===// 353// Multiclass helpers... 354// 355 356/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 357/// binop that produces a value. 358multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode, 359 bit Commutable = 0> { 360 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 361 opc, " $dst, $a, $b", 362 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 363 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, 364 opc, " $dst, $a, $b", 365 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> { 366 let isCommutable = Commutable; 367 } 368 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 369 opc, " $dst, $a, $b", 370 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 371} 372 373/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the 374/// instruction modifies the CSPR register. 375let Defs = [CPSR] in { 376multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode, 377 bit Commutable = 0> { 378 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 379 opc, "s $dst, $a, $b", 380 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 381 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, 382 opc, "s $dst, $a, $b", 383 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> { 384 let isCommutable = Commutable; 385 } 386 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 387 opc, "s $dst, $a, $b", 388 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 389} 390} 391 392/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 393/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 394/// a explicit result, only implicitly set CPSR. 395let Defs = [CPSR] in { 396multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode, 397 bit Commutable = 0> { 398 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, 399 opc, " $a, $b", 400 [(opnode GPR:$a, so_imm:$b)]>; 401 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, 402 opc, " $a, $b", 403 [(opnode GPR:$a, GPR:$b)]> { 404 let isCommutable = Commutable; 405 } 406 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 407 opc, " $a, $b", 408 [(opnode GPR:$a, so_reg:$b)]>; 409} 410} 411 412/// AI_unary_rrot - A unary operation with two forms: one whose operand is a 413/// register and one whose operand is a register rotated by 8/16/24. 414/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 415multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> { 416 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src), 417 opc, " $dst, $Src", 418 [(set GPR:$dst, (opnode GPR:$Src))]>, 419 Requires<[IsARM, HasV6]> { 420 let Inst{19-16} = 0b1111; 421 } 422 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), 423 opc, " $dst, $Src, ror $rot", 424 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>, 425 Requires<[IsARM, HasV6]> { 426 let Inst{19-16} = 0b1111; 427 } 428} 429 430/// AI_bin_rrot - A binary operation with two forms: one whose operand is a 431/// register and one whose operand is a register rotated by 8/16/24. 432multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> { 433 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 434 opc, " $dst, $LHS, $RHS", 435 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, 436 Requires<[IsARM, HasV6]>; 437 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 438 opc, " $dst, $LHS, $RHS, ror $rot", 439 [(set GPR:$dst, (opnode GPR:$LHS, 440 (rotr GPR:$RHS, rot_imm:$rot)))]>, 441 Requires<[IsARM, HasV6]>; 442} 443 444/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 445let Uses = [CPSR] in { 446multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 447 bit Commutable = 0> { 448 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 449 DPFrm, opc, " $dst, $a, $b", 450 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, 451 Requires<[IsARM, CarryDefIsUnused]>; 452 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 453 DPFrm, opc, " $dst, $a, $b", 454 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, 455 Requires<[IsARM, CarryDefIsUnused]> { 456 let isCommutable = Commutable; 457 } 458 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 459 DPSoRegFrm, opc, " $dst, $a, $b", 460 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, 461 Requires<[IsARM, CarryDefIsUnused]>; 462 // Carry setting variants 463 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 464 DPFrm, !strconcat(opc, "s $dst, $a, $b"), 465 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, 466 Requires<[IsARM, CarryDefIsUsed]> { 467 let Defs = [CPSR]; 468 } 469 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 470 DPFrm, !strconcat(opc, "s $dst, $a, $b"), 471 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, 472 Requires<[IsARM, CarryDefIsUsed]> { 473 let Defs = [CPSR]; 474 } 475 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 476 DPSoRegFrm, !strconcat(opc, "s $dst, $a, $b"), 477 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, 478 Requires<[IsARM, CarryDefIsUsed]> { 479 let Defs = [CPSR]; 480 } 481} 482} 483 484//===----------------------------------------------------------------------===// 485// Instructions 486//===----------------------------------------------------------------------===// 487 488//===----------------------------------------------------------------------===// 489// Miscellaneous Instructions. 490// 491 492/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 493/// the function. The first operand is the ID# for this instruction, the second 494/// is the index into the MachineConstantPool that this is, the third is the 495/// size in bytes of this constant pool entry. 496let neverHasSideEffects = 1, isNotDuplicable = 1 in 497def CONSTPOOL_ENTRY : 498PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 499 i32imm:$size), 500 "${instid:label} ${cpidx:cpentry}", []>; 501 502let Defs = [SP], Uses = [SP] in { 503def ADJCALLSTACKUP : 504PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), 505 "@ ADJCALLSTACKUP $amt1", 506 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 507 508def ADJCALLSTACKDOWN : 509PseudoInst<(outs), (ins i32imm:$amt, pred:$p), 510 "@ ADJCALLSTACKDOWN $amt", 511 [(ARMcallseq_start timm:$amt)]>; 512} 513 514def DWARF_LOC : 515PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), 516 ".loc $file, $line, $col", 517 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; 518 519 520// Address computation and loads and stores in PIC mode. 521let isNotDuplicable = 1 in { 522def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 523 Pseudo, "$cp:\n\tadd$p $dst, pc, $a", 524 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; 525 526let AddedComplexity = 10 in { 527let canFoldAsLoad = 1 in 528def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 529 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", 530 [(set GPR:$dst, (load addrmodepc:$addr))]>; 531 532def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 533 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", 534 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; 535 536def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 537 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", 538 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; 539 540def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 541 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr", 542 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; 543 544def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 545 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr", 546 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; 547} 548let AddedComplexity = 10 in { 549def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 550 Pseudo, "${addr:label}:\n\tstr$p $src, $addr", 551 [(store GPR:$src, addrmodepc:$addr)]>; 552 553def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 554 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr", 555 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; 556 557def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 558 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr", 559 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 560} 561} // isNotDuplicable = 1 562 563 564// LEApcrel - Load a pc-relative address into a register without offending the 565// assembler. 566def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo, 567 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", 568 "${:private}PCRELL${:uid}+8))\n"), 569 !strconcat("${:private}PCRELL${:uid}:\n\t", 570 "add$p $dst, pc, #PCRELV${:uid}")), 571 []>; 572 573def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), 574 (ins i32imm:$label, i32imm:$id, pred:$p), 575 Pseudo, 576 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", 577 "${:private}PCRELL${:uid}+8))\n"), 578 !strconcat("${:private}PCRELL${:uid}:\n\t", 579 "add$p $dst, pc, #PCRELV${:uid}")), 580 []>; 581 582//===----------------------------------------------------------------------===// 583// Control Flow Instructions. 584// 585 586let isReturn = 1, isTerminator = 1 in 587 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> { 588 let Inst{7-4} = 0b0001; 589 let Inst{19-8} = 0b111111111111; 590 let Inst{27-20} = 0b00010010; 591} 592 593// FIXME: remove when we have a way to marking a MI with these properties. 594// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 595// operand list. 596// FIXME: Should pc be an implicit operand like PICADD, etc? 597let isReturn = 1, isTerminator = 1 in 598 def LDM_RET : AXI4ld<(outs), 599 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 600 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", 601 []>; 602 603// On non-Darwin platforms R9 is callee-saved. 604let isCall = 1, Itinerary = IIC_Br, 605 Defs = [R0, R1, R2, R3, R12, LR, 606 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { 607 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), 608 "bl ${func:call}", 609 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>; 610 611 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), 612 "bl", " ${func:call}", 613 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>; 614 615 // ARMv5T and above 616 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 617 "blx $func", 618 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> { 619 let Inst{7-4} = 0b0011; 620 let Inst{19-8} = 0b111111111111; 621 let Inst{27-20} = 0b00010010; 622 } 623 624 let Uses = [LR] in { 625 // ARMv4T 626 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops), 627 "mov lr, pc\n\tbx $func", 628 [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>; 629 } 630} 631 632// On Darwin R9 is call-clobbered. 633let isCall = 1, Itinerary = IIC_Br, 634 Defs = [R0, R1, R2, R3, R9, R12, LR, 635 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { 636 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), 637 "bl ${func:call}", 638 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>; 639 640 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), 641 "bl", " ${func:call}", 642 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>; 643 644 // ARMv5T and above 645 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 646 "blx $func", 647 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> { 648 let Inst{7-4} = 0b0011; 649 let Inst{19-8} = 0b111111111111; 650 let Inst{27-20} = 0b00010010; 651 } 652 653 let Uses = [LR] in { 654 // ARMv4T 655 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops), 656 "mov lr, pc\n\tbx $func", 657 [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>; 658 } 659} 660 661let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in { 662 // B is "predicable" since it can be xformed into a Bcc. 663 let isBarrier = 1 in { 664 let isPredicable = 1 in 665 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target", 666 [(br bb:$target)]>; 667 668 let isNotDuplicable = 1, isIndirectBranch = 1 in { 669 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), 670 "mov pc, $target \n$jt", 671 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { 672 let Inst{20} = 0; // S Bit 673 let Inst{24-21} = 0b1101; 674 let Inst{27-26} = {0,0}; 675 } 676 def BR_JTm : JTI<(outs), 677 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), 678 "ldr pc, $target \n$jt", 679 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 680 imm:$id)]> { 681 let Inst{20} = 1; // L bit 682 let Inst{21} = 0; // W bit 683 let Inst{22} = 0; // B bit 684 let Inst{24} = 1; // P bit 685 let Inst{27-26} = {0,1}; 686 } 687 def BR_JTadd : JTI<(outs), 688 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), 689 "add pc, $target, $idx \n$jt", 690 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 691 imm:$id)]> { 692 let Inst{20} = 0; // S bit 693 let Inst{24-21} = 0b0100; 694 let Inst{27-26} = {0,0}; 695 } 696 } // isNotDuplicable = 1, isIndirectBranch = 1 697 } // isBarrier = 1 698 699 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 700 // a two-value operand where a dag node expects two operands. :( 701 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target), 702 "b", " $target", 703 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; 704} 705 706//===----------------------------------------------------------------------===// 707// Load / store Instructions. 708// 709 710// Load 711let canFoldAsLoad = 1 in 712def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 713 "ldr", " $dst, $addr", 714 [(set GPR:$dst, (load addrmode2:$addr))]>; 715 716// Special LDR for loads from non-pc-relative constpools. 717let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in 718def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 719 "ldr", " $dst, $addr", []>; 720 721// Loads with zero extension 722def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 723 "ldr", "h $dst, $addr", 724 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; 725 726def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 727 "ldr", "b $dst, $addr", 728 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; 729 730// Loads with sign extension 731def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 732 "ldr", "sh $dst, $addr", 733 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; 734 735def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 736 "ldr", "sb $dst, $addr", 737 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; 738 739let mayLoad = 1 in { 740// Load doubleword 741def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, 742 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>; 743 744// Indexed loads 745def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), 746 (ins addrmode2:$addr), LdFrm, 747 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; 748 749def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), 750 (ins GPR:$base, am2offset:$offset), LdFrm, 751 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; 752 753def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), 754 (ins addrmode3:$addr), LdMiscFrm, 755 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; 756 757def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), 758 (ins GPR:$base,am3offset:$offset), LdMiscFrm, 759 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; 760 761def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), 762 (ins addrmode2:$addr), LdFrm, 763 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; 764 765def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), 766 (ins GPR:$base,am2offset:$offset), LdFrm, 767 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; 768 769def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), 770 (ins addrmode3:$addr), LdMiscFrm, 771 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; 772 773def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), 774 (ins GPR:$base,am3offset:$offset), LdMiscFrm, 775 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; 776 777def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), 778 (ins addrmode3:$addr), LdMiscFrm, 779 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; 780 781def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), 782 (ins GPR:$base,am3offset:$offset), LdMiscFrm, 783 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; 784} 785 786// Store 787def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, 788 "str", " $src, $addr", 789 [(store GPR:$src, addrmode2:$addr)]>; 790 791// Stores with truncate 792def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, 793 "str", "h $src, $addr", 794 [(truncstorei16 GPR:$src, addrmode3:$addr)]>; 795 796def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, 797 "str", "b $src, $addr", 798 [(truncstorei8 GPR:$src, addrmode2:$addr)]>; 799 800// Store doubleword 801let mayStore = 1 in 802def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm, 803 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>; 804 805// Indexed stores 806def STR_PRE : AI2stwpr<(outs GPR:$base_wb), 807 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, 808 "str", " $src, [$base, $offset]!", "$base = $base_wb", 809 [(set GPR:$base_wb, 810 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; 811 812def STR_POST : AI2stwpo<(outs GPR:$base_wb), 813 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 814 "str", " $src, [$base], $offset", "$base = $base_wb", 815 [(set GPR:$base_wb, 816 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; 817 818def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), 819 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, 820 "str", "h $src, [$base, $offset]!", "$base = $base_wb", 821 [(set GPR:$base_wb, 822 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; 823 824def STRH_POST: AI3sthpo<(outs GPR:$base_wb), 825 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, 826 "str", "h $src, [$base], $offset", "$base = $base_wb", 827 [(set GPR:$base_wb, (post_truncsti16 GPR:$src, 828 GPR:$base, am3offset:$offset))]>; 829 830def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), 831 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 832 "str", "b $src, [$base, $offset]!", "$base = $base_wb", 833 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, 834 GPR:$base, am2offset:$offset))]>; 835 836def STRB_POST: AI2stbpo<(outs GPR:$base_wb), 837 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 838 "str", "b $src, [$base], $offset", "$base = $base_wb", 839 [(set GPR:$base_wb, (post_truncsti8 GPR:$src, 840 GPR:$base, am2offset:$offset))]>; 841 842//===----------------------------------------------------------------------===// 843// Load / store multiple Instructions. 844// 845 846// FIXME: $dst1 should be a def. 847let mayLoad = 1 in 848def LDM : AXI4ld<(outs), 849 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 850 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", 851 []>; 852 853let mayStore = 1 in 854def STM : AXI4st<(outs), 855 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), 856 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1", 857 []>; 858 859//===----------------------------------------------------------------------===// 860// Move Instructions. 861// 862 863let neverHasSideEffects = 1 in 864def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, 865 "mov", " $dst, $src", []>, UnaryDP; 866def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, 867 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP; 868 869let isReMaterializable = 1, isAsCheapAsAMove = 1 in 870def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, 871 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP; 872 873def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 874 "mov", " $dst, $src, rrx", 875 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP; 876 877// These aren't really mov instructions, but we have to define them this way 878// due to flag operands. 879 880let Defs = [CPSR] in { 881def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 882 "mov", "s $dst, $src, lsr #1", 883 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP; 884def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 885 "mov", "s $dst, $src, asr #1", 886 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP; 887} 888 889//===----------------------------------------------------------------------===// 890// Extend Instructions. 891// 892 893// Sign extenders 894 895defm SXTB : AI_unary_rrot<0b01101010, 896 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 897defm SXTH : AI_unary_rrot<0b01101011, 898 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 899 900defm SXTAB : AI_bin_rrot<0b01101010, 901 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 902defm SXTAH : AI_bin_rrot<0b01101011, 903 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 904 905// TODO: SXT(A){B|H}16 906 907// Zero extenders 908 909let AddedComplexity = 16 in { 910defm UXTB : AI_unary_rrot<0b01101110, 911 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 912defm UXTH : AI_unary_rrot<0b01101111, 913 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 914defm UXTB16 : AI_unary_rrot<0b01101100, 915 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 916 917def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 918 (UXTB16r_rot GPR:$Src, 24)>; 919def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 920 (UXTB16r_rot GPR:$Src, 8)>; 921 922defm UXTAB : AI_bin_rrot<0b01101110, "uxtab", 923 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 924defm UXTAH : AI_bin_rrot<0b01101111, "uxtah", 925 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 926} 927 928// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 929//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>; 930 931// TODO: UXT(A){B|H}16 932 933//===----------------------------------------------------------------------===// 934// Arithmetic Instructions. 935// 936 937defm ADD : AsI1_bin_irs<0b0100, "add", 938 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 939defm SUB : AsI1_bin_irs<0b0010, "sub", 940 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 941 942// ADD and SUB with 's' bit set. 943defm ADDS : AI1_bin_s_irs<0b0100, "add", 944 BinOpFrag<(addc node:$LHS, node:$RHS)>>; 945defm SUBS : AI1_bin_s_irs<0b0010, "sub", 946 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 947 948defm ADC : AI1_adde_sube_irs<0b0101, "adc", 949 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>; 950defm SBC : AI1_adde_sube_irs<0b0110, "sbc", 951 BinOpFrag<(sube node:$LHS, node:$RHS)>>; 952 953// These don't define reg/reg forms, because they are handled above. 954def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 955 "rsb", " $dst, $a, $b", 956 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; 957 958def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 959 "rsb", " $dst, $a, $b", 960 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; 961 962// RSB with 's' bit set. 963let Defs = [CPSR] in { 964def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 965 "rsb", "s $dst, $a, $b", 966 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>; 967def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 968 "rsb", "s $dst, $a, $b", 969 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; 970} 971 972let Uses = [CPSR] in { 973def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 974 DPFrm, "rsc", " $dst, $a, $b", 975 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, 976 Requires<[IsARM, CarryDefIsUnused]>; 977def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 978 DPSoRegFrm, "rsc", " $dst, $a, $b", 979 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, 980 Requires<[IsARM, CarryDefIsUnused]>; 981} 982 983// FIXME: Allow these to be predicated. 984let Defs = [CPSR], Uses = [CPSR] in { 985def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), 986 DPFrm, "rscs $dst, $a, $b", 987 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, 988 Requires<[IsARM, CarryDefIsUnused]>; 989def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), 990 DPSoRegFrm, "rscs $dst, $a, $b", 991 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, 992 Requires<[IsARM, CarryDefIsUnused]>; 993} 994 995// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 996def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 997 (SUBri GPR:$src, so_imm_neg:$imm)>; 998 999//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), 1000// (SUBSri GPR:$src, so_imm_neg:$imm)>; 1001//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), 1002// (SBCri GPR:$src, so_imm_neg:$imm)>; 1003 1004// Note: These are implemented in C++ code, because they have to generate 1005// ADD/SUBrs instructions, which use a complex pattern that a xform function 1006// cannot produce. 1007// (mul X, 2^n+1) -> (add (X << n), X) 1008// (mul X, 2^n-1) -> (rsb X, (X << n)) 1009 1010 1011//===----------------------------------------------------------------------===// 1012// Bitwise Instructions. 1013// 1014 1015defm AND : AsI1_bin_irs<0b0000, "and", 1016 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 1017defm ORR : AsI1_bin_irs<0b1100, "orr", 1018 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 1019defm EOR : AsI1_bin_irs<0b0001, "eor", 1020 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 1021defm BIC : AsI1_bin_irs<0b1110, "bic", 1022 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1023 1024def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, 1025 "mvn", " $dst, $src", 1026 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP; 1027def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, 1028 "mvn", " $dst, $src", 1029 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP; 1030let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1031def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, 1032 "mvn", " $dst, $imm", 1033 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP; 1034 1035def : ARMPat<(and GPR:$src, so_imm_not:$imm), 1036 (BICri GPR:$src, so_imm_not:$imm)>; 1037 1038//===----------------------------------------------------------------------===// 1039// Multiply Instructions. 1040// 1041 1042let isCommutable = 1 in 1043def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1044 "mul", " $dst, $a, $b", 1045 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 1046 1047def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1048 "mla", " $dst, $a, $b, $c", 1049 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 1050 1051// Extra precision multiplies with low / high results 1052let neverHasSideEffects = 1 in { 1053let isCommutable = 1 in { 1054def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst), 1055 (ins GPR:$a, GPR:$b), 1056 "smull", " $ldst, $hdst, $a, $b", []>; 1057 1058def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst), 1059 (ins GPR:$a, GPR:$b), 1060 "umull", " $ldst, $hdst, $a, $b", []>; 1061} 1062 1063// Multiply + accumulate 1064def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst), 1065 (ins GPR:$a, GPR:$b), 1066 "smlal", " $ldst, $hdst, $a, $b", []>; 1067 1068def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst), 1069 (ins GPR:$a, GPR:$b), 1070 "umlal", " $ldst, $hdst, $a, $b", []>; 1071 1072def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst), 1073 (ins GPR:$a, GPR:$b), 1074 "umaal", " $ldst, $hdst, $a, $b", []>, 1075 Requires<[IsARM, HasV6]>; 1076} // neverHasSideEffects 1077 1078// Most significant word multiply 1079def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1080 "smmul", " $dst, $a, $b", 1081 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, 1082 Requires<[IsARM, HasV6]> { 1083 let Inst{7-4} = 0b0001; 1084 let Inst{15-12} = 0b1111; 1085} 1086 1087def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1088 "smmla", " $dst, $a, $b, $c", 1089 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, 1090 Requires<[IsARM, HasV6]> { 1091 let Inst{7-4} = 0b0001; 1092} 1093 1094 1095def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 1096 "smmls", " $dst, $a, $b, $c", 1097 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, 1098 Requires<[IsARM, HasV6]> { 1099 let Inst{7-4} = 0b1101; 1100} 1101 1102multiclass AI_smul<string opc, PatFrag opnode> { 1103 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1104 !strconcat(opc, "bb"), " $dst, $a, $b", 1105 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1106 (sext_inreg GPR:$b, i16)))]>, 1107 Requires<[IsARM, HasV5TE]> { 1108 let Inst{5} = 0; 1109 let Inst{6} = 0; 1110 } 1111 1112 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1113 !strconcat(opc, "bt"), " $dst, $a, $b", 1114 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1115 (sra GPR:$b, (i32 16))))]>, 1116 Requires<[IsARM, HasV5TE]> { 1117 let Inst{5} = 0; 1118 let Inst{6} = 1; 1119 } 1120 1121 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1122 !strconcat(opc, "tb"), " $dst, $a, $b", 1123 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1124 (sext_inreg GPR:$b, i16)))]>, 1125 Requires<[IsARM, HasV5TE]> { 1126 let Inst{5} = 1; 1127 let Inst{6} = 0; 1128 } 1129 1130 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1131 !strconcat(opc, "tt"), " $dst, $a, $b", 1132 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1133 (sra GPR:$b, (i32 16))))]>, 1134 Requires<[IsARM, HasV5TE]> { 1135 let Inst{5} = 1; 1136 let Inst{6} = 1; 1137 } 1138 1139 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1140 !strconcat(opc, "wb"), " $dst, $a, $b", 1141 [(set GPR:$dst, (sra (opnode GPR:$a, 1142 (sext_inreg GPR:$b, i16)), (i32 16)))]>, 1143 Requires<[IsARM, HasV5TE]> { 1144 let Inst{5} = 1; 1145 let Inst{6} = 0; 1146 } 1147 1148 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1149 !strconcat(opc, "wt"), " $dst, $a, $b", 1150 [(set GPR:$dst, (sra (opnode GPR:$a, 1151 (sra GPR:$b, (i32 16))), (i32 16)))]>, 1152 Requires<[IsARM, HasV5TE]> { 1153 let Inst{5} = 1; 1154 let Inst{6} = 1; 1155 } 1156} 1157 1158 1159multiclass AI_smla<string opc, PatFrag opnode> { 1160 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1161 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 1162 [(set GPR:$dst, (add GPR:$acc, 1163 (opnode (sext_inreg GPR:$a, i16), 1164 (sext_inreg GPR:$b, i16))))]>, 1165 Requires<[IsARM, HasV5TE]> { 1166 let Inst{5} = 0; 1167 let Inst{6} = 0; 1168 } 1169 1170 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1171 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 1172 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 1173 (sra GPR:$b, (i32 16)))))]>, 1174 Requires<[IsARM, HasV5TE]> { 1175 let Inst{5} = 0; 1176 let Inst{6} = 1; 1177 } 1178 1179 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1180 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 1181 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1182 (sext_inreg GPR:$b, i16))))]>, 1183 Requires<[IsARM, HasV5TE]> { 1184 let Inst{5} = 1; 1185 let Inst{6} = 0; 1186 } 1187 1188 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1189 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 1190 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1191 (sra GPR:$b, (i32 16)))))]>, 1192 Requires<[IsARM, HasV5TE]> { 1193 let Inst{5} = 1; 1194 let Inst{6} = 1; 1195 } 1196 1197 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1198 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 1199 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1200 (sext_inreg GPR:$b, i16)), (i32 16))))]>, 1201 Requires<[IsARM, HasV5TE]> { 1202 let Inst{5} = 0; 1203 let Inst{6} = 0; 1204 } 1205 1206 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1207 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 1208 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1209 (sra GPR:$b, (i32 16))), (i32 16))))]>, 1210 Requires<[IsARM, HasV5TE]> { 1211 let Inst{5} = 0; 1212 let Inst{6} = 1; 1213 } 1214} 1215 1216defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1217defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1218 1219// TODO: Halfword multiple accumulate long: SMLAL<x><y> 1220// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 1221 1222//===----------------------------------------------------------------------===// 1223// Misc. Arithmetic Instructions. 1224// 1225 1226def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), 1227 "clz", " $dst, $src", 1228 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> { 1229 let Inst{7-4} = 0b0001; 1230 let Inst{11-8} = 0b1111; 1231 let Inst{19-16} = 0b1111; 1232} 1233 1234def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), 1235 "rev", " $dst, $src", 1236 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> { 1237 let Inst{7-4} = 0b0011; 1238 let Inst{11-8} = 0b1111; 1239 let Inst{19-16} = 0b1111; 1240} 1241 1242def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), 1243 "rev16", " $dst, $src", 1244 [(set GPR:$dst, 1245 (or (and (srl GPR:$src, (i32 8)), 0xFF), 1246 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 1247 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 1248 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>, 1249 Requires<[IsARM, HasV6]> { 1250 let Inst{7-4} = 0b1011; 1251 let Inst{11-8} = 0b1111; 1252 let Inst{19-16} = 0b1111; 1253} 1254 1255def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), 1256 "revsh", " $dst, $src", 1257 [(set GPR:$dst, 1258 (sext_inreg 1259 (or (srl (and GPR:$src, 0xFF00), (i32 8)), 1260 (shl GPR:$src, (i32 8))), i16))]>, 1261 Requires<[IsARM, HasV6]> { 1262 let Inst{7-4} = 0b1011; 1263 let Inst{11-8} = 0b1111; 1264 let Inst{19-16} = 0b1111; 1265} 1266 1267def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst), 1268 (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 1269 "pkhbt", " $dst, $src1, $src2, LSL $shamt", 1270 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 1271 (and (shl GPR:$src2, (i32 imm:$shamt)), 1272 0xFFFF0000)))]>, 1273 Requires<[IsARM, HasV6]> { 1274 let Inst{6-4} = 0b001; 1275} 1276 1277// Alternate cases for PKHBT where identities eliminate some nodes. 1278def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 1279 (PKHBT GPR:$src1, GPR:$src2, 0)>; 1280def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 1281 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 1282 1283 1284def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst), 1285 (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 1286 "pkhtb", " $dst, $src1, $src2, ASR $shamt", 1287 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 1288 (and (sra GPR:$src2, imm16_31:$shamt), 1289 0xFFFF)))]>, Requires<[IsARM, HasV6]> { 1290 let Inst{6-4} = 0b101; 1291} 1292 1293// Alternate cases for PKHTB where identities eliminate some nodes. Note that 1294// a shift amount of 0 is *not legal* here, it is PKHBT instead. 1295def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 1296 (PKHTB GPR:$src1, GPR:$src2, 16)>; 1297def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), 1298 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 1299 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 1300 1301//===----------------------------------------------------------------------===// 1302// Comparison Instructions... 1303// 1304 1305defm CMP : AI1_cmp_irs<0b1010, "cmp", 1306 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 1307defm CMN : AI1_cmp_irs<0b1011, "cmn", 1308 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 1309 1310// Note that TST/TEQ don't set all the same flags that CMP does! 1311defm TST : AI1_cmp_irs<0b1000, "tst", 1312 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>, 1>; 1313defm TEQ : AI1_cmp_irs<0b1001, "teq", 1314 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>, 1>; 1315 1316defm CMPnz : AI1_cmp_irs<0b1010, "cmp", 1317 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; 1318defm CMNnz : AI1_cmp_irs<0b1011, "cmn", 1319 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; 1320 1321def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 1322 (CMNri GPR:$src, so_imm_neg:$imm)>; 1323 1324def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), 1325 (CMNri GPR:$src, so_imm_neg:$imm)>; 1326 1327 1328// Conditional moves 1329// FIXME: should be able to write a pattern for ARMcmov, but can't use 1330// a two-value operand where a dag node expects two operands. :( 1331def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, 1332 "mov", " $dst, $true", 1333 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 1334 RegConstraint<"$false = $dst">, UnaryDP; 1335 1336def MOVCCs : AI1<0b1101, (outs GPR:$dst), 1337 (ins GPR:$false, so_reg:$true), DPSoRegFrm, 1338 "mov", " $dst, $true", 1339 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 1340 RegConstraint<"$false = $dst">, UnaryDP; 1341 1342def MOVCCi : AI1<0b1101, (outs GPR:$dst), 1343 (ins GPR:$false, so_imm:$true), DPFrm, 1344 "mov", " $dst, $true", 1345 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 1346 RegConstraint<"$false = $dst">, UnaryDP; 1347 1348 1349//===----------------------------------------------------------------------===// 1350// TLS Instructions 1351// 1352 1353// __aeabi_read_tp preserves the registers r1-r3. 1354let isCall = 1, 1355 Defs = [R0, R12, LR, CPSR] in { 1356 def TPsoft : ABXI<0b1011, (outs), (ins), 1357 "bl __aeabi_read_tp", 1358 [(set R0, ARMthread_pointer)]>; 1359} 1360 1361//===----------------------------------------------------------------------===// 1362// SJLJ Exception handling intrinsics 1363// eh_sjlj_setjmp() is a three instruction sequence to store the return 1364// address and save #0 in R0 for the non-longjmp case. 1365// Since by its nature we may be coming from some other function to get 1366// here, and we're using the stack frame for the containing function to 1367// save/restore registers, we can't keep anything live in regs across 1368// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 1369// when we get here from a longjmp(). We force everthing out of registers 1370// except for our own input by listing the relevant registers in Defs. By 1371// doing so, we also cause the prologue/epilogue code to actively preserve 1372// all of the callee-saved resgisters, which is exactly what we want. 1373let Defs = 1374 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, 1375 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in { 1376 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src), 1377 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, 1378 "add r0, pc, #4\n\t" 1379 "str r0, [$src, #+4]\n\t" 1380 "mov r0, #0 @ eh_setjmp", "", 1381 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>; 1382} 1383 1384//===----------------------------------------------------------------------===// 1385// Non-Instruction Patterns 1386// 1387 1388// ConstantPool, GlobalAddress, and JumpTable 1389def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>; 1390def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 1391def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1392 (LEApcrelJT tjumptable:$dst, imm:$id)>; 1393 1394// Large immediate handling. 1395 1396// Two piece so_imms. 1397let isReMaterializable = 1 in 1398def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo, 1399 "mov", " $dst, $src", 1400 [(set GPR:$dst, so_imm2part:$src)]>; 1401 1402def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), 1403 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 1404 (so_imm2part_2 imm:$RHS))>; 1405def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), 1406 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 1407 (so_imm2part_2 imm:$RHS))>; 1408 1409// TODO: add,sub,and, 3-instr forms? 1410 1411 1412// Direct calls 1413def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>, 1414 Requires<[IsNotDarwin]>; 1415def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>, 1416 Requires<[IsDarwin]>; 1417 1418// zextload i1 -> zextload i8 1419def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1420 1421// extload -> zextload 1422def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1423def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1424def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 1425 1426def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 1427def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 1428 1429// smul* and smla* 1430def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 1431 (sra (shl GPR:$b, (i32 16)), (i32 16))), 1432 (SMULBB GPR:$a, GPR:$b)>; 1433def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 1434 (SMULBB GPR:$a, GPR:$b)>; 1435def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 1436 (sra GPR:$b, (i32 16))), 1437 (SMULBT GPR:$a, GPR:$b)>; 1438def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))), 1439 (SMULBT GPR:$a, GPR:$b)>; 1440def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), 1441 (sra (shl GPR:$b, (i32 16)), (i32 16))), 1442 (SMULTB GPR:$a, GPR:$b)>; 1443def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b), 1444 (SMULTB GPR:$a, GPR:$b)>; 1445def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 1446 (i32 16)), 1447 (SMULWB GPR:$a, GPR:$b)>; 1448def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)), 1449 (SMULWB GPR:$a, GPR:$b)>; 1450 1451def : ARMV5TEPat<(add GPR:$acc, 1452 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 1453 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 1454 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 1455def : ARMV5TEPat<(add GPR:$acc, 1456 (mul sext_16_node:$a, sext_16_node:$b)), 1457 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 1458def : ARMV5TEPat<(add GPR:$acc, 1459 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)), 1460 (sra GPR:$b, (i32 16)))), 1461 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 1462def : ARMV5TEPat<(add GPR:$acc, 1463 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))), 1464 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 1465def : ARMV5TEPat<(add GPR:$acc, 1466 (mul (sra GPR:$a, (i32 16)), 1467 (sra (shl GPR:$b, (i32 16)), (i32 16)))), 1468 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 1469def : ARMV5TEPat<(add GPR:$acc, 1470 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)), 1471 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 1472def : ARMV5TEPat<(add GPR:$acc, 1473 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))), 1474 (i32 16))), 1475 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 1476def : ARMV5TEPat<(add GPR:$acc, 1477 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))), 1478 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 1479 1480//===----------------------------------------------------------------------===// 1481// Thumb Support 1482// 1483 1484include "ARMInstrThumb.td" 1485 1486//===----------------------------------------------------------------------===// 1487// Thumb2 Support 1488// 1489 1490include "ARMInstrThumb2.td" 1491 1492//===----------------------------------------------------------------------===// 1493// Floating Point Support 1494// 1495 1496include "ARMInstrVFP.td" 1497 1498//===----------------------------------------------------------------------===// 1499// Advanced SIMD (NEON) Support 1500// 1501 1502include "ARMInstrNEON.td" 1503