ARMInstrInfo.td revision 194612
1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 20def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 21 22def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 23 24def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 25 26def SDT_ARMCMov : SDTypeProfile<1, 3, 27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 28 SDTCisVT<3, i32>]>; 29 30def SDT_ARMBrcond : SDTypeProfile<0, 2, 31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 32 33def SDT_ARMBrJT : SDTypeProfile<0, 3, 34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 35 SDTCisVT<2, i32>]>; 36 37def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 38 39def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 41 42def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 43def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 44 45// Node definitions. 46def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 47def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; 48 49def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 50 [SDNPHasChain, SDNPOutFlag]>; 51def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 53 54def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 56def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 58def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 60 61def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 62 [SDNPHasChain, SDNPOptInFlag]>; 63 64def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 65 [SDNPInFlag]>; 66def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov, 67 [SDNPInFlag]>; 68 69def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>; 71 72def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 73 [SDNPHasChain]>; 74 75def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 76 [SDNPOutFlag]>; 77 78def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp, 79 [SDNPOutFlag]>; 80 81def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 82 83def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 84def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>; 85def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>; 86 87def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 88def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>; 89 90//===----------------------------------------------------------------------===// 91// ARM Instruction Predicate Definitions. 92// 93def HasV5T : Predicate<"Subtarget->hasV5TOps()">; 94def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">; 95def HasV6 : Predicate<"Subtarget->hasV6Ops()">; 96def IsThumb : Predicate<"Subtarget->isThumb()">; 97def HasThumb2 : Predicate<"Subtarget->hasThumb2()">; 98def IsARM : Predicate<"!Subtarget->isThumb()">; 99 100//===----------------------------------------------------------------------===// 101// ARM Flag Definitions. 102 103class RegConstraint<string C> { 104 string Constraints = C; 105} 106 107//===----------------------------------------------------------------------===// 108// ARM specific transformation functions and pattern fragments. 109// 110 111// so_imm_XFORM - Return a so_imm value packed into the format described for 112// so_imm def below. 113def so_imm_XFORM : SDNodeXForm<imm, [{ 114 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()), 115 MVT::i32); 116}]>; 117 118// so_imm_neg_XFORM - Return a so_imm value packed into the format described for 119// so_imm_neg def below. 120def so_imm_neg_XFORM : SDNodeXForm<imm, [{ 121 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()), 122 MVT::i32); 123}]>; 124 125// so_imm_not_XFORM - Return a so_imm value packed into the format described for 126// so_imm_not def below. 127def so_imm_not_XFORM : SDNodeXForm<imm, [{ 128 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()), 129 MVT::i32); 130}]>; 131 132// rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. 133def rot_imm : PatLeaf<(i32 imm), [{ 134 int32_t v = (int32_t)N->getZExtValue(); 135 return v == 8 || v == 16 || v == 24; 136}]>; 137 138/// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15]. 139def imm1_15 : PatLeaf<(i32 imm), [{ 140 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16; 141}]>; 142 143/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 144def imm16_31 : PatLeaf<(i32 imm), [{ 145 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32; 146}]>; 147 148def so_imm_neg : 149 PatLeaf<(imm), [{ 150 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1; 151 }], so_imm_neg_XFORM>; 152 153def so_imm_not : 154 PatLeaf<(imm), [{ 155 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1; 156 }], so_imm_not_XFORM>; 157 158// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 159def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 160 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 161}]>; 162 163class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 164class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 165 166//===----------------------------------------------------------------------===// 167// Operand Definitions. 168// 169 170// Branch target. 171def brtarget : Operand<OtherVT>; 172 173// A list of registers separated by comma. Used by load/store multiple. 174def reglist : Operand<i32> { 175 let PrintMethod = "printRegisterList"; 176} 177 178// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 179def cpinst_operand : Operand<i32> { 180 let PrintMethod = "printCPInstOperand"; 181} 182 183def jtblock_operand : Operand<i32> { 184 let PrintMethod = "printJTBlockOperand"; 185} 186 187// Local PC labels. 188def pclabel : Operand<i32> { 189 let PrintMethod = "printPCLabel"; 190} 191 192// shifter_operand operands: so_reg and so_imm. 193def so_reg : Operand<i32>, // reg reg imm 194 ComplexPattern<i32, 3, "SelectShifterOperandReg", 195 [shl,srl,sra,rotr]> { 196 let PrintMethod = "printSORegOperand"; 197 let MIOperandInfo = (ops GPR, GPR, i32imm); 198} 199 200// so_imm - Match a 32-bit shifter_operand immediate operand, which is an 201// 8-bit immediate rotated by an arbitrary number of bits. so_imm values are 202// represented in the imm field in the same 12-bit form that they are encoded 203// into so_imm instructions: the 8-bit immediate is the least significant bits 204// [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. 205def so_imm : Operand<i32>, 206 PatLeaf<(imm), 207 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }], 208 so_imm_XFORM> { 209 let PrintMethod = "printSOImmOperand"; 210} 211 212// Break so_imm's up into two pieces. This handles immediates with up to 16 213// bits set in them. This uses so_imm2part to match and so_imm2part_[12] to 214// get the first/second pieces. 215def so_imm2part : Operand<i32>, 216 PatLeaf<(imm), [{ 217 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 218 }]> { 219 let PrintMethod = "printSOImm2PartOperand"; 220} 221 222def so_imm2part_1 : SDNodeXForm<imm, [{ 223 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue()); 224 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); 225}]>; 226 227def so_imm2part_2 : SDNodeXForm<imm, [{ 228 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue()); 229 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32); 230}]>; 231 232 233// Define ARM specific addressing modes. 234 235// addrmode2 := reg +/- reg shop imm 236// addrmode2 := reg +/- imm12 237// 238def addrmode2 : Operand<i32>, 239 ComplexPattern<i32, 3, "SelectAddrMode2", []> { 240 let PrintMethod = "printAddrMode2Operand"; 241 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 242} 243 244def am2offset : Operand<i32>, 245 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> { 246 let PrintMethod = "printAddrMode2OffsetOperand"; 247 let MIOperandInfo = (ops GPR, i32imm); 248} 249 250// addrmode3 := reg +/- reg 251// addrmode3 := reg +/- imm8 252// 253def addrmode3 : Operand<i32>, 254 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 255 let PrintMethod = "printAddrMode3Operand"; 256 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 257} 258 259def am3offset : Operand<i32>, 260 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> { 261 let PrintMethod = "printAddrMode3OffsetOperand"; 262 let MIOperandInfo = (ops GPR, i32imm); 263} 264 265// addrmode4 := reg, <mode|W> 266// 267def addrmode4 : Operand<i32>, 268 ComplexPattern<i32, 2, "", []> { 269 let PrintMethod = "printAddrMode4Operand"; 270 let MIOperandInfo = (ops GPR, i32imm); 271} 272 273// addrmode5 := reg +/- imm8*4 274// 275def addrmode5 : Operand<i32>, 276 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 277 let PrintMethod = "printAddrMode5Operand"; 278 let MIOperandInfo = (ops GPR, i32imm); 279} 280 281// addrmodepc := pc + reg 282// 283def addrmodepc : Operand<i32>, 284 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 285 let PrintMethod = "printAddrModePCOperand"; 286 let MIOperandInfo = (ops GPR, i32imm); 287} 288 289// ARM Predicate operand. Default to 14 = always (AL). Second part is CC 290// register whose default is 0 (no register). 291def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), 292 (ops (i32 14), (i32 zero_reg))> { 293 let PrintMethod = "printPredicateOperand"; 294} 295 296// Conditional code result for instructions whose 's' bit is set, e.g. subs. 297// 298def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { 299 let PrintMethod = "printSBitModifierOperand"; 300} 301 302//===----------------------------------------------------------------------===// 303// ARM Instruction flags. These need to match ARMInstrInfo.h. 304// 305 306// Addressing mode. 307class AddrMode<bits<4> val> { 308 bits<4> Value = val; 309} 310def AddrModeNone : AddrMode<0>; 311def AddrMode1 : AddrMode<1>; 312def AddrMode2 : AddrMode<2>; 313def AddrMode3 : AddrMode<3>; 314def AddrMode4 : AddrMode<4>; 315def AddrMode5 : AddrMode<5>; 316def AddrModeT1 : AddrMode<6>; 317def AddrModeT2 : AddrMode<7>; 318def AddrModeT4 : AddrMode<8>; 319def AddrModeTs : AddrMode<9>; 320 321// Instruction size. 322class SizeFlagVal<bits<3> val> { 323 bits<3> Value = val; 324} 325def SizeInvalid : SizeFlagVal<0>; // Unset. 326def SizeSpecial : SizeFlagVal<1>; // Pseudo or special. 327def Size8Bytes : SizeFlagVal<2>; 328def Size4Bytes : SizeFlagVal<3>; 329def Size2Bytes : SizeFlagVal<4>; 330 331// Load / store index mode. 332class IndexMode<bits<2> val> { 333 bits<2> Value = val; 334} 335def IndexModeNone : IndexMode<0>; 336def IndexModePre : IndexMode<1>; 337def IndexModePost : IndexMode<2>; 338 339//===----------------------------------------------------------------------===// 340 341include "ARMInstrFormats.td" 342 343//===----------------------------------------------------------------------===// 344// Multiclass helpers... 345// 346 347/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a 348/// binop that produces a value. 349multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> { 350 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 351 opc, " $dst, $a, $b", 352 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 353 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, 354 opc, " $dst, $a, $b", 355 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; 356 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 357 opc, " $dst, $a, $b", 358 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 359} 360 361/// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the 362/// instruction modifies the CSPR register. 363let Defs = [CPSR] in { 364multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> { 365 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 366 opc, "s $dst, $a, $b", 367 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 368 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, 369 opc, "s $dst, $a, $b", 370 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; 371 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 372 opc, "s $dst, $a, $b", 373 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 374} 375} 376 377/// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 378/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 379/// a explicit result, only implicitly set CPSR. 380let Defs = [CPSR] in { 381multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> { 382 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, 383 opc, " $a, $b", 384 [(opnode GPR:$a, so_imm:$b)]>; 385 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, 386 opc, " $a, $b", 387 [(opnode GPR:$a, GPR:$b)]>; 388 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 389 opc, " $a, $b", 390 [(opnode GPR:$a, so_reg:$b)]>; 391} 392} 393 394/// AI_unary_rrot - A unary operation with two forms: one whose operand is a 395/// register and one whose operand is a register rotated by 8/16/24. 396/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 397multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> { 398 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src), 399 opc, " $dst, $Src", 400 [(set GPR:$dst, (opnode GPR:$Src))]>, 401 Requires<[IsARM, HasV6]> { 402 let Inst{19-16} = 0b1111; 403 } 404 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), 405 opc, " $dst, $Src, ror $rot", 406 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>, 407 Requires<[IsARM, HasV6]> { 408 let Inst{19-16} = 0b1111; 409 } 410} 411 412/// AI_bin_rrot - A binary operation with two forms: one whose operand is a 413/// register and one whose operand is a register rotated by 8/16/24. 414multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> { 415 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 416 opc, " $dst, $LHS, $RHS", 417 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, 418 Requires<[IsARM, HasV6]>; 419 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 420 opc, " $dst, $LHS, $RHS, ror $rot", 421 [(set GPR:$dst, (opnode GPR:$LHS, 422 (rotr GPR:$RHS, rot_imm:$rot)))]>, 423 Requires<[IsARM, HasV6]>; 424} 425 426/// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and 427/// setting carry bit. But it can optionally set CPSR. 428let Uses = [CPSR] in { 429multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> { 430 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), 431 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"), 432 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>; 433 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s), 434 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"), 435 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>; 436 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), 437 DPSoRegFrm, !strconcat(opc, "${s} $dst, $a, $b"), 438 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>; 439} 440} 441 442//===----------------------------------------------------------------------===// 443// Instructions 444//===----------------------------------------------------------------------===// 445 446//===----------------------------------------------------------------------===// 447// Miscellaneous Instructions. 448// 449 450/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 451/// the function. The first operand is the ID# for this instruction, the second 452/// is the index into the MachineConstantPool that this is, the third is the 453/// size in bytes of this constant pool entry. 454let neverHasSideEffects = 1, isNotDuplicable = 1 in 455def CONSTPOOL_ENTRY : 456PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 457 i32imm:$size), 458 "${instid:label} ${cpidx:cpentry}", []>; 459 460let Defs = [SP], Uses = [SP] in { 461def ADJCALLSTACKUP : 462PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), 463 "@ ADJCALLSTACKUP $amt1", 464 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 465 466def ADJCALLSTACKDOWN : 467PseudoInst<(outs), (ins i32imm:$amt, pred:$p), 468 "@ ADJCALLSTACKDOWN $amt", 469 [(ARMcallseq_start timm:$amt)]>; 470} 471 472def DWARF_LOC : 473PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), 474 ".loc $file, $line, $col", 475 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>; 476 477 478// Address computation and loads and stores in PIC mode. 479let isNotDuplicable = 1 in { 480def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 481 Pseudo, "$cp:\n\tadd$p $dst, pc, $a", 482 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; 483 484let AddedComplexity = 10 in { 485let canFoldAsLoad = 1 in 486def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 487 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", 488 [(set GPR:$dst, (load addrmodepc:$addr))]>; 489 490def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 491 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", 492 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; 493 494def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 495 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", 496 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; 497 498def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 499 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr", 500 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; 501 502def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 503 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr", 504 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; 505} 506let AddedComplexity = 10 in { 507def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 508 Pseudo, "${addr:label}:\n\tstr$p $src, $addr", 509 [(store GPR:$src, addrmodepc:$addr)]>; 510 511def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 512 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr", 513 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>; 514 515def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 516 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr", 517 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 518} 519} // isNotDuplicable = 1 520 521//===----------------------------------------------------------------------===// 522// Control Flow Instructions. 523// 524 525let isReturn = 1, isTerminator = 1 in 526 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> { 527 let Inst{7-4} = 0b0001; 528 let Inst{19-8} = 0b111111111111; 529 let Inst{27-20} = 0b00010010; 530} 531 532// FIXME: remove when we have a way to marking a MI with these properties. 533// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 534// operand list. 535// FIXME: Should pc be an implicit operand like PICADD, etc? 536let isReturn = 1, isTerminator = 1 in 537 def LDM_RET : AXI4ld<(outs), 538 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 539 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", 540 []>; 541 542let isCall = 1, Itinerary = IIC_Br, 543 Defs = [R0, R1, R2, R3, R12, LR, 544 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { 545 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops), 546 "bl ${func:call}", 547 [(ARMcall tglobaladdr:$func)]>; 548 549 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops), 550 "bl", " ${func:call}", 551 [(ARMcall_pred tglobaladdr:$func)]>; 552 553 // ARMv5T and above 554 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm, 555 "blx $func", 556 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> { 557 let Inst{7-4} = 0b0011; 558 let Inst{19-8} = 0b111111111111; 559 let Inst{27-20} = 0b00010010; 560 } 561 562 let Uses = [LR] in { 563 // ARMv4T 564 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops), 565 "mov lr, pc\n\tbx $func", 566 [(ARMcall_nolink GPR:$func)]>; 567 } 568} 569 570let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in { 571 // B is "predicable" since it can be xformed into a Bcc. 572 let isBarrier = 1 in { 573 let isPredicable = 1 in 574 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target", 575 [(br bb:$target)]>; 576 577 let isNotDuplicable = 1, isIndirectBranch = 1 in { 578 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), 579 "mov pc, $target \n$jt", 580 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> { 581 let Inst{20} = 0; // S Bit 582 let Inst{24-21} = 0b1101; 583 let Inst{27-26} = {0,0}; 584 } 585 def BR_JTm : JTI<(outs), 586 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), 587 "ldr pc, $target \n$jt", 588 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, 589 imm:$id)]> { 590 let Inst{20} = 1; // L bit 591 let Inst{21} = 0; // W bit 592 let Inst{22} = 0; // B bit 593 let Inst{24} = 1; // P bit 594 let Inst{27-26} = {0,1}; 595 } 596 def BR_JTadd : JTI<(outs), 597 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), 598 "add pc, $target, $idx \n$jt", 599 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, 600 imm:$id)]> { 601 let Inst{20} = 0; // S bit 602 let Inst{24-21} = 0b0100; 603 let Inst{27-26} = {0,0}; 604 } 605 } // isNotDuplicable = 1, isIndirectBranch = 1 606 } // isBarrier = 1 607 608 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 609 // a two-value operand where a dag node expects two operands. :( 610 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target), 611 "b", " $target", 612 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; 613} 614 615//===----------------------------------------------------------------------===// 616// Load / store Instructions. 617// 618 619// Load 620let canFoldAsLoad = 1 in 621def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 622 "ldr", " $dst, $addr", 623 [(set GPR:$dst, (load addrmode2:$addr))]>; 624 625// Special LDR for loads from non-pc-relative constpools. 626let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in 627def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 628 "ldr", " $dst, $addr", []>; 629 630// Loads with zero extension 631def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 632 "ldr", "h $dst, $addr", 633 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; 634 635def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, 636 "ldr", "b $dst, $addr", 637 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; 638 639// Loads with sign extension 640def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 641 "ldr", "sh $dst, $addr", 642 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; 643 644def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, 645 "ldr", "sb $dst, $addr", 646 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; 647 648let mayLoad = 1 in { 649// Load doubleword 650def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm, 651 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>; 652 653// Indexed loads 654def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb), 655 (ins addrmode2:$addr), LdFrm, 656 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; 657 658def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb), 659 (ins GPR:$base, am2offset:$offset), LdFrm, 660 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; 661 662def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb), 663 (ins addrmode3:$addr), LdMiscFrm, 664 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; 665 666def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb), 667 (ins GPR:$base,am3offset:$offset), LdMiscFrm, 668 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; 669 670def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb), 671 (ins addrmode2:$addr), LdFrm, 672 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; 673 674def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb), 675 (ins GPR:$base,am2offset:$offset), LdFrm, 676 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; 677 678def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb), 679 (ins addrmode3:$addr), LdMiscFrm, 680 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; 681 682def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb), 683 (ins GPR:$base,am3offset:$offset), LdMiscFrm, 684 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; 685 686def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb), 687 (ins addrmode3:$addr), LdMiscFrm, 688 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; 689 690def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb), 691 (ins GPR:$base,am3offset:$offset), LdMiscFrm, 692 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; 693} 694 695// Store 696def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, 697 "str", " $src, $addr", 698 [(store GPR:$src, addrmode2:$addr)]>; 699 700// Stores with truncate 701def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, 702 "str", "h $src, $addr", 703 [(truncstorei16 GPR:$src, addrmode3:$addr)]>; 704 705def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, 706 "str", "b $src, $addr", 707 [(truncstorei8 GPR:$src, addrmode2:$addr)]>; 708 709// Store doubleword 710let mayStore = 1 in 711def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm, 712 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>; 713 714// Indexed stores 715def STR_PRE : AI2stwpr<(outs GPR:$base_wb), 716 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, 717 "str", " $src, [$base, $offset]!", "$base = $base_wb", 718 [(set GPR:$base_wb, 719 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; 720 721def STR_POST : AI2stwpo<(outs GPR:$base_wb), 722 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 723 "str", " $src, [$base], $offset", "$base = $base_wb", 724 [(set GPR:$base_wb, 725 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>; 726 727def STRH_PRE : AI3sthpr<(outs GPR:$base_wb), 728 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, 729 "str", "h $src, [$base, $offset]!", "$base = $base_wb", 730 [(set GPR:$base_wb, 731 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; 732 733def STRH_POST: AI3sthpo<(outs GPR:$base_wb), 734 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, 735 "str", "h $src, [$base], $offset", "$base = $base_wb", 736 [(set GPR:$base_wb, (post_truncsti16 GPR:$src, 737 GPR:$base, am3offset:$offset))]>; 738 739def STRB_PRE : AI2stbpr<(outs GPR:$base_wb), 740 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 741 "str", "b $src, [$base, $offset]!", "$base = $base_wb", 742 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src, 743 GPR:$base, am2offset:$offset))]>; 744 745def STRB_POST: AI2stbpo<(outs GPR:$base_wb), 746 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, 747 "str", "b $src, [$base], $offset", "$base = $base_wb", 748 [(set GPR:$base_wb, (post_truncsti8 GPR:$src, 749 GPR:$base, am2offset:$offset))]>; 750 751//===----------------------------------------------------------------------===// 752// Load / store multiple Instructions. 753// 754 755// FIXME: $dst1 should be a def. 756let mayLoad = 1 in 757def LDM : AXI4ld<(outs), 758 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 759 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1", 760 []>; 761 762let mayStore = 1 in 763def STM : AXI4st<(outs), 764 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), 765 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1", 766 []>; 767 768//===----------------------------------------------------------------------===// 769// Move Instructions. 770// 771 772let neverHasSideEffects = 1 in 773def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, 774 "mov", " $dst, $src", []>, UnaryDP; 775def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, 776 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP; 777 778let isReMaterializable = 1, isAsCheapAsAMove = 1 in 779def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, 780 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP; 781 782def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 783 "mov", " $dst, $src, rrx", 784 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP; 785 786// These aren't really mov instructions, but we have to define them this way 787// due to flag operands. 788 789let Defs = [CPSR] in { 790def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 791 "mov", "s $dst, $src, lsr #1", 792 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP; 793def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, 794 "mov", "s $dst, $src, asr #1", 795 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP; 796} 797 798//===----------------------------------------------------------------------===// 799// Extend Instructions. 800// 801 802// Sign extenders 803 804defm SXTB : AI_unary_rrot<0b01101010, 805 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 806defm SXTH : AI_unary_rrot<0b01101011, 807 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 808 809defm SXTAB : AI_bin_rrot<0b01101010, 810 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 811defm SXTAH : AI_bin_rrot<0b01101011, 812 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 813 814// TODO: SXT(A){B|H}16 815 816// Zero extenders 817 818let AddedComplexity = 16 in { 819defm UXTB : AI_unary_rrot<0b01101110, 820 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 821defm UXTH : AI_unary_rrot<0b01101111, 822 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 823defm UXTB16 : AI_unary_rrot<0b01101100, 824 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 825 826def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF), 827 (UXTB16r_rot GPR:$Src, 24)>; 828def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF), 829 (UXTB16r_rot GPR:$Src, 8)>; 830 831defm UXTAB : AI_bin_rrot<0b01101110, "uxtab", 832 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 833defm UXTAH : AI_bin_rrot<0b01101111, "uxtah", 834 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 835} 836 837// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 838//defm UXTAB16 : xxx<"uxtab16", 0xff00ff>; 839 840// TODO: UXT(A){B|H}16 841 842//===----------------------------------------------------------------------===// 843// Arithmetic Instructions. 844// 845 846defm ADD : AsI1_bin_irs<0b0100, "add", 847 BinOpFrag<(add node:$LHS, node:$RHS)>>; 848defm SUB : AsI1_bin_irs<0b0010, "sub", 849 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 850 851// ADD and SUB with 's' bit set. 852defm ADDS : ASI1_bin_s_irs<0b0100, "add", 853 BinOpFrag<(addc node:$LHS, node:$RHS)>>; 854defm SUBS : ASI1_bin_s_irs<0b0010, "sub", 855 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 856 857// FIXME: Do not allow ADC / SBC to be predicated for now. 858defm ADC : AsXI1_bin_c_irs<0b0101, "adc", 859 BinOpFrag<(adde node:$LHS, node:$RHS)>>; 860defm SBC : AsXI1_bin_c_irs<0b0110, "sbc", 861 BinOpFrag<(sube node:$LHS, node:$RHS)>>; 862 863// These don't define reg/reg forms, because they are handled above. 864def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 865 "rsb", " $dst, $a, $b", 866 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>; 867 868def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 869 "rsb", " $dst, $a, $b", 870 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>; 871 872// RSB with 's' bit set. 873let Defs = [CPSR] in { 874def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm, 875 "rsb", "s $dst, $a, $b", 876 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>; 877def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm, 878 "rsb", "s $dst, $a, $b", 879 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>; 880} 881 882// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR. 883let Uses = [CPSR] in { 884def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s), 885 DPFrm, "rsc${s} $dst, $a, $b", 886 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>; 887def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s), 888 DPSoRegFrm, "rsc${s} $dst, $a, $b", 889 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>; 890} 891 892// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 893def : ARMPat<(add GPR:$src, so_imm_neg:$imm), 894 (SUBri GPR:$src, so_imm_neg:$imm)>; 895 896//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), 897// (SUBSri GPR:$src, so_imm_neg:$imm)>; 898//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), 899// (SBCri GPR:$src, so_imm_neg:$imm)>; 900 901// Note: These are implemented in C++ code, because they have to generate 902// ADD/SUBrs instructions, which use a complex pattern that a xform function 903// cannot produce. 904// (mul X, 2^n+1) -> (add (X << n), X) 905// (mul X, 2^n-1) -> (rsb X, (X << n)) 906 907 908//===----------------------------------------------------------------------===// 909// Bitwise Instructions. 910// 911 912defm AND : AsI1_bin_irs<0b0000, "and", 913 BinOpFrag<(and node:$LHS, node:$RHS)>>; 914defm ORR : AsI1_bin_irs<0b1100, "orr", 915 BinOpFrag<(or node:$LHS, node:$RHS)>>; 916defm EOR : AsI1_bin_irs<0b0001, "eor", 917 BinOpFrag<(xor node:$LHS, node:$RHS)>>; 918defm BIC : AsI1_bin_irs<0b1110, "bic", 919 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 920 921def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, 922 "mvn", " $dst, $src", 923 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP; 924def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, 925 "mvn", " $dst, $src", 926 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP; 927let isReMaterializable = 1, isAsCheapAsAMove = 1 in 928def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm, 929 "mvn", " $dst, $imm", 930 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP; 931 932def : ARMPat<(and GPR:$src, so_imm_not:$imm), 933 (BICri GPR:$src, so_imm_not:$imm)>; 934 935//===----------------------------------------------------------------------===// 936// Multiply Instructions. 937// 938 939def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 940 "mul", " $dst, $a, $b", 941 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 942 943def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 944 "mla", " $dst, $a, $b, $c", 945 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 946 947// Extra precision multiplies with low / high results 948let neverHasSideEffects = 1 in { 949def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst), 950 (ins GPR:$a, GPR:$b), 951 "smull", " $ldst, $hdst, $a, $b", []>; 952 953def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst), 954 (ins GPR:$a, GPR:$b), 955 "umull", " $ldst, $hdst, $a, $b", []>; 956 957// Multiply + accumulate 958def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst), 959 (ins GPR:$a, GPR:$b), 960 "smlal", " $ldst, $hdst, $a, $b", []>; 961 962def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst), 963 (ins GPR:$a, GPR:$b), 964 "umlal", " $ldst, $hdst, $a, $b", []>; 965 966def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst), 967 (ins GPR:$a, GPR:$b), 968 "umaal", " $ldst, $hdst, $a, $b", []>, 969 Requires<[IsARM, HasV6]>; 970} // neverHasSideEffects 971 972// Most significant word multiply 973def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 974 "smmul", " $dst, $a, $b", 975 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>, 976 Requires<[IsARM, HasV6]> { 977 let Inst{7-4} = 0b0001; 978 let Inst{15-12} = 0b1111; 979} 980 981def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 982 "smmla", " $dst, $a, $b, $c", 983 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>, 984 Requires<[IsARM, HasV6]> { 985 let Inst{7-4} = 0b0001; 986} 987 988 989def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 990 "smmls", " $dst, $a, $b, $c", 991 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>, 992 Requires<[IsARM, HasV6]> { 993 let Inst{7-4} = 0b1101; 994} 995 996multiclass AI_smul<string opc, PatFrag opnode> { 997 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 998 !strconcat(opc, "bb"), " $dst, $a, $b", 999 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1000 (sext_inreg GPR:$b, i16)))]>, 1001 Requires<[IsARM, HasV5TE]> { 1002 let Inst{5} = 0; 1003 let Inst{6} = 0; 1004 } 1005 1006 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1007 !strconcat(opc, "bt"), " $dst, $a, $b", 1008 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1009 (sra GPR:$b, 16)))]>, 1010 Requires<[IsARM, HasV5TE]> { 1011 let Inst{5} = 0; 1012 let Inst{6} = 1; 1013 } 1014 1015 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1016 !strconcat(opc, "tb"), " $dst, $a, $b", 1017 [(set GPR:$dst, (opnode (sra GPR:$a, 16), 1018 (sext_inreg GPR:$b, i16)))]>, 1019 Requires<[IsARM, HasV5TE]> { 1020 let Inst{5} = 1; 1021 let Inst{6} = 0; 1022 } 1023 1024 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1025 !strconcat(opc, "tt"), " $dst, $a, $b", 1026 [(set GPR:$dst, (opnode (sra GPR:$a, 16), 1027 (sra GPR:$b, 16)))]>, 1028 Requires<[IsARM, HasV5TE]> { 1029 let Inst{5} = 1; 1030 let Inst{6} = 1; 1031 } 1032 1033 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1034 !strconcat(opc, "wb"), " $dst, $a, $b", 1035 [(set GPR:$dst, (sra (opnode GPR:$a, 1036 (sext_inreg GPR:$b, i16)), 16))]>, 1037 Requires<[IsARM, HasV5TE]> { 1038 let Inst{5} = 1; 1039 let Inst{6} = 0; 1040 } 1041 1042 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1043 !strconcat(opc, "wt"), " $dst, $a, $b", 1044 [(set GPR:$dst, (sra (opnode GPR:$a, 1045 (sra GPR:$b, 16)), 16))]>, 1046 Requires<[IsARM, HasV5TE]> { 1047 let Inst{5} = 1; 1048 let Inst{6} = 1; 1049 } 1050} 1051 1052 1053multiclass AI_smla<string opc, PatFrag opnode> { 1054 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1055 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 1056 [(set GPR:$dst, (add GPR:$acc, 1057 (opnode (sext_inreg GPR:$a, i16), 1058 (sext_inreg GPR:$b, i16))))]>, 1059 Requires<[IsARM, HasV5TE]> { 1060 let Inst{5} = 0; 1061 let Inst{6} = 0; 1062 } 1063 1064 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1065 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 1066 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 1067 (sra GPR:$b, 16))))]>, 1068 Requires<[IsARM, HasV5TE]> { 1069 let Inst{5} = 0; 1070 let Inst{6} = 1; 1071 } 1072 1073 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1074 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 1075 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), 1076 (sext_inreg GPR:$b, i16))))]>, 1077 Requires<[IsARM, HasV5TE]> { 1078 let Inst{5} = 1; 1079 let Inst{6} = 0; 1080 } 1081 1082 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1083 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 1084 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16), 1085 (sra GPR:$b, 16))))]>, 1086 Requires<[IsARM, HasV5TE]> { 1087 let Inst{5} = 1; 1088 let Inst{6} = 1; 1089 } 1090 1091 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1092 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 1093 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1094 (sext_inreg GPR:$b, i16)), 16)))]>, 1095 Requires<[IsARM, HasV5TE]> { 1096 let Inst{5} = 0; 1097 let Inst{6} = 0; 1098 } 1099 1100 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 1101 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 1102 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1103 (sra GPR:$b, 16)), 16)))]>, 1104 Requires<[IsARM, HasV5TE]> { 1105 let Inst{5} = 0; 1106 let Inst{6} = 1; 1107 } 1108} 1109 1110defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1111defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1112 1113// TODO: Halfword multiple accumulate long: SMLAL<x><y> 1114// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 1115 1116//===----------------------------------------------------------------------===// 1117// Misc. Arithmetic Instructions. 1118// 1119 1120def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), 1121 "clz", " $dst, $src", 1122 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> { 1123 let Inst{7-4} = 0b0001; 1124 let Inst{11-8} = 0b1111; 1125 let Inst{19-16} = 0b1111; 1126} 1127 1128def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), 1129 "rev", " $dst, $src", 1130 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> { 1131 let Inst{7-4} = 0b0011; 1132 let Inst{11-8} = 0b1111; 1133 let Inst{19-16} = 0b1111; 1134} 1135 1136def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), 1137 "rev16", " $dst, $src", 1138 [(set GPR:$dst, 1139 (or (and (srl GPR:$src, 8), 0xFF), 1140 (or (and (shl GPR:$src, 8), 0xFF00), 1141 (or (and (srl GPR:$src, 8), 0xFF0000), 1142 (and (shl GPR:$src, 8), 0xFF000000)))))]>, 1143 Requires<[IsARM, HasV6]> { 1144 let Inst{7-4} = 0b1011; 1145 let Inst{11-8} = 0b1111; 1146 let Inst{19-16} = 0b1111; 1147} 1148 1149def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), 1150 "revsh", " $dst, $src", 1151 [(set GPR:$dst, 1152 (sext_inreg 1153 (or (srl (and GPR:$src, 0xFF00), 8), 1154 (shl GPR:$src, 8)), i16))]>, 1155 Requires<[IsARM, HasV6]> { 1156 let Inst{7-4} = 0b1011; 1157 let Inst{11-8} = 0b1111; 1158 let Inst{19-16} = 0b1111; 1159} 1160 1161def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst), 1162 (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 1163 "pkhbt", " $dst, $src1, $src2, LSL $shamt", 1164 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 1165 (and (shl GPR:$src2, (i32 imm:$shamt)), 1166 0xFFFF0000)))]>, 1167 Requires<[IsARM, HasV6]> { 1168 let Inst{6-4} = 0b001; 1169} 1170 1171// Alternate cases for PKHBT where identities eliminate some nodes. 1172def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 1173 (PKHBT GPR:$src1, GPR:$src2, 0)>; 1174def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 1175 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 1176 1177 1178def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst), 1179 (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 1180 "pkhtb", " $dst, $src1, $src2, ASR $shamt", 1181 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 1182 (and (sra GPR:$src2, imm16_31:$shamt), 1183 0xFFFF)))]>, Requires<[IsARM, HasV6]> { 1184 let Inst{6-4} = 0b101; 1185} 1186 1187// Alternate cases for PKHTB where identities eliminate some nodes. Note that 1188// a shift amount of 0 is *not legal* here, it is PKHBT instead. 1189def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)), 1190 (PKHTB GPR:$src1, GPR:$src2, 16)>; 1191def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), 1192 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 1193 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 1194 1195//===----------------------------------------------------------------------===// 1196// Comparison Instructions... 1197// 1198 1199defm CMP : AI1_cmp_irs<0b1010, "cmp", 1200 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 1201defm CMN : AI1_cmp_irs<0b1011, "cmn", 1202 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 1203 1204// Note that TST/TEQ don't set all the same flags that CMP does! 1205defm TST : AI1_cmp_irs<0b1000, "tst", 1206 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; 1207defm TEQ : AI1_cmp_irs<0b1001, "teq", 1208 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; 1209 1210defm CMPnz : AI1_cmp_irs<0b1010, "cmp", 1211 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>; 1212defm CMNnz : AI1_cmp_irs<0b1011, "cmn", 1213 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>; 1214 1215def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm), 1216 (CMNri GPR:$src, so_imm_neg:$imm)>; 1217 1218def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm), 1219 (CMNri GPR:$src, so_imm_neg:$imm)>; 1220 1221 1222// Conditional moves 1223// FIXME: should be able to write a pattern for ARMcmov, but can't use 1224// a two-value operand where a dag node expects two operands. :( 1225def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, 1226 "mov", " $dst, $true", 1227 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 1228 RegConstraint<"$false = $dst">, UnaryDP; 1229 1230def MOVCCs : AI1<0b1101, (outs GPR:$dst), 1231 (ins GPR:$false, so_reg:$true), DPSoRegFrm, 1232 "mov", " $dst, $true", 1233 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 1234 RegConstraint<"$false = $dst">, UnaryDP; 1235 1236def MOVCCi : AI1<0b1101, (outs GPR:$dst), 1237 (ins GPR:$false, so_imm:$true), DPFrm, 1238 "mov", " $dst, $true", 1239 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 1240 RegConstraint<"$false = $dst">, UnaryDP; 1241 1242 1243// LEApcrel - Load a pc-relative address into a register without offending the 1244// assembler. 1245def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo, 1246 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(", 1247 "${:private}PCRELL${:uid}+8))\n"), 1248 !strconcat("${:private}PCRELL${:uid}:\n\t", 1249 "add$p $dst, pc, #PCRELV${:uid}")), 1250 []>; 1251 1252def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p), 1253 Pseudo, 1254 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(", 1255 "${:private}PCRELL${:uid}+8))\n"), 1256 !strconcat("${:private}PCRELL${:uid}:\n\t", 1257 "add$p $dst, pc, #PCRELV${:uid}")), 1258 []>; 1259 1260//===----------------------------------------------------------------------===// 1261// TLS Instructions 1262// 1263 1264// __aeabi_read_tp preserves the registers r1-r3. 1265let isCall = 1, 1266 Defs = [R0, R12, LR, CPSR] in { 1267 def TPsoft : ABXI<0b1011, (outs), (ins), 1268 "bl __aeabi_read_tp", 1269 [(set R0, ARMthread_pointer)]>; 1270} 1271 1272//===----------------------------------------------------------------------===// 1273// SJLJ Exception handling intrinsics 1274// eh_sjlj_setjmp() is a three instruction sequence to store the return 1275// address and save #0 in R0 for the non-longjmp case. 1276// Since by its nature we may be coming from some other function to get 1277// here, and we're using the stack frame for the containing function to 1278// save/restore registers, we can't keep anything live in regs across 1279// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 1280// when we get here from a longjmp(). We force everthing out of registers 1281// except for our own input by listing the relevant registers in Defs. By 1282// doing so, we also cause the prologue/epilogue code to actively preserve 1283// all of the callee-saved resgisters, which is exactly what we want. 1284let Defs = 1285 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, 1286 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in { 1287 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src), 1288 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, 1289 "add r0, pc, #4\n\t" 1290 "str r0, [$src, #+4]\n\t" 1291 "mov r0, #0 @ eh_setjmp", "", 1292 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>; 1293} 1294 1295//===----------------------------------------------------------------------===// 1296// Non-Instruction Patterns 1297// 1298 1299// ConstantPool, GlobalAddress, and JumpTable 1300def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>; 1301def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 1302def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1303 (LEApcrelJT tjumptable:$dst, imm:$id)>; 1304 1305// Large immediate handling. 1306 1307// Two piece so_imms. 1308let isReMaterializable = 1 in 1309def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo, 1310 "mov", " $dst, $src", 1311 [(set GPR:$dst, so_imm2part:$src)]>; 1312 1313def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS), 1314 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 1315 (so_imm2part_2 imm:$RHS))>; 1316def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS), 1317 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)), 1318 (so_imm2part_2 imm:$RHS))>; 1319 1320// TODO: add,sub,and, 3-instr forms? 1321 1322 1323// Direct calls 1324def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 1325 1326// zextload i1 -> zextload i8 1327def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1328 1329// extload -> zextload 1330def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1331def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; 1332def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 1333 1334def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 1335def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 1336 1337// smul* and smla* 1338def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)), 1339 (SMULBB GPR:$a, GPR:$b)>; 1340def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 1341 (SMULBB GPR:$a, GPR:$b)>; 1342def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)), 1343 (SMULBT GPR:$a, GPR:$b)>; 1344def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)), 1345 (SMULBT GPR:$a, GPR:$b)>; 1346def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)), 1347 (SMULTB GPR:$a, GPR:$b)>; 1348def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b), 1349 (SMULTB GPR:$a, GPR:$b)>; 1350def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16), 1351 (SMULWB GPR:$a, GPR:$b)>; 1352def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16), 1353 (SMULWB GPR:$a, GPR:$b)>; 1354 1355def : ARMV5TEPat<(add GPR:$acc, 1356 (mul (sra (shl GPR:$a, 16), 16), 1357 (sra (shl GPR:$b, 16), 16))), 1358 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 1359def : ARMV5TEPat<(add GPR:$acc, 1360 (mul sext_16_node:$a, sext_16_node:$b)), 1361 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 1362def : ARMV5TEPat<(add GPR:$acc, 1363 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))), 1364 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 1365def : ARMV5TEPat<(add GPR:$acc, 1366 (mul sext_16_node:$a, (sra GPR:$b, 16))), 1367 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 1368def : ARMV5TEPat<(add GPR:$acc, 1369 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))), 1370 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 1371def : ARMV5TEPat<(add GPR:$acc, 1372 (mul (sra GPR:$a, 16), sext_16_node:$b)), 1373 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 1374def : ARMV5TEPat<(add GPR:$acc, 1375 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)), 1376 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 1377def : ARMV5TEPat<(add GPR:$acc, 1378 (sra (mul GPR:$a, sext_16_node:$b), 16)), 1379 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 1380 1381//===----------------------------------------------------------------------===// 1382// Thumb Support 1383// 1384 1385include "ARMInstrThumb.td" 1386 1387//===----------------------------------------------------------------------===// 1388// Thumb2 Support 1389// 1390 1391include "ARMInstrThumb2.td" 1392 1393//===----------------------------------------------------------------------===// 1394// Floating Point Support 1395// 1396 1397include "ARMInstrVFP.td" 1398