ARMISelLowering.h revision 212904
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/CodeGen/FastISel.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include <vector> 25 26namespace llvm { 27 class ARMConstantPoolValue; 28 29 namespace ARMISD { 30 // ARM Specific DAG Nodes 31 enum NodeType { 32 // Start the numbering where the builtin ops and target ops leave off. 33 FIRST_NUMBER = ISD::BUILTIN_OP_END, 34 35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 36 // TargetExternalSymbol, and TargetGlobalAddress. 37 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 38 39 CALL, // Function call. 40 CALL_PRED, // Function call that's predicable. 41 CALL_NOLINK, // Function call with branch not branch-and-link. 42 tCALL, // Thumb function call. 43 BRCOND, // Conditional branch. 44 BR_JT, // Jumptable branch. 45 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 46 RET_FLAG, // Return with a flag operand. 47 48 PIC_ADD, // Add with a PC operand and a PIC label. 49 50 AND, // ARM "and" instruction that sets the 's' flag in CPSR. 51 52 CMP, // ARM compare instructions. 53 CMPZ, // ARM compare that sets only Z flag. 54 CMPFP, // ARM VFP compare instruction, sets FPSCR. 55 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 56 FMSTAT, // ARM fmstat instruction. 57 CMOV, // ARM conditional move instructions. 58 CNEG, // ARM conditional negate instructions. 59 60 BCC_i64, 61 62 RBIT, // ARM bitreverse instruction 63 64 FTOSI, // FP to sint within a FP register. 65 FTOUI, // FP to uint within a FP register. 66 SITOF, // sint to FP within a FP register. 67 UITOF, // uint to FP within a FP register. 68 69 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 70 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 71 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 72 73 VMOVRRD, // double to two gprs. 74 VMOVDRR, // Two gprs to double. 75 76 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 77 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 78 79 TC_RETURN, // Tail call return pseudo. 80 81 THREAD_POINTER, 82 83 DYN_ALLOC, // Dynamic allocation on the stack. 84 85 MEMBARRIER, // Memory barrier 86 SYNCBARRIER, // Memory sync barrier 87 88 VCEQ, // Vector compare equal. 89 VCGE, // Vector compare greater than or equal. 90 VCGEU, // Vector compare unsigned greater than or equal. 91 VCGT, // Vector compare greater than. 92 VCGTU, // Vector compare unsigned greater than. 93 VTST, // Vector test bits. 94 95 // Vector shift by immediate: 96 VSHL, // ...left 97 VSHRs, // ...right (signed) 98 VSHRu, // ...right (unsigned) 99 VSHLLs, // ...left long (signed) 100 VSHLLu, // ...left long (unsigned) 101 VSHLLi, // ...left long (with maximum shift count) 102 VSHRN, // ...right narrow 103 104 // Vector rounding shift by immediate: 105 VRSHRs, // ...right (signed) 106 VRSHRu, // ...right (unsigned) 107 VRSHRN, // ...right narrow 108 109 // Vector saturating shift by immediate: 110 VQSHLs, // ...left (signed) 111 VQSHLu, // ...left (unsigned) 112 VQSHLsu, // ...left (signed to unsigned) 113 VQSHRNs, // ...right narrow (signed) 114 VQSHRNu, // ...right narrow (unsigned) 115 VQSHRNsu, // ...right narrow (signed to unsigned) 116 117 // Vector saturating rounding shift by immediate: 118 VQRSHRNs, // ...right narrow (signed) 119 VQRSHRNu, // ...right narrow (unsigned) 120 VQRSHRNsu, // ...right narrow (signed to unsigned) 121 122 // Vector shift and insert: 123 VSLI, // ...left 124 VSRI, // ...right 125 126 // Vector get lane (VMOV scalar to ARM core register) 127 // (These are used for 8- and 16-bit element types only.) 128 VGETLANEu, // zero-extend vector extract element 129 VGETLANEs, // sign-extend vector extract element 130 131 // Vector move immediate and move negated immediate: 132 VMOVIMM, 133 VMVNIMM, 134 135 // Vector duplicate: 136 VDUP, 137 VDUPLANE, 138 139 // Vector shuffles: 140 VEXT, // extract 141 VREV64, // reverse elements within 64-bit doublewords 142 VREV32, // reverse elements within 32-bit words 143 VREV16, // reverse elements within 16-bit halfwords 144 VZIP, // zip (interleave) 145 VUZP, // unzip (deinterleave) 146 VTRN, // transpose 147 148 // Vector multiply long: 149 VMULLs, // ...signed 150 VMULLu, // ...unsigned 151 152 // Operands of the standard BUILD_VECTOR node are not legalized, which 153 // is fine if BUILD_VECTORs are always lowered to shuffles or other 154 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 155 // operands need to be legalized. Define an ARM-specific version of 156 // BUILD_VECTOR for this purpose. 157 BUILD_VECTOR, 158 159 // Floating-point max and min: 160 FMAX, 161 FMIN, 162 163 // Bit-field insert 164 BFI 165 }; 166 } 167 168 /// Define some predicates that are used for node matching. 169 namespace ARM { 170 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 171 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 172 /// instruction, returns its 8-bit integer representation. Otherwise, 173 /// returns -1. 174 int getVFPf32Imm(const APFloat &FPImm); 175 int getVFPf64Imm(const APFloat &FPImm); 176 bool isBitFieldInvertedMask(unsigned v); 177 } 178 179 //===--------------------------------------------------------------------===// 180 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 181 182 class ARMTargetLowering : public TargetLowering { 183 public: 184 explicit ARMTargetLowering(TargetMachine &TM); 185 186 virtual unsigned getJumpTableEncoding(void) const; 187 188 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 189 190 /// ReplaceNodeResults - Replace the results of node with an illegal result 191 /// type with new values built out of custom code. 192 /// 193 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 194 SelectionDAG &DAG) const; 195 196 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 197 198 virtual const char *getTargetNodeName(unsigned Opcode) const; 199 200 virtual MachineBasicBlock * 201 EmitInstrWithCustomInserter(MachineInstr *MI, 202 MachineBasicBlock *MBB) const; 203 204 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 205 /// unaligned memory accesses. of the specified type. 206 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 207 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 208 209 /// isLegalAddressingMode - Return true if the addressing mode represented 210 /// by AM is legal for this target, for a load/store of the specified type. 211 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 212 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 213 214 /// isLegalICmpImmediate - Return true if the specified immediate is legal 215 /// icmp immediate, that is the target has icmp instructions which can 216 /// compare a register against the immediate without having to materialize 217 /// the immediate into a register. 218 virtual bool isLegalICmpImmediate(int64_t Imm) const; 219 220 /// getPreIndexedAddressParts - returns true by value, base pointer and 221 /// offset pointer and addressing mode by reference if the node's address 222 /// can be legally represented as pre-indexed load / store address. 223 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 224 SDValue &Offset, 225 ISD::MemIndexedMode &AM, 226 SelectionDAG &DAG) const; 227 228 /// getPostIndexedAddressParts - returns true by value, base pointer and 229 /// offset pointer and addressing mode by reference if this node can be 230 /// combined with a load / store to form a post-indexed load / store. 231 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 232 SDValue &Base, SDValue &Offset, 233 ISD::MemIndexedMode &AM, 234 SelectionDAG &DAG) const; 235 236 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 237 const APInt &Mask, 238 APInt &KnownZero, 239 APInt &KnownOne, 240 const SelectionDAG &DAG, 241 unsigned Depth) const; 242 243 244 ConstraintType getConstraintType(const std::string &Constraint) const; 245 std::pair<unsigned, const TargetRegisterClass*> 246 getRegForInlineAsmConstraint(const std::string &Constraint, 247 EVT VT) const; 248 std::vector<unsigned> 249 getRegClassForInlineAsmConstraint(const std::string &Constraint, 250 EVT VT) const; 251 252 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 253 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 254 /// true it means one of the asm constraint of the inline asm instruction 255 /// being processed is 'm'. 256 virtual void LowerAsmOperandForConstraint(SDValue Op, 257 char ConstraintLetter, 258 std::vector<SDValue> &Ops, 259 SelectionDAG &DAG) const; 260 261 const ARMSubtarget* getSubtarget() const { 262 return Subtarget; 263 } 264 265 /// getRegClassFor - Return the register class that should be used for the 266 /// specified value type. 267 virtual TargetRegisterClass *getRegClassFor(EVT VT) const; 268 269 /// getFunctionAlignment - Return the Log2 alignment of this function. 270 virtual unsigned getFunctionAlignment(const Function *F) const; 271 272 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 273 /// be used for loads / stores from the global. 274 virtual unsigned getMaximalGlobalOffset() const; 275 276 /// createFastISel - This method returns a target specific FastISel object, 277 /// or null if the target does not support "fast" ISel. 278 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 279 280 Sched::Preference getSchedulingPreference(SDNode *N) const; 281 282 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 283 MachineFunction &MF) const; 284 285 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 286 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 287 288 /// isFPImmLegal - Returns true if the target can instruction select the 289 /// specified FP immediate natively. If false, the legalizer will 290 /// materialize the FP immediate as a load from a constant pool. 291 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 292 293 protected: 294 std::pair<const TargetRegisterClass*, uint8_t> 295 findRepresentativeClass(EVT VT) const; 296 297 private: 298 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 299 /// make the right decision when generating code for different targets. 300 const ARMSubtarget *Subtarget; 301 302 const TargetRegisterInfo *RegInfo; 303 304 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 305 /// 306 unsigned ARMPCLabelIndex; 307 308 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 309 void addDRTypeForNEON(EVT VT); 310 void addQRTypeForNEON(EVT VT); 311 312 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 313 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 314 SDValue Chain, SDValue &Arg, 315 RegsToPassVector &RegsToPass, 316 CCValAssign &VA, CCValAssign &NextVA, 317 SDValue &StackPtr, 318 SmallVector<SDValue, 8> &MemOpChains, 319 ISD::ArgFlagsTy Flags) const; 320 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 321 SDValue &Root, SelectionDAG &DAG, 322 DebugLoc dl) const; 323 324 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 325 bool isVarArg) const; 326 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 327 DebugLoc dl, SelectionDAG &DAG, 328 const CCValAssign &VA, 329 ISD::ArgFlagsTy Flags) const; 330 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 331 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 332 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 333 const ARMSubtarget *Subtarget) const; 334 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 335 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 336 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 337 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 338 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 339 SelectionDAG &DAG) const; 340 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 341 SelectionDAG &DAG) const; 342 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 343 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 344 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 345 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 346 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 347 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 348 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 349 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 350 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 351 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 352 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 353 354 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 355 CallingConv::ID CallConv, bool isVarArg, 356 const SmallVectorImpl<ISD::InputArg> &Ins, 357 DebugLoc dl, SelectionDAG &DAG, 358 SmallVectorImpl<SDValue> &InVals) const; 359 360 virtual SDValue 361 LowerFormalArguments(SDValue Chain, 362 CallingConv::ID CallConv, bool isVarArg, 363 const SmallVectorImpl<ISD::InputArg> &Ins, 364 DebugLoc dl, SelectionDAG &DAG, 365 SmallVectorImpl<SDValue> &InVals) const; 366 367 virtual SDValue 368 LowerCall(SDValue Chain, SDValue Callee, 369 CallingConv::ID CallConv, bool isVarArg, 370 bool &isTailCall, 371 const SmallVectorImpl<ISD::OutputArg> &Outs, 372 const SmallVectorImpl<SDValue> &OutVals, 373 const SmallVectorImpl<ISD::InputArg> &Ins, 374 DebugLoc dl, SelectionDAG &DAG, 375 SmallVectorImpl<SDValue> &InVals) const; 376 377 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 378 /// for tail call optimization. Targets which want to do tail call 379 /// optimization should implement this function. 380 bool IsEligibleForTailCallOptimization(SDValue Callee, 381 CallingConv::ID CalleeCC, 382 bool isVarArg, 383 bool isCalleeStructRet, 384 bool isCallerStructRet, 385 const SmallVectorImpl<ISD::OutputArg> &Outs, 386 const SmallVectorImpl<SDValue> &OutVals, 387 const SmallVectorImpl<ISD::InputArg> &Ins, 388 SelectionDAG& DAG) const; 389 virtual SDValue 390 LowerReturn(SDValue Chain, 391 CallingConv::ID CallConv, bool isVarArg, 392 const SmallVectorImpl<ISD::OutputArg> &Outs, 393 const SmallVectorImpl<SDValue> &OutVals, 394 DebugLoc dl, SelectionDAG &DAG) const; 395 396 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 397 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 398 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 399 SelectionDAG &DAG, DebugLoc dl) const; 400 401 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 402 403 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 404 MachineBasicBlock *BB, 405 unsigned Size) const; 406 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 407 MachineBasicBlock *BB, 408 unsigned Size, 409 unsigned BinOpcode) const; 410 411 }; 412 413 namespace ARM { 414 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 415 } 416} 417 418#endif // ARMISELLOWERING_H 419