ARMISelLowering.h revision 210299
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include <vector> 23 24namespace llvm { 25 class ARMConstantPoolValue; 26 27 namespace ARMISD { 28 // ARM Specific DAG Nodes 29 enum NodeType { 30 // Start the numbering where the builtin ops and target ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 34 // TargetExternalSymbol, and TargetGlobalAddress. 35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 36 37 CALL, // Function call. 38 CALL_PRED, // Function call that's predicable. 39 CALL_NOLINK, // Function call with branch not branch-and-link. 40 tCALL, // Thumb function call. 41 BRCOND, // Conditional branch. 42 BR_JT, // Jumptable branch. 43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 44 RET_FLAG, // Return with a flag operand. 45 46 PIC_ADD, // Add with a PC operand and a PIC label. 47 48 CMP, // ARM compare instructions. 49 CMPZ, // ARM compare that sets only Z flag. 50 CMPFP, // ARM VFP compare instruction, sets FPSCR. 51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 52 FMSTAT, // ARM fmstat instruction. 53 CMOV, // ARM conditional move instructions. 54 CNEG, // ARM conditional negate instructions. 55 56 BCC_i64, 57 58 RBIT, // ARM bitreverse instruction 59 60 FTOSI, // FP to sint within a FP register. 61 FTOUI, // FP to uint within a FP register. 62 SITOF, // sint to FP within a FP register. 63 UITOF, // uint to FP within a FP register. 64 65 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 66 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 67 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 68 69 VMOVRRD, // double to two gprs. 70 VMOVDRR, // Two gprs to double. 71 72 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 73 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 74 75 TC_RETURN, // Tail call return pseudo. 76 77 THREAD_POINTER, 78 79 DYN_ALLOC, // Dynamic allocation on the stack. 80 81 MEMBARRIER, // Memory barrier 82 SYNCBARRIER, // Memory sync barrier 83 84 VCEQ, // Vector compare equal. 85 VCGE, // Vector compare greater than or equal. 86 VCGEU, // Vector compare unsigned greater than or equal. 87 VCGT, // Vector compare greater than. 88 VCGTU, // Vector compare unsigned greater than. 89 VTST, // Vector test bits. 90 91 // Vector shift by immediate: 92 VSHL, // ...left 93 VSHRs, // ...right (signed) 94 VSHRu, // ...right (unsigned) 95 VSHLLs, // ...left long (signed) 96 VSHLLu, // ...left long (unsigned) 97 VSHLLi, // ...left long (with maximum shift count) 98 VSHRN, // ...right narrow 99 100 // Vector rounding shift by immediate: 101 VRSHRs, // ...right (signed) 102 VRSHRu, // ...right (unsigned) 103 VRSHRN, // ...right narrow 104 105 // Vector saturating shift by immediate: 106 VQSHLs, // ...left (signed) 107 VQSHLu, // ...left (unsigned) 108 VQSHLsu, // ...left (signed to unsigned) 109 VQSHRNs, // ...right narrow (signed) 110 VQSHRNu, // ...right narrow (unsigned) 111 VQSHRNsu, // ...right narrow (signed to unsigned) 112 113 // Vector saturating rounding shift by immediate: 114 VQRSHRNs, // ...right narrow (signed) 115 VQRSHRNu, // ...right narrow (unsigned) 116 VQRSHRNsu, // ...right narrow (signed to unsigned) 117 118 // Vector shift and insert: 119 VSLI, // ...left 120 VSRI, // ...right 121 122 // Vector get lane (VMOV scalar to ARM core register) 123 // (These are used for 8- and 16-bit element types only.) 124 VGETLANEu, // zero-extend vector extract element 125 VGETLANEs, // sign-extend vector extract element 126 127 // Vector move immediate and move negated immediate: 128 VMOVIMM, 129 VMVNIMM, 130 131 // Vector duplicate: 132 VDUP, 133 VDUPLANE, 134 135 // Vector shuffles: 136 VEXT, // extract 137 VREV64, // reverse elements within 64-bit doublewords 138 VREV32, // reverse elements within 32-bit words 139 VREV16, // reverse elements within 16-bit halfwords 140 VZIP, // zip (interleave) 141 VUZP, // unzip (deinterleave) 142 VTRN, // transpose 143 144 // Operands of the standard BUILD_VECTOR node are not legalized, which 145 // is fine if BUILD_VECTORs are always lowered to shuffles or other 146 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 147 // operands need to be legalized. Define an ARM-specific version of 148 // BUILD_VECTOR for this purpose. 149 BUILD_VECTOR, 150 151 // Floating-point max and min: 152 FMAX, 153 FMIN 154 }; 155 } 156 157 /// Define some predicates that are used for node matching. 158 namespace ARM { 159 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 160 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 161 /// instruction, returns its 8-bit integer representation. Otherwise, 162 /// returns -1. 163 int getVFPf32Imm(const APFloat &FPImm); 164 int getVFPf64Imm(const APFloat &FPImm); 165 } 166 167 //===--------------------------------------------------------------------===// 168 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 169 170 class ARMTargetLowering : public TargetLowering { 171 public: 172 explicit ARMTargetLowering(TargetMachine &TM); 173 174 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 175 176 /// ReplaceNodeResults - Replace the results of node with an illegal result 177 /// type with new values built out of custom code. 178 /// 179 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 180 SelectionDAG &DAG) const; 181 182 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 183 184 virtual const char *getTargetNodeName(unsigned Opcode) const; 185 186 virtual MachineBasicBlock * 187 EmitInstrWithCustomInserter(MachineInstr *MI, 188 MachineBasicBlock *MBB) const; 189 190 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 191 /// unaligned memory accesses. of the specified type. 192 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 193 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 194 195 /// isLegalAddressingMode - Return true if the addressing mode represented 196 /// by AM is legal for this target, for a load/store of the specified type. 197 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 198 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 199 200 /// isLegalICmpImmediate - Return true if the specified immediate is legal 201 /// icmp immediate, that is the target has icmp instructions which can 202 /// compare a register against the immediate without having to materialize 203 /// the immediate into a register. 204 virtual bool isLegalICmpImmediate(int64_t Imm) const; 205 206 /// getPreIndexedAddressParts - returns true by value, base pointer and 207 /// offset pointer and addressing mode by reference if the node's address 208 /// can be legally represented as pre-indexed load / store address. 209 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 210 SDValue &Offset, 211 ISD::MemIndexedMode &AM, 212 SelectionDAG &DAG) const; 213 214 /// getPostIndexedAddressParts - returns true by value, base pointer and 215 /// offset pointer and addressing mode by reference if this node can be 216 /// combined with a load / store to form a post-indexed load / store. 217 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 218 SDValue &Base, SDValue &Offset, 219 ISD::MemIndexedMode &AM, 220 SelectionDAG &DAG) const; 221 222 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 223 const APInt &Mask, 224 APInt &KnownZero, 225 APInt &KnownOne, 226 const SelectionDAG &DAG, 227 unsigned Depth) const; 228 229 230 ConstraintType getConstraintType(const std::string &Constraint) const; 231 std::pair<unsigned, const TargetRegisterClass*> 232 getRegForInlineAsmConstraint(const std::string &Constraint, 233 EVT VT) const; 234 std::vector<unsigned> 235 getRegClassForInlineAsmConstraint(const std::string &Constraint, 236 EVT VT) const; 237 238 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 239 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 240 /// true it means one of the asm constraint of the inline asm instruction 241 /// being processed is 'm'. 242 virtual void LowerAsmOperandForConstraint(SDValue Op, 243 char ConstraintLetter, 244 std::vector<SDValue> &Ops, 245 SelectionDAG &DAG) const; 246 247 const ARMSubtarget* getSubtarget() const { 248 return Subtarget; 249 } 250 251 /// getRegClassFor - Return the register class that should be used for the 252 /// specified value type. 253 virtual TargetRegisterClass *getRegClassFor(EVT VT) const; 254 255 /// getFunctionAlignment - Return the Log2 alignment of this function. 256 virtual unsigned getFunctionAlignment(const Function *F) const; 257 258 Sched::Preference getSchedulingPreference(SDNode *N) const; 259 260 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 261 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 262 263 /// isFPImmLegal - Returns true if the target can instruction select the 264 /// specified FP immediate natively. If false, the legalizer will 265 /// materialize the FP immediate as a load from a constant pool. 266 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 267 268 private: 269 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 270 /// make the right decision when generating code for different targets. 271 const ARMSubtarget *Subtarget; 272 273 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 274 /// 275 unsigned ARMPCLabelIndex; 276 277 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 278 void addDRTypeForNEON(EVT VT); 279 void addQRTypeForNEON(EVT VT); 280 281 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 282 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 283 SDValue Chain, SDValue &Arg, 284 RegsToPassVector &RegsToPass, 285 CCValAssign &VA, CCValAssign &NextVA, 286 SDValue &StackPtr, 287 SmallVector<SDValue, 8> &MemOpChains, 288 ISD::ArgFlagsTy Flags) const; 289 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 290 SDValue &Root, SelectionDAG &DAG, 291 DebugLoc dl) const; 292 293 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 294 bool isVarArg) const; 295 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 296 DebugLoc dl, SelectionDAG &DAG, 297 const CCValAssign &VA, 298 ISD::ArgFlagsTy Flags) const; 299 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 300 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 301 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 302 const ARMSubtarget *Subtarget) const; 303 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 304 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 305 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 306 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 307 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 308 SelectionDAG &DAG) const; 309 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 310 SelectionDAG &DAG) const; 311 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 312 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 313 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 314 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 315 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 316 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 317 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 318 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 319 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 320 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 321 322 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 323 CallingConv::ID CallConv, bool isVarArg, 324 const SmallVectorImpl<ISD::InputArg> &Ins, 325 DebugLoc dl, SelectionDAG &DAG, 326 SmallVectorImpl<SDValue> &InVals) const; 327 328 virtual SDValue 329 LowerFormalArguments(SDValue Chain, 330 CallingConv::ID CallConv, bool isVarArg, 331 const SmallVectorImpl<ISD::InputArg> &Ins, 332 DebugLoc dl, SelectionDAG &DAG, 333 SmallVectorImpl<SDValue> &InVals) const; 334 335 virtual SDValue 336 LowerCall(SDValue Chain, SDValue Callee, 337 CallingConv::ID CallConv, bool isVarArg, 338 bool &isTailCall, 339 const SmallVectorImpl<ISD::OutputArg> &Outs, 340 const SmallVectorImpl<SDValue> &OutVals, 341 const SmallVectorImpl<ISD::InputArg> &Ins, 342 DebugLoc dl, SelectionDAG &DAG, 343 SmallVectorImpl<SDValue> &InVals) const; 344 345 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 346 /// for tail call optimization. Targets which want to do tail call 347 /// optimization should implement this function. 348 bool IsEligibleForTailCallOptimization(SDValue Callee, 349 CallingConv::ID CalleeCC, 350 bool isVarArg, 351 bool isCalleeStructRet, 352 bool isCallerStructRet, 353 const SmallVectorImpl<ISD::OutputArg> &Outs, 354 const SmallVectorImpl<SDValue> &OutVals, 355 const SmallVectorImpl<ISD::InputArg> &Ins, 356 SelectionDAG& DAG) const; 357 virtual SDValue 358 LowerReturn(SDValue Chain, 359 CallingConv::ID CallConv, bool isVarArg, 360 const SmallVectorImpl<ISD::OutputArg> &Outs, 361 const SmallVectorImpl<SDValue> &OutVals, 362 DebugLoc dl, SelectionDAG &DAG) const; 363 364 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 365 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 366 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 367 SelectionDAG &DAG, DebugLoc dl) const; 368 369 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 370 371 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 372 MachineBasicBlock *BB, 373 unsigned Size) const; 374 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 375 MachineBasicBlock *BB, 376 unsigned Size, 377 unsigned BinOpcode) const; 378 379 }; 380} 381 382#endif // ARMISELLOWERING_H 383