ARMISelLowering.h revision 199481
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include <vector> 23 24namespace llvm { 25 class ARMConstantPoolValue; 26 27 namespace ARMISD { 28 // ARM Specific DAG Nodes 29 enum NodeType { 30 // Start the numbering where the builtin ops and target ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 34 // TargetExternalSymbol, and TargetGlobalAddress. 35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 36 37 CALL, // Function call. 38 CALL_PRED, // Function call that's predicable. 39 CALL_NOLINK, // Function call with branch not branch-and-link. 40 tCALL, // Thumb function call. 41 BRCOND, // Conditional branch. 42 BR_JT, // Jumptable branch. 43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 44 RET_FLAG, // Return with a flag operand. 45 46 PIC_ADD, // Add with a PC operand and a PIC label. 47 48 CMP, // ARM compare instructions. 49 CMPZ, // ARM compare that sets only Z flag. 50 CMPFP, // ARM VFP compare instruction, sets FPSCR. 51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 52 FMSTAT, // ARM fmstat instruction. 53 CMOV, // ARM conditional move instructions. 54 CNEG, // ARM conditional negate instructions. 55 56 FTOSI, // FP to sint within a FP register. 57 FTOUI, // FP to uint within a FP register. 58 SITOF, // sint to FP within a FP register. 59 UITOF, // uint to FP within a FP register. 60 61 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 62 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 63 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 64 65 VMOVRRD, // double to two gprs. 66 VMOVDRR, // Two gprs to double. 67 68 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 69 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 70 71 THREAD_POINTER, 72 73 DYN_ALLOC, // Dynamic allocation on the stack. 74 75 VCEQ, // Vector compare equal. 76 VCGE, // Vector compare greater than or equal. 77 VCGEU, // Vector compare unsigned greater than or equal. 78 VCGT, // Vector compare greater than. 79 VCGTU, // Vector compare unsigned greater than. 80 VTST, // Vector test bits. 81 82 // Vector shift by immediate: 83 VSHL, // ...left 84 VSHRs, // ...right (signed) 85 VSHRu, // ...right (unsigned) 86 VSHLLs, // ...left long (signed) 87 VSHLLu, // ...left long (unsigned) 88 VSHLLi, // ...left long (with maximum shift count) 89 VSHRN, // ...right narrow 90 91 // Vector rounding shift by immediate: 92 VRSHRs, // ...right (signed) 93 VRSHRu, // ...right (unsigned) 94 VRSHRN, // ...right narrow 95 96 // Vector saturating shift by immediate: 97 VQSHLs, // ...left (signed) 98 VQSHLu, // ...left (unsigned) 99 VQSHLsu, // ...left (signed to unsigned) 100 VQSHRNs, // ...right narrow (signed) 101 VQSHRNu, // ...right narrow (unsigned) 102 VQSHRNsu, // ...right narrow (signed to unsigned) 103 104 // Vector saturating rounding shift by immediate: 105 VQRSHRNs, // ...right narrow (signed) 106 VQRSHRNu, // ...right narrow (unsigned) 107 VQRSHRNsu, // ...right narrow (signed to unsigned) 108 109 // Vector shift and insert: 110 VSLI, // ...left 111 VSRI, // ...right 112 113 // Vector get lane (VMOV scalar to ARM core register) 114 // (These are used for 8- and 16-bit element types only.) 115 VGETLANEu, // zero-extend vector extract element 116 VGETLANEs, // sign-extend vector extract element 117 118 // Vector duplicate: 119 VDUP, 120 VDUPLANE, 121 122 // Vector shuffles: 123 VEXT, // extract 124 VREV64, // reverse elements within 64-bit doublewords 125 VREV32, // reverse elements within 32-bit words 126 VREV16, // reverse elements within 16-bit halfwords 127 VZIP, // zip (interleave) 128 VUZP, // unzip (deinterleave) 129 VTRN // transpose 130 }; 131 } 132 133 /// Define some predicates that are used for node matching. 134 namespace ARM { 135 /// getVMOVImm - If this is a build_vector of constants which can be 136 /// formed by using a VMOV instruction of the specified element size, 137 /// return the constant being splatted. The ByteSize field indicates the 138 /// number of bytes of each element [1248]. 139 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 140 141 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 142 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 143 /// instruction, returns its 8-bit integer representation. Otherwise, 144 /// returns -1. 145 int getVFPf32Imm(const APFloat &FPImm); 146 int getVFPf64Imm(const APFloat &FPImm); 147 } 148 149 //===--------------------------------------------------------------------===// 150 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 151 152 class ARMTargetLowering : public TargetLowering { 153 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 154 public: 155 explicit ARMTargetLowering(TargetMachine &TM); 156 157 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 158 159 /// ReplaceNodeResults - Replace the results of node with an illegal result 160 /// type with new values built out of custom code. 161 /// 162 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 163 SelectionDAG &DAG); 164 165 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 166 167 virtual const char *getTargetNodeName(unsigned Opcode) const; 168 169 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 170 MachineBasicBlock *MBB, 171 DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const; 172 173 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 174 /// unaligned memory accesses. of the specified type. 175 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 176 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 177 178 /// isLegalAddressingMode - Return true if the addressing mode represented 179 /// by AM is legal for this target, for a load/store of the specified type. 180 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 181 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 182 183 /// isLegalICmpImmediate - Return true if the specified immediate is legal 184 /// icmp immediate, that is the target has icmp instructions which can compare 185 /// a register against the immediate without having to materialize the 186 /// immediate into a register. 187 virtual bool isLegalICmpImmediate(int64_t Imm) const; 188 189 /// getPreIndexedAddressParts - returns true by value, base pointer and 190 /// offset pointer and addressing mode by reference if the node's address 191 /// can be legally represented as pre-indexed load / store address. 192 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 193 SDValue &Offset, 194 ISD::MemIndexedMode &AM, 195 SelectionDAG &DAG) const; 196 197 /// getPostIndexedAddressParts - returns true by value, base pointer and 198 /// offset pointer and addressing mode by reference if this node can be 199 /// combined with a load / store to form a post-indexed load / store. 200 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 201 SDValue &Base, SDValue &Offset, 202 ISD::MemIndexedMode &AM, 203 SelectionDAG &DAG) const; 204 205 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 206 const APInt &Mask, 207 APInt &KnownZero, 208 APInt &KnownOne, 209 const SelectionDAG &DAG, 210 unsigned Depth) const; 211 212 213 ConstraintType getConstraintType(const std::string &Constraint) const; 214 std::pair<unsigned, const TargetRegisterClass*> 215 getRegForInlineAsmConstraint(const std::string &Constraint, 216 EVT VT) const; 217 std::vector<unsigned> 218 getRegClassForInlineAsmConstraint(const std::string &Constraint, 219 EVT VT) const; 220 221 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 222 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 223 /// true it means one of the asm constraint of the inline asm instruction 224 /// being processed is 'm'. 225 virtual void LowerAsmOperandForConstraint(SDValue Op, 226 char ConstraintLetter, 227 bool hasMemory, 228 std::vector<SDValue> &Ops, 229 SelectionDAG &DAG) const; 230 231 virtual const ARMSubtarget* getSubtarget() { 232 return Subtarget; 233 } 234 235 /// getFunctionAlignment - Return the Log2 alignment of this function. 236 virtual unsigned getFunctionAlignment(const Function *F) const; 237 238 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 239 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 240 241 /// isFPImmLegal - Returns true if the target can instruction select the 242 /// specified FP immediate natively. If false, the legalizer will 243 /// materialize the FP immediate as a load from a constant pool. 244 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 245 246 private: 247 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 248 /// make the right decision when generating code for different targets. 249 const ARMSubtarget *Subtarget; 250 251 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 252 /// 253 unsigned ARMPCLabelIndex; 254 255 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 256 void addDRTypeForNEON(EVT VT); 257 void addQRTypeForNEON(EVT VT); 258 259 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 260 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 261 SDValue Chain, SDValue &Arg, 262 RegsToPassVector &RegsToPass, 263 CCValAssign &VA, CCValAssign &NextVA, 264 SDValue &StackPtr, 265 SmallVector<SDValue, 8> &MemOpChains, 266 ISD::ArgFlagsTy Flags); 267 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 268 SDValue &Root, SelectionDAG &DAG, DebugLoc dl); 269 270 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const; 271 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 272 DebugLoc dl, SelectionDAG &DAG, 273 const CCValAssign &VA, 274 ISD::ArgFlagsTy Flags); 275 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG); 276 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 277 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 278 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG); 279 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG); 280 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 281 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 282 SelectionDAG &DAG); 283 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 284 SelectionDAG &DAG); 285 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG); 286 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); 287 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); 288 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); 289 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 290 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 291 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG); 292 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG); 293 294 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 295 SDValue Chain, 296 SDValue Dst, SDValue Src, 297 SDValue Size, unsigned Align, 298 bool AlwaysInline, 299 const Value *DstSV, uint64_t DstSVOff, 300 const Value *SrcSV, uint64_t SrcSVOff); 301 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 302 CallingConv::ID CallConv, bool isVarArg, 303 const SmallVectorImpl<ISD::InputArg> &Ins, 304 DebugLoc dl, SelectionDAG &DAG, 305 SmallVectorImpl<SDValue> &InVals); 306 307 virtual SDValue 308 LowerFormalArguments(SDValue Chain, 309 CallingConv::ID CallConv, bool isVarArg, 310 const SmallVectorImpl<ISD::InputArg> &Ins, 311 DebugLoc dl, SelectionDAG &DAG, 312 SmallVectorImpl<SDValue> &InVals); 313 314 virtual SDValue 315 LowerCall(SDValue Chain, SDValue Callee, 316 CallingConv::ID CallConv, bool isVarArg, 317 bool isTailCall, 318 const SmallVectorImpl<ISD::OutputArg> &Outs, 319 const SmallVectorImpl<ISD::InputArg> &Ins, 320 DebugLoc dl, SelectionDAG &DAG, 321 SmallVectorImpl<SDValue> &InVals); 322 323 virtual SDValue 324 LowerReturn(SDValue Chain, 325 CallingConv::ID CallConv, bool isVarArg, 326 const SmallVectorImpl<ISD::OutputArg> &Outs, 327 DebugLoc dl, SelectionDAG &DAG); 328 329 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 330 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl); 331 }; 332} 333 334#endif // ARMISELLOWERING_H 335