ARMISelLowering.h revision 194710
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include <vector> 23 24namespace llvm { 25 class ARMConstantPoolValue; 26 27 namespace ARMISD { 28 // ARM Specific DAG Nodes 29 enum NodeType { 30 // Start the numbering where the builtin ops and target ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 34 // TargetExternalSymbol, and TargetGlobalAddress. 35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 36 37 CALL, // Function call. 38 CALL_PRED, // Function call that's predicable. 39 CALL_NOLINK, // Function call with branch not branch-and-link. 40 tCALL, // Thumb function call. 41 BRCOND, // Conditional branch. 42 BR_JT, // Jumptable branch. 43 RET_FLAG, // Return with a flag operand. 44 45 PIC_ADD, // Add with a PC operand and a PIC label. 46 47 CMP, // ARM compare instructions. 48 CMPNZ, // ARM compare that uses only N or Z flags. 49 CMPFP, // ARM VFP compare instruction, sets FPSCR. 50 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 51 FMSTAT, // ARM fmstat instruction. 52 CMOV, // ARM conditional move instructions. 53 CNEG, // ARM conditional negate instructions. 54 55 FTOSI, // FP to sint within a FP register. 56 FTOUI, // FP to uint within a FP register. 57 SITOF, // sint to FP within a FP register. 58 UITOF, // uint to FP within a FP register. 59 60 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 61 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 62 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 63 64 FMRRD, // double to two gprs. 65 FMDRR, // Two gprs to double. 66 67 EH_SJLJ_SETJMP, // SjLj exception handling setjmp 68 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp 69 70 THREAD_POINTER, 71 72 VCEQ, // Vector compare equal. 73 VCGE, // Vector compare greater than or equal. 74 VCGEU, // Vector compare unsigned greater than or equal. 75 VCGT, // Vector compare greater than. 76 VCGTU, // Vector compare unsigned greater than. 77 VTST, // Vector test bits. 78 79 // Vector shift by immediate: 80 VSHL, // ...left 81 VSHRs, // ...right (signed) 82 VSHRu, // ...right (unsigned) 83 VSHLLs, // ...left long (signed) 84 VSHLLu, // ...left long (unsigned) 85 VSHLLi, // ...left long (with maximum shift count) 86 VSHRN, // ...right narrow 87 88 // Vector rounding shift by immediate: 89 VRSHRs, // ...right (signed) 90 VRSHRu, // ...right (unsigned) 91 VRSHRN, // ...right narrow 92 93 // Vector saturating shift by immediate: 94 VQSHLs, // ...left (signed) 95 VQSHLu, // ...left (unsigned) 96 VQSHLsu, // ...left (signed to unsigned) 97 VQSHRNs, // ...right narrow (signed) 98 VQSHRNu, // ...right narrow (unsigned) 99 VQSHRNsu, // ...right narrow (signed to unsigned) 100 101 // Vector saturating rounding shift by immediate: 102 VQRSHRNs, // ...right narrow (signed) 103 VQRSHRNu, // ...right narrow (unsigned) 104 VQRSHRNsu, // ...right narrow (signed to unsigned) 105 106 // Vector shift and insert: 107 VSLI, // ...left 108 VSRI, // ...right 109 110 // Vector get lane (VMOV scalar to ARM core register) 111 // (These are used for 8- and 16-bit element types only.) 112 VGETLANEu, // zero-extend vector extract element 113 VGETLANEs, // sign-extend vector extract element 114 115 // Vector duplicate lane (128-bit result only; 64-bit is a shuffle) 116 VDUPLANEQ // splat a lane from a 64-bit vector to a 128-bit vector 117 }; 118 } 119 120 /// Define some predicates that are used for node matching. 121 namespace ARM { 122 /// getVMOVImm - If this is a build_vector of constants which can be 123 /// formed by using a VMOV instruction of the specified element size, 124 /// return the constant being splatted. The ByteSize field indicates the 125 /// number of bytes of each element [1248]. 126 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 127 } 128 129 //===--------------------------------------------------------------------===// 130 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 131 132 class ARMTargetLowering : public TargetLowering { 133 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 134 public: 135 explicit ARMTargetLowering(TargetMachine &TM); 136 137 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 138 139 /// ReplaceNodeResults - Replace the results of node with an illegal result 140 /// type with new values built out of custom code. 141 /// 142 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 143 SelectionDAG &DAG); 144 145 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 146 147 virtual const char *getTargetNodeName(unsigned Opcode) const; 148 149 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 150 MachineBasicBlock *MBB) const; 151 152 /// isLegalAddressingMode - Return true if the addressing mode represented 153 /// by AM is legal for this target, for a load/store of the specified type. 154 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 155 156 /// getPreIndexedAddressParts - returns true by value, base pointer and 157 /// offset pointer and addressing mode by reference if the node's address 158 /// can be legally represented as pre-indexed load / store address. 159 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 160 SDValue &Offset, 161 ISD::MemIndexedMode &AM, 162 SelectionDAG &DAG) const; 163 164 /// getPostIndexedAddressParts - returns true by value, base pointer and 165 /// offset pointer and addressing mode by reference if this node can be 166 /// combined with a load / store to form a post-indexed load / store. 167 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 168 SDValue &Base, SDValue &Offset, 169 ISD::MemIndexedMode &AM, 170 SelectionDAG &DAG) const; 171 172 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 173 const APInt &Mask, 174 APInt &KnownZero, 175 APInt &KnownOne, 176 const SelectionDAG &DAG, 177 unsigned Depth) const; 178 ConstraintType getConstraintType(const std::string &Constraint) const; 179 std::pair<unsigned, const TargetRegisterClass*> 180 getRegForInlineAsmConstraint(const std::string &Constraint, 181 MVT VT) const; 182 std::vector<unsigned> 183 getRegClassForInlineAsmConstraint(const std::string &Constraint, 184 MVT VT) const; 185 186 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 187 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 188 /// true it means one of the asm constraint of the inline asm instruction 189 /// being processed is 'm'. 190 virtual void LowerAsmOperandForConstraint(SDValue Op, 191 char ConstraintLetter, 192 bool hasMemory, 193 std::vector<SDValue> &Ops, 194 SelectionDAG &DAG) const; 195 196 virtual const ARMSubtarget* getSubtarget() { 197 return Subtarget; 198 } 199 200 private: 201 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 202 /// make the right decision when generating code for different targets. 203 const ARMSubtarget *Subtarget; 204 205 /// ARMPCLabelIndex - Keep track the number of ARM PC labels created. 206 /// 207 unsigned ARMPCLabelIndex; 208 209 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 210 void addDRTypeForNEON(MVT VT); 211 void addQRTypeForNEON(MVT VT); 212 213 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 214 void PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG, 215 SDValue Chain, SDValue &Arg, 216 RegsToPassVector &RegsToPass, 217 CCValAssign &VA, CCValAssign &NextVA, 218 SDValue &StackPtr, 219 SmallVector<SDValue, 8> &MemOpChains, 220 ISD::ArgFlagsTy Flags); 221 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 222 SDValue &Root, SelectionDAG &DAG, DebugLoc dl); 223 224 CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return) const; 225 SDValue LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, 226 const SDValue &StackPtr, const CCValAssign &VA, 227 SDValue Chain, SDValue Arg, ISD::ArgFlagsTy Flags); 228 SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, 229 unsigned CallingConv, SelectionDAG &DAG); 230 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG); 231 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 232 SDValue LowerRET(SDValue Op, SelectionDAG &DAG); 233 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG); 234 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG); 235 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 236 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 237 SelectionDAG &DAG); 238 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 239 SelectionDAG &DAG); 240 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG); 241 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); 242 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); 243 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 244 245 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 246 SDValue Chain, 247 SDValue Dst, SDValue Src, 248 SDValue Size, unsigned Align, 249 bool AlwaysInline, 250 const Value *DstSV, uint64_t DstSVOff, 251 const Value *SrcSV, uint64_t SrcSVOff); 252 }; 253} 254 255#endif // ARMISELLOWERING_H 256