ARMBaseRegisterInfo.cpp revision 243830
1234353Sdim//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2198090Srdivacky// 3198090Srdivacky// The LLVM Compiler Infrastructure 4198090Srdivacky// 5198090Srdivacky// This file is distributed under the University of Illinois Open Source 6198090Srdivacky// License. See LICENSE.TXT for details. 7198090Srdivacky// 8198090Srdivacky//===----------------------------------------------------------------------===// 9198090Srdivacky// 10198090Srdivacky// This file contains the base ARM implementation of TargetRegisterInfo class. 11198090Srdivacky// 12198090Srdivacky//===----------------------------------------------------------------------===// 13198090Srdivacky 14234353Sdim#include "ARMBaseRegisterInfo.h" 15198090Srdivacky#include "ARM.h" 16198090Srdivacky#include "ARMBaseInstrInfo.h" 17218893Sdim#include "ARMFrameLowering.h" 18198090Srdivacky#include "ARMMachineFunctionInfo.h" 19198090Srdivacky#include "ARMSubtarget.h" 20226633Sdim#include "MCTargetDesc/ARMAddressingModes.h" 21198090Srdivacky#include "llvm/Constants.h" 22198090Srdivacky#include "llvm/DerivedTypes.h" 23198090Srdivacky#include "llvm/Function.h" 24198090Srdivacky#include "llvm/LLVMContext.h" 25198090Srdivacky#include "llvm/CodeGen/MachineConstantPool.h" 26198090Srdivacky#include "llvm/CodeGen/MachineFrameInfo.h" 27198090Srdivacky#include "llvm/CodeGen/MachineFunction.h" 28198090Srdivacky#include "llvm/CodeGen/MachineInstrBuilder.h" 29198090Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 30198090Srdivacky#include "llvm/CodeGen/RegisterScavenging.h" 31198892Srdivacky#include "llvm/Support/Debug.h" 32198090Srdivacky#include "llvm/Support/ErrorHandling.h" 33198090Srdivacky#include "llvm/Support/raw_ostream.h" 34218893Sdim#include "llvm/Target/TargetFrameLowering.h" 35198090Srdivacky#include "llvm/Target/TargetMachine.h" 36198090Srdivacky#include "llvm/Target/TargetOptions.h" 37198090Srdivacky#include "llvm/ADT/BitVector.h" 38198090Srdivacky#include "llvm/ADT/SmallVector.h" 39198396Srdivacky#include "llvm/Support/CommandLine.h" 40198090Srdivacky 41224145Sdim#define GET_REGINFO_TARGET_DESC 42224145Sdim#include "ARMGenRegisterInfo.inc" 43224145Sdim 44218893Sdimusing namespace llvm; 45218893Sdim 46212904Sdimstatic cl::opt<bool> 47212904SdimForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), 48212904Sdim cl::desc("Force use of virtual base registers for stack load/store")); 49212904Sdimstatic cl::opt<bool> 50212904SdimEnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, 51212904Sdim cl::desc("Enable pre-regalloc stack frame index allocation")); 52212904Sdimstatic cl::opt<bool> 53212904SdimEnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), 54212904Sdim cl::desc("Enable use of a base pointer for complex stack frames")); 55212904Sdim 56198090SrdivackyARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 57198090Srdivacky const ARMSubtarget &sti) 58226633Sdim : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), 59212904Sdim FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 60212904Sdim BasePtr(ARM::R6) { 61198090Srdivacky} 62198090Srdivacky 63234353Sdimconst uint16_t* 64198090SrdivackyARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 65239462Sdim bool ghcCall = false; 66239462Sdim 67239462Sdim if (MF) { 68239462Sdim const Function *F = MF->getFunction(); 69239462Sdim ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 70239462Sdim } 71239462Sdim 72239462Sdim if (ghcCall) { 73239462Sdim return CSR_GHC_SaveList; 74239462Sdim } 75239462Sdim else { 76239462Sdim return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 77239462Sdim ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 78239462Sdim } 79234353Sdim} 80228379Sdim 81234353Sdimconst uint32_t* 82234353SdimARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 83239462Sdim return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 84239462Sdim ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 85198090Srdivacky} 86198090Srdivacky 87243830Sdimconst uint32_t* 88243830SdimARMBaseRegisterInfo::getNoPreservedMask() const { 89243830Sdim return CSR_NoRegs_RegMask; 90243830Sdim} 91243830Sdim 92202375SrdivackyBitVector ARMBaseRegisterInfo:: 93202375SrdivackygetReservedRegs(const MachineFunction &MF) const { 94218893Sdim const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 95218893Sdim 96221345Sdim // FIXME: avoid re-calculating this every time. 97198090Srdivacky BitVector Reserved(getNumRegs()); 98198090Srdivacky Reserved.set(ARM::SP); 99198090Srdivacky Reserved.set(ARM::PC); 100212904Sdim Reserved.set(ARM::FPSCR); 101218893Sdim if (TFI->hasFP(MF)) 102198090Srdivacky Reserved.set(FramePtr); 103212904Sdim if (hasBasePointer(MF)) 104212904Sdim Reserved.set(BasePtr); 105198090Srdivacky // Some targets reserve R9. 106198090Srdivacky if (STI.isR9Reserved()) 107198090Srdivacky Reserved.set(ARM::R9); 108224145Sdim // Reserve D16-D31 if the subtarget doesn't support them. 109224145Sdim if (!STI.hasVFP3() || STI.hasD16()) { 110224145Sdim assert(ARM::D31 == ARM::D16 + 15); 111224145Sdim for (unsigned i = 0; i != 16; ++i) 112224145Sdim Reserved.set(ARM::D16 + i); 113224145Sdim } 114243830Sdim const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 115243830Sdim for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 116243830Sdim for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 117243830Sdim if (Reserved.test(*SI)) Reserved.set(*I); 118243830Sdim 119198090Srdivacky return Reserved; 120198090Srdivacky} 121198090Srdivacky 122221345Sdimconst TargetRegisterClass* 123221345SdimARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 124221345Sdim const { 125221345Sdim const TargetRegisterClass *Super = RC; 126226633Sdim TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 127221345Sdim do { 128221345Sdim switch (Super->getID()) { 129221345Sdim case ARM::GPRRegClassID: 130221345Sdim case ARM::SPRRegClassID: 131221345Sdim case ARM::DPRRegClassID: 132221345Sdim case ARM::QPRRegClassID: 133221345Sdim case ARM::QQPRRegClassID: 134221345Sdim case ARM::QQQQPRRegClassID: 135243830Sdim case ARM::GPRPairRegClassID: 136221345Sdim return Super; 137221345Sdim } 138221345Sdim Super = *I++; 139221345Sdim } while (Super); 140221345Sdim return RC; 141221345Sdim} 142208599Srdivacky 143198892Srdivackyconst TargetRegisterClass * 144239462SdimARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 145239462Sdim const { 146239462Sdim return &ARM::GPRRegClass; 147198090Srdivacky} 148198090Srdivacky 149226633Sdimconst TargetRegisterClass * 150226633SdimARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 151226633Sdim if (RC == &ARM::CCRRegClass) 152226633Sdim return 0; // Can't copy CCR registers. 153226633Sdim return RC; 154226633Sdim} 155226633Sdim 156221345Sdimunsigned 157221345SdimARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 158221345Sdim MachineFunction &MF) const { 159221345Sdim const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 160221345Sdim 161221345Sdim switch (RC->getID()) { 162221345Sdim default: 163221345Sdim return 0; 164221345Sdim case ARM::tGPRRegClassID: 165221345Sdim return TFI->hasFP(MF) ? 4 : 5; 166221345Sdim case ARM::GPRRegClassID: { 167221345Sdim unsigned FP = TFI->hasFP(MF) ? 1 : 0; 168221345Sdim return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 169221345Sdim } 170221345Sdim case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 171221345Sdim case ARM::DPRRegClassID: 172221345Sdim return 32 - 10; 173221345Sdim } 174221345Sdim} 175221345Sdim 176224145Sdim/// getRawAllocationOrder - Returns the register allocation order for a 177224145Sdim/// specified register class with a target-dependent hint. 178234353SdimArrayRef<uint16_t> 179224145SdimARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, 180224145Sdim unsigned HintType, unsigned HintReg, 181224145Sdim const MachineFunction &MF) const { 182218893Sdim const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 183198090Srdivacky // Alternative register allocation orders when favoring even / odd registers 184198090Srdivacky // of register pairs. 185198090Srdivacky 186198090Srdivacky // No FP, R9 is available. 187234353Sdim static const uint16_t GPREven1[] = { 188198090Srdivacky ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 189198090Srdivacky ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 190198090Srdivacky ARM::R9, ARM::R11 191198090Srdivacky }; 192234353Sdim static const uint16_t GPROdd1[] = { 193198090Srdivacky ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 194198090Srdivacky ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 195198090Srdivacky ARM::R8, ARM::R10 196198090Srdivacky }; 197198090Srdivacky 198198090Srdivacky // FP is R7, R9 is available. 199234353Sdim static const uint16_t GPREven2[] = { 200198090Srdivacky ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 201198090Srdivacky ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 202198090Srdivacky ARM::R9, ARM::R11 203198090Srdivacky }; 204234353Sdim static const uint16_t GPROdd2[] = { 205198090Srdivacky ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 206198090Srdivacky ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 207198090Srdivacky ARM::R8, ARM::R10 208198090Srdivacky }; 209198090Srdivacky 210198090Srdivacky // FP is R11, R9 is available. 211234353Sdim static const uint16_t GPREven3[] = { 212198090Srdivacky ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 213198090Srdivacky ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 214198090Srdivacky ARM::R9 215198090Srdivacky }; 216234353Sdim static const uint16_t GPROdd3[] = { 217198090Srdivacky ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 218198090Srdivacky ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 219198090Srdivacky ARM::R8 220198090Srdivacky }; 221198090Srdivacky 222198090Srdivacky // No FP, R9 is not available. 223234353Sdim static const uint16_t GPREven4[] = { 224198090Srdivacky ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 225198090Srdivacky ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 226198090Srdivacky ARM::R11 227198090Srdivacky }; 228234353Sdim static const uint16_t GPROdd4[] = { 229198090Srdivacky ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 230198090Srdivacky ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 231198090Srdivacky ARM::R10 232198090Srdivacky }; 233198090Srdivacky 234198090Srdivacky // FP is R7, R9 is not available. 235234353Sdim static const uint16_t GPREven5[] = { 236198090Srdivacky ARM::R0, ARM::R2, ARM::R4, ARM::R10, 237198090Srdivacky ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 238198090Srdivacky ARM::R11 239198090Srdivacky }; 240234353Sdim static const uint16_t GPROdd5[] = { 241198090Srdivacky ARM::R1, ARM::R3, ARM::R5, ARM::R11, 242198090Srdivacky ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 243198090Srdivacky ARM::R10 244198090Srdivacky }; 245198090Srdivacky 246198090Srdivacky // FP is R11, R9 is not available. 247234353Sdim static const uint16_t GPREven6[] = { 248198090Srdivacky ARM::R0, ARM::R2, ARM::R4, ARM::R6, 249198090Srdivacky ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 250198090Srdivacky }; 251234353Sdim static const uint16_t GPROdd6[] = { 252198090Srdivacky ARM::R1, ARM::R3, ARM::R5, ARM::R7, 253198090Srdivacky ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 254198090Srdivacky }; 255198090Srdivacky 256221345Sdim // We only support even/odd hints for GPR and rGPR. 257239462Sdim if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass) 258224145Sdim return RC->getRawAllocationOrder(MF); 259198090Srdivacky 260198090Srdivacky if (HintType == ARMRI::RegPairEven) { 261198090Srdivacky if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 262198090Srdivacky // It's no longer possible to fulfill this hint. Return the default 263198090Srdivacky // allocation order. 264224145Sdim return RC->getRawAllocationOrder(MF); 265198090Srdivacky 266218893Sdim if (!TFI->hasFP(MF)) { 267198090Srdivacky if (!STI.isR9Reserved()) 268226633Sdim return makeArrayRef(GPREven1); 269198090Srdivacky else 270226633Sdim return makeArrayRef(GPREven4); 271198090Srdivacky } else if (FramePtr == ARM::R7) { 272198090Srdivacky if (!STI.isR9Reserved()) 273226633Sdim return makeArrayRef(GPREven2); 274198090Srdivacky else 275226633Sdim return makeArrayRef(GPREven5); 276198090Srdivacky } else { // FramePtr == ARM::R11 277198090Srdivacky if (!STI.isR9Reserved()) 278226633Sdim return makeArrayRef(GPREven3); 279198090Srdivacky else 280226633Sdim return makeArrayRef(GPREven6); 281198090Srdivacky } 282198090Srdivacky } else if (HintType == ARMRI::RegPairOdd) { 283198090Srdivacky if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 284198090Srdivacky // It's no longer possible to fulfill this hint. Return the default 285198090Srdivacky // allocation order. 286224145Sdim return RC->getRawAllocationOrder(MF); 287198090Srdivacky 288218893Sdim if (!TFI->hasFP(MF)) { 289198090Srdivacky if (!STI.isR9Reserved()) 290226633Sdim return makeArrayRef(GPROdd1); 291198090Srdivacky else 292226633Sdim return makeArrayRef(GPROdd4); 293198090Srdivacky } else if (FramePtr == ARM::R7) { 294198090Srdivacky if (!STI.isR9Reserved()) 295226633Sdim return makeArrayRef(GPROdd2); 296198090Srdivacky else 297226633Sdim return makeArrayRef(GPROdd5); 298198090Srdivacky } else { // FramePtr == ARM::R11 299198090Srdivacky if (!STI.isR9Reserved()) 300226633Sdim return makeArrayRef(GPROdd3); 301198090Srdivacky else 302226633Sdim return makeArrayRef(GPROdd6); 303198090Srdivacky } 304198090Srdivacky } 305224145Sdim return RC->getRawAllocationOrder(MF); 306198090Srdivacky} 307198090Srdivacky 308198090Srdivacky/// ResolveRegAllocHint - Resolves the specified register allocation hint 309198090Srdivacky/// to a physical register. Returns the physical register if it is successful. 310198090Srdivackyunsigned 311198090SrdivackyARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 312198090Srdivacky const MachineFunction &MF) const { 313198090Srdivacky if (Reg == 0 || !isPhysicalRegister(Reg)) 314198090Srdivacky return 0; 315198090Srdivacky if (Type == 0) 316198090Srdivacky return Reg; 317198090Srdivacky else if (Type == (unsigned)ARMRI::RegPairOdd) 318198090Srdivacky // Odd register. 319198090Srdivacky return getRegisterPairOdd(Reg, MF); 320198090Srdivacky else if (Type == (unsigned)ARMRI::RegPairEven) 321198090Srdivacky // Even register. 322198090Srdivacky return getRegisterPairEven(Reg, MF); 323198090Srdivacky return 0; 324198090Srdivacky} 325198090Srdivacky 326198090Srdivackyvoid 327198090SrdivackyARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 328198090Srdivacky MachineFunction &MF) const { 329198090Srdivacky MachineRegisterInfo *MRI = &MF.getRegInfo(); 330198090Srdivacky std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 331198090Srdivacky if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 332198090Srdivacky Hint.first == (unsigned)ARMRI::RegPairEven) && 333218893Sdim TargetRegisterInfo::isVirtualRegister(Hint.second)) { 334198090Srdivacky // If 'Reg' is one of the even / odd register pair and it's now changed 335198090Srdivacky // (e.g. coalesced) into a different register. The other register of the 336198090Srdivacky // pair allocation hint must be updated to reflect the relationship 337198090Srdivacky // change. 338198090Srdivacky unsigned OtherReg = Hint.second; 339198090Srdivacky Hint = MRI->getRegAllocationHint(OtherReg); 340198090Srdivacky if (Hint.second == Reg) 341198090Srdivacky // Make sure the pair has not already divorced. 342198090Srdivacky MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 343198090Srdivacky } 344198090Srdivacky} 345198090Srdivacky 346221345Sdimbool 347221345SdimARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 348221345Sdim // CortexA9 has a Write-after-write hazard for NEON registers. 349243830Sdim if (!STI.isLikeA9()) 350221345Sdim return false; 351221345Sdim 352221345Sdim switch (RC->getID()) { 353221345Sdim case ARM::DPRRegClassID: 354221345Sdim case ARM::DPR_8RegClassID: 355221345Sdim case ARM::DPR_VFP2RegClassID: 356221345Sdim case ARM::QPRRegClassID: 357221345Sdim case ARM::QPR_8RegClassID: 358221345Sdim case ARM::QPR_VFP2RegClassID: 359221345Sdim case ARM::SPRRegClassID: 360221345Sdim case ARM::SPR_8RegClassID: 361221345Sdim // Avoid reusing S, D, and Q registers. 362221345Sdim // Don't increase register pressure for QQ and QQQQ. 363221345Sdim return true; 364221345Sdim default: 365221345Sdim return false; 366221345Sdim } 367221345Sdim} 368221345Sdim 369212904Sdimbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 370212904Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 371212904Sdim const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 372234353Sdim const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 373212904Sdim 374212904Sdim if (!EnableBasePointer) 375212904Sdim return false; 376212904Sdim 377234353Sdim // When outgoing call frames are so large that we adjust the stack pointer 378234353Sdim // around the call, we can no longer use the stack pointer to reach the 379234353Sdim // emergency spill slot. 380234353Sdim if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 381212904Sdim return true; 382212904Sdim 383212904Sdim // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 384212904Sdim // negative range for ldr/str (255), and thumb1 is positive offsets only. 385212904Sdim // It's going to be better to use the SP or Base Pointer instead. When there 386212904Sdim // are variable sized objects, we can't reference off of the SP, so we 387212904Sdim // reserve a Base Pointer. 388212904Sdim if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 389212904Sdim // Conservatively estimate whether the negative offset from the frame 390212904Sdim // pointer will be sufficient to reach. If a function has a smallish 391212904Sdim // frame, it's less likely to have lots of spills and callee saved 392212904Sdim // space, so it's all more likely to be within range of the frame pointer. 393212904Sdim // If it's wrong, the scavenger will still enable access to work, it just 394212904Sdim // won't be optimal. 395212904Sdim if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 396212904Sdim return false; 397212904Sdim return true; 398212904Sdim } 399212904Sdim 400212904Sdim return false; 401212904Sdim} 402212904Sdim 403202878Srdivackybool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 404234353Sdim const MachineRegisterInfo *MRI = &MF.getRegInfo(); 405202878Srdivacky const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 406212904Sdim // We can't realign the stack if: 407212904Sdim // 1. Dynamic stack realignment is explicitly disabled, 408212904Sdim // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 409212904Sdim // 3. There are VLAs in the function and the base pointer is disabled. 410234353Sdim if (!MF.getTarget().Options.RealignStack) 411234353Sdim return false; 412234353Sdim if (AFI->isThumb1OnlyFunction()) 413234353Sdim return false; 414234353Sdim // Stack realignment requires a frame pointer. If we already started 415234353Sdim // register allocation with frame pointer elimination, it is too late now. 416234353Sdim if (!MRI->canReserveReg(FramePtr)) 417234353Sdim return false; 418234353Sdim // We may also need a base pointer if there are dynamic allocas or stack 419234353Sdim // pointer adjustments around calls. 420234353Sdim if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 421234353Sdim return true; 422234353Sdim if (!EnableBasePointer) 423234353Sdim return false; 424234353Sdim // A base pointer is required and allowed. Check that it isn't too late to 425234353Sdim // reserve it. 426234353Sdim return MRI->canReserveReg(BasePtr); 427202878Srdivacky} 428202878Srdivacky 429198892Srdivackybool ARMBaseRegisterInfo:: 430198892SrdivackyneedsStackRealignment(const MachineFunction &MF) const { 431198892Srdivacky const MachineFrameInfo *MFI = MF.getFrameInfo(); 432212904Sdim const Function *F = MF.getFunction(); 433218893Sdim unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 434243830Sdim bool requiresRealignment = 435243830Sdim ((MFI->getMaxAlignment() > StackAlign) || 436243830Sdim F->getFnAttributes().hasAttribute(Attributes::StackAlignment)); 437212904Sdim 438212904Sdim return requiresRealignment && canRealignStack(MF); 439198892Srdivacky} 440198892Srdivacky 441202375Srdivackybool ARMBaseRegisterInfo:: 442202375SrdivackycannotEliminateFrame(const MachineFunction &MF) const { 443198090Srdivacky const MachineFrameInfo *MFI = MF.getFrameInfo(); 444234353Sdim if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 445198090Srdivacky return true; 446199481Srdivacky return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 447199481Srdivacky || needsStackRealignment(MF); 448198090Srdivacky} 449198090Srdivacky 450212904Sdimunsigned 451199481SrdivackyARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 452218893Sdim const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 453218893Sdim 454218893Sdim if (TFI->hasFP(MF)) 455198090Srdivacky return FramePtr; 456198090Srdivacky return ARM::SP; 457198090Srdivacky} 458198090Srdivacky 459198090Srdivackyunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 460198090Srdivacky llvm_unreachable("What is the exception register"); 461198090Srdivacky} 462198090Srdivacky 463198090Srdivackyunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 464198090Srdivacky llvm_unreachable("What is the exception handler register"); 465198090Srdivacky} 466198090Srdivacky 467198090Srdivackyunsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 468202375Srdivacky const MachineFunction &MF) const { 469243830Sdim const MachineRegisterInfo &MRI = MF.getRegInfo(); 470198090Srdivacky switch (Reg) { 471198090Srdivacky default: break; 472198090Srdivacky // Return 0 if either register of the pair is a special register. 473198090Srdivacky // So no R12, etc. 474226633Sdim case ARM::R1: return ARM::R0; 475226633Sdim case ARM::R3: return ARM::R2; 476226633Sdim case ARM::R5: return ARM::R4; 477198090Srdivacky case ARM::R7: 478243830Sdim return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6)) 479212904Sdim ? 0 : ARM::R6; 480243830Sdim case ARM::R9: return MRI.isReserved(ARM::R9) ? 0 :ARM::R8; 481243830Sdim case ARM::R11: return MRI.isReserved(ARM::R11) ? 0 : ARM::R10; 482198090Srdivacky 483226633Sdim case ARM::S1: return ARM::S0; 484226633Sdim case ARM::S3: return ARM::S2; 485226633Sdim case ARM::S5: return ARM::S4; 486226633Sdim case ARM::S7: return ARM::S6; 487226633Sdim case ARM::S9: return ARM::S8; 488226633Sdim case ARM::S11: return ARM::S10; 489226633Sdim case ARM::S13: return ARM::S12; 490226633Sdim case ARM::S15: return ARM::S14; 491226633Sdim case ARM::S17: return ARM::S16; 492226633Sdim case ARM::S19: return ARM::S18; 493226633Sdim case ARM::S21: return ARM::S20; 494226633Sdim case ARM::S23: return ARM::S22; 495226633Sdim case ARM::S25: return ARM::S24; 496226633Sdim case ARM::S27: return ARM::S26; 497226633Sdim case ARM::S29: return ARM::S28; 498226633Sdim case ARM::S31: return ARM::S30; 499198090Srdivacky 500226633Sdim case ARM::D1: return ARM::D0; 501226633Sdim case ARM::D3: return ARM::D2; 502226633Sdim case ARM::D5: return ARM::D4; 503226633Sdim case ARM::D7: return ARM::D6; 504226633Sdim case ARM::D9: return ARM::D8; 505226633Sdim case ARM::D11: return ARM::D10; 506226633Sdim case ARM::D13: return ARM::D12; 507226633Sdim case ARM::D15: return ARM::D14; 508226633Sdim case ARM::D17: return ARM::D16; 509226633Sdim case ARM::D19: return ARM::D18; 510226633Sdim case ARM::D21: return ARM::D20; 511226633Sdim case ARM::D23: return ARM::D22; 512226633Sdim case ARM::D25: return ARM::D24; 513226633Sdim case ARM::D27: return ARM::D26; 514226633Sdim case ARM::D29: return ARM::D28; 515226633Sdim case ARM::D31: return ARM::D30; 516198090Srdivacky } 517198090Srdivacky 518198090Srdivacky return 0; 519198090Srdivacky} 520198090Srdivacky 521198090Srdivackyunsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 522198090Srdivacky const MachineFunction &MF) const { 523243830Sdim const MachineRegisterInfo &MRI = MF.getRegInfo(); 524198090Srdivacky switch (Reg) { 525198090Srdivacky default: break; 526198090Srdivacky // Return 0 if either register of the pair is a special register. 527198090Srdivacky // So no R12, etc. 528226633Sdim case ARM::R0: return ARM::R1; 529226633Sdim case ARM::R2: return ARM::R3; 530226633Sdim case ARM::R4: return ARM::R5; 531198090Srdivacky case ARM::R6: 532243830Sdim return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6)) 533212904Sdim ? 0 : ARM::R7; 534243830Sdim case ARM::R8: return MRI.isReserved(ARM::R9) ? 0 :ARM::R9; 535243830Sdim case ARM::R10: return MRI.isReserved(ARM::R11) ? 0 : ARM::R11; 536198090Srdivacky 537226633Sdim case ARM::S0: return ARM::S1; 538226633Sdim case ARM::S2: return ARM::S3; 539226633Sdim case ARM::S4: return ARM::S5; 540226633Sdim case ARM::S6: return ARM::S7; 541226633Sdim case ARM::S8: return ARM::S9; 542226633Sdim case ARM::S10: return ARM::S11; 543226633Sdim case ARM::S12: return ARM::S13; 544226633Sdim case ARM::S14: return ARM::S15; 545226633Sdim case ARM::S16: return ARM::S17; 546226633Sdim case ARM::S18: return ARM::S19; 547226633Sdim case ARM::S20: return ARM::S21; 548226633Sdim case ARM::S22: return ARM::S23; 549226633Sdim case ARM::S24: return ARM::S25; 550226633Sdim case ARM::S26: return ARM::S27; 551226633Sdim case ARM::S28: return ARM::S29; 552226633Sdim case ARM::S30: return ARM::S31; 553198090Srdivacky 554226633Sdim case ARM::D0: return ARM::D1; 555226633Sdim case ARM::D2: return ARM::D3; 556226633Sdim case ARM::D4: return ARM::D5; 557226633Sdim case ARM::D6: return ARM::D7; 558226633Sdim case ARM::D8: return ARM::D9; 559226633Sdim case ARM::D10: return ARM::D11; 560226633Sdim case ARM::D12: return ARM::D13; 561226633Sdim case ARM::D14: return ARM::D15; 562226633Sdim case ARM::D16: return ARM::D17; 563226633Sdim case ARM::D18: return ARM::D19; 564226633Sdim case ARM::D20: return ARM::D21; 565226633Sdim case ARM::D22: return ARM::D23; 566226633Sdim case ARM::D24: return ARM::D25; 567226633Sdim case ARM::D26: return ARM::D27; 568226633Sdim case ARM::D28: return ARM::D29; 569226633Sdim case ARM::D30: return ARM::D31; 570198090Srdivacky } 571198090Srdivacky 572198090Srdivacky return 0; 573198090Srdivacky} 574198090Srdivacky 575198090Srdivacky/// emitLoadConstPool - Emits a load from constpool to materialize the 576198090Srdivacky/// specified immediate. 577198090Srdivackyvoid ARMBaseRegisterInfo:: 578198090SrdivackyemitLoadConstPool(MachineBasicBlock &MBB, 579198090Srdivacky MachineBasicBlock::iterator &MBBI, 580198090Srdivacky DebugLoc dl, 581198090Srdivacky unsigned DestReg, unsigned SubIdx, int Val, 582198090Srdivacky ARMCC::CondCodes Pred, 583221345Sdim unsigned PredReg, unsigned MIFlags) const { 584198090Srdivacky MachineFunction &MF = *MBB.getParent(); 585198090Srdivacky MachineConstantPool *ConstantPool = MF.getConstantPool(); 586207618Srdivacky const Constant *C = 587198090Srdivacky ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 588198090Srdivacky unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 589198090Srdivacky 590198090Srdivacky BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 591198090Srdivacky .addReg(DestReg, getDefRegState(true), SubIdx) 592198090Srdivacky .addConstantPoolIndex(Idx) 593221345Sdim .addImm(0).addImm(Pred).addReg(PredReg) 594221345Sdim .setMIFlags(MIFlags); 595198090Srdivacky} 596198090Srdivacky 597198090Srdivackybool ARMBaseRegisterInfo:: 598198090SrdivackyrequiresRegisterScavenging(const MachineFunction &MF) const { 599198090Srdivacky return true; 600198090Srdivacky} 601198090Srdivacky 602198396Srdivackybool ARMBaseRegisterInfo:: 603239462SdimtrackLivenessAfterRegAlloc(const MachineFunction &MF) const { 604239462Sdim return true; 605239462Sdim} 606239462Sdim 607239462Sdimbool ARMBaseRegisterInfo:: 608198396SrdivackyrequiresFrameIndexScavenging(const MachineFunction &MF) const { 609198892Srdivacky return true; 610198396Srdivacky} 611198396Srdivacky 612212904Sdimbool ARMBaseRegisterInfo:: 613212904SdimrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 614212904Sdim return EnableLocalStackAlloc; 615212904Sdim} 616212904Sdim 617198090Srdivackystatic void 618198090SrdivackyemitSPUpdate(bool isARM, 619198090Srdivacky MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 620198090Srdivacky DebugLoc dl, const ARMBaseInstrInfo &TII, 621198090Srdivacky int NumBytes, 622198090Srdivacky ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 623198090Srdivacky if (isARM) 624198090Srdivacky emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 625198090Srdivacky Pred, PredReg, TII); 626198090Srdivacky else 627198090Srdivacky emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 628198090Srdivacky Pred, PredReg, TII); 629198090Srdivacky} 630198090Srdivacky 631198090Srdivacky 632198090Srdivackyvoid ARMBaseRegisterInfo:: 633198090SrdivackyeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 634198090Srdivacky MachineBasicBlock::iterator I) const { 635218893Sdim const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 636218893Sdim if (!TFI->hasReservedCallFrame(MF)) { 637198090Srdivacky // If we have alloca, convert as follows: 638198090Srdivacky // ADJCALLSTACKDOWN -> sub, sp, sp, amount 639198090Srdivacky // ADJCALLSTACKUP -> add, sp, sp, amount 640198090Srdivacky MachineInstr *Old = I; 641198090Srdivacky DebugLoc dl = Old->getDebugLoc(); 642198090Srdivacky unsigned Amount = Old->getOperand(0).getImm(); 643198090Srdivacky if (Amount != 0) { 644198090Srdivacky // We need to keep the stack aligned properly. To do this, we round the 645198090Srdivacky // amount of space needed for the outgoing arguments up to the next 646198090Srdivacky // alignment boundary. 647218893Sdim unsigned Align = TFI->getStackAlignment(); 648198090Srdivacky Amount = (Amount+Align-1)/Align*Align; 649198090Srdivacky 650198090Srdivacky ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 651198090Srdivacky assert(!AFI->isThumb1OnlyFunction() && 652204642Srdivacky "This eliminateCallFramePseudoInstr does not support Thumb1!"); 653198090Srdivacky bool isARM = !AFI->isThumbFunction(); 654198090Srdivacky 655198090Srdivacky // Replace the pseudo instruction with a new instruction... 656198090Srdivacky unsigned Opc = Old->getOpcode(); 657204642Srdivacky int PIdx = Old->findFirstPredOperandIdx(); 658204642Srdivacky ARMCC::CondCodes Pred = (PIdx == -1) 659204642Srdivacky ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 660198090Srdivacky if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 661198090Srdivacky // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 662198090Srdivacky unsigned PredReg = Old->getOperand(2).getReg(); 663198090Srdivacky emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 664198090Srdivacky } else { 665198090Srdivacky // Note: PredReg is operand 3 for ADJCALLSTACKUP. 666198090Srdivacky unsigned PredReg = Old->getOperand(3).getReg(); 667198090Srdivacky assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 668198090Srdivacky emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 669198090Srdivacky } 670198090Srdivacky } 671198090Srdivacky } 672198090Srdivacky MBB.erase(I); 673198090Srdivacky} 674198090Srdivacky 675212904Sdimint64_t ARMBaseRegisterInfo:: 676212904SdimgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 677224145Sdim const MCInstrDesc &Desc = MI->getDesc(); 678212904Sdim unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 679234353Sdim int64_t InstrOffs = 0; 680212904Sdim int Scale = 1; 681212904Sdim unsigned ImmIdx = 0; 682212904Sdim switch (AddrMode) { 683212904Sdim case ARMII::AddrModeT2_i8: 684212904Sdim case ARMII::AddrModeT2_i12: 685218893Sdim case ARMII::AddrMode_i12: 686212904Sdim InstrOffs = MI->getOperand(Idx+1).getImm(); 687212904Sdim Scale = 1; 688212904Sdim break; 689212904Sdim case ARMII::AddrMode5: { 690212904Sdim // VFP address mode. 691212904Sdim const MachineOperand &OffOp = MI->getOperand(Idx+1); 692212904Sdim InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 693212904Sdim if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 694212904Sdim InstrOffs = -InstrOffs; 695212904Sdim Scale = 4; 696212904Sdim break; 697212904Sdim } 698212904Sdim case ARMII::AddrMode2: { 699212904Sdim ImmIdx = Idx+2; 700212904Sdim InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 701212904Sdim if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 702212904Sdim InstrOffs = -InstrOffs; 703212904Sdim break; 704212904Sdim } 705212904Sdim case ARMII::AddrMode3: { 706212904Sdim ImmIdx = Idx+2; 707212904Sdim InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 708212904Sdim if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 709212904Sdim InstrOffs = -InstrOffs; 710212904Sdim break; 711212904Sdim } 712212904Sdim case ARMII::AddrModeT1_s: { 713212904Sdim ImmIdx = Idx+1; 714212904Sdim InstrOffs = MI->getOperand(ImmIdx).getImm(); 715212904Sdim Scale = 4; 716212904Sdim break; 717212904Sdim } 718212904Sdim default: 719212904Sdim llvm_unreachable("Unsupported addressing mode!"); 720212904Sdim } 721212904Sdim 722212904Sdim return InstrOffs * Scale; 723212904Sdim} 724212904Sdim 725212904Sdim/// needsFrameBaseReg - Returns true if the instruction's frame index 726212904Sdim/// reference would be better served by a base register other than FP 727212904Sdim/// or SP. Used by LocalStackFrameAllocation to determine which frame index 728212904Sdim/// references it should create new base registers for. 729212904Sdimbool ARMBaseRegisterInfo:: 730212904SdimneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 731212904Sdim for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 732212904Sdim assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 733212904Sdim } 734212904Sdim 735212904Sdim // It's the load/store FI references that cause issues, as it can be difficult 736212904Sdim // to materialize the offset if it won't fit in the literal field. Estimate 737212904Sdim // based on the size of the local frame and some conservative assumptions 738212904Sdim // about the rest of the stack frame (note, this is pre-regalloc, so 739212904Sdim // we don't know everything for certain yet) whether this offset is likely 740212904Sdim // to be out of range of the immediate. Return true if so. 741212904Sdim 742212904Sdim // We only generate virtual base registers for loads and stores, so 743212904Sdim // return false for everything else. 744212904Sdim unsigned Opc = MI->getOpcode(); 745212904Sdim switch (Opc) { 746218893Sdim case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 747218893Sdim case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 748212904Sdim case ARM::t2LDRi12: case ARM::t2LDRi8: 749212904Sdim case ARM::t2STRi12: case ARM::t2STRi8: 750212904Sdim case ARM::VLDRS: case ARM::VLDRD: 751212904Sdim case ARM::VSTRS: case ARM::VSTRD: 752212904Sdim case ARM::tSTRspi: case ARM::tLDRspi: 753212904Sdim if (ForceAllBaseRegAlloc) 754212904Sdim return true; 755212904Sdim break; 756212904Sdim default: 757212904Sdim return false; 758212904Sdim } 759212904Sdim 760212904Sdim // Without a virtual base register, if the function has variable sized 761212904Sdim // objects, all fixed-size local references will be via the frame pointer, 762212904Sdim // Approximate the offset and see if it's legal for the instruction. 763212904Sdim // Note that the incoming offset is based on the SP value at function entry, 764212904Sdim // so it'll be negative. 765212904Sdim MachineFunction &MF = *MI->getParent()->getParent(); 766218893Sdim const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 767212904Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 768212904Sdim ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 769212904Sdim 770212904Sdim // Estimate an offset from the frame pointer. 771212904Sdim // Conservatively assume all callee-saved registers get pushed. R4-R6 772212904Sdim // will be earlier than the FP, so we ignore those. 773212904Sdim // R7, LR 774212904Sdim int64_t FPOffset = Offset - 8; 775212904Sdim // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 776212904Sdim if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 777212904Sdim FPOffset -= 80; 778212904Sdim // Estimate an offset from the stack pointer. 779212904Sdim // The incoming offset is relating to the SP at the start of the function, 780212904Sdim // but when we access the local it'll be relative to the SP after local 781212904Sdim // allocation, so adjust our SP-relative offset by that allocation size. 782212904Sdim Offset = -Offset; 783212904Sdim Offset += MFI->getLocalFrameSize(); 784212904Sdim // Assume that we'll have at least some spill slots allocated. 785212904Sdim // FIXME: This is a total SWAG number. We should run some statistics 786212904Sdim // and pick a real one. 787212904Sdim Offset += 128; // 128 bytes of spill slots 788212904Sdim 789212904Sdim // If there is a frame pointer, try using it. 790212904Sdim // The FP is only available if there is no dynamic realignment. We 791212904Sdim // don't know for sure yet whether we'll need that, so we guess based 792212904Sdim // on whether there are any local variables that would trigger it. 793218893Sdim unsigned StackAlign = TFI->getStackAlignment(); 794218893Sdim if (TFI->hasFP(MF) && 795212904Sdim !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 796212904Sdim if (isFrameOffsetLegal(MI, FPOffset)) 797212904Sdim return false; 798212904Sdim } 799212904Sdim // If we can reference via the stack pointer, try that. 800212904Sdim // FIXME: This (and the code that resolves the references) can be improved 801212904Sdim // to only disallow SP relative references in the live range of 802212904Sdim // the VLA(s). In practice, it's unclear how much difference that 803212904Sdim // would make, but it may be worth doing. 804212904Sdim if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 805212904Sdim return false; 806212904Sdim 807212904Sdim // The offset likely isn't legal, we want to allocate a virtual base register. 808212904Sdim return true; 809212904Sdim} 810212904Sdim 811218893Sdim/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 812218893Sdim/// be a pointer to FrameIdx at the beginning of the basic block. 813212904Sdimvoid ARMBaseRegisterInfo:: 814218893SdimmaterializeFrameBaseRegister(MachineBasicBlock *MBB, 815218893Sdim unsigned BaseReg, int FrameIdx, 816218893Sdim int64_t Offset) const { 817218893Sdim ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 818212904Sdim unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 819212904Sdim (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 820212904Sdim 821218893Sdim MachineBasicBlock::iterator Ins = MBB->begin(); 822218893Sdim DebugLoc DL; // Defaults to "unknown" 823218893Sdim if (Ins != MBB->end()) 824218893Sdim DL = Ins->getDebugLoc(); 825218893Sdim 826224145Sdim const MCInstrDesc &MCID = TII.get(ADDriOpc); 827223017Sdim MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 828239462Sdim const MachineFunction &MF = *MBB->getParent(); 829239462Sdim MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 830223017Sdim 831226633Sdim MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 832226633Sdim .addFrameIndex(FrameIdx).addImm(Offset)); 833218893Sdim 834212904Sdim if (!AFI->isThumb1OnlyFunction()) 835226633Sdim AddDefaultCC(MIB); 836212904Sdim} 837212904Sdim 838212904Sdimvoid 839212904SdimARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 840212904Sdim unsigned BaseReg, int64_t Offset) const { 841212904Sdim MachineInstr &MI = *I; 842212904Sdim MachineBasicBlock &MBB = *MI.getParent(); 843212904Sdim MachineFunction &MF = *MBB.getParent(); 844212904Sdim ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 845212904Sdim int Off = Offset; // ARM doesn't need the general 64-bit offsets 846212904Sdim unsigned i = 0; 847212904Sdim 848212904Sdim assert(!AFI->isThumb1OnlyFunction() && 849212904Sdim "This resolveFrameIndex does not support Thumb1!"); 850212904Sdim 851212904Sdim while (!MI.getOperand(i).isFI()) { 852212904Sdim ++i; 853212904Sdim assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 854212904Sdim } 855212904Sdim bool Done = false; 856212904Sdim if (!AFI->isThumbFunction()) 857212904Sdim Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 858212904Sdim else { 859212904Sdim assert(AFI->isThumb2Function()); 860212904Sdim Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 861212904Sdim } 862212904Sdim assert (Done && "Unable to resolve frame index!"); 863226633Sdim (void)Done; 864212904Sdim} 865212904Sdim 866212904Sdimbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 867212904Sdim int64_t Offset) const { 868224145Sdim const MCInstrDesc &Desc = MI->getDesc(); 869212904Sdim unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 870212904Sdim unsigned i = 0; 871212904Sdim 872212904Sdim while (!MI->getOperand(i).isFI()) { 873212904Sdim ++i; 874212904Sdim assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 875212904Sdim } 876212904Sdim 877212904Sdim // AddrMode4 and AddrMode6 cannot handle any offset. 878212904Sdim if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 879212904Sdim return Offset == 0; 880212904Sdim 881212904Sdim unsigned NumBits = 0; 882212904Sdim unsigned Scale = 1; 883212904Sdim bool isSigned = true; 884212904Sdim switch (AddrMode) { 885212904Sdim case ARMII::AddrModeT2_i8: 886212904Sdim case ARMII::AddrModeT2_i12: 887212904Sdim // i8 supports only negative, and i12 supports only positive, so 888212904Sdim // based on Offset sign, consider the appropriate instruction 889212904Sdim Scale = 1; 890212904Sdim if (Offset < 0) { 891212904Sdim NumBits = 8; 892212904Sdim Offset = -Offset; 893212904Sdim } else { 894212904Sdim NumBits = 12; 895212904Sdim } 896212904Sdim break; 897212904Sdim case ARMII::AddrMode5: 898212904Sdim // VFP address mode. 899212904Sdim NumBits = 8; 900212904Sdim Scale = 4; 901212904Sdim break; 902218893Sdim case ARMII::AddrMode_i12: 903212904Sdim case ARMII::AddrMode2: 904212904Sdim NumBits = 12; 905212904Sdim break; 906212904Sdim case ARMII::AddrMode3: 907212904Sdim NumBits = 8; 908212904Sdim break; 909212904Sdim case ARMII::AddrModeT1_s: 910212904Sdim NumBits = 5; 911212904Sdim Scale = 4; 912212904Sdim isSigned = false; 913212904Sdim break; 914212904Sdim default: 915212904Sdim llvm_unreachable("Unsupported addressing mode!"); 916212904Sdim } 917212904Sdim 918212904Sdim Offset += getFrameIndexInstrOffset(MI, i); 919212904Sdim // Make sure the offset is encodable for instructions that scale the 920212904Sdim // immediate. 921212904Sdim if ((Offset & (Scale-1)) != 0) 922212904Sdim return false; 923212904Sdim 924212904Sdim if (isSigned && Offset < 0) 925212904Sdim Offset = -Offset; 926212904Sdim 927212904Sdim unsigned Mask = (1 << NumBits) - 1; 928212904Sdim if ((unsigned)Offset <= Mask * Scale) 929212904Sdim return true; 930212904Sdim 931212904Sdim return false; 932212904Sdim} 933212904Sdim 934212904Sdimvoid 935198090SrdivackyARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 936212904Sdim int SPAdj, RegScavenger *RS) const { 937198090Srdivacky unsigned i = 0; 938198090Srdivacky MachineInstr &MI = *II; 939198090Srdivacky MachineBasicBlock &MBB = *MI.getParent(); 940198090Srdivacky MachineFunction &MF = *MBB.getParent(); 941218893Sdim const ARMFrameLowering *TFI = 942218893Sdim static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 943198090Srdivacky ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 944198090Srdivacky assert(!AFI->isThumb1OnlyFunction() && 945198090Srdivacky "This eliminateFrameIndex does not support Thumb1!"); 946198090Srdivacky 947198090Srdivacky while (!MI.getOperand(i).isFI()) { 948198090Srdivacky ++i; 949198090Srdivacky assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 950198090Srdivacky } 951198090Srdivacky 952198090Srdivacky int FrameIndex = MI.getOperand(i).getIndex(); 953199989Srdivacky unsigned FrameReg; 954198090Srdivacky 955218893Sdim int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 956198090Srdivacky 957234353Sdim // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 958234353Sdim // call frame setup/destroy instructions have already been eliminated. That 959234353Sdim // means the stack pointer cannot be used to access the emergency spill slot 960234353Sdim // when !hasReservedCallFrame(). 961234353Sdim#ifndef NDEBUG 962234353Sdim if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){ 963234353Sdim assert(TFI->hasReservedCallFrame(MF) && 964234353Sdim "Cannot use SP to access the emergency spill slot in " 965234353Sdim "functions without a reserved call frame"); 966234353Sdim assert(!MF.getFrameInfo()->hasVarSizedObjects() && 967234353Sdim "Cannot use SP to access the emergency spill slot in " 968234353Sdim "functions with variable sized frame objects"); 969234353Sdim } 970234353Sdim#endif // NDEBUG 971234353Sdim 972207618Srdivacky // Special handling of dbg_value instructions. 973207618Srdivacky if (MI.isDebugValue()) { 974207618Srdivacky MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 975207618Srdivacky MI.getOperand(i+1).ChangeToImmediate(Offset); 976212904Sdim return; 977207618Srdivacky } 978207618Srdivacky 979198892Srdivacky // Modify MI as necessary to handle as much of 'Offset' as possible 980198090Srdivacky bool Done = false; 981198090Srdivacky if (!AFI->isThumbFunction()) 982198090Srdivacky Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 983198090Srdivacky else { 984198090Srdivacky assert(AFI->isThumb2Function()); 985198090Srdivacky Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 986198090Srdivacky } 987198090Srdivacky if (Done) 988212904Sdim return; 989198090Srdivacky 990198090Srdivacky // If we get here, the immediate doesn't fit into the instruction. We folded 991198090Srdivacky // as much as possible above, handle the rest, providing a register that is 992198090Srdivacky // SP+LargeImm. 993198090Srdivacky assert((Offset || 994199481Srdivacky (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 995199481Srdivacky (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 996198090Srdivacky "This code isn't needed if offset already handled!"); 997198090Srdivacky 998198396Srdivacky unsigned ScratchReg = 0; 999198090Srdivacky int PIdx = MI.findFirstPredOperandIdx(); 1000198090Srdivacky ARMCC::CondCodes Pred = (PIdx == -1) 1001198090Srdivacky ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1002198090Srdivacky unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1003198090Srdivacky if (Offset == 0) 1004199481Srdivacky // Must be addrmode4/6. 1005198090Srdivacky MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1006198090Srdivacky else { 1007239462Sdim ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 1008198090Srdivacky if (!AFI->isThumbFunction()) 1009198090Srdivacky emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1010198090Srdivacky Offset, Pred, PredReg, TII); 1011198090Srdivacky else { 1012198090Srdivacky assert(AFI->isThumb2Function()); 1013198090Srdivacky emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1014198090Srdivacky Offset, Pred, PredReg, TII); 1015198090Srdivacky } 1016218893Sdim // Update the original instruction to use the scratch register. 1017198090Srdivacky MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1018198090Srdivacky } 1019198090Srdivacky} 1020