ARM.td revision 249423 
1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget state.
21//
22
23def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
24                                  "Thumb mode">;
25
26//===----------------------------------------------------------------------===//
27// ARM Subtarget features.
28//
29
30def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
31                                   "Enable VFP2 instructions">;
32def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
33                                   "Enable VFP3 instructions",
34                                   [FeatureVFP2]>;
35def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
36                                   "Enable NEON instructions",
37                                   [FeatureVFP3]>;
38def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
39                                     "Enable Thumb2 instructions">;
40def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
41                                     "Does not support ARM mode execution">;
42def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
43                                     "Enable half-precision floating point">;
44def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
45                                     "Enable VFP4 instructions",
46                                     [FeatureVFP3, FeatureFP16]>;
47def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
48                                     "Restrict VFP3 to 16 double registers">;
49def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
50                                     "Enable divide instructions">;
51def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
52                                        "HasHardwareDivideInARM", "true",
53                                      "Enable divide instructions in ARM mode">;
54def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
55                                 "Enable Thumb2 extract and pack instructions">;
56def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
57                                   "Has data barrier (dmb / dsb) instructions">;
58def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
59                                         "FP compare + branch is slow">;
60def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
61                          "Floating point unit supports single precision only">;
62
63// Some processors have FP multiply-accumulate instructions that don't
64// play nicely with other VFP / NEON instructions, and it's generally better
65// to just not use them.
66def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
67                                         "Disable VFP / NEON MAC instructions">;
68
69// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
70def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
71                                       "HasVMLxForwarding", "true",
72                                       "Has multiplier accumulator forwarding">;
73
74// Some processors benefit from using NEON instructions for scalar
75// single-precision FP operations.
76def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
77                                        "true",
78                                        "Use NEON for single precision FP">;
79
80// Disable 32-bit to 16-bit narrowing for experimentation.
81def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
82                                             "Prefer 32-bit Thumb instrs">;
83
84/// Some instructions update CPSR partially, which can add false dependency for
85/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
86/// mapped to a separate physical register. Avoid partial CPSR update for these
87/// processors.
88def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
89                                               "AvoidCPSRPartialUpdate", "true",
90                                 "Avoid CPSR partial update for OOO execution">;
91
92def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
93                                            "AvoidMOVsShifterOperand", "true",
94                                "Avoid movs instructions with shifter operand">;
95
96// Some processors perform return stack prediction. CodeGen should avoid issue
97// "normal" call instructions to callees which do not return.
98def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
99                                     "Has return address stack">;
100
101/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
102def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
103                                 "Supports v7 DSP instructions in Thumb2">;
104
105// Multiprocessing extension.
106def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
107                                 "Supports Multiprocessing extension">;
108
109// M-series ISA?
110def FeatureMClass : SubtargetFeature<"mclass", "IsMClass", "true",
111                                     "Is microcontroller profile ('M' series)">;
112
113// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
114// See ARMInstrInfo.td for details.
115def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
116                                       "NaCl trap">;
117
118// ARM ISAs.
119def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
120                                   "Support ARM v4T instructions">;
121def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
122                                   "Support ARM v5T instructions",
123                                   [HasV4TOps]>;
124def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
125                             "Support ARM v5TE, v5TEj, and v5TExp instructions",
126                                   [HasV5TOps]>;
127def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
128                                   "Support ARM v6 instructions",
129                                   [HasV5TEOps]>;
130def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
131                                   "Support ARM v6t2 instructions",
132                                   [HasV6Ops, FeatureThumb2]>;
133def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
134                                   "Support ARM v7 instructions",
135                                   [HasV6T2Ops]>;
136
137//===----------------------------------------------------------------------===//
138// ARM Processors supported.
139//
140
141include "ARMSchedule.td"
142
143// ARM processor families.
144def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
145                                   "Cortex-A5 ARM processors",
146                                   [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
147                                    FeatureVMLxForwarding, FeatureT2XtPk]>;
148def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
149                                   "Cortex-A8 ARM processors",
150                                   [FeatureSlowFPBrcc, FeatureHasSlowFPVMLx,
151                                    FeatureVMLxForwarding, FeatureT2XtPk]>;
152def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
153                                   "Cortex-A9 ARM processors",
154                                   [FeatureVMLxForwarding,
155                                    FeatureT2XtPk, FeatureFP16,
156                                    FeatureAvoidPartialCPSR]>;
157def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
158                                   "Swift ARM processors",
159                                   [FeatureNEONForFP, FeatureT2XtPk,
160                                    FeatureVFP4, FeatureMP, FeatureHWDiv,
161                                    FeatureHWDivARM, FeatureAvoidPartialCPSR,
162                                    FeatureAvoidMOVsShOp,
163                                    FeatureHasSlowFPVMLx]>;
164
165// FIXME: It has not been determined if A15 has these features.
166def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
167                                   "Cortex-A15 ARM processors",
168                                   [FeatureT2XtPk, FeatureFP16,
169                                    FeatureAvoidPartialCPSR]>;
170def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
171                                   "Cortex-R5 ARM processors",
172                                   [FeatureSlowFPBrcc, FeatureHWDivARM,
173                                    FeatureHasSlowFPVMLx,
174                                    FeatureAvoidPartialCPSR,
175                                    FeatureT2XtPk]>;
176
177class ProcNoItin<string Name, list<SubtargetFeature> Features>
178 : Processor<Name, NoItineraries, Features>;
179
180// V4 Processors.
181def : ProcNoItin<"generic",         []>;
182def : ProcNoItin<"arm8",            []>;
183def : ProcNoItin<"arm810",          []>;
184def : ProcNoItin<"strongarm",       []>;
185def : ProcNoItin<"strongarm110",    []>;
186def : ProcNoItin<"strongarm1100",   []>;
187def : ProcNoItin<"strongarm1110",   []>;
188
189// V4T Processors.
190def : ProcNoItin<"arm7tdmi",        [HasV4TOps]>;
191def : ProcNoItin<"arm7tdmi-s",      [HasV4TOps]>;
192def : ProcNoItin<"arm710t",         [HasV4TOps]>;
193def : ProcNoItin<"arm720t",         [HasV4TOps]>;
194def : ProcNoItin<"arm9",            [HasV4TOps]>;
195def : ProcNoItin<"arm9tdmi",        [HasV4TOps]>;
196def : ProcNoItin<"arm920",          [HasV4TOps]>;
197def : ProcNoItin<"arm920t",         [HasV4TOps]>;
198def : ProcNoItin<"arm922t",         [HasV4TOps]>;
199def : ProcNoItin<"arm940t",         [HasV4TOps]>;
200def : ProcNoItin<"ep9312",          [HasV4TOps]>;
201
202// V5T Processors.
203def : ProcNoItin<"arm10tdmi",       [HasV5TOps]>;
204def : ProcNoItin<"arm1020t",        [HasV5TOps]>;
205
206// V5TE Processors.
207def : ProcNoItin<"arm9e",           [HasV5TEOps]>;
208def : ProcNoItin<"arm926ej-s",      [HasV5TEOps]>;
209def : ProcNoItin<"arm946e-s",       [HasV5TEOps]>;
210def : ProcNoItin<"arm966e-s",       [HasV5TEOps]>;
211def : ProcNoItin<"arm968e-s",       [HasV5TEOps]>;
212def : ProcNoItin<"arm10e",          [HasV5TEOps]>;
213def : ProcNoItin<"arm1020e",        [HasV5TEOps]>;
214def : ProcNoItin<"arm1022e",        [HasV5TEOps]>;
215def : ProcNoItin<"xscale",          [HasV5TEOps]>;
216def : ProcNoItin<"iwmmxt",          [HasV5TEOps]>;
217
218// V6 Processors.
219def : Processor<"arm1136j-s",       ARMV6Itineraries, [HasV6Ops]>;
220def : Processor<"arm1136jf-s",      ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
221                                                       FeatureHasSlowFPVMLx]>;
222def : Processor<"arm1176jz-s",      ARMV6Itineraries, [HasV6Ops]>;
223def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
224                                                       FeatureHasSlowFPVMLx]>;
225def : Processor<"mpcorenovfp",      ARMV6Itineraries, [HasV6Ops]>;
226def : Processor<"mpcore",           ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
227                                                       FeatureHasSlowFPVMLx]>;
228
229// V6M Processors.
230def : Processor<"cortex-m0",        ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
231                                                       FeatureDB, FeatureMClass]>;
232
233// V6T2 Processors.
234def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
235                                                       FeatureDSPThumb2]>;
236def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
237                                                       FeatureHasSlowFPVMLx,
238                                                       FeatureDSPThumb2]>;
239
240// V7a Processors.
241// FIXME: A5 has currently the same Schedule model as A8
242def : ProcessorModel<"cortex-a5",   CortexA8Model,
243                                    [ProcA5, HasV7Ops, FeatureNEON, FeatureDB,
244                                     FeatureVFP4, FeatureDSPThumb2,
245                                     FeatureHasRAS]>;
246def : ProcessorModel<"cortex-a8",   CortexA8Model,
247                                    [ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
248                                     FeatureDSPThumb2, FeatureHasRAS]>;
249def : ProcessorModel<"cortex-a9",   CortexA9Model,
250                                    [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
251                                     FeatureDSPThumb2, FeatureHasRAS]>;
252def : ProcessorModel<"cortex-a9-mp", CortexA9Model,
253                                    [ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
254                                     FeatureDSPThumb2, FeatureMP,
255                                     FeatureHasRAS]>;
256// FIXME: A15 has currently the same ProcessorModel as A9.
257def : ProcessorModel<"cortex-a15",   CortexA9Model,
258                                    [ProcA15, HasV7Ops, FeatureNEON, FeatureDB,
259                                     FeatureDSPThumb2, FeatureHasRAS]>;
260// FIXME: R5 has currently the same ProcessorModel as A8.
261def : ProcessorModel<"cortex-r5",   CortexA8Model,
262                                    [ProcR5, HasV7Ops, FeatureDB,
263                                     FeatureVFP3, FeatureDSPThumb2,
264                                     FeatureHasRAS]>;
265
266// V7M Processors.
267def : ProcNoItin<"cortex-m3",       [HasV7Ops,
268                                     FeatureThumb2, FeatureNoARM, FeatureDB,
269                                     FeatureHWDiv, FeatureMClass]>;
270
271// V7EM Processors.
272def : ProcNoItin<"cortex-m4",       [HasV7Ops,
273                                     FeatureThumb2, FeatureNoARM, FeatureDB,
274                                     FeatureHWDiv, FeatureDSPThumb2,
275                                     FeatureT2XtPk, FeatureVFP4,
276                                     FeatureVFPOnlySP, FeatureMClass]>;
277
278// Swift uArch Processors.
279def : ProcessorModel<"swift",       SwiftModel,
280                                    [ProcSwift, HasV7Ops, FeatureNEON,
281                                     FeatureDB, FeatureDSPThumb2,
282                                     FeatureHasRAS]>;
283
284//===----------------------------------------------------------------------===//
285// Register File Description
286//===----------------------------------------------------------------------===//
287
288include "ARMRegisterInfo.td"
289
290include "ARMCallingConv.td"
291
292//===----------------------------------------------------------------------===//
293// Instruction Descriptions
294//===----------------------------------------------------------------------===//
295
296include "ARMInstrInfo.td"
297
298def ARMInstrInfo : InstrInfo;
299
300
301//===----------------------------------------------------------------------===//
302// Assembly printer
303//===----------------------------------------------------------------------===//
304// ARM Uses the MC printer for asm output, so make sure the TableGen
305// AsmWriter bits get associated with the correct class.
306def ARMAsmWriter : AsmWriter {
307  string AsmWriterClassName  = "InstPrinter";
308  bit isMCAsmWriter = 1;
309}
310
311//===----------------------------------------------------------------------===//
312// Declare the target which we are implementing
313//===----------------------------------------------------------------------===//
314
315def ARM : Target {
316  // Pull in Instruction Info:
317  let InstructionSet = ARMInstrInfo;
318
319  let AssemblyWriters = [ARMAsmWriter];
320}
321