ARM.td revision 212904 
1//===- ARM.td - Describe the ARM Target Machine ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget features.
21//
22
23def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
24                                   "Enable VFP2 instructions">;
25def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
26                                   "Enable VFP3 instructions">;
27def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
28                                   "Enable NEON instructions">;
29def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
30                                     "Enable Thumb2 instructions">;
31def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
32                                     "Does not support ARM mode execution">;
33def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
34                                     "Enable half-precision floating point">;
35def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
36                                     "Enable divide instructions">;
37def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
38                                 "Enable Thumb2 extract and pack instructions">;
39def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
40                                   "Has data barrier (dmb / dsb) instructions">;
41def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
42                                         "FP compare + branch is slow">;
43def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
44                          "Floating point unit supports single precision only">;
45
46// Some processors have multiply-accumulate instructions that don't
47// play nicely with other VFP instructions, and it's generally better
48// to just not use them.
49// FIXME: Currently, this is only flagged for Cortex-A8. It may be true for
50// others as well. We should do more benchmarking and confirm one way or
51// the other.
52def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true",
53                                          "Disable VFP MAC instructions">;
54// Some processors benefit from using NEON instructions for scalar
55// single-precision FP operations.
56def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
57                                        "true",
58                                        "Use NEON for single precision FP">;
59
60// Disable 32-bit to 16-bit narrowing for experimentation.
61def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
62                                             "Prefer 32-bit Thumb instrs">;
63
64
65// ARM architectures.
66def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
67                                   "ARM v4T">;
68def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
69                                   "ARM v5T">;
70def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
71                                   "ARM v5TE, v5TEj, v5TExp">;
72def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
73                                   "ARM v6">;
74def ArchV6M     : SubtargetFeature<"v6m", "ARMArchVersion", "V6M",
75                                   "ARM v6m",
76                                   [FeatureNoARM, FeatureDB]>;
77def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
78                                   "ARM v6t2",
79                                   [FeatureThumb2]>;
80def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
81                                   "ARM v7A",
82                                   [FeatureThumb2, FeatureNEON, FeatureDB]>;
83def ArchV7M     : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
84                                   "ARM v7M",
85                                   [FeatureThumb2, FeatureNoARM, FeatureDB,
86                                    FeatureHWDiv]>;
87
88//===----------------------------------------------------------------------===//
89// ARM Processors supported.
90//
91
92include "ARMSchedule.td"
93
94class ProcNoItin<string Name, list<SubtargetFeature> Features>
95 : Processor<Name, GenericItineraries, Features>;
96
97// V4 Processors.
98def : ProcNoItin<"generic",         []>;
99def : ProcNoItin<"arm8",            []>;
100def : ProcNoItin<"arm810",          []>;
101def : ProcNoItin<"strongarm",       []>;
102def : ProcNoItin<"strongarm110",    []>;
103def : ProcNoItin<"strongarm1100",   []>;
104def : ProcNoItin<"strongarm1110",   []>;
105
106// V4T Processors.
107def : ProcNoItin<"arm7tdmi",        [ArchV4T]>;
108def : ProcNoItin<"arm7tdmi-s",      [ArchV4T]>;
109def : ProcNoItin<"arm710t",         [ArchV4T]>;
110def : ProcNoItin<"arm720t",         [ArchV4T]>;
111def : ProcNoItin<"arm9",            [ArchV4T]>;
112def : ProcNoItin<"arm9tdmi",        [ArchV4T]>;
113def : ProcNoItin<"arm920",          [ArchV4T]>;
114def : ProcNoItin<"arm920t",         [ArchV4T]>;
115def : ProcNoItin<"arm922t",         [ArchV4T]>;
116def : ProcNoItin<"arm940t",         [ArchV4T]>;
117def : ProcNoItin<"ep9312",          [ArchV4T]>;
118
119// V5T Processors.
120def : ProcNoItin<"arm10tdmi",       [ArchV5T]>;
121def : ProcNoItin<"arm1020t",        [ArchV5T]>;
122
123// V5TE Processors.
124def : ProcNoItin<"arm9e",           [ArchV5TE]>;
125def : ProcNoItin<"arm926ej-s",      [ArchV5TE]>;
126def : ProcNoItin<"arm946e-s",       [ArchV5TE]>;
127def : ProcNoItin<"arm966e-s",       [ArchV5TE]>;
128def : ProcNoItin<"arm968e-s",       [ArchV5TE]>;
129def : ProcNoItin<"arm10e",          [ArchV5TE]>;
130def : ProcNoItin<"arm1020e",        [ArchV5TE]>;
131def : ProcNoItin<"arm1022e",        [ArchV5TE]>;
132def : ProcNoItin<"xscale",          [ArchV5TE]>;
133def : ProcNoItin<"iwmmxt",          [ArchV5TE]>;
134
135// V6 Processors.
136def : Processor<"arm1136j-s",       ARMV6Itineraries, [ArchV6]>;
137def : Processor<"arm1136jf-s",      ARMV6Itineraries, [ArchV6, FeatureVFP2,
138                                                       FeatureHasSlowVMLx]>;
139def : Processor<"arm1176jz-s",      ARMV6Itineraries, [ArchV6]>;
140def : Processor<"arm1176jzf-s",     ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
141def : Processor<"mpcorenovfp",      ARMV6Itineraries, [ArchV6]>;
142def : Processor<"mpcore",           ARMV6Itineraries, [ArchV6, FeatureVFP2]>;
143
144// V6M Processors.
145def : Processor<"cortex-m0",        ARMV6Itineraries, [ArchV6M]>;
146
147// V6T2 Processors.
148def : Processor<"arm1156t2-s",      ARMV6Itineraries, [ArchV6T2]>;
149def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [ArchV6T2, FeatureVFP2]>;
150
151// V7 Processors.
152def : Processor<"cortex-a8",        CortexA8Itineraries,
153                [ArchV7A, FeatureHasSlowVMLx,
154                 FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2XtPk]>;
155def : Processor<"cortex-a9",        CortexA9Itineraries,
156                [ArchV7A, FeatureT2XtPk]>;
157
158// V7M Processors.
159def : ProcNoItin<"cortex-m3",       [ArchV7M]>;
160def : ProcNoItin<"cortex-m4",       [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
161
162//===----------------------------------------------------------------------===//
163// Register File Description
164//===----------------------------------------------------------------------===//
165
166include "ARMRegisterInfo.td"
167
168include "ARMCallingConv.td"
169
170//===----------------------------------------------------------------------===//
171// Instruction Descriptions
172//===----------------------------------------------------------------------===//
173
174include "ARMInstrInfo.td"
175
176def ARMInstrInfo : InstrInfo;
177
178//===----------------------------------------------------------------------===//
179// Declare the target which we are implementing
180//===----------------------------------------------------------------------===//
181
182def ARM : Target {
183  // Pull in Instruction Info:
184  let InstructionSet = ARMInstrInfo;
185}
186