ARM.td revision 206083
1//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Target-independent interfaces which we are implementing 15//===----------------------------------------------------------------------===// 16 17include "llvm/Target/Target.td" 18 19//===----------------------------------------------------------------------===// 20// ARM Subtarget features. 21// 22 23def ArchV4T : SubtargetFeature<"v4t", "ARMArchVersion", "V4T", 24 "ARM v4T">; 25def ArchV5T : SubtargetFeature<"v5t", "ARMArchVersion", "V5T", 26 "ARM v5T">; 27def ArchV5TE : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE", 28 "ARM v5TE, v5TEj, v5TExp">; 29def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6", 30 "ARM v6">; 31def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2", 32 "ARM v6t2">; 33def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A", 34 "ARM v7A">; 35def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2", 36 "Enable VFP2 instructions">; 37def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3", 38 "Enable VFP3 instructions">; 39def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", 40 "Enable NEON instructions">; 41def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", 42 "Enable Thumb2 instructions">; 43def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", 44 "Enable half-precision floating point">; 45 46// Some processors have multiply-accumulate instructions that don't 47// play nicely with other VFP instructions, and it's generally better 48// to just not use them. 49// FIXME: Currently, this is only flagged for Cortex-A8. It may be true for 50// others as well. We should do more benchmarking and confirm one way or 51// the other. 52def FeatureHasSlowVMLx : SubtargetFeature<"vmlx", "SlowVMLx", "true", 53 "Disable VFP MAC instructions">; 54// Some processors benefit from using NEON instructions for scalar 55// single-precision FP operations. 56def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", 57 "true", 58 "Use NEON for single precision FP">; 59 60 61//===----------------------------------------------------------------------===// 62// ARM Processors supported. 63// 64 65include "ARMSchedule.td" 66 67class ProcNoItin<string Name, list<SubtargetFeature> Features> 68 : Processor<Name, GenericItineraries, Features>; 69 70// V4 Processors. 71def : ProcNoItin<"generic", []>; 72def : ProcNoItin<"arm8", []>; 73def : ProcNoItin<"arm810", []>; 74def : ProcNoItin<"strongarm", []>; 75def : ProcNoItin<"strongarm110", []>; 76def : ProcNoItin<"strongarm1100", []>; 77def : ProcNoItin<"strongarm1110", []>; 78 79// V4T Processors. 80def : ProcNoItin<"arm7tdmi", [ArchV4T]>; 81def : ProcNoItin<"arm7tdmi-s", [ArchV4T]>; 82def : ProcNoItin<"arm710t", [ArchV4T]>; 83def : ProcNoItin<"arm720t", [ArchV4T]>; 84def : ProcNoItin<"arm9", [ArchV4T]>; 85def : ProcNoItin<"arm9tdmi", [ArchV4T]>; 86def : ProcNoItin<"arm920", [ArchV4T]>; 87def : ProcNoItin<"arm920t", [ArchV4T]>; 88def : ProcNoItin<"arm922t", [ArchV4T]>; 89def : ProcNoItin<"arm940t", [ArchV4T]>; 90def : ProcNoItin<"ep9312", [ArchV4T]>; 91 92// V5T Processors. 93def : ProcNoItin<"arm10tdmi", [ArchV5T]>; 94def : ProcNoItin<"arm1020t", [ArchV5T]>; 95 96// V5TE Processors. 97def : ProcNoItin<"arm9e", [ArchV5TE]>; 98def : ProcNoItin<"arm926ej-s", [ArchV5TE]>; 99def : ProcNoItin<"arm946e-s", [ArchV5TE]>; 100def : ProcNoItin<"arm966e-s", [ArchV5TE]>; 101def : ProcNoItin<"arm968e-s", [ArchV5TE]>; 102def : ProcNoItin<"arm10e", [ArchV5TE]>; 103def : ProcNoItin<"arm1020e", [ArchV5TE]>; 104def : ProcNoItin<"arm1022e", [ArchV5TE]>; 105def : ProcNoItin<"xscale", [ArchV5TE]>; 106def : ProcNoItin<"iwmmxt", [ArchV5TE]>; 107 108// V6 Processors. 109def : Processor<"arm1136j-s", ARMV6Itineraries, [ArchV6]>; 110def : Processor<"arm1136jf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2, 111 FeatureHasSlowVMLx]>; 112def : Processor<"arm1176jz-s", ARMV6Itineraries, [ArchV6]>; 113def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ArchV6, FeatureVFP2]>; 114def : Processor<"mpcorenovfp", ARMV6Itineraries, [ArchV6]>; 115def : Processor<"mpcore", ARMV6Itineraries, [ArchV6, FeatureVFP2]>; 116 117// V6T2 Processors. 118def : Processor<"arm1156t2-s", ARMV6Itineraries, 119 [ArchV6T2, FeatureThumb2]>; 120def : Processor<"arm1156t2f-s", ARMV6Itineraries, 121 [ArchV6T2, FeatureThumb2, FeatureVFP2]>; 122 123// V7 Processors. 124def : Processor<"cortex-a8", CortexA8Itineraries, 125 [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx, 126 FeatureNEONForFP]>; 127def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; 128 129//===----------------------------------------------------------------------===// 130// Register File Description 131//===----------------------------------------------------------------------===// 132 133include "ARMRegisterInfo.td" 134 135include "ARMCallingConv.td" 136 137//===----------------------------------------------------------------------===// 138// Instruction Descriptions 139//===----------------------------------------------------------------------===// 140 141include "ARMInstrInfo.td" 142 143def ARMInstrInfo : InstrInfo { 144 // Define how we want to layout our target-specific information field. 145 let TSFlagsFields = ["AddrModeBits", 146 "SizeFlag", 147 "IndexModeBits", 148 "Form", 149 "isUnaryDataProc", 150 "canXformTo16Bit", 151 "Dom"]; 152 let TSFlagsShifts = [0, 153 4, 154 7, 155 9, 156 15, 157 16, 158 17]; 159} 160 161//===----------------------------------------------------------------------===// 162// Declare the target which we are implementing 163//===----------------------------------------------------------------------===// 164 165def ARM : Target { 166 // Pull in Instruction Info: 167 let InstructionSet = ARMInstrInfo; 168} 169