ARM.td revision 194178 
1//===- ARM.td - Describe the ARM Target Machine -----------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// ARM Subtarget features.
21//
22
23def ArchV4T     : SubtargetFeature<"v4t", "ARMArchVersion", "V4T",
24                                   "ARM v4T">;
25def ArchV5T     : SubtargetFeature<"v5t", "ARMArchVersion", "V5T",
26                                   "ARM v5T">;
27def ArchV5TE    : SubtargetFeature<"v5te", "ARMArchVersion", "V5TE",
28                                   "ARM v5TE, v5TEj, v5TExp">;
29def ArchV6      : SubtargetFeature<"v6", "ARMArchVersion", "V6",
30                                   "ARM v6">;
31def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
32                                   "ARM v6t2">;
33def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
34                                   "ARM v7A">;
35def FeatureVFP2 : SubtargetFeature<"vfp2", "ARMFPUType", "VFPv2",
36                                   "Enable VFP2 instructions">;
37def FeatureVFP3 : SubtargetFeature<"vfp3", "ARMFPUType", "VFPv3",
38                                   "Enable VFP3 instructions">;
39def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON",
40                                   "Enable NEON instructions">;
41def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
42                                     "Enable Thumb2 instructions">;
43
44//===----------------------------------------------------------------------===//
45// ARM Processors supported.
46//
47
48class Proc<string Name, list<SubtargetFeature> Features>
49 : Processor<Name, NoItineraries, Features>;
50
51// V4 Processors.
52def : Proc<"generic",         []>;
53def : Proc<"arm8",            []>;
54def : Proc<"arm810",          []>;
55def : Proc<"strongarm",       []>;
56def : Proc<"strongarm110",    []>;
57def : Proc<"strongarm1100",   []>;
58def : Proc<"strongarm1110",   []>;
59
60// V4T Processors.
61def : Proc<"arm7tdmi",        [ArchV4T]>;
62def : Proc<"arm7tdmi-s",      [ArchV4T]>;
63def : Proc<"arm710t",         [ArchV4T]>;
64def : Proc<"arm720t",         [ArchV4T]>;
65def : Proc<"arm9",            [ArchV4T]>;
66def : Proc<"arm9tdmi",        [ArchV4T]>;
67def : Proc<"arm920",          [ArchV4T]>;
68def : Proc<"arm920t",         [ArchV4T]>;
69def : Proc<"arm922t",         [ArchV4T]>;
70def : Proc<"arm940t",         [ArchV4T]>;
71def : Proc<"ep9312",          [ArchV4T]>;
72
73// V5T Processors.
74def : Proc<"arm10tdmi",       [ArchV5T]>;
75def : Proc<"arm1020t",        [ArchV5T]>;
76
77// V5TE Processors.
78def : Proc<"arm9e",           [ArchV5TE]>;
79def : Proc<"arm926ej-s",      [ArchV5TE]>;
80def : Proc<"arm946e-s",       [ArchV5TE]>;
81def : Proc<"arm966e-s",       [ArchV5TE]>;
82def : Proc<"arm968e-s",       [ArchV5TE]>;
83def : Proc<"arm10e",          [ArchV5TE]>;
84def : Proc<"arm1020e",        [ArchV5TE]>;
85def : Proc<"arm1022e",        [ArchV5TE]>;
86def : Proc<"xscale",          [ArchV5TE]>;
87def : Proc<"iwmmxt",          [ArchV5TE]>;
88
89// V6 Processors.
90def : Proc<"arm1136j-s",      [ArchV6]>;
91def : Proc<"arm1136jf-s",     [ArchV6, FeatureVFP2]>;
92def : Proc<"arm1176jz-s",     [ArchV6]>;
93def : Proc<"arm1176jzf-s",    [ArchV6, FeatureVFP2]>;
94def : Proc<"mpcorenovfp",     [ArchV6]>;
95def : Proc<"mpcore",          [ArchV6, FeatureVFP2]>;
96
97// V6T2 Processors.
98def : Proc<"arm1156t2-s",     [ArchV6T2, FeatureThumb2]>;
99def : Proc<"arm1156t2f-s",    [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
100
101// V7 Processors.
102def : Proc<"cortex-a8",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
103def : Proc<"cortex-a9",       [ArchV7A, FeatureThumb2, FeatureNEON]>;
104
105//===----------------------------------------------------------------------===//
106// Register File Description
107//===----------------------------------------------------------------------===//
108
109include "ARMRegisterInfo.td"
110
111include "ARMCallingConv.td"
112
113//===----------------------------------------------------------------------===//
114// Instruction Descriptions
115//===----------------------------------------------------------------------===//
116
117include "ARMInstrInfo.td"
118
119def ARMInstrInfo : InstrInfo {
120  // Define how we want to layout our target-specific information field.
121  let TSFlagsFields = ["AddrModeBits",
122                       "SizeFlag",
123                       "IndexModeBits",
124                       "isUnaryDataProc",
125                       "Form"];
126  let TSFlagsShifts = [0,
127                       4,
128                       7,
129                       9,
130                       10];
131}
132
133//===----------------------------------------------------------------------===//
134// Declare the target which we are implementing
135//===----------------------------------------------------------------------===//
136
137def ARM : Target {
138  // Pull in Instruction Info:
139  let InstructionSet = ARMInstrInfo;
140}
141