AArch64ISelLowering.h revision 251662
1228753Smm//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==// 2228753Smm// 3228753Smm// The LLVM Compiler Infrastructure 4228753Smm// 5228753Smm// This file is distributed under the University of Illinois Open Source 6228753Smm// License. See LICENSE.TXT for details. 7228753Smm// 8228753Smm//===----------------------------------------------------------------------===// 9228753Smm// 10228753Smm// This file defines the interfaces that AArch64 uses to lower LLVM code into a 11228753Smm// selection DAG. 12228753Smm// 13228753Smm//===----------------------------------------------------------------------===// 14228753Smm 15228753Smm#ifndef LLVM_TARGET_AARCH64_ISELLOWERING_H 16228753Smm#define LLVM_TARGET_AARCH64_ISELLOWERING_H 17228753Smm 18228753Smm#include "Utils/AArch64BaseInfo.h" 19228753Smm#include "llvm/CodeGen/CallingConvLower.h" 20228753Smm#include "llvm/CodeGen/SelectionDAG.h" 21228753Smm#include "llvm/Target/TargetLowering.h" 22228753Smm 23228753Smm 24228753Smmnamespace llvm { 25228753Smmnamespace AArch64ISD { 26228763Smm enum NodeType { 27228753Smm // Start the numbering from where ISD NodeType finishes. 28228753Smm FIRST_NUMBER = ISD::BUILTIN_OP_END, 29228753Smm 30228753Smm // This is a conditional branch which also notes the flag needed 31228753Smm // (eq/sgt/...). A64 puts this information on the branches rather than 32228753Smm // compares as LLVM does. 33228753Smm BR_CC, 34228753Smm 35228753Smm // A node to be selected to an actual call operation: either BL or BLR in 36228753Smm // the absence of tail calls. 37228753Smm Call, 38228753Smm 39228753Smm // Indicates a floating-point immediate which fits into the format required 40228753Smm // by the FMOV instructions. First (and only) operand is the 8-bit encoded 41228753Smm // value of that immediate. 42228753Smm FPMOV, 43228753Smm 44228753Smm // Corresponds directly to an EXTR instruction. Operands are an LHS an RHS 45228753Smm // and an LSB. 46228753Smm EXTR, 47228753Smm 48228753Smm // Wraps a load from the GOT, which should always be performed with a 64-bit 49228753Smm // load instruction. This prevents the DAG combiner folding a truncate to 50228753Smm // form a smaller memory access. 51228753Smm GOTLoad, 52228753Smm 53228753Smm // Performs a bitfield insert. Arguments are: the value being inserted into; 54228753Smm // the value being inserted; least significant bit changed; width of the 55228753Smm // field. 56228753Smm BFI, 57228753Smm 58228753Smm // Simply a convenient node inserted during ISelLowering to represent 59228753Smm // procedure return. Will almost certainly be selected to "RET". 60228753Smm Ret, 61228753Smm 62228753Smm /// Extracts a field of contiguous bits from the source and sign extends 63228753Smm /// them into a single register. Arguments are: source; immr; imms. Note 64228753Smm /// these are pre-encoded since DAG matching can't cope with combining LSB 65228753Smm /// and Width into these values itself. 66228753Smm SBFX, 67228753Smm 68228753Smm /// This is an A64-ification of the standard LLVM SELECT_CC operation. The 69228753Smm /// main difference is that it only has the values and an A64 condition, 70228753Smm /// which will be produced by a setcc instruction. 71228753Smm SELECT_CC, 72228753Smm 73228753Smm /// This serves most of the functions of the LLVM SETCC instruction, for two 74228753Smm /// purposes. First, it prevents optimisations from fiddling with the 75228753Smm /// compare after we've moved the CondCode information onto the SELECT_CC or 76228753Smm /// BR_CC instructions. Second, it gives a legal instruction for the actual 77228753Smm /// comparison. 78228753Smm /// 79 /// It keeps a record of the condition flags asked for because certain 80 /// instructions are only valid for a subset of condition codes. 81 SETCC, 82 83 // Designates a node which is a tail call: both a call and a return 84 // instruction as far as selction is concerned. It should be selected to an 85 // unconditional branch. Has the usual plethora of call operands, but: 1st 86 // is callee, 2nd is stack adjustment required immediately before branch. 87 TC_RETURN, 88 89 // Designates a call used to support the TLS descriptor ABI. The call itself 90 // will be indirect ("BLR xN") but a relocation-specifier (".tlsdesccall 91 // var") must be attached somehow during code generation. It takes two 92 // operands: the callee and the symbol to be relocated against. 93 TLSDESCCALL, 94 95 // Leaf node which will be lowered to an appropriate MRS to obtain the 96 // thread pointer: TPIDR_EL0. 97 THREAD_POINTER, 98 99 /// Extracts a field of contiguous bits from the source and zero extends 100 /// them into a single register. Arguments are: source; immr; imms. Note 101 /// these are pre-encoded since DAG matching can't cope with combining LSB 102 /// and Width into these values itself. 103 UBFX, 104 105 // Wraps an address which the ISelLowering phase has decided should be 106 // created using the large memory model style: i.e. a sequence of four 107 // movz/movk instructions. 108 WrapperLarge, 109 110 // Wraps an address which the ISelLowering phase has decided should be 111 // created using the small memory model style: i.e. adrp/add or 112 // adrp/mem-op. This exists to prevent bare TargetAddresses which may never 113 // get selected. 114 WrapperSmall 115 }; 116} 117 118 119class AArch64Subtarget; 120class AArch64TargetMachine; 121 122class AArch64TargetLowering : public TargetLowering { 123public: 124 explicit AArch64TargetLowering(AArch64TargetMachine &TM); 125 126 const char *getTargetNodeName(unsigned Opcode) const; 127 128 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const; 129 130 SDValue LowerFormalArguments(SDValue Chain, 131 CallingConv::ID CallConv, bool isVarArg, 132 const SmallVectorImpl<ISD::InputArg> &Ins, 133 DebugLoc dl, SelectionDAG &DAG, 134 SmallVectorImpl<SDValue> &InVals) const; 135 136 SDValue LowerReturn(SDValue Chain, 137 CallingConv::ID CallConv, bool isVarArg, 138 const SmallVectorImpl<ISD::OutputArg> &Outs, 139 const SmallVectorImpl<SDValue> &OutVals, 140 DebugLoc dl, SelectionDAG &DAG) const; 141 142 SDValue LowerCall(CallLoweringInfo &CLI, 143 SmallVectorImpl<SDValue> &InVals) const; 144 145 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 146 CallingConv::ID CallConv, bool IsVarArg, 147 const SmallVectorImpl<ISD::InputArg> &Ins, 148 DebugLoc dl, SelectionDAG &DAG, 149 SmallVectorImpl<SDValue> &InVals) const; 150 151 void SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, 152 DebugLoc DL, SDValue &Chain) const; 153 154 155 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 156 /// for tail call optimization. Targets which want to do tail call 157 /// optimization should implement this function. 158 bool IsEligibleForTailCallOptimization(SDValue Callee, 159 CallingConv::ID CalleeCC, 160 bool IsVarArg, 161 bool IsCalleeStructRet, 162 bool IsCallerStructRet, 163 const SmallVectorImpl<ISD::OutputArg> &Outs, 164 const SmallVectorImpl<SDValue> &OutVals, 165 const SmallVectorImpl<ISD::InputArg> &Ins, 166 SelectionDAG& DAG) const; 167 168 /// Finds the incoming stack arguments which overlap the given fixed stack 169 /// object and incorporates their load into the current chain. This prevents 170 /// an upcoming store from clobbering the stack argument before it's used. 171 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG, 172 MachineFrameInfo *MFI, int ClobberedFI) const; 173 174 EVT getSetCCResultType(EVT VT) const; 175 176 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const; 177 178 bool IsTailCallConvention(CallingConv::ID CallCC) const; 179 180 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 181 182 bool isLegalICmpImmediate(int64_t Val) const; 183 SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, 184 SDValue &A64cc, SelectionDAG &DAG, DebugLoc &dl) const; 185 186 virtual MachineBasicBlock * 187 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; 188 189 MachineBasicBlock * 190 emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB, 191 unsigned Size, unsigned Opcode) const; 192 193 MachineBasicBlock * 194 emitAtomicBinaryMinMax(MachineInstr *MI, MachineBasicBlock *BB, 195 unsigned Size, unsigned CmpOp, 196 A64CC::CondCodes Cond) const; 197 MachineBasicBlock * 198 emitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB, 199 unsigned Size) const; 200 201 MachineBasicBlock * 202 EmitF128CSEL(MachineInstr *MI, MachineBasicBlock *MBB) const; 203 204 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 205 SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const; 206 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 207 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 208 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 209 SDValue LowerF128ToCall(SDValue Op, SelectionDAG &DAG, 210 RTLIB::Libcall Call) const; 211 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 212 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 213 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, bool IsSigned) const; 214 215 SDValue LowerGlobalAddressELFSmall(SDValue Op, SelectionDAG &DAG) const; 216 SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const; 217 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 218 219 SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, DebugLoc DL, 220 SelectionDAG &DAG) const; 221 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 222 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool IsSigned) const; 223 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 224 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 225 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 226 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 227 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 228 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 229 230 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 231 232 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than 233 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to 234 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd 235 /// is expanded to mul + add. 236 virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; } 237 238 ConstraintType getConstraintType(const std::string &Constraint) const; 239 240 ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, 241 const char *Constraint) const; 242 void LowerAsmOperandForConstraint(SDValue Op, 243 std::string &Constraint, 244 std::vector<SDValue> &Ops, 245 SelectionDAG &DAG) const; 246 247 std::pair<unsigned, const TargetRegisterClass*> 248 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; 249private: 250 const AArch64Subtarget *Subtarget; 251 const TargetRegisterInfo *RegInfo; 252 const InstrItineraryData *Itins; 253}; 254} // namespace llvm 255 256#endif // LLVM_TARGET_AARCH64_ISELLOWERING_H 257