InstrEmitter.cpp revision 208599
1198090Srdivacky//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2198090Srdivacky// 3198090Srdivacky// The LLVM Compiler Infrastructure 4198090Srdivacky// 5198090Srdivacky// This file is distributed under the University of Illinois Open Source 6198090Srdivacky// License. See LICENSE.TXT for details. 7198090Srdivacky// 8198090Srdivacky//===----------------------------------------------------------------------===// 9198090Srdivacky// 10198090Srdivacky// This implements the Emit routines for the SelectionDAG class, which creates 11198090Srdivacky// MachineInstrs based on the decisions of the SelectionDAG instruction 12198090Srdivacky// selection. 13198090Srdivacky// 14198090Srdivacky//===----------------------------------------------------------------------===// 15198090Srdivacky 16198090Srdivacky#define DEBUG_TYPE "instr-emitter" 17198090Srdivacky#include "InstrEmitter.h" 18205218Srdivacky#include "SDNodeDbgValue.h" 19198090Srdivacky#include "llvm/CodeGen/MachineConstantPool.h" 20198090Srdivacky#include "llvm/CodeGen/MachineFunction.h" 21198090Srdivacky#include "llvm/CodeGen/MachineInstrBuilder.h" 22198090Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 23198090Srdivacky#include "llvm/Target/TargetData.h" 24198090Srdivacky#include "llvm/Target/TargetMachine.h" 25198090Srdivacky#include "llvm/Target/TargetInstrInfo.h" 26198090Srdivacky#include "llvm/Target/TargetLowering.h" 27198090Srdivacky#include "llvm/ADT/Statistic.h" 28198090Srdivacky#include "llvm/Support/Debug.h" 29198090Srdivacky#include "llvm/Support/ErrorHandling.h" 30198090Srdivacky#include "llvm/Support/MathExtras.h" 31198090Srdivackyusing namespace llvm; 32198090Srdivacky 33198090Srdivacky/// CountResults - The results of target nodes have register or immediate 34198090Srdivacky/// operands first, then an optional chain, and optional flag operands (which do 35198090Srdivacky/// not go into the resulting MachineInstr). 36198090Srdivackyunsigned InstrEmitter::CountResults(SDNode *Node) { 37198090Srdivacky unsigned N = Node->getNumValues(); 38198090Srdivacky while (N && Node->getValueType(N - 1) == MVT::Flag) 39198090Srdivacky --N; 40198090Srdivacky if (N && Node->getValueType(N - 1) == MVT::Other) 41198090Srdivacky --N; // Skip over chain result. 42198090Srdivacky return N; 43198090Srdivacky} 44198090Srdivacky 45198090Srdivacky/// CountOperands - The inputs to target nodes have any actual inputs first, 46198090Srdivacky/// followed by an optional chain operand, then an optional flag operand. 47198090Srdivacky/// Compute the number of actual operands that will go into the resulting 48198090Srdivacky/// MachineInstr. 49198090Srdivackyunsigned InstrEmitter::CountOperands(SDNode *Node) { 50198090Srdivacky unsigned N = Node->getNumOperands(); 51198090Srdivacky while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) 52198090Srdivacky --N; 53198090Srdivacky if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 54198090Srdivacky --N; // Ignore chain if it exists. 55198090Srdivacky return N; 56198090Srdivacky} 57198090Srdivacky 58198090Srdivacky/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 59198090Srdivacky/// implicit physical register output. 60198090Srdivackyvoid InstrEmitter:: 61198090SrdivackyEmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 62198090Srdivacky unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 63198090Srdivacky unsigned VRBase = 0; 64198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 65198090Srdivacky // Just use the input register directly! 66198090Srdivacky SDValue Op(Node, ResNo); 67198090Srdivacky if (IsClone) 68198090Srdivacky VRBaseMap.erase(Op); 69198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 70198090Srdivacky isNew = isNew; // Silence compiler warning. 71198090Srdivacky assert(isNew && "Node emitted out of order - early"); 72198090Srdivacky return; 73198090Srdivacky } 74198090Srdivacky 75198090Srdivacky // If the node is only used by a CopyToReg and the dest reg is a vreg, use 76198090Srdivacky // the CopyToReg'd destination register instead of creating a new vreg. 77198090Srdivacky bool MatchReg = true; 78198090Srdivacky const TargetRegisterClass *UseRC = NULL; 79198090Srdivacky if (!IsClone && !IsCloned) 80198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 81198090Srdivacky UI != E; ++UI) { 82198090Srdivacky SDNode *User = *UI; 83198090Srdivacky bool Match = true; 84198090Srdivacky if (User->getOpcode() == ISD::CopyToReg && 85198090Srdivacky User->getOperand(2).getNode() == Node && 86198090Srdivacky User->getOperand(2).getResNo() == ResNo) { 87198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 88198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 89198090Srdivacky VRBase = DestReg; 90198090Srdivacky Match = false; 91198090Srdivacky } else if (DestReg != SrcReg) 92198090Srdivacky Match = false; 93198090Srdivacky } else { 94198090Srdivacky for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 95198090Srdivacky SDValue Op = User->getOperand(i); 96198090Srdivacky if (Op.getNode() != Node || Op.getResNo() != ResNo) 97198090Srdivacky continue; 98198090Srdivacky EVT VT = Node->getValueType(Op.getResNo()); 99198090Srdivacky if (VT == MVT::Other || VT == MVT::Flag) 100198090Srdivacky continue; 101198090Srdivacky Match = false; 102198090Srdivacky if (User->isMachineOpcode()) { 103198090Srdivacky const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); 104198090Srdivacky const TargetRegisterClass *RC = 0; 105198090Srdivacky if (i+II.getNumDefs() < II.getNumOperands()) 106198090Srdivacky RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); 107198090Srdivacky if (!UseRC) 108198090Srdivacky UseRC = RC; 109198090Srdivacky else if (RC) { 110198090Srdivacky const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); 111198090Srdivacky // If multiple uses expect disjoint register classes, we emit 112198090Srdivacky // copies in AddRegisterOperand. 113198090Srdivacky if (ComRC) 114198090Srdivacky UseRC = ComRC; 115198090Srdivacky } 116198090Srdivacky } 117198090Srdivacky } 118198090Srdivacky } 119198090Srdivacky MatchReg &= Match; 120198090Srdivacky if (VRBase) 121198090Srdivacky break; 122198090Srdivacky } 123198090Srdivacky 124198090Srdivacky EVT VT = Node->getValueType(ResNo); 125198090Srdivacky const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 126198090Srdivacky SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); 127198090Srdivacky 128198090Srdivacky // Figure out the register class to create for the destreg. 129198090Srdivacky if (VRBase) { 130198090Srdivacky DstRC = MRI->getRegClass(VRBase); 131198090Srdivacky } else if (UseRC) { 132198090Srdivacky assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 133198090Srdivacky DstRC = UseRC; 134198090Srdivacky } else { 135198090Srdivacky DstRC = TLI->getRegClassFor(VT); 136198090Srdivacky } 137198090Srdivacky 138198090Srdivacky // If all uses are reading from the src physical register and copying the 139198090Srdivacky // register is either impossible or very expensive, then don't create a copy. 140198090Srdivacky if (MatchReg && SrcRC->getCopyCost() < 0) { 141198090Srdivacky VRBase = SrcReg; 142198090Srdivacky } else { 143198090Srdivacky // Create the reg, emit the copy. 144198090Srdivacky VRBase = MRI->createVirtualRegister(DstRC); 145198090Srdivacky bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg, 146208599Srdivacky DstRC, SrcRC, Node->getDebugLoc()); 147198090Srdivacky 148198090Srdivacky assert(Emitted && "Unable to issue a copy instruction!\n"); 149198090Srdivacky (void) Emitted; 150198090Srdivacky } 151198090Srdivacky 152198090Srdivacky SDValue Op(Node, ResNo); 153198090Srdivacky if (IsClone) 154198090Srdivacky VRBaseMap.erase(Op); 155198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 156198090Srdivacky isNew = isNew; // Silence compiler warning. 157198090Srdivacky assert(isNew && "Node emitted out of order - early"); 158198090Srdivacky} 159198090Srdivacky 160198090Srdivacky/// getDstOfCopyToRegUse - If the only use of the specified result number of 161198090Srdivacky/// node is a CopyToReg, return its destination register. Return 0 otherwise. 162198090Srdivackyunsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 163198090Srdivacky unsigned ResNo) const { 164198090Srdivacky if (!Node->hasOneUse()) 165198090Srdivacky return 0; 166198090Srdivacky 167198090Srdivacky SDNode *User = *Node->use_begin(); 168198090Srdivacky if (User->getOpcode() == ISD::CopyToReg && 169198090Srdivacky User->getOperand(2).getNode() == Node && 170198090Srdivacky User->getOperand(2).getResNo() == ResNo) { 171198090Srdivacky unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 172198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(Reg)) 173198090Srdivacky return Reg; 174198090Srdivacky } 175198090Srdivacky return 0; 176198090Srdivacky} 177198090Srdivacky 178198090Srdivackyvoid InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 179198090Srdivacky const TargetInstrDesc &II, 180198090Srdivacky bool IsClone, bool IsCloned, 181198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 182203954Srdivacky assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 183198090Srdivacky "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 184198090Srdivacky 185198090Srdivacky for (unsigned i = 0; i < II.getNumDefs(); ++i) { 186198090Srdivacky // If the specific node value is only used by a CopyToReg and the dest reg 187198090Srdivacky // is a vreg in the same register class, use the CopyToReg'd destination 188198090Srdivacky // register instead of creating a new vreg. 189198090Srdivacky unsigned VRBase = 0; 190198090Srdivacky const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); 191198090Srdivacky if (II.OpInfo[i].isOptionalDef()) { 192198090Srdivacky // Optional def must be a physical register. 193198090Srdivacky unsigned NumResults = CountResults(Node); 194198090Srdivacky VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 195198090Srdivacky assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 196198090Srdivacky MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 197198090Srdivacky } 198198090Srdivacky 199198090Srdivacky if (!VRBase && !IsClone && !IsCloned) 200198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 201198090Srdivacky UI != E; ++UI) { 202198090Srdivacky SDNode *User = *UI; 203198090Srdivacky if (User->getOpcode() == ISD::CopyToReg && 204198090Srdivacky User->getOperand(2).getNode() == Node && 205198090Srdivacky User->getOperand(2).getResNo() == i) { 206198090Srdivacky unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 207198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(Reg)) { 208198090Srdivacky const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 209198090Srdivacky if (RegRC == RC) { 210198090Srdivacky VRBase = Reg; 211198090Srdivacky MI->addOperand(MachineOperand::CreateReg(Reg, true)); 212198090Srdivacky break; 213198090Srdivacky } 214198090Srdivacky } 215198090Srdivacky } 216198090Srdivacky } 217198090Srdivacky 218198090Srdivacky // Create the result registers for this node and add the result regs to 219198090Srdivacky // the machine instruction. 220198090Srdivacky if (VRBase == 0) { 221198090Srdivacky assert(RC && "Isn't a register operand!"); 222198090Srdivacky VRBase = MRI->createVirtualRegister(RC); 223198090Srdivacky MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 224198090Srdivacky } 225198090Srdivacky 226198090Srdivacky SDValue Op(Node, i); 227198090Srdivacky if (IsClone) 228198090Srdivacky VRBaseMap.erase(Op); 229198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 230198090Srdivacky isNew = isNew; // Silence compiler warning. 231198090Srdivacky assert(isNew && "Node emitted out of order - early"); 232198090Srdivacky } 233198090Srdivacky} 234198090Srdivacky 235198090Srdivacky/// getVR - Return the virtual register corresponding to the specified result 236198090Srdivacky/// of the specified node. 237198090Srdivackyunsigned InstrEmitter::getVR(SDValue Op, 238198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 239198090Srdivacky if (Op.isMachineOpcode() && 240203954Srdivacky Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 241198090Srdivacky // Add an IMPLICIT_DEF instruction before every use. 242198090Srdivacky unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 243198090Srdivacky // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc 244198090Srdivacky // does not include operand register class info. 245198090Srdivacky if (!VReg) { 246198090Srdivacky const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); 247198090Srdivacky VReg = MRI->createVirtualRegister(RC); 248198090Srdivacky } 249198090Srdivacky BuildMI(MBB, Op.getDebugLoc(), 250203954Srdivacky TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 251198090Srdivacky return VReg; 252198090Srdivacky } 253198090Srdivacky 254198090Srdivacky DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 255198090Srdivacky assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 256198090Srdivacky return I->second; 257198090Srdivacky} 258198090Srdivacky 259198090Srdivacky 260198090Srdivacky/// AddRegisterOperand - Add the specified register as an operand to the 261198090Srdivacky/// specified machine instr. Insert register copies if the register is 262198090Srdivacky/// not in the required register class. 263198090Srdivackyvoid 264198090SrdivackyInstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, 265198090Srdivacky unsigned IIOpNum, 266198090Srdivacky const TargetInstrDesc *II, 267206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 268208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned) { 269198090Srdivacky assert(Op.getValueType() != MVT::Other && 270198090Srdivacky Op.getValueType() != MVT::Flag && 271198090Srdivacky "Chain and flag operands should occur at end of operand list!"); 272198090Srdivacky // Get/emit the operand. 273198090Srdivacky unsigned VReg = getVR(Op, VRBaseMap); 274198090Srdivacky assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 275198090Srdivacky 276198090Srdivacky const TargetInstrDesc &TID = MI->getDesc(); 277198090Srdivacky bool isOptDef = IIOpNum < TID.getNumOperands() && 278198090Srdivacky TID.OpInfo[IIOpNum].isOptionalDef(); 279198090Srdivacky 280198090Srdivacky // If the instruction requires a register in a different class, create 281198090Srdivacky // a new virtual register and copy the value into it. 282198090Srdivacky if (II) { 283198090Srdivacky const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 284198090Srdivacky const TargetRegisterClass *DstRC = 0; 285198090Srdivacky if (IIOpNum < II->getNumOperands()) 286198090Srdivacky DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); 287198090Srdivacky assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && 288198090Srdivacky "Don't have operand info for this instruction!"); 289198090Srdivacky if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { 290198090Srdivacky unsigned NewVReg = MRI->createVirtualRegister(DstRC); 291198090Srdivacky bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 292208599Srdivacky DstRC, SrcRC, Op.getNode()->getDebugLoc()); 293198090Srdivacky assert(Emitted && "Unable to issue a copy instruction!\n"); 294198090Srdivacky (void) Emitted; 295198090Srdivacky VReg = NewVReg; 296198090Srdivacky } 297198090Srdivacky } 298198090Srdivacky 299207618Srdivacky // If this value has only one use, that use is a kill. This is a 300208599Srdivacky // conservative approximation. InstrEmitter does trivial coalescing 301208599Srdivacky // with CopyFromReg nodes, so don't emit kill flags for them. 302208599Srdivacky // Avoid kill flags on Schedule cloned nodes, since there will be 303208599Srdivacky // multiple uses. 304208599Srdivacky // Tied operands are never killed, so we need to check that. And that 305208599Srdivacky // means we need to determine the index of the operand. 306208599Srdivacky bool isKill = Op.hasOneUse() && 307208599Srdivacky Op.getNode()->getOpcode() != ISD::CopyFromReg && 308208599Srdivacky !IsDebug && 309208599Srdivacky !(IsClone || IsCloned); 310208599Srdivacky if (isKill) { 311208599Srdivacky unsigned Idx = MI->getNumOperands(); 312208599Srdivacky while (Idx > 0 && 313208599Srdivacky MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) 314208599Srdivacky --Idx; 315208599Srdivacky bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; 316208599Srdivacky if (isTied) 317208599Srdivacky isKill = false; 318208599Srdivacky } 319207618Srdivacky 320206083Srdivacky MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 321207618Srdivacky false/*isImp*/, isKill, 322206083Srdivacky false/*isDead*/, false/*isUndef*/, 323206083Srdivacky false/*isEarlyClobber*/, 324206083Srdivacky 0/*SubReg*/, IsDebug)); 325198090Srdivacky} 326198090Srdivacky 327198090Srdivacky/// AddOperand - Add the specified operand to the specified machine instr. II 328198090Srdivacky/// specifies the instruction information for the node, and IIOpNum is the 329198090Srdivacky/// operand number (in the II) that we are adding. IIOpNum and II are used for 330198090Srdivacky/// assertions only. 331198090Srdivackyvoid InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, 332198090Srdivacky unsigned IIOpNum, 333198090Srdivacky const TargetInstrDesc *II, 334206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 335208599Srdivacky bool IsDebug, bool IsClone, bool IsCloned) { 336198090Srdivacky if (Op.isMachineOpcode()) { 337208599Srdivacky AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 338208599Srdivacky IsDebug, IsClone, IsCloned); 339198090Srdivacky } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 340198090Srdivacky MI->addOperand(MachineOperand::CreateImm(C->getSExtValue())); 341198090Srdivacky } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 342198090Srdivacky const ConstantFP *CFP = F->getConstantFPValue(); 343198090Srdivacky MI->addOperand(MachineOperand::CreateFPImm(CFP)); 344198090Srdivacky } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 345198090Srdivacky MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); 346198090Srdivacky } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 347198090Srdivacky MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(), 348198090Srdivacky TGA->getTargetFlags())); 349198090Srdivacky } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 350198090Srdivacky MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock())); 351198090Srdivacky } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 352198090Srdivacky MI->addOperand(MachineOperand::CreateFI(FI->getIndex())); 353198090Srdivacky } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 354198090Srdivacky MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(), 355198090Srdivacky JT->getTargetFlags())); 356198090Srdivacky } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 357198090Srdivacky int Offset = CP->getOffset(); 358198090Srdivacky unsigned Align = CP->getAlignment(); 359198090Srdivacky const Type *Type = CP->getType(); 360198090Srdivacky // MachineConstantPool wants an explicit alignment. 361198090Srdivacky if (Align == 0) { 362198090Srdivacky Align = TM->getTargetData()->getPrefTypeAlignment(Type); 363198090Srdivacky if (Align == 0) { 364198090Srdivacky // Alignment of vector types. FIXME! 365198090Srdivacky Align = TM->getTargetData()->getTypeAllocSize(Type); 366198090Srdivacky } 367198090Srdivacky } 368198090Srdivacky 369198090Srdivacky unsigned Idx; 370198090Srdivacky MachineConstantPool *MCP = MF->getConstantPool(); 371198090Srdivacky if (CP->isMachineConstantPoolEntry()) 372198090Srdivacky Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 373198090Srdivacky else 374198090Srdivacky Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 375198090Srdivacky MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, 376198090Srdivacky CP->getTargetFlags())); 377198090Srdivacky } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 378198090Srdivacky MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 379198090Srdivacky ES->getTargetFlags())); 380198892Srdivacky } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 381199989Srdivacky MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(), 382199989Srdivacky BA->getTargetFlags())); 383198090Srdivacky } else { 384198090Srdivacky assert(Op.getValueType() != MVT::Other && 385198090Srdivacky Op.getValueType() != MVT::Flag && 386198090Srdivacky "Chain and flag operands should occur at end of operand list!"); 387208599Srdivacky AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap, 388208599Srdivacky IsDebug, IsClone, IsCloned); 389198090Srdivacky } 390198090Srdivacky} 391198090Srdivacky 392198090Srdivacky/// getSuperRegisterRegClass - Returns the register class of a superreg A whose 393198090Srdivacky/// "SubIdx"'th sub-register class is the specified register class and whose 394198090Srdivacky/// type matches the specified type. 395198090Srdivackystatic const TargetRegisterClass* 396198090SrdivackygetSuperRegisterRegClass(const TargetRegisterClass *TRC, 397198090Srdivacky unsigned SubIdx, EVT VT) { 398198090Srdivacky // Pick the register class of the superegister for this type 399198090Srdivacky for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), 400198090Srdivacky E = TRC->superregclasses_end(); I != E; ++I) 401198090Srdivacky if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC) 402198090Srdivacky return *I; 403198090Srdivacky assert(false && "Couldn't find the register class"); 404198090Srdivacky return 0; 405198090Srdivacky} 406198090Srdivacky 407198090Srdivacky/// EmitSubregNode - Generate machine code for subreg nodes. 408198090Srdivacky/// 409198090Srdivackyvoid InstrEmitter::EmitSubregNode(SDNode *Node, 410208599Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 411208599Srdivacky bool IsClone, bool IsCloned) { 412198090Srdivacky unsigned VRBase = 0; 413198090Srdivacky unsigned Opc = Node->getMachineOpcode(); 414198090Srdivacky 415198090Srdivacky // If the node is only used by a CopyToReg and the dest reg is a vreg, use 416198090Srdivacky // the CopyToReg'd destination register instead of creating a new vreg. 417198090Srdivacky for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 418198090Srdivacky UI != E; ++UI) { 419198090Srdivacky SDNode *User = *UI; 420198090Srdivacky if (User->getOpcode() == ISD::CopyToReg && 421198090Srdivacky User->getOperand(2).getNode() == Node) { 422198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 423198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 424198090Srdivacky VRBase = DestReg; 425198090Srdivacky break; 426198090Srdivacky } 427198090Srdivacky } 428198090Srdivacky } 429198090Srdivacky 430203954Srdivacky if (Opc == TargetOpcode::EXTRACT_SUBREG) { 431198090Srdivacky unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 432198090Srdivacky 433198090Srdivacky // Create the extract_subreg machine instruction. 434198090Srdivacky MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 435203954Srdivacky TII->get(TargetOpcode::EXTRACT_SUBREG)); 436198090Srdivacky 437198090Srdivacky // Figure out the register class to create for the destreg. 438198090Srdivacky unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 439198090Srdivacky const TargetRegisterClass *TRC = MRI->getRegClass(VReg); 440198090Srdivacky const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx); 441198090Srdivacky assert(SRC && "Invalid subregister index in EXTRACT_SUBREG"); 442198090Srdivacky 443198090Srdivacky // Figure out the register class to create for the destreg. 444198090Srdivacky // Note that if we're going to directly use an existing register, 445198090Srdivacky // it must be precisely the required class, and not a subclass 446198090Srdivacky // thereof. 447198090Srdivacky if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 448198090Srdivacky // Create the reg 449198090Srdivacky assert(SRC && "Couldn't find source register class"); 450198090Srdivacky VRBase = MRI->createVirtualRegister(SRC); 451198090Srdivacky } 452198090Srdivacky 453198090Srdivacky // Add def, source, and subreg index 454198090Srdivacky MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 455208599Srdivacky AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false, 456208599Srdivacky IsClone, IsCloned); 457198090Srdivacky MI->addOperand(MachineOperand::CreateImm(SubIdx)); 458198090Srdivacky MBB->insert(InsertPos, MI); 459203954Srdivacky } else if (Opc == TargetOpcode::INSERT_SUBREG || 460203954Srdivacky Opc == TargetOpcode::SUBREG_TO_REG) { 461198090Srdivacky SDValue N0 = Node->getOperand(0); 462198090Srdivacky SDValue N1 = Node->getOperand(1); 463198090Srdivacky SDValue N2 = Node->getOperand(2); 464198090Srdivacky unsigned SubReg = getVR(N1, VRBaseMap); 465198090Srdivacky unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 466198090Srdivacky const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 467198090Srdivacky const TargetRegisterClass *SRC = 468207618Srdivacky getSuperRegisterRegClass(TRC, SubIdx, Node->getValueType(0)); 469198090Srdivacky 470198090Srdivacky // Figure out the register class to create for the destreg. 471198090Srdivacky // Note that if we're going to directly use an existing register, 472198090Srdivacky // it must be precisely the required class, and not a subclass 473198090Srdivacky // thereof. 474198090Srdivacky if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) { 475198090Srdivacky // Create the reg 476198090Srdivacky assert(SRC && "Couldn't find source register class"); 477198090Srdivacky VRBase = MRI->createVirtualRegister(SRC); 478198090Srdivacky } 479198090Srdivacky 480198090Srdivacky // Create the insert_subreg or subreg_to_reg machine instruction. 481198090Srdivacky MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc)); 482198090Srdivacky MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 483198090Srdivacky 484198090Srdivacky // If creating a subreg_to_reg, then the first input operand 485198090Srdivacky // is an implicit value immediate, otherwise it's a register 486203954Srdivacky if (Opc == TargetOpcode::SUBREG_TO_REG) { 487198090Srdivacky const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 488198090Srdivacky MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue())); 489198090Srdivacky } else 490208599Srdivacky AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false, 491208599Srdivacky IsClone, IsCloned); 492198090Srdivacky // Add the subregster being inserted 493208599Srdivacky AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false, 494208599Srdivacky IsClone, IsCloned); 495198090Srdivacky MI->addOperand(MachineOperand::CreateImm(SubIdx)); 496198090Srdivacky MBB->insert(InsertPos, MI); 497198090Srdivacky } else 498198090Srdivacky llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 499198090Srdivacky 500198090Srdivacky SDValue Op(Node, 0); 501198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 502198090Srdivacky isNew = isNew; // Silence compiler warning. 503198090Srdivacky assert(isNew && "Node emitted out of order - early"); 504198090Srdivacky} 505198090Srdivacky 506198090Srdivacky/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 507198090Srdivacky/// COPY_TO_REGCLASS is just a normal copy, except that the destination 508198090Srdivacky/// register is constrained to be in a particular register class. 509198090Srdivacky/// 510198090Srdivackyvoid 511198090SrdivackyInstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 512198090Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 513198090Srdivacky unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 514198090Srdivacky const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); 515198090Srdivacky 516198090Srdivacky unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 517198090Srdivacky const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); 518198090Srdivacky 519198090Srdivacky // Create the new VReg in the destination class and emit a copy. 520198090Srdivacky unsigned NewVReg = MRI->createVirtualRegister(DstRC); 521198090Srdivacky bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg, 522208599Srdivacky DstRC, SrcRC, Node->getDebugLoc()); 523198090Srdivacky assert(Emitted && 524198090Srdivacky "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n"); 525198090Srdivacky (void) Emitted; 526198090Srdivacky 527198090Srdivacky SDValue Op(Node, 0); 528198090Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 529198090Srdivacky isNew = isNew; // Silence compiler warning. 530198090Srdivacky assert(isNew && "Node emitted out of order - early"); 531198090Srdivacky} 532198090Srdivacky 533207618Srdivacky/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 534207618Srdivacky/// 535207618Srdivackyvoid InstrEmitter::EmitRegSequence(SDNode *Node, 536208599Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap, 537208599Srdivacky bool IsClone, bool IsCloned) { 538207618Srdivacky const TargetRegisterClass *RC = TLI->getRegClassFor(Node->getValueType(0)); 539207618Srdivacky unsigned NewVReg = MRI->createVirtualRegister(RC); 540207618Srdivacky MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 541207618Srdivacky TII->get(TargetOpcode::REG_SEQUENCE), NewVReg); 542207618Srdivacky unsigned NumOps = Node->getNumOperands(); 543207618Srdivacky assert((NumOps & 1) == 0 && 544207618Srdivacky "REG_SEQUENCE must have an even number of operands!"); 545207618Srdivacky const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 546207618Srdivacky for (unsigned i = 0; i != NumOps; ++i) { 547207618Srdivacky SDValue Op = Node->getOperand(i); 548207618Srdivacky if (i & 1) { 549207618Srdivacky unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 550207618Srdivacky unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 551208599Srdivacky const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 552208599Srdivacky const TargetRegisterClass *SRC = 553208599Srdivacky TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 554208599Srdivacky if (!SRC) 555208599Srdivacky llvm_unreachable("Invalid subregister index in REG_SEQUENCE"); 556208599Srdivacky if (SRC != RC) { 557208599Srdivacky MRI->setRegClass(NewVReg, SRC); 558208599Srdivacky RC = SRC; 559208599Srdivacky } 560207618Srdivacky } 561208599Srdivacky AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 562208599Srdivacky IsClone, IsCloned); 563207618Srdivacky } 564207618Srdivacky 565207618Srdivacky MBB->insert(InsertPos, MI); 566207618Srdivacky SDValue Op(Node, 0); 567207618Srdivacky bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 568207618Srdivacky isNew = isNew; // Silence compiler warning. 569207618Srdivacky assert(isNew && "Node emitted out of order - early"); 570207618Srdivacky} 571207618Srdivacky 572206083Srdivacky/// EmitDbgValue - Generate machine instruction for a dbg_value node. 573206083Srdivacky/// 574207618SrdivackyMachineInstr * 575207618SrdivackyInstrEmitter::EmitDbgValue(SDDbgValue *SD, 576207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 577206083Srdivacky uint64_t Offset = SD->getOffset(); 578206083Srdivacky MDNode* MDPtr = SD->getMDPtr(); 579206083Srdivacky DebugLoc DL = SD->getDebugLoc(); 580204792Srdivacky 581207618Srdivacky if (SD->getKind() == SDDbgValue::FRAMEIX) { 582207618Srdivacky // Stack address; this needs to be lowered in target-dependent fashion. 583207618Srdivacky // EmitTargetCodeForFrameDebugValue is responsible for allocation. 584207618Srdivacky unsigned FrameIx = SD->getFrameIx(); 585207618Srdivacky return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); 586207618Srdivacky } 587207618Srdivacky // Otherwise, we're going to create an instruction here. 588204792Srdivacky const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 589206083Srdivacky MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 590206083Srdivacky if (SD->getKind() == SDDbgValue::SDNODE) { 591207618Srdivacky SDNode *Node = SD->getSDNode(); 592207618Srdivacky SDValue Op = SDValue(Node, SD->getResNo()); 593207618Srdivacky // It's possible we replaced this SDNode with other(s) and therefore 594207618Srdivacky // didn't generate code for it. It's better to catch these cases where 595207618Srdivacky // they happen and transfer the debug info, but trying to guarantee that 596207618Srdivacky // in all cases would be very fragile; this is a safeguard for any 597207618Srdivacky // that were missed. 598207618Srdivacky DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 599207618Srdivacky if (I==VRBaseMap.end()) 600207618Srdivacky MIB.addReg(0U); // undef 601207618Srdivacky else 602207618Srdivacky AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 603208599Srdivacky /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 604206083Srdivacky } else if (SD->getKind() == SDDbgValue::CONST) { 605207618Srdivacky const Value *V = SD->getConst(); 606207618Srdivacky if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 607208599Srdivacky // FIXME: SDDbgValues aren't updated with legalization, so it's possible 608208599Srdivacky // to have i128 values in them at this point. As a crude workaround, just 609208599Srdivacky // drop the debug info if this happens. 610208599Srdivacky if (!CI->getValue().isSignedIntN(64)) 611208599Srdivacky MIB.addReg(0U); 612208599Srdivacky else 613208599Srdivacky MIB.addImm(CI->getSExtValue()); 614207618Srdivacky } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 615206083Srdivacky MIB.addFPImm(CF); 616205218Srdivacky } else { 617205218Srdivacky // Could be an Undef. In any case insert an Undef so we can see what we 618205218Srdivacky // dropped. 619206083Srdivacky MIB.addReg(0U); 620205218Srdivacky } 621204792Srdivacky } else { 622204792Srdivacky // Insert an Undef so we can see what we dropped. 623206083Srdivacky MIB.addReg(0U); 624204792Srdivacky } 625206083Srdivacky 626206083Srdivacky MIB.addImm(Offset).addMetadata(MDPtr); 627206083Srdivacky return &*MIB; 628204792Srdivacky} 629204792Srdivacky 630206083Srdivacky/// EmitMachineNode - Generate machine code for a target-specific node and 631206083Srdivacky/// needed dependencies. 632198090Srdivacky/// 633206083Srdivackyvoid InstrEmitter:: 634206083SrdivackyEmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 635207618Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 636206083Srdivacky unsigned Opc = Node->getMachineOpcode(); 637206083Srdivacky 638206083Srdivacky // Handle subreg insert/extract specially 639206083Srdivacky if (Opc == TargetOpcode::EXTRACT_SUBREG || 640206083Srdivacky Opc == TargetOpcode::INSERT_SUBREG || 641206083Srdivacky Opc == TargetOpcode::SUBREG_TO_REG) { 642208599Srdivacky EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 643206083Srdivacky return; 644206083Srdivacky } 645198090Srdivacky 646206083Srdivacky // Handle COPY_TO_REGCLASS specially. 647206083Srdivacky if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 648206083Srdivacky EmitCopyToRegClassNode(Node, VRBaseMap); 649206083Srdivacky return; 650206083Srdivacky } 651198090Srdivacky 652207618Srdivacky // Handle REG_SEQUENCE specially. 653207618Srdivacky if (Opc == TargetOpcode::REG_SEQUENCE) { 654208599Srdivacky EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 655207618Srdivacky return; 656207618Srdivacky } 657207618Srdivacky 658206083Srdivacky if (Opc == TargetOpcode::IMPLICIT_DEF) 659206083Srdivacky // We want a unique VR for each IMPLICIT_DEF use. 660206083Srdivacky return; 661206083Srdivacky 662206083Srdivacky const TargetInstrDesc &II = TII->get(Opc); 663206083Srdivacky unsigned NumResults = CountResults(Node); 664206083Srdivacky unsigned NodeOperands = CountOperands(Node); 665206083Srdivacky bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; 666198090Srdivacky#ifndef NDEBUG 667206083Srdivacky unsigned NumMIOperands = NodeOperands + NumResults; 668206083Srdivacky if (II.isVariadic()) 669206083Srdivacky assert(NumMIOperands >= II.getNumOperands() && 670206083Srdivacky "Too few operands for a variadic node!"); 671206083Srdivacky else 672206083Srdivacky assert(NumMIOperands >= II.getNumOperands() && 673206083Srdivacky NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() && 674206083Srdivacky "#operands for dag node doesn't match .td file!"); 675198090Srdivacky#endif 676198090Srdivacky 677206083Srdivacky // Create the new machine instruction. 678206083Srdivacky MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II); 679206083Srdivacky 680206083Srdivacky // Add result register values for things that are defined by this 681206083Srdivacky // instruction. 682206083Srdivacky if (NumResults) 683206083Srdivacky CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap); 684206083Srdivacky 685206083Srdivacky // Emit all of the actual operands of this instruction, adding them to the 686206083Srdivacky // instruction as appropriate. 687206083Srdivacky bool HasOptPRefs = II.getNumDefs() > NumResults; 688206083Srdivacky assert((!HasOptPRefs || !HasPhysRegOuts) && 689206083Srdivacky "Unable to cope with optional defs and phys regs defs!"); 690206083Srdivacky unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; 691206083Srdivacky for (unsigned i = NumSkip; i != NodeOperands; ++i) 692206083Srdivacky AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, 693208599Srdivacky VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 694198090Srdivacky 695206083Srdivacky // Transfer all of the memory reference descriptions of this instruction. 696206083Srdivacky MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 697206083Srdivacky cast<MachineSDNode>(Node)->memoperands_end()); 698198090Srdivacky 699206083Srdivacky if (II.usesCustomInsertionHook()) { 700206083Srdivacky // Insert this instruction into the basic block using a target 701206083Srdivacky // specific inserter which may returns a new basic block. 702207618Srdivacky MBB = TLI->EmitInstrWithCustomInserter(MI, MBB); 703206083Srdivacky InsertPos = MBB->end(); 704206083Srdivacky return; 705206083Srdivacky } 706206083Srdivacky 707206083Srdivacky MBB->insert(InsertPos, MI); 708198090Srdivacky 709206083Srdivacky // Additional results must be an physical register def. 710206083Srdivacky if (HasPhysRegOuts) { 711206083Srdivacky for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { 712206083Srdivacky unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; 713206083Srdivacky if (Node->hasAnyUseOfValue(i)) 714206083Srdivacky EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 715206083Srdivacky // If there are no uses, mark the register as dead now, so that 716206083Srdivacky // MachineLICM/Sink can see that it's dead. Don't do this if the 717206083Srdivacky // node has a Flag value, for the benefit of targets still using 718206083Srdivacky // Flag for values in physregs. 719206083Srdivacky else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 720206083Srdivacky MI->addRegisterDead(Reg, TRI); 721198090Srdivacky } 722198090Srdivacky } 723206083Srdivacky 724206083Srdivacky // If the instruction has implicit defs and the node doesn't, mark the 725206083Srdivacky // implicit def as dead. If the node has any flag outputs, we don't do this 726206083Srdivacky // because we don't know what implicit defs are being used by flagged nodes. 727206083Srdivacky if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag) 728206083Srdivacky if (const unsigned *IDList = II.getImplicitDefs()) { 729206083Srdivacky for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); 730206083Srdivacky i != e; ++i) 731206083Srdivacky MI->addRegisterDead(IDList[i-II.getNumDefs()], TRI); 732206083Srdivacky } 733206083Srdivacky} 734198090Srdivacky 735206083Srdivacky/// EmitSpecialNode - Generate machine code for a target-independent node and 736206083Srdivacky/// needed dependencies. 737206083Srdivackyvoid InstrEmitter:: 738206083SrdivackyEmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 739206083Srdivacky DenseMap<SDValue, unsigned> &VRBaseMap) { 740198090Srdivacky switch (Node->getOpcode()) { 741198090Srdivacky default: 742198090Srdivacky#ifndef NDEBUG 743198090Srdivacky Node->dump(); 744198090Srdivacky#endif 745198090Srdivacky llvm_unreachable("This target-independent node should have been selected!"); 746198090Srdivacky break; 747198090Srdivacky case ISD::EntryToken: 748198090Srdivacky llvm_unreachable("EntryToken should have been excluded from the schedule!"); 749198090Srdivacky break; 750198090Srdivacky case ISD::MERGE_VALUES: 751198090Srdivacky case ISD::TokenFactor: // fall thru 752198090Srdivacky break; 753198090Srdivacky case ISD::CopyToReg: { 754198090Srdivacky unsigned SrcReg; 755198090Srdivacky SDValue SrcVal = Node->getOperand(2); 756198090Srdivacky if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 757198090Srdivacky SrcReg = R->getReg(); 758198090Srdivacky else 759198090Srdivacky SrcReg = getVR(SrcVal, VRBaseMap); 760198090Srdivacky 761198090Srdivacky unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 762198090Srdivacky if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 763198090Srdivacky break; 764198090Srdivacky 765198090Srdivacky const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0; 766198090Srdivacky // Get the register classes of the src/dst. 767198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(SrcReg)) 768198090Srdivacky SrcTRC = MRI->getRegClass(SrcReg); 769198090Srdivacky else 770198090Srdivacky SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType()); 771198090Srdivacky 772198090Srdivacky if (TargetRegisterInfo::isVirtualRegister(DestReg)) 773198090Srdivacky DstTRC = MRI->getRegClass(DestReg); 774198090Srdivacky else 775198090Srdivacky DstTRC = TRI->getPhysicalRegisterRegClass(DestReg, 776198090Srdivacky Node->getOperand(1).getValueType()); 777198090Srdivacky 778198090Srdivacky bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg, 779208599Srdivacky DstTRC, SrcTRC, Node->getDebugLoc()); 780198090Srdivacky assert(Emitted && "Unable to issue a copy instruction!\n"); 781198090Srdivacky (void) Emitted; 782198090Srdivacky break; 783198090Srdivacky } 784198090Srdivacky case ISD::CopyFromReg: { 785198090Srdivacky unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 786198090Srdivacky EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 787198090Srdivacky break; 788198090Srdivacky } 789205218Srdivacky case ISD::EH_LABEL: { 790205218Srdivacky MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 791205218Srdivacky BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 792205218Srdivacky TII->get(TargetOpcode::EH_LABEL)).addSym(S); 793205218Srdivacky break; 794205218Srdivacky } 795205218Srdivacky 796198090Srdivacky case ISD::INLINEASM: { 797198090Srdivacky unsigned NumOps = Node->getNumOperands(); 798198090Srdivacky if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) 799198090Srdivacky --NumOps; // Ignore the flag operand. 800198090Srdivacky 801198090Srdivacky // Create the inline asm machine instruction. 802198090Srdivacky MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), 803203954Srdivacky TII->get(TargetOpcode::INLINEASM)); 804198090Srdivacky 805198090Srdivacky // Add the asm string as an external symbol operand. 806207618Srdivacky SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 807207618Srdivacky const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 808198090Srdivacky MI->addOperand(MachineOperand::CreateES(AsmStr)); 809198090Srdivacky 810198090Srdivacky // Add all of the operand registers to the instruction. 811207618Srdivacky for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 812198090Srdivacky unsigned Flags = 813198090Srdivacky cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 814198090Srdivacky unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 815198090Srdivacky 816198090Srdivacky MI->addOperand(MachineOperand::CreateImm(Flags)); 817198090Srdivacky ++i; // Skip the ID value. 818198090Srdivacky 819207618Srdivacky switch (InlineAsm::getKind(Flags)) { 820198090Srdivacky default: llvm_unreachable("Bad flags!"); 821207618Srdivacky case InlineAsm::Kind_RegDef: 822198090Srdivacky for (; NumVals; --NumVals, ++i) { 823198090Srdivacky unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 824198090Srdivacky MI->addOperand(MachineOperand::CreateReg(Reg, true)); 825198090Srdivacky } 826198090Srdivacky break; 827207618Srdivacky case InlineAsm::Kind_RegDefEarlyClobber: 828198090Srdivacky for (; NumVals; --NumVals, ++i) { 829198090Srdivacky unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 830198090Srdivacky MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false, 831198090Srdivacky false, false, true)); 832198090Srdivacky } 833198090Srdivacky break; 834207618Srdivacky case InlineAsm::Kind_RegUse: // Use of register. 835207618Srdivacky case InlineAsm::Kind_Imm: // Immediate. 836207618Srdivacky case InlineAsm::Kind_Mem: // Addressing mode. 837198090Srdivacky // The addressing mode has been selected, just add all of the 838198090Srdivacky // operands to the machine instruction. 839198090Srdivacky for (; NumVals; --NumVals, ++i) 840208599Srdivacky AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 841208599Srdivacky /*IsDebug=*/false, IsClone, IsCloned); 842198090Srdivacky break; 843198090Srdivacky } 844198090Srdivacky } 845207618Srdivacky 846207618Srdivacky // Get the mdnode from the asm if it exists and add it to the instruction. 847207618Srdivacky SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 848207618Srdivacky const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 849207618Srdivacky if (MD) 850207618Srdivacky MI->addOperand(MachineOperand::CreateMetadata(MD)); 851207618Srdivacky 852198090Srdivacky MBB->insert(InsertPos, MI); 853198090Srdivacky break; 854198090Srdivacky } 855198090Srdivacky } 856198090Srdivacky} 857198090Srdivacky 858198090Srdivacky/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 859198090Srdivacky/// at the given position in the given block. 860198090SrdivackyInstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 861198090Srdivacky MachineBasicBlock::iterator insertpos) 862198090Srdivacky : MF(mbb->getParent()), 863198090Srdivacky MRI(&MF->getRegInfo()), 864198090Srdivacky TM(&MF->getTarget()), 865198090Srdivacky TII(TM->getInstrInfo()), 866198090Srdivacky TRI(TM->getRegisterInfo()), 867198090Srdivacky TLI(TM->getTargetLowering()), 868198090Srdivacky MBB(mbb), InsertPos(insertpos) { 869198090Srdivacky} 870