RegisterClassInfo.cpp revision 224145
1195098Sed//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===// 2195098Sed// 3195098Sed// The LLVM Compiler Infrastructure 4195098Sed// 5195098Sed// This file is distributed under the University of Illinois Open Source 6195098Sed// License. See LICENSE.TXT for details. 7195098Sed// 8195098Sed//===----------------------------------------------------------------------===// 9195098Sed// 10249423Sdim// This file implements the RegisterClassInfo class which provides dynamic 11249423Sdim// information about target register classes. Callee saved and reserved 12249423Sdim// registers depends on calling conventions and other dynamic information, so 13263508Sdim// some things cannot be determined statically. 14218893Sdim// 15218893Sdim//===----------------------------------------------------------------------===// 16202878Srdivacky 17218893Sdim#define DEBUG_TYPE "regalloc" 18221345Sdim#include "RegisterClassInfo.h" 19218893Sdim#include "llvm/CodeGen/MachineFunction.h" 20249423Sdim#include "llvm/Target/TargetMachine.h" 21202878Srdivacky 22206274Srdivacky#include "llvm/Support/Debug.h" 23195098Sed#include "llvm/Support/raw_ostream.h" 24195098Sed 25263508Sdimusing namespace llvm; 26263508Sdim 27263508SdimRegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) 28263508Sdim{} 29263508Sdim 30263508Sdimvoid RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { 31263508Sdim bool Update = false; 32263508Sdim MF = &mf; 33251662Sdim 34263508Sdim // Allocate new array the first time we see a new target. 35263508Sdim if (MF->getTarget().getRegisterInfo() != TRI) { 36195098Sed TRI = MF->getTarget().getRegisterInfo(); 37195098Sed RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 38195098Sed Update = true; 39223017Sdim } 40223017Sdim 41195098Sed // Does this MF have different CSRs? 42202878Srdivacky const unsigned *CSR = TRI->getCalleeSavedRegs(MF); 43249423Sdim if (Update || CSR != CalleeSaved) { 44249423Sdim // Build a CSRNum map. Every CSR alias gets an entry pointing to the last 45249423Sdim // overlapping CSR. 46251662Sdim CSRNum.clear(); 47249423Sdim CSRNum.resize(TRI->getNumRegs(), 0); 48249423Sdim for (unsigned N = 0; unsigned Reg = CSR[N]; ++N) 49249423Sdim for (const unsigned *AS = TRI->getOverlaps(Reg); 50249423Sdim unsigned Alias = *AS; ++AS) 51249423Sdim CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ... 52251662Sdim Update = true; 53249423Sdim } 54249423Sdim CalleeSaved = CSR; 55221345Sdim 56221345Sdim // Different reserved registers? 57221345Sdim BitVector RR = TRI->getReservedRegs(*MF); 58221345Sdim if (RR != Reserved) 59221345Sdim Update = true; 60221345Sdim Reserved = RR; 61221345Sdim 62221345Sdim // Invalidate cached information from previous function. 63221345Sdim if (Update) 64221345Sdim ++Tag; 65221345Sdim} 66221345Sdim 67221345Sdim/// compute - Compute the preferred allocation order for RC with reserved 68223017Sdim/// registers filtered out. Volatile registers come first followed by CSR 69263508Sdim/// aliases ordered according to the CSR order specified by the target. 70223017Sdimvoid RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 71223017Sdim RCInfo &RCI = RegClass[RC->getID()]; 72221345Sdim 73223017Sdim // Raw register count, including all reserved regs. 74223017Sdim unsigned NumRegs = RC->getNumRegs(); 75223017Sdim 76221345Sdim if (!RCI.Order) 77221345Sdim RCI.Order.reset(new unsigned[NumRegs]); 78202878Srdivacky 79202878Srdivacky unsigned N = 0; 80202878Srdivacky SmallVector<unsigned, 16> CSRAlias; 81202878Srdivacky 82202878Srdivacky // FIXME: Once targets reserve registers instead of removing them from the 83263508Sdim // allocation order, we can simply use begin/end here. 84263508Sdim ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF); 85263508Sdim for (unsigned i = 0; i != RawOrder.size(); ++i) { 86263508Sdim unsigned PhysReg = RawOrder[i]; 87263508Sdim // Remove reserved registers from the allocation order. 88263508Sdim if (Reserved.test(PhysReg)) 89263508Sdim continue; 90218893Sdim if (CSRNum[PhysReg]) 91218893Sdim // PhysReg aliases a CSR, save it for later. 92218893Sdim CSRAlias.push_back(PhysReg); 93218893Sdim else 94218893Sdim RCI.Order[N++] = PhysReg; 95218893Sdim } 96218893Sdim RCI.NumRegs = N + CSRAlias.size(); 97202878Srdivacky assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 98218893Sdim 99218893Sdim // CSR aliases go after the volatile registers, preserve the target's order. 100218893Sdim std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]); 101218893Sdim 102202878Srdivacky DEBUG({ 103202878Srdivacky dbgs() << "AllocationOrder(" << RC->getName() << ") = ["; 104263508Sdim for (unsigned I = 0; I != RCI.NumRegs; ++I) 105218893Sdim dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); 106218893Sdim dbgs() << " ]\n"; 107218893Sdim }); 108218893Sdim 109263508Sdim // RCI is now up-to-date. 110223017Sdim RCI.Tag = Tag; 111223017Sdim} 112223017Sdim 113223017Sdim