MachineSink.cpp revision 208954
165310Sarchie//===-- MachineSink.cpp - Sinking for machine instructions ----------------===// 265310Sarchie// 365310Sarchie// The LLVM Compiler Infrastructure 465310Sarchie// 565310Sarchie// This file is distributed under the University of Illinois Open Source 665310Sarchie// License. See LICENSE.TXT for details. 765310Sarchie// 865310Sarchie//===----------------------------------------------------------------------===// 965310Sarchie// 1065310Sarchie// This pass moves instructions into successor blocks, when possible, so that 1165310Sarchie// they aren't executed on paths where their results aren't needed. 1265310Sarchie// 1365310Sarchie// This pass is not intended to be a replacement or a complete alternative 1465310Sarchie// for an LLVM-IR-level sinking pass. It is only designed to sink simple 1565310Sarchie// constructs that are not exposed before lowering and instruction selection. 1665310Sarchie// 1765310Sarchie//===----------------------------------------------------------------------===// 1865310Sarchie 1965310Sarchie#define DEBUG_TYPE "machine-sink" 2065310Sarchie#include "llvm/CodeGen/Passes.h" 2165310Sarchie#include "llvm/CodeGen/MachineRegisterInfo.h" 2265310Sarchie#include "llvm/CodeGen/MachineDominators.h" 2365310Sarchie#include "llvm/CodeGen/MachineLoopInfo.h" 2465310Sarchie#include "llvm/Analysis/AliasAnalysis.h" 2565310Sarchie#include "llvm/Target/TargetRegisterInfo.h" 2665310Sarchie#include "llvm/Target/TargetInstrInfo.h" 2765310Sarchie#include "llvm/Target/TargetMachine.h" 2865310Sarchie#include "llvm/ADT/Statistic.h" 2965310Sarchie#include "llvm/Support/Debug.h" 3065310Sarchie#include "llvm/Support/raw_ostream.h" 3165310Sarchieusing namespace llvm; 3265310Sarchie 3365310SarchieSTATISTIC(NumSunk, "Number of machine instructions sunk"); 3465310Sarchie 3565310Sarchienamespace { 3665310Sarchie class MachineSinking : public MachineFunctionPass { 3765310Sarchie const TargetInstrInfo *TII; 3865310Sarchie const TargetRegisterInfo *TRI; 3965310Sarchie MachineRegisterInfo *RegInfo; // Machine register information 4065310Sarchie MachineDominatorTree *DT; // Machine dominator tree 4165310Sarchie MachineLoopInfo *LI; 4265310Sarchie AliasAnalysis *AA; 4365310Sarchie BitVector AllocatableSet; // Which physregs are allocatable? 4465310Sarchie 4565310Sarchie public: 4665310Sarchie static char ID; // Pass identification 4765310Sarchie MachineSinking() : MachineFunctionPass(&ID) {} 4865310Sarchie 4965310Sarchie virtual bool runOnMachineFunction(MachineFunction &MF); 5065310Sarchie 5165310Sarchie virtual void getAnalysisUsage(AnalysisUsage &AU) const { 5265310Sarchie AU.setPreservesCFG(); 5365310Sarchie MachineFunctionPass::getAnalysisUsage(AU); 5465310Sarchie AU.addRequired<AliasAnalysis>(); 5565310Sarchie AU.addRequired<MachineDominatorTree>(); 5665310Sarchie AU.addRequired<MachineLoopInfo>(); 5765310Sarchie AU.addPreserved<MachineDominatorTree>(); 5865310Sarchie AU.addPreserved<MachineLoopInfo>(); 5965310Sarchie } 6065310Sarchie private: 6165310Sarchie bool ProcessBlock(MachineBasicBlock &MBB); 6265310Sarchie bool SinkInstruction(MachineInstr *MI, bool &SawStore); 6365310Sarchie bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const; 6465310Sarchie }; 6565310Sarchie} // end anonymous namespace 6665310Sarchie 6765310Sarchiechar MachineSinking::ID = 0; 6865310Sarchiestatic RegisterPass<MachineSinking> 6965310SarchieX("machine-sink", "Machine code sinking"); 7065310Sarchie 7165310SarchieFunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); } 7265310Sarchie 7365310Sarchie/// AllUsesDominatedByBlock - Return true if all uses of the specified register 7465310Sarchie/// occur in blocks dominated by the specified block. 7565310Sarchiebool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, 7665310Sarchie MachineBasicBlock *MBB) const { 7765310Sarchie assert(TargetRegisterInfo::isVirtualRegister(Reg) && 7865310Sarchie "Only makes sense for vregs"); 7965310Sarchie // Ignoring debug uses is necessary so debug info doesn't affect the code. 8065310Sarchie // This may leave a referencing dbg_value in the original block, before 8165310Sarchie // the definition of the vreg. Dwarf generator handles this although the 8270870Sjulian // user might not get the right info at runtime. 8370870Sjulian for (MachineRegisterInfo::use_nodbg_iterator I = 8470870Sjulian RegInfo->use_nodbg_begin(Reg), 8570870Sjulian E = RegInfo->use_nodbg_end(); I != E; ++I) { 8670870Sjulian // Determine the block of the use. 8770870Sjulian MachineInstr *UseInst = &*I; 8865310Sarchie MachineBasicBlock *UseBlock = UseInst->getParent(); 8965310Sarchie if (UseInst->isPHI()) { 9065310Sarchie // PHI nodes use the operand in the predecessor block, not the block with 9165310Sarchie // the PHI. 9265310Sarchie UseBlock = UseInst->getOperand(I.getOperandNo()+1).getMBB(); 9365310Sarchie } 9465310Sarchie // Check that it dominates. 9565310Sarchie if (!DT->dominates(MBB, UseBlock)) 9665310Sarchie return false; 9765310Sarchie } 9865310Sarchie return true; 9965310Sarchie} 10065310Sarchie 10165310Sarchiebool MachineSinking::runOnMachineFunction(MachineFunction &MF) { 10265310Sarchie DEBUG(dbgs() << "******** Machine Sinking ********\n"); 10365310Sarchie 10465310Sarchie const TargetMachine &TM = MF.getTarget(); 10565310Sarchie TII = TM.getInstrInfo(); 10665310Sarchie TRI = TM.getRegisterInfo(); 10765310Sarchie RegInfo = &MF.getRegInfo(); 10865310Sarchie DT = &getAnalysis<MachineDominatorTree>(); 10965310Sarchie LI = &getAnalysis<MachineLoopInfo>(); 11065310Sarchie AA = &getAnalysis<AliasAnalysis>(); 11165310Sarchie AllocatableSet = TRI->getAllocatableSet(MF); 11265310Sarchie 11365310Sarchie bool EverMadeChange = false; 11465310Sarchie 11565310Sarchie while (1) { 11665310Sarchie bool MadeChange = false; 11765310Sarchie 11865310Sarchie // Process all basic blocks. 11965310Sarchie for (MachineFunction::iterator I = MF.begin(), E = MF.end(); 12065310Sarchie I != E; ++I) 12170700Sjulian MadeChange |= ProcessBlock(*I); 12265310Sarchie 12365310Sarchie // If this iteration over the code changed anything, keep iterating. 12465310Sarchie if (!MadeChange) break; 12565310Sarchie EverMadeChange = true; 12665310Sarchie } 12765310Sarchie return EverMadeChange; 12865310Sarchie} 12965310Sarchie 13065310Sarchiebool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) { 13165310Sarchie // Can't sink anything out of a block that has less than two successors. 13265310Sarchie if (MBB.succ_size() <= 1 || MBB.empty()) return false; 13365310Sarchie 13465310Sarchie // Don't bother sinking code out of unreachable blocks. In addition to being 13565310Sarchie // unprofitable, it can also lead to infinite looping, because in an unreachable 13665310Sarchie // loop there may be nowhere to stop. 13765310Sarchie if (!DT->isReachableFromEntry(&MBB)) return false; 13865310Sarchie 13965310Sarchie bool MadeChange = false; 14065310Sarchie 14165310Sarchie // Walk the basic block bottom-up. Remember if we saw a store. 14265310Sarchie MachineBasicBlock::iterator I = MBB.end(); 14365310Sarchie --I; 14465310Sarchie bool ProcessedBegin, SawStore = false; 14565310Sarchie do { 14665310Sarchie MachineInstr *MI = I; // The instruction to sink. 14765310Sarchie 14865310Sarchie // Predecrement I (if it's not begin) so that it isn't invalidated by 14965310Sarchie // sinking. 15065310Sarchie ProcessedBegin = I == MBB.begin(); 15165310Sarchie if (!ProcessedBegin) 15265310Sarchie --I; 15365310Sarchie 15465310Sarchie if (MI->isDebugValue()) 15565310Sarchie continue; 15665310Sarchie 15765310Sarchie if (SinkInstruction(MI, SawStore)) 15865310Sarchie ++NumSunk, MadeChange = true; 15965310Sarchie 16065310Sarchie // If we just processed the first instruction in the block, we're done. 16165310Sarchie } while (!ProcessedBegin); 16265310Sarchie 16365310Sarchie return MadeChange; 16465310Sarchie} 16565310Sarchie 16665310Sarchie/// SinkInstruction - Determine whether it is safe to sink the specified machine 16765310Sarchie/// instruction out of its current block into a successor. 16865310Sarchiebool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { 16965310Sarchie // Check if it's safe to move the instruction. 17065310Sarchie if (!MI->isSafeToMove(TII, AA, SawStore)) 17165310Sarchie return false; 17265310Sarchie 17365310Sarchie // FIXME: This should include support for sinking instructions within the 17497685Sarchie // block they are currently in to shorten the live ranges. We often get 17565310Sarchie // instructions sunk into the top of a large block, but it would be better to 17665310Sarchie // also sink them down before their first use in the block. This xform has to 17765310Sarchie // be careful not to *increase* register pressure though, e.g. sinking 17897685Sarchie // "x = y + z" down if it kills y and z would increase the live ranges of y 17965310Sarchie // and z and only shrink the live range of x. 18065310Sarchie 18165310Sarchie // Loop over all the operands of the specified instruction. If there is 18265310Sarchie // anything we can't handle, bail out. 18365310Sarchie MachineBasicBlock *ParentBlock = MI->getParent(); 18465310Sarchie 18565310Sarchie // SuccToSinkTo - This is the successor to sink this instruction to, once we 18665310Sarchie // decide. 18765310Sarchie MachineBasicBlock *SuccToSinkTo = 0; 18897685Sarchie 18965310Sarchie for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 19065310Sarchie const MachineOperand &MO = MI->getOperand(i); 19165310Sarchie if (!MO.isReg()) continue; // Ignore non-register operands. 19297685Sarchie 19365310Sarchie unsigned Reg = MO.getReg(); 19465310Sarchie if (Reg == 0) continue; 19565310Sarchie 19665310Sarchie if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 19765310Sarchie if (MO.isUse()) { 19865310Sarchie // If the physreg has no defs anywhere, it's just an ambient register 19965310Sarchie // and we can freely move its uses. Alternatively, if it's allocatable, 20065310Sarchie // it could get allocated to something with a def during allocation. 20165310Sarchie if (!RegInfo->def_empty(Reg)) 20265310Sarchie return false; 20365310Sarchie if (AllocatableSet.test(Reg)) 20497685Sarchie return false; 20565310Sarchie // Check for a def among the register's aliases too. 20665310Sarchie for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 20765310Sarchie unsigned AliasReg = *Alias; 20897685Sarchie if (!RegInfo->def_empty(AliasReg)) 20965310Sarchie return false; 21065310Sarchie if (AllocatableSet.test(AliasReg)) 21165310Sarchie return false; 21297685Sarchie } 21397685Sarchie } else if (!MO.isDead()) { 21465310Sarchie // A def that isn't dead. We can't move it. 21565310Sarchie return false; 21697685Sarchie } 21765310Sarchie } else { 21865310Sarchie // Virtual register uses are always safe to sink. 21965310Sarchie if (MO.isUse()) continue; 22065310Sarchie 22165310Sarchie // If it's not safe to move defs of the register class, then abort. 22265310Sarchie if (!TII->isSafeToMoveRegClassDefs(RegInfo->getRegClass(Reg))) 22365310Sarchie return false; 22465310Sarchie 22565310Sarchie // FIXME: This picks a successor to sink into based on having one 22665310Sarchie // successor that dominates all the uses. However, there are cases where 22765310Sarchie // sinking can happen but where the sink point isn't a successor. For 22865310Sarchie // example: 22965310Sarchie // x = computation 23065310Sarchie // if () {} else {} 23165310Sarchie // use x 23265310Sarchie // the instruction could be sunk over the whole diamond for the 23365310Sarchie // if/then/else (or loop, etc), allowing it to be sunk into other blocks 23465310Sarchie // after that. 23565310Sarchie 23665310Sarchie // Virtual register defs can only be sunk if all their uses are in blocks 23765310Sarchie // dominated by one of the successors. 23865310Sarchie if (SuccToSinkTo) { 23965310Sarchie // If a previous operand picked a block to sink to, then this operand 24065310Sarchie // must be sinkable to the same block. 24165310Sarchie if (!AllUsesDominatedByBlock(Reg, SuccToSinkTo)) 24265310Sarchie return false; 24365310Sarchie continue; 24465310Sarchie } 24565310Sarchie 24665310Sarchie // Otherwise, we should look at all the successors and decide which one 24765310Sarchie // we should sink to. 24865310Sarchie for (MachineBasicBlock::succ_iterator SI = ParentBlock->succ_begin(), 24965310Sarchie E = ParentBlock->succ_end(); SI != E; ++SI) { 25065310Sarchie if (AllUsesDominatedByBlock(Reg, *SI)) { 25165310Sarchie SuccToSinkTo = *SI; 25265310Sarchie break; 25365310Sarchie } 25465310Sarchie } 25565310Sarchie 25665310Sarchie // If we couldn't find a block to sink to, ignore this instruction. 25765310Sarchie if (SuccToSinkTo == 0) 25865310Sarchie return false; 25965310Sarchie } 26065310Sarchie } 26165310Sarchie 26265310Sarchie // If there are no outputs, it must have side-effects. 26365310Sarchie if (SuccToSinkTo == 0) 26465310Sarchie return false; 26565310Sarchie 26665310Sarchie // It's not safe to sink instructions to EH landing pad. Control flow into 26765310Sarchie // landing pad is implicitly defined. 26865310Sarchie if (SuccToSinkTo->isLandingPad()) 26965310Sarchie return false; 27065310Sarchie 27165310Sarchie // It is not possible to sink an instruction into its own block. This can 27265310Sarchie // happen with loops. 27365310Sarchie if (MI->getParent() == SuccToSinkTo) 27465310Sarchie return false; 27570159Sjulian 27665310Sarchie DEBUG(dbgs() << "Sink instr " << *MI); 27765310Sarchie DEBUG(dbgs() << "to block " << *SuccToSinkTo); 27865310Sarchie 27965310Sarchie // If the block has multiple predecessors, this would introduce computation on 28070700Sjulian // a path that it doesn't already exist. We could split the critical edge, 28165310Sarchie // but for now we just punt. 28265310Sarchie // FIXME: Split critical edges if not backedges. 28365310Sarchie if (SuccToSinkTo->pred_size() > 1) { 28465310Sarchie // We cannot sink a load across a critical edge - there may be stores in 28565310Sarchie // other code paths. 28665310Sarchie bool store = true; 28765310Sarchie if (!MI->isSafeToMove(TII, AA, store)) { 28866887Sarchie DEBUG(dbgs() << " *** PUNTING: Wont sink load along critical edge.\n"); 28965310Sarchie return false; 29065310Sarchie } 29165310Sarchie 29265310Sarchie // We don't want to sink across a critical edge if we don't dominate the 29365310Sarchie // successor. We could be introducing calculations to new code paths. 29465310Sarchie if (!DT->dominates(ParentBlock, SuccToSinkTo)) { 29565310Sarchie DEBUG(dbgs() << " *** PUNTING: Critical edge found\n"); 29665310Sarchie return false; 29765310Sarchie } 29865310Sarchie 29965310Sarchie // Don't sink instructions into a loop. 30065310Sarchie if (LI->isLoopHeader(SuccToSinkTo)) { 30170700Sjulian DEBUG(dbgs() << " *** PUNTING: Loop header found\n"); 30265310Sarchie return false; 30365310Sarchie } 30465310Sarchie 30565310Sarchie // Otherwise we are OK with sinking along a critical edge. 30670870Sjulian DEBUG(dbgs() << "Sinking along critical edge.\n"); 30765310Sarchie } 30865310Sarchie 30969225Sjlemon // Determine where to insert into. Skip phi nodes. 31065310Sarchie MachineBasicBlock::iterator InsertPos = SuccToSinkTo->begin(); 31165310Sarchie while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI()) 31265310Sarchie ++InsertPos; 31370870Sjulian 31465310Sarchie // Move the instruction. 31570870Sjulian SuccToSinkTo->splice(InsertPos, ParentBlock, MI, 31665310Sarchie ++MachineBasicBlock::iterator(MI)); 31765310Sarchie 31865310Sarchie // Conservatively, clear any kill flags, since it's possible that 31965310Sarchie // they are no longer correct. 32065310Sarchie MI->clearKillInfo(); 32165310Sarchie 32265310Sarchie return true; 32365310Sarchie} 32465310Sarchie