longlong.h revision 161651
1/* longlong.h -- definitions for mixed size 32/64 bit arithmetic. 2 Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2005 Free Software Foundation, Inc. 4 5 This definition file is free software; you can redistribute it 6 and/or modify it under the terms of the GNU General Public 7 License as published by the Free Software Foundation; either 8 version 2, or (at your option) any later version. 9 10 This definition file is distributed in the hope that it will be 11 useful, but WITHOUT ANY WARRANTY; without even the implied 12 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 13 See the GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place - Suite 330, 18 Boston, MA 02111-1307, USA. */ 19 20/* You have to define the following before including this file: 21 22 UWtype -- An unsigned type, default type for operations (typically a "word") 23 UHWtype -- An unsigned type, at least half the size of UWtype. 24 UDWtype -- An unsigned type, at least twice as large a UWtype 25 W_TYPE_SIZE -- size in bits of UWtype 26 27 UQItype -- Unsigned 8 bit type. 28 SItype, USItype -- Signed and unsigned 32 bit types. 29 DItype, UDItype -- Signed and unsigned 64 bit types. 30 31 On a 32 bit machine UWtype should typically be USItype; 32 on a 64 bit machine, UWtype should typically be UDItype. 33*/ 34 35#define __BITS4 (W_TYPE_SIZE / 4) 36#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) 37#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) 38#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2)) 39 40#ifndef W_TYPE_SIZE 41#define W_TYPE_SIZE 32 42#define UWtype USItype 43#define UHWtype USItype 44#define UDWtype UDItype 45#endif 46 47/* Define auxiliary asm macros. 48 49 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two 50 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype 51 word product in HIGH_PROD and LOW_PROD. 52 53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a 54 UDWtype product. This is just a variant of umul_ppmm. 55 56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 57 denominator) divides a UDWtype, composed by the UWtype integers 58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient 59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less 60 than DENOMINATOR for correct operation. If, in addition, the most 61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol 62 UDIV_NEEDS_NORMALIZATION is defined to 1. 63 64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient 66 is rounded towards 0. 67 68 5) count_leading_zeros(count, x) counts the number of zero-bits from the 69 msb to the first nonzero bit in the UWtype X. This is the number of 70 steps X needs to be shifted left to set the msb. Undefined for X == 0, 71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value. 72 73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts 74 from the least significant end. 75 76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, 77 high_addend_2, low_addend_2) adds two UWtype integers, composed by 78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2 79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow 80 (i.e. carry out) is not stored anywhere, and is lost. 81 82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend, 83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers, 84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and 85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE 86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, 87 and is lost. 88 89 If any of these macros are left undefined for a particular CPU, 90 C macros are used. */ 91 92/* The CPUs come in alphabetical order below. 93 94 Please add support for more CPUs here, or improve the current support 95 for the CPUs below! 96 (E.g. WE32100, IBM360.) */ 97 98#if defined (__GNUC__) && !defined (NO_ASM) 99 100/* We sometimes need to clobber "cc" with gcc2, but that would not be 101 understood by gcc1. Use cpp to avoid major code duplication. */ 102#if __GNUC__ < 2 103#define __CLOBBER_CC 104#define __AND_CLOBBER_CC 105#else /* __GNUC__ >= 2 */ 106#define __CLOBBER_CC : "cc" 107#define __AND_CLOBBER_CC , "cc" 108#endif /* __GNUC__ < 2 */ 109 110#if defined (__alpha) && W_TYPE_SIZE == 64 111#define umul_ppmm(ph, pl, m0, m1) \ 112 do { \ 113 UDItype __m0 = (m0), __m1 = (m1); \ 114 (ph) = __builtin_alpha_umulh (__m0, __m1); \ 115 (pl) = __m0 * __m1; \ 116 } while (0) 117#define UMUL_TIME 46 118#ifndef LONGLONG_STANDALONE 119#define udiv_qrnnd(q, r, n1, n0, d) \ 120 do { UDItype __r; \ 121 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \ 122 (r) = __r; \ 123 } while (0) 124extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype); 125#define UDIV_TIME 220 126#endif /* LONGLONG_STANDALONE */ 127#ifdef __alpha_cix__ 128#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X)) 129#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X)) 130#define COUNT_LEADING_ZEROS_0 64 131#else 132extern const UQItype __clz_tab[] ATTRIBUTE_HIDDEN; 133#define count_leading_zeros(COUNT,X) \ 134 do { \ 135 UDItype __xr = (X), __t, __a; \ 136 __t = __builtin_alpha_cmpbge (0, __xr); \ 137 __a = __clz_tab[__t ^ 0xff] - 1; \ 138 __t = __builtin_alpha_extbl (__xr, __a); \ 139 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \ 140 } while (0) 141#define count_trailing_zeros(COUNT,X) \ 142 do { \ 143 UDItype __xr = (X), __t, __a; \ 144 __t = __builtin_alpha_cmpbge (0, __xr); \ 145 __t = ~__t & -~__t; \ 146 __a = ((__t & 0xCC) != 0) * 2; \ 147 __a += ((__t & 0xF0) != 0) * 4; \ 148 __a += ((__t & 0xAA) != 0); \ 149 __t = __builtin_alpha_extbl (__xr, __a); \ 150 __a <<= 3; \ 151 __t &= -__t; \ 152 __a += ((__t & 0xCC) != 0) * 2; \ 153 __a += ((__t & 0xF0) != 0) * 4; \ 154 __a += ((__t & 0xAA) != 0); \ 155 (COUNT) = __a; \ 156 } while (0) 157#endif /* __alpha_cix__ */ 158#endif /* __alpha */ 159 160#if defined (__arc__) && W_TYPE_SIZE == 32 161#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 162 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \ 163 : "=r" ((USItype) (sh)), \ 164 "=&r" ((USItype) (sl)) \ 165 : "%r" ((USItype) (ah)), \ 166 "rIJ" ((USItype) (bh)), \ 167 "%r" ((USItype) (al)), \ 168 "rIJ" ((USItype) (bl))) 169#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 170 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \ 171 : "=r" ((USItype) (sh)), \ 172 "=&r" ((USItype) (sl)) \ 173 : "r" ((USItype) (ah)), \ 174 "rIJ" ((USItype) (bh)), \ 175 "r" ((USItype) (al)), \ 176 "rIJ" ((USItype) (bl))) 177/* Call libgcc routine. */ 178#define umul_ppmm(w1, w0, u, v) \ 179do { \ 180 DWunion __w; \ 181 __w.ll = __umulsidi3 (u, v); \ 182 w1 = __w.s.high; \ 183 w0 = __w.s.low; \ 184} while (0) 185#define __umulsidi3 __umulsidi3 186UDItype __umulsidi3 (USItype, USItype); 187#endif 188 189#if defined (__arm__) && W_TYPE_SIZE == 32 190#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 191 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \ 192 : "=r" ((USItype) (sh)), \ 193 "=&r" ((USItype) (sl)) \ 194 : "%r" ((USItype) (ah)), \ 195 "rI" ((USItype) (bh)), \ 196 "%r" ((USItype) (al)), \ 197 "rI" ((USItype) (bl))) 198#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 199 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \ 200 : "=r" ((USItype) (sh)), \ 201 "=&r" ((USItype) (sl)) \ 202 : "r" ((USItype) (ah)), \ 203 "rI" ((USItype) (bh)), \ 204 "r" ((USItype) (al)), \ 205 "rI" ((USItype) (bl))) 206#define umul_ppmm(xh, xl, a, b) \ 207{register USItype __t0, __t1, __t2; \ 208 __asm__ ("%@ Inlined umul_ppmm\n" \ 209 " mov %2, %5, lsr #16\n" \ 210 " mov %0, %6, lsr #16\n" \ 211 " bic %3, %5, %2, lsl #16\n" \ 212 " bic %4, %6, %0, lsl #16\n" \ 213 " mul %1, %3, %4\n" \ 214 " mul %4, %2, %4\n" \ 215 " mul %3, %0, %3\n" \ 216 " mul %0, %2, %0\n" \ 217 " adds %3, %4, %3\n" \ 218 " addcs %0, %0, #65536\n" \ 219 " adds %1, %1, %3, lsl #16\n" \ 220 " adc %0, %0, %3, lsr #16" \ 221 : "=&r" ((USItype) (xh)), \ 222 "=r" ((USItype) (xl)), \ 223 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ 224 : "r" ((USItype) (a)), \ 225 "r" ((USItype) (b)));} 226#define UMUL_TIME 20 227#define UDIV_TIME 100 228#endif /* __arm__ */ 229 230#if defined (__hppa) && W_TYPE_SIZE == 32 231#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 232 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ 233 : "=r" ((USItype) (sh)), \ 234 "=&r" ((USItype) (sl)) \ 235 : "%rM" ((USItype) (ah)), \ 236 "rM" ((USItype) (bh)), \ 237 "%rM" ((USItype) (al)), \ 238 "rM" ((USItype) (bl))) 239#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 240 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \ 241 : "=r" ((USItype) (sh)), \ 242 "=&r" ((USItype) (sl)) \ 243 : "rM" ((USItype) (ah)), \ 244 "rM" ((USItype) (bh)), \ 245 "rM" ((USItype) (al)), \ 246 "rM" ((USItype) (bl))) 247#if defined (_PA_RISC1_1) 248#define umul_ppmm(w1, w0, u, v) \ 249 do { \ 250 union \ 251 { \ 252 UDItype __f; \ 253 struct {USItype __w1, __w0;} __w1w0; \ 254 } __t; \ 255 __asm__ ("xmpyu %1,%2,%0" \ 256 : "=x" (__t.__f) \ 257 : "x" ((USItype) (u)), \ 258 "x" ((USItype) (v))); \ 259 (w1) = __t.__w1w0.__w1; \ 260 (w0) = __t.__w1w0.__w0; \ 261 } while (0) 262#define UMUL_TIME 8 263#else 264#define UMUL_TIME 30 265#endif 266#define UDIV_TIME 40 267#define count_leading_zeros(count, x) \ 268 do { \ 269 USItype __tmp; \ 270 __asm__ ( \ 271 "ldi 1,%0\n" \ 272" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \ 273" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\ 274" ldo 16(%0),%0 ; Yes. Perform add.\n" \ 275" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \ 276" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\ 277" ldo 8(%0),%0 ; Yes. Perform add.\n" \ 278" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \ 279" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\ 280" ldo 4(%0),%0 ; Yes. Perform add.\n" \ 281" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \ 282" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\ 283" ldo 2(%0),%0 ; Yes. Perform add.\n" \ 284" extru %1,30,1,%1 ; Extract bit 1.\n" \ 285" sub %0,%1,%0 ; Subtract it.\n" \ 286 : "=r" (count), "=r" (__tmp) : "1" (x)); \ 287 } while (0) 288#endif 289 290#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32 291#define smul_ppmm(xh, xl, m0, m1) \ 292 do { \ 293 union {DItype __ll; \ 294 struct {USItype __h, __l;} __i; \ 295 } __x; \ 296 __asm__ ("lr %N0,%1\n\tmr %0,%2" \ 297 : "=&r" (__x.__ll) \ 298 : "r" (m0), "r" (m1)); \ 299 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \ 300 } while (0) 301#define sdiv_qrnnd(q, r, n1, n0, d) \ 302 do { \ 303 union {DItype __ll; \ 304 struct {USItype __h, __l;} __i; \ 305 } __x; \ 306 __x.__i.__h = n1; __x.__i.__l = n0; \ 307 __asm__ ("dr %0,%2" \ 308 : "=r" (__x.__ll) \ 309 : "0" (__x.__ll), "r" (d)); \ 310 (q) = __x.__i.__l; (r) = __x.__i.__h; \ 311 } while (0) 312#endif 313 314#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 315#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 316 __asm__ ("addl %5,%1\n\tadcl %3,%0" \ 317 : "=r" ((USItype) (sh)), \ 318 "=&r" ((USItype) (sl)) \ 319 : "%0" ((USItype) (ah)), \ 320 "g" ((USItype) (bh)), \ 321 "%1" ((USItype) (al)), \ 322 "g" ((USItype) (bl))) 323#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 324 __asm__ ("subl %5,%1\n\tsbbl %3,%0" \ 325 : "=r" ((USItype) (sh)), \ 326 "=&r" ((USItype) (sl)) \ 327 : "0" ((USItype) (ah)), \ 328 "g" ((USItype) (bh)), \ 329 "1" ((USItype) (al)), \ 330 "g" ((USItype) (bl))) 331#define umul_ppmm(w1, w0, u, v) \ 332 __asm__ ("mull %3" \ 333 : "=a" ((USItype) (w0)), \ 334 "=d" ((USItype) (w1)) \ 335 : "%0" ((USItype) (u)), \ 336 "rm" ((USItype) (v))) 337#define udiv_qrnnd(q, r, n1, n0, dv) \ 338 __asm__ ("divl %4" \ 339 : "=a" ((USItype) (q)), \ 340 "=d" ((USItype) (r)) \ 341 : "0" ((USItype) (n0)), \ 342 "1" ((USItype) (n1)), \ 343 "rm" ((USItype) (dv))) 344#define count_leading_zeros(count, x) \ 345 do { \ 346 USItype __cbtmp; \ 347 __asm__ ("bsrl %1,%0" \ 348 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \ 349 (count) = __cbtmp ^ 31; \ 350 } while (0) 351#define count_trailing_zeros(count, x) \ 352 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x))) 353#define UMUL_TIME 40 354#define UDIV_TIME 40 355#endif /* 80x86 */ 356 357#if defined (__i960__) && W_TYPE_SIZE == 32 358#define umul_ppmm(w1, w0, u, v) \ 359 ({union {UDItype __ll; \ 360 struct {USItype __l, __h;} __i; \ 361 } __xx; \ 362 __asm__ ("emul %2,%1,%0" \ 363 : "=d" (__xx.__ll) \ 364 : "%dI" ((USItype) (u)), \ 365 "dI" ((USItype) (v))); \ 366 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 367#define __umulsidi3(u, v) \ 368 ({UDItype __w; \ 369 __asm__ ("emul %2,%1,%0" \ 370 : "=d" (__w) \ 371 : "%dI" ((USItype) (u)), \ 372 "dI" ((USItype) (v))); \ 373 __w; }) 374#endif /* __i960__ */ 375 376#if defined (__M32R__) && W_TYPE_SIZE == 32 377#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 378 /* The cmp clears the condition bit. */ \ 379 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \ 380 : "=r" ((USItype) (sh)), \ 381 "=&r" ((USItype) (sl)) \ 382 : "0" ((USItype) (ah)), \ 383 "r" ((USItype) (bh)), \ 384 "1" ((USItype) (al)), \ 385 "r" ((USItype) (bl)) \ 386 : "cbit") 387#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 388 /* The cmp clears the condition bit. */ \ 389 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \ 390 : "=r" ((USItype) (sh)), \ 391 "=&r" ((USItype) (sl)) \ 392 : "0" ((USItype) (ah)), \ 393 "r" ((USItype) (bh)), \ 394 "1" ((USItype) (al)), \ 395 "r" ((USItype) (bl)) \ 396 : "cbit") 397#endif /* __M32R__ */ 398 399#if defined (__mc68000__) && W_TYPE_SIZE == 32 400#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 401 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \ 402 : "=d" ((USItype) (sh)), \ 403 "=&d" ((USItype) (sl)) \ 404 : "%0" ((USItype) (ah)), \ 405 "d" ((USItype) (bh)), \ 406 "%1" ((USItype) (al)), \ 407 "g" ((USItype) (bl))) 408#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 409 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \ 410 : "=d" ((USItype) (sh)), \ 411 "=&d" ((USItype) (sl)) \ 412 : "0" ((USItype) (ah)), \ 413 "d" ((USItype) (bh)), \ 414 "1" ((USItype) (al)), \ 415 "g" ((USItype) (bl))) 416 417/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */ 418#if defined (__mc68020__) || defined(mc68020) \ 419 || defined(__mc68030__) || defined(mc68030) \ 420 || defined(__mc68040__) || defined(mc68040) \ 421 || defined(__mcpu32__) || defined(mcpu32) 422#define umul_ppmm(w1, w0, u, v) \ 423 __asm__ ("mulu%.l %3,%1:%0" \ 424 : "=d" ((USItype) (w0)), \ 425 "=d" ((USItype) (w1)) \ 426 : "%0" ((USItype) (u)), \ 427 "dmi" ((USItype) (v))) 428#define UMUL_TIME 45 429#define udiv_qrnnd(q, r, n1, n0, d) \ 430 __asm__ ("divu%.l %4,%1:%0" \ 431 : "=d" ((USItype) (q)), \ 432 "=d" ((USItype) (r)) \ 433 : "0" ((USItype) (n0)), \ 434 "1" ((USItype) (n1)), \ 435 "dmi" ((USItype) (d))) 436#define UDIV_TIME 90 437#define sdiv_qrnnd(q, r, n1, n0, d) \ 438 __asm__ ("divs%.l %4,%1:%0" \ 439 : "=d" ((USItype) (q)), \ 440 "=d" ((USItype) (r)) \ 441 : "0" ((USItype) (n0)), \ 442 "1" ((USItype) (n1)), \ 443 "dmi" ((USItype) (d))) 444 445#else /* not mc68020 */ 446#if defined(__mcoldfire__) 447#define umul_ppmm(xh, xl, a, b) \ 448 __asm__ ("| Inlined umul_ppmm\n" \ 449 " move%.l %2,%/d0\n" \ 450 " move%.l %3,%/d1\n" \ 451 " move%.l %/d0,%/d2\n" \ 452 " swap %/d0\n" \ 453 " move%.l %/d1,%/d3\n" \ 454 " swap %/d1\n" \ 455 " move%.w %/d2,%/d4\n" \ 456 " mulu %/d3,%/d4\n" \ 457 " mulu %/d1,%/d2\n" \ 458 " mulu %/d0,%/d3\n" \ 459 " mulu %/d0,%/d1\n" \ 460 " move%.l %/d4,%/d0\n" \ 461 " clr%.w %/d0\n" \ 462 " swap %/d0\n" \ 463 " add%.l %/d0,%/d2\n" \ 464 " add%.l %/d3,%/d2\n" \ 465 " jcc 1f\n" \ 466 " add%.l %#65536,%/d1\n" \ 467 "1: swap %/d2\n" \ 468 " moveq %#0,%/d0\n" \ 469 " move%.w %/d2,%/d0\n" \ 470 " move%.w %/d4,%/d2\n" \ 471 " move%.l %/d2,%1\n" \ 472 " add%.l %/d1,%/d0\n" \ 473 " move%.l %/d0,%0" \ 474 : "=g" ((USItype) (xh)), \ 475 "=g" ((USItype) (xl)) \ 476 : "g" ((USItype) (a)), \ 477 "g" ((USItype) (b)) \ 478 : "d0", "d1", "d2", "d3", "d4") 479#define UMUL_TIME 100 480#define UDIV_TIME 400 481#else /* not ColdFire */ 482/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */ 483#define umul_ppmm(xh, xl, a, b) \ 484 __asm__ ("| Inlined umul_ppmm\n" \ 485 " move%.l %2,%/d0\n" \ 486 " move%.l %3,%/d1\n" \ 487 " move%.l %/d0,%/d2\n" \ 488 " swap %/d0\n" \ 489 " move%.l %/d1,%/d3\n" \ 490 " swap %/d1\n" \ 491 " move%.w %/d2,%/d4\n" \ 492 " mulu %/d3,%/d4\n" \ 493 " mulu %/d1,%/d2\n" \ 494 " mulu %/d0,%/d3\n" \ 495 " mulu %/d0,%/d1\n" \ 496 " move%.l %/d4,%/d0\n" \ 497 " eor%.w %/d0,%/d0\n" \ 498 " swap %/d0\n" \ 499 " add%.l %/d0,%/d2\n" \ 500 " add%.l %/d3,%/d2\n" \ 501 " jcc 1f\n" \ 502 " add%.l %#65536,%/d1\n" \ 503 "1: swap %/d2\n" \ 504 " moveq %#0,%/d0\n" \ 505 " move%.w %/d2,%/d0\n" \ 506 " move%.w %/d4,%/d2\n" \ 507 " move%.l %/d2,%1\n" \ 508 " add%.l %/d1,%/d0\n" \ 509 " move%.l %/d0,%0" \ 510 : "=g" ((USItype) (xh)), \ 511 "=g" ((USItype) (xl)) \ 512 : "g" ((USItype) (a)), \ 513 "g" ((USItype) (b)) \ 514 : "d0", "d1", "d2", "d3", "d4") 515#define UMUL_TIME 100 516#define UDIV_TIME 400 517#endif /* not ColdFire */ 518#endif /* not mc68020 */ 519 520/* The '020, '030, '040 and '060 have bitfield insns. 521 cpu32 disguises as a 68020, but lacks them. */ 522#if ( defined (__mc68020__) || defined(mc68020) \ 523 || defined(__mc68030__) || defined(mc68030) \ 524 || defined(__mc68040__) || defined(mc68040) \ 525 || defined(__mc68060__) || defined(mc68060) ) \ 526 && !defined(__mcpu32__) 527#define count_leading_zeros(count, x) \ 528 __asm__ ("bfffo %1{%b2:%b2},%0" \ 529 : "=d" ((USItype) (count)) \ 530 : "od" ((USItype) (x)), "n" (0)) 531#endif 532#endif /* mc68000 */ 533 534#if defined (__m88000__) && W_TYPE_SIZE == 32 535#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 536 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \ 537 : "=r" ((USItype) (sh)), \ 538 "=&r" ((USItype) (sl)) \ 539 : "%rJ" ((USItype) (ah)), \ 540 "rJ" ((USItype) (bh)), \ 541 "%rJ" ((USItype) (al)), \ 542 "rJ" ((USItype) (bl))) 543#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 544 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \ 545 : "=r" ((USItype) (sh)), \ 546 "=&r" ((USItype) (sl)) \ 547 : "rJ" ((USItype) (ah)), \ 548 "rJ" ((USItype) (bh)), \ 549 "rJ" ((USItype) (al)), \ 550 "rJ" ((USItype) (bl))) 551#define count_leading_zeros(count, x) \ 552 do { \ 553 USItype __cbtmp; \ 554 __asm__ ("ff1 %0,%1" \ 555 : "=r" (__cbtmp) \ 556 : "r" ((USItype) (x))); \ 557 (count) = __cbtmp ^ 31; \ 558 } while (0) 559#define COUNT_LEADING_ZEROS_0 63 /* sic */ 560#if defined (__mc88110__) 561#define umul_ppmm(wh, wl, u, v) \ 562 do { \ 563 union {UDItype __ll; \ 564 struct {USItype __h, __l;} __i; \ 565 } __xx; \ 566 __asm__ ("mulu.d %0,%1,%2" \ 567 : "=r" (__xx.__ll) \ 568 : "r" ((USItype) (u)), \ 569 "r" ((USItype) (v))); \ 570 (wh) = __xx.__i.__h; \ 571 (wl) = __xx.__i.__l; \ 572 } while (0) 573#define udiv_qrnnd(q, r, n1, n0, d) \ 574 ({union {UDItype __ll; \ 575 struct {USItype __h, __l;} __i; \ 576 } __xx; \ 577 USItype __q; \ 578 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 579 __asm__ ("divu.d %0,%1,%2" \ 580 : "=r" (__q) \ 581 : "r" (__xx.__ll), \ 582 "r" ((USItype) (d))); \ 583 (r) = (n0) - __q * (d); (q) = __q; }) 584#define UMUL_TIME 5 585#define UDIV_TIME 25 586#else 587#define UMUL_TIME 17 588#define UDIV_TIME 150 589#endif /* __mc88110__ */ 590#endif /* __m88000__ */ 591 592#if defined (__mips__) && W_TYPE_SIZE == 32 593#define umul_ppmm(w1, w0, u, v) \ 594 __asm__ ("multu %2,%3" \ 595 : "=l" ((USItype) (w0)), \ 596 "=h" ((USItype) (w1)) \ 597 : "d" ((USItype) (u)), \ 598 "d" ((USItype) (v))) 599#define UMUL_TIME 10 600#define UDIV_TIME 100 601#endif /* __mips__ */ 602 603#if defined (__ns32000__) && W_TYPE_SIZE == 32 604#define umul_ppmm(w1, w0, u, v) \ 605 ({union {UDItype __ll; \ 606 struct {USItype __l, __h;} __i; \ 607 } __xx; \ 608 __asm__ ("meid %2,%0" \ 609 : "=g" (__xx.__ll) \ 610 : "%0" ((USItype) (u)), \ 611 "g" ((USItype) (v))); \ 612 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;}) 613#define __umulsidi3(u, v) \ 614 ({UDItype __w; \ 615 __asm__ ("meid %2,%0" \ 616 : "=g" (__w) \ 617 : "%0" ((USItype) (u)), \ 618 "g" ((USItype) (v))); \ 619 __w; }) 620#define udiv_qrnnd(q, r, n1, n0, d) \ 621 ({union {UDItype __ll; \ 622 struct {USItype __l, __h;} __i; \ 623 } __xx; \ 624 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \ 625 __asm__ ("deid %2,%0" \ 626 : "=g" (__xx.__ll) \ 627 : "0" (__xx.__ll), \ 628 "g" ((USItype) (d))); \ 629 (r) = __xx.__i.__l; (q) = __xx.__i.__h; }) 630#define count_trailing_zeros(count,x) \ 631 do { \ 632 __asm__ ("ffsd %2,%0" \ 633 : "=r" ((USItype) (count)) \ 634 : "0" ((USItype) 0), \ 635 "r" ((USItype) (x))); \ 636 } while (0) 637#endif /* __ns32000__ */ 638 639/* FIXME: We should test _IBMR2 here when we add assembly support for the 640 system vendor compilers. 641 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good 642 enough, since that hits ARM and m68k too. */ 643#if (defined (_ARCH_PPC) /* AIX */ \ 644 || defined (_ARCH_PWR) /* AIX */ \ 645 || defined (_ARCH_COM) /* AIX */ \ 646 || defined (__powerpc__) /* gcc */ \ 647 || defined (__POWERPC__) /* BEOS */ \ 648 || defined (__ppc__) /* Darwin */ \ 649 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ 650 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ 651 && CPU_FAMILY == PPC) \ 652 ) && W_TYPE_SIZE == 32 653#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 654 do { \ 655 if (__builtin_constant_p (bh) && (bh) == 0) \ 656 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 657 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 658 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 659 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 660 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 661 else \ 662 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 663 : "=r" (sh), "=&r" (sl) \ 664 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 665 } while (0) 666#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 667 do { \ 668 if (__builtin_constant_p (ah) && (ah) == 0) \ 669 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 670 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 671 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \ 672 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 673 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 674 else if (__builtin_constant_p (bh) && (bh) == 0) \ 675 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 676 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 677 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \ 678 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 679 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 680 else \ 681 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 682 : "=r" (sh), "=&r" (sl) \ 683 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 684 } while (0) 685#define count_leading_zeros(count, x) \ 686 __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x)) 687#define COUNT_LEADING_ZEROS_0 32 688#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \ 689 || defined (__ppc__) \ 690 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \ 691 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \ 692 && CPU_FAMILY == PPC) 693#define umul_ppmm(ph, pl, m0, m1) \ 694 do { \ 695 USItype __m0 = (m0), __m1 = (m1); \ 696 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 697 (pl) = __m0 * __m1; \ 698 } while (0) 699#define UMUL_TIME 15 700#define smul_ppmm(ph, pl, m0, m1) \ 701 do { \ 702 SItype __m0 = (m0), __m1 = (m1); \ 703 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 704 (pl) = __m0 * __m1; \ 705 } while (0) 706#define SMUL_TIME 14 707#define UDIV_TIME 120 708#elif defined (_ARCH_PWR) 709#define UMUL_TIME 8 710#define smul_ppmm(xh, xl, m0, m1) \ 711 __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1)) 712#define SMUL_TIME 4 713#define sdiv_qrnnd(q, r, nh, nl, d) \ 714 __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d)) 715#define UDIV_TIME 100 716#endif 717#endif /* 32-bit POWER architecture variants. */ 718 719/* We should test _IBMR2 here when we add assembly support for the system 720 vendor compilers. */ 721#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64 722#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 723 do { \ 724 if (__builtin_constant_p (bh) && (bh) == 0) \ 725 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \ 726 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 727 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 728 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \ 729 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\ 730 else \ 731 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \ 732 : "=r" (sh), "=&r" (sl) \ 733 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \ 734 } while (0) 735#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 736 do { \ 737 if (__builtin_constant_p (ah) && (ah) == 0) \ 738 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \ 739 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 740 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \ 741 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \ 742 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\ 743 else if (__builtin_constant_p (bh) && (bh) == 0) \ 744 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \ 745 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 746 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \ 747 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \ 748 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\ 749 else \ 750 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \ 751 : "=r" (sh), "=&r" (sl) \ 752 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \ 753 } while (0) 754#define count_leading_zeros(count, x) \ 755 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x)) 756#define COUNT_LEADING_ZEROS_0 64 757#define umul_ppmm(ph, pl, m0, m1) \ 758 do { \ 759 UDItype __m0 = (m0), __m1 = (m1); \ 760 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 761 (pl) = __m0 * __m1; \ 762 } while (0) 763#define UMUL_TIME 15 764#define smul_ppmm(ph, pl, m0, m1) \ 765 do { \ 766 DItype __m0 = (m0), __m1 = (m1); \ 767 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \ 768 (pl) = __m0 * __m1; \ 769 } while (0) 770#define SMUL_TIME 14 /* ??? */ 771#define UDIV_TIME 120 /* ??? */ 772#endif /* 64-bit PowerPC. */ 773 774#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 775#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 776 __asm__ ("a %1,%5\n\tae %0,%3" \ 777 : "=r" ((USItype) (sh)), \ 778 "=&r" ((USItype) (sl)) \ 779 : "%0" ((USItype) (ah)), \ 780 "r" ((USItype) (bh)), \ 781 "%1" ((USItype) (al)), \ 782 "r" ((USItype) (bl))) 783#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 784 __asm__ ("s %1,%5\n\tse %0,%3" \ 785 : "=r" ((USItype) (sh)), \ 786 "=&r" ((USItype) (sl)) \ 787 : "0" ((USItype) (ah)), \ 788 "r" ((USItype) (bh)), \ 789 "1" ((USItype) (al)), \ 790 "r" ((USItype) (bl))) 791#define umul_ppmm(ph, pl, m0, m1) \ 792 do { \ 793 USItype __m0 = (m0), __m1 = (m1); \ 794 __asm__ ( \ 795 "s r2,r2\n" \ 796" mts r10,%2\n" \ 797" m r2,%3\n" \ 798" m r2,%3\n" \ 799" m r2,%3\n" \ 800" m r2,%3\n" \ 801" m r2,%3\n" \ 802" m r2,%3\n" \ 803" m r2,%3\n" \ 804" m r2,%3\n" \ 805" m r2,%3\n" \ 806" m r2,%3\n" \ 807" m r2,%3\n" \ 808" m r2,%3\n" \ 809" m r2,%3\n" \ 810" m r2,%3\n" \ 811" m r2,%3\n" \ 812" m r2,%3\n" \ 813" cas %0,r2,r0\n" \ 814" mfs r10,%1" \ 815 : "=r" ((USItype) (ph)), \ 816 "=r" ((USItype) (pl)) \ 817 : "%r" (__m0), \ 818 "r" (__m1) \ 819 : "r2"); \ 820 (ph) += ((((SItype) __m0 >> 31) & __m1) \ 821 + (((SItype) __m1 >> 31) & __m0)); \ 822 } while (0) 823#define UMUL_TIME 20 824#define UDIV_TIME 200 825#define count_leading_zeros(count, x) \ 826 do { \ 827 if ((x) >= 0x10000) \ 828 __asm__ ("clz %0,%1" \ 829 : "=r" ((USItype) (count)) \ 830 : "r" ((USItype) (x) >> 16)); \ 831 else \ 832 { \ 833 __asm__ ("clz %0,%1" \ 834 : "=r" ((USItype) (count)) \ 835 : "r" ((USItype) (x))); \ 836 (count) += 16; \ 837 } \ 838 } while (0) 839#endif 840 841#if defined (__sh2__) && W_TYPE_SIZE == 32 842#define umul_ppmm(w1, w0, u, v) \ 843 __asm__ ( \ 844 "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \ 845 : "=r" ((USItype)(w1)), \ 846 "=r" ((USItype)(w0)) \ 847 : "r" ((USItype)(u)), \ 848 "r" ((USItype)(v)) \ 849 : "macl", "mach") 850#define UMUL_TIME 5 851#endif 852 853#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32 854#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v) 855#define count_leading_zeros(count, x) \ 856 do \ 857 { \ 858 UDItype x_ = (USItype)(x); \ 859 SItype c_; \ 860 \ 861 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \ 862 (count) = c_ - 31; \ 863 } \ 864 while (0) 865#define COUNT_LEADING_ZEROS_0 32 866#endif 867 868#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \ 869 && W_TYPE_SIZE == 32 870#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 871 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \ 872 : "=r" ((USItype) (sh)), \ 873 "=&r" ((USItype) (sl)) \ 874 : "%rJ" ((USItype) (ah)), \ 875 "rI" ((USItype) (bh)), \ 876 "%rJ" ((USItype) (al)), \ 877 "rI" ((USItype) (bl)) \ 878 __CLOBBER_CC) 879#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 880 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \ 881 : "=r" ((USItype) (sh)), \ 882 "=&r" ((USItype) (sl)) \ 883 : "rJ" ((USItype) (ah)), \ 884 "rI" ((USItype) (bh)), \ 885 "rJ" ((USItype) (al)), \ 886 "rI" ((USItype) (bl)) \ 887 __CLOBBER_CC) 888#if defined (__sparc_v8__) 889#define umul_ppmm(w1, w0, u, v) \ 890 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 891 : "=r" ((USItype) (w1)), \ 892 "=r" ((USItype) (w0)) \ 893 : "r" ((USItype) (u)), \ 894 "r" ((USItype) (v))) 895#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 896 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\ 897 : "=&r" ((USItype) (__q)), \ 898 "=&r" ((USItype) (__r)) \ 899 : "r" ((USItype) (__n1)), \ 900 "r" ((USItype) (__n0)), \ 901 "r" ((USItype) (__d))) 902#else 903#if defined (__sparclite__) 904/* This has hardware multiply but not divide. It also has two additional 905 instructions scan (ffs from high bit) and divscc. */ 906#define umul_ppmm(w1, w0, u, v) \ 907 __asm__ ("umul %2,%3,%1;rd %%y,%0" \ 908 : "=r" ((USItype) (w1)), \ 909 "=r" ((USItype) (w0)) \ 910 : "r" ((USItype) (u)), \ 911 "r" ((USItype) (v))) 912#define udiv_qrnnd(q, r, n1, n0, d) \ 913 __asm__ ("! Inlined udiv_qrnnd\n" \ 914" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \ 915" tst %%g0\n" \ 916" divscc %3,%4,%%g1\n" \ 917" divscc %%g1,%4,%%g1\n" \ 918" divscc %%g1,%4,%%g1\n" \ 919" divscc %%g1,%4,%%g1\n" \ 920" divscc %%g1,%4,%%g1\n" \ 921" divscc %%g1,%4,%%g1\n" \ 922" divscc %%g1,%4,%%g1\n" \ 923" divscc %%g1,%4,%%g1\n" \ 924" divscc %%g1,%4,%%g1\n" \ 925" divscc %%g1,%4,%%g1\n" \ 926" divscc %%g1,%4,%%g1\n" \ 927" divscc %%g1,%4,%%g1\n" \ 928" divscc %%g1,%4,%%g1\n" \ 929" divscc %%g1,%4,%%g1\n" \ 930" divscc %%g1,%4,%%g1\n" \ 931" divscc %%g1,%4,%%g1\n" \ 932" divscc %%g1,%4,%%g1\n" \ 933" divscc %%g1,%4,%%g1\n" \ 934" divscc %%g1,%4,%%g1\n" \ 935" divscc %%g1,%4,%%g1\n" \ 936" divscc %%g1,%4,%%g1\n" \ 937" divscc %%g1,%4,%%g1\n" \ 938" divscc %%g1,%4,%%g1\n" \ 939" divscc %%g1,%4,%%g1\n" \ 940" divscc %%g1,%4,%%g1\n" \ 941" divscc %%g1,%4,%%g1\n" \ 942" divscc %%g1,%4,%%g1\n" \ 943" divscc %%g1,%4,%%g1\n" \ 944" divscc %%g1,%4,%%g1\n" \ 945" divscc %%g1,%4,%%g1\n" \ 946" divscc %%g1,%4,%%g1\n" \ 947" divscc %%g1,%4,%0\n" \ 948" rd %%y,%1\n" \ 949" bl,a 1f\n" \ 950" add %1,%4,%1\n" \ 951"1: ! End of inline udiv_qrnnd" \ 952 : "=r" ((USItype) (q)), \ 953 "=r" ((USItype) (r)) \ 954 : "r" ((USItype) (n1)), \ 955 "r" ((USItype) (n0)), \ 956 "rI" ((USItype) (d)) \ 957 : "g1" __AND_CLOBBER_CC) 958#define UDIV_TIME 37 959#define count_leading_zeros(count, x) \ 960 do { \ 961 __asm__ ("scan %1,1,%0" \ 962 : "=r" ((USItype) (count)) \ 963 : "r" ((USItype) (x))); \ 964 } while (0) 965/* Early sparclites return 63 for an argument of 0, but they warn that future 966 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0 967 undefined. */ 968#else 969/* SPARC without integer multiplication and divide instructions. 970 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */ 971#define umul_ppmm(w1, w0, u, v) \ 972 __asm__ ("! Inlined umul_ppmm\n" \ 973" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\ 974" sra %3,31,%%o5 ! Don't move this insn\n" \ 975" and %2,%%o5,%%o5 ! Don't move this insn\n" \ 976" andcc %%g0,0,%%g1 ! Don't move this insn\n" \ 977" mulscc %%g1,%3,%%g1\n" \ 978" mulscc %%g1,%3,%%g1\n" \ 979" mulscc %%g1,%3,%%g1\n" \ 980" mulscc %%g1,%3,%%g1\n" \ 981" mulscc %%g1,%3,%%g1\n" \ 982" mulscc %%g1,%3,%%g1\n" \ 983" mulscc %%g1,%3,%%g1\n" \ 984" mulscc %%g1,%3,%%g1\n" \ 985" mulscc %%g1,%3,%%g1\n" \ 986" mulscc %%g1,%3,%%g1\n" \ 987" mulscc %%g1,%3,%%g1\n" \ 988" mulscc %%g1,%3,%%g1\n" \ 989" mulscc %%g1,%3,%%g1\n" \ 990" mulscc %%g1,%3,%%g1\n" \ 991" mulscc %%g1,%3,%%g1\n" \ 992" mulscc %%g1,%3,%%g1\n" \ 993" mulscc %%g1,%3,%%g1\n" \ 994" mulscc %%g1,%3,%%g1\n" \ 995" mulscc %%g1,%3,%%g1\n" \ 996" mulscc %%g1,%3,%%g1\n" \ 997" mulscc %%g1,%3,%%g1\n" \ 998" mulscc %%g1,%3,%%g1\n" \ 999" mulscc %%g1,%3,%%g1\n" \ 1000" mulscc %%g1,%3,%%g1\n" \ 1001" mulscc %%g1,%3,%%g1\n" \ 1002" mulscc %%g1,%3,%%g1\n" \ 1003" mulscc %%g1,%3,%%g1\n" \ 1004" mulscc %%g1,%3,%%g1\n" \ 1005" mulscc %%g1,%3,%%g1\n" \ 1006" mulscc %%g1,%3,%%g1\n" \ 1007" mulscc %%g1,%3,%%g1\n" \ 1008" mulscc %%g1,%3,%%g1\n" \ 1009" mulscc %%g1,0,%%g1\n" \ 1010" add %%g1,%%o5,%0\n" \ 1011" rd %%y,%1" \ 1012 : "=r" ((USItype) (w1)), \ 1013 "=r" ((USItype) (w0)) \ 1014 : "%rI" ((USItype) (u)), \ 1015 "r" ((USItype) (v)) \ 1016 : "g1", "o5" __AND_CLOBBER_CC) 1017#define UMUL_TIME 39 /* 39 instructions */ 1018/* It's quite necessary to add this much assembler for the sparc. 1019 The default udiv_qrnnd (in C) is more than 10 times slower! */ 1020#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \ 1021 __asm__ ("! Inlined udiv_qrnnd\n" \ 1022" mov 32,%%g1\n" \ 1023" subcc %1,%2,%%g0\n" \ 1024"1: bcs 5f\n" \ 1025" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 1026" sub %1,%2,%1 ! this kills msb of n\n" \ 1027" addx %1,%1,%1 ! so this can't give carry\n" \ 1028" subcc %%g1,1,%%g1\n" \ 1029"2: bne 1b\n" \ 1030" subcc %1,%2,%%g0\n" \ 1031" bcs 3f\n" \ 1032" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ 1033" b 3f\n" \ 1034" sub %1,%2,%1 ! this kills msb of n\n" \ 1035"4: sub %1,%2,%1\n" \ 1036"5: addxcc %1,%1,%1\n" \ 1037" bcc 2b\n" \ 1038" subcc %%g1,1,%%g1\n" \ 1039"! Got carry from n. Subtract next step to cancel this carry.\n" \ 1040" bne 4b\n" \ 1041" addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \ 1042" sub %1,%2,%1\n" \ 1043"3: xnor %0,0,%0\n" \ 1044" ! End of inline udiv_qrnnd" \ 1045 : "=&r" ((USItype) (__q)), \ 1046 "=&r" ((USItype) (__r)) \ 1047 : "r" ((USItype) (__d)), \ 1048 "1" ((USItype) (__n1)), \ 1049 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC) 1050#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */ 1051#endif /* __sparclite__ */ 1052#endif /* __sparc_v8__ */ 1053#endif /* sparc32 */ 1054 1055#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \ 1056 && W_TYPE_SIZE == 64 1057#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1058 __asm__ ("addcc %r4,%5,%1\n\t" \ 1059 "add %r2,%3,%0\n\t" \ 1060 "bcs,a,pn %%xcc, 1f\n\t" \ 1061 "add %0, 1, %0\n" \ 1062 "1:" \ 1063 : "=r" ((UDItype)(sh)), \ 1064 "=&r" ((UDItype)(sl)) \ 1065 : "%rJ" ((UDItype)(ah)), \ 1066 "rI" ((UDItype)(bh)), \ 1067 "%rJ" ((UDItype)(al)), \ 1068 "rI" ((UDItype)(bl)) \ 1069 __CLOBBER_CC) 1070 1071#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1072 __asm__ ("subcc %r4,%5,%1\n\t" \ 1073 "sub %r2,%3,%0\n\t" \ 1074 "bcs,a,pn %%xcc, 1f\n\t" \ 1075 "sub %0, 1, %0\n\t" \ 1076 "1:" \ 1077 : "=r" ((UDItype)(sh)), \ 1078 "=&r" ((UDItype)(sl)) \ 1079 : "rJ" ((UDItype)(ah)), \ 1080 "rI" ((UDItype)(bh)), \ 1081 "rJ" ((UDItype)(al)), \ 1082 "rI" ((UDItype)(bl)) \ 1083 __CLOBBER_CC) 1084 1085#define umul_ppmm(wh, wl, u, v) \ 1086 do { \ 1087 UDItype tmp1, tmp2, tmp3, tmp4; \ 1088 __asm__ __volatile__ ( \ 1089 "srl %7,0,%3\n\t" \ 1090 "mulx %3,%6,%1\n\t" \ 1091 "srlx %6,32,%2\n\t" \ 1092 "mulx %2,%3,%4\n\t" \ 1093 "sllx %4,32,%5\n\t" \ 1094 "srl %6,0,%3\n\t" \ 1095 "sub %1,%5,%5\n\t" \ 1096 "srlx %5,32,%5\n\t" \ 1097 "addcc %4,%5,%4\n\t" \ 1098 "srlx %7,32,%5\n\t" \ 1099 "mulx %3,%5,%3\n\t" \ 1100 "mulx %2,%5,%5\n\t" \ 1101 "sethi %%hi(0x80000000),%2\n\t" \ 1102 "addcc %4,%3,%4\n\t" \ 1103 "srlx %4,32,%4\n\t" \ 1104 "add %2,%2,%2\n\t" \ 1105 "movcc %%xcc,%%g0,%2\n\t" \ 1106 "addcc %5,%4,%5\n\t" \ 1107 "sllx %3,32,%3\n\t" \ 1108 "add %1,%3,%1\n\t" \ 1109 "add %5,%2,%0" \ 1110 : "=r" ((UDItype)(wh)), \ 1111 "=&r" ((UDItype)(wl)), \ 1112 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ 1113 : "r" ((UDItype)(u)), \ 1114 "r" ((UDItype)(v)) \ 1115 __CLOBBER_CC); \ 1116 } while (0) 1117#define UMUL_TIME 96 1118#define UDIV_TIME 230 1119#endif /* sparc64 */ 1120 1121#if defined (__vax__) && W_TYPE_SIZE == 32 1122#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1123 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \ 1124 : "=g" ((USItype) (sh)), \ 1125 "=&g" ((USItype) (sl)) \ 1126 : "%0" ((USItype) (ah)), \ 1127 "g" ((USItype) (bh)), \ 1128 "%1" ((USItype) (al)), \ 1129 "g" ((USItype) (bl))) 1130#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1131 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \ 1132 : "=g" ((USItype) (sh)), \ 1133 "=&g" ((USItype) (sl)) \ 1134 : "0" ((USItype) (ah)), \ 1135 "g" ((USItype) (bh)), \ 1136 "1" ((USItype) (al)), \ 1137 "g" ((USItype) (bl))) 1138#define umul_ppmm(xh, xl, m0, m1) \ 1139 do { \ 1140 union { \ 1141 UDItype __ll; \ 1142 struct {USItype __l, __h;} __i; \ 1143 } __xx; \ 1144 USItype __m0 = (m0), __m1 = (m1); \ 1145 __asm__ ("emul %1,%2,$0,%0" \ 1146 : "=r" (__xx.__ll) \ 1147 : "g" (__m0), \ 1148 "g" (__m1)); \ 1149 (xh) = __xx.__i.__h; \ 1150 (xl) = __xx.__i.__l; \ 1151 (xh) += ((((SItype) __m0 >> 31) & __m1) \ 1152 + (((SItype) __m1 >> 31) & __m0)); \ 1153 } while (0) 1154#define sdiv_qrnnd(q, r, n1, n0, d) \ 1155 do { \ 1156 union {DItype __ll; \ 1157 struct {SItype __l, __h;} __i; \ 1158 } __xx; \ 1159 __xx.__i.__h = n1; __xx.__i.__l = n0; \ 1160 __asm__ ("ediv %3,%2,%0,%1" \ 1161 : "=g" (q), "=g" (r) \ 1162 : "g" (__xx.__ll), "g" (d)); \ 1163 } while (0) 1164#endif /* __vax__ */ 1165 1166#if defined (__z8000__) && W_TYPE_SIZE == 16 1167#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1168 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \ 1169 : "=r" ((unsigned int)(sh)), \ 1170 "=&r" ((unsigned int)(sl)) \ 1171 : "%0" ((unsigned int)(ah)), \ 1172 "r" ((unsigned int)(bh)), \ 1173 "%1" ((unsigned int)(al)), \ 1174 "rQR" ((unsigned int)(bl))) 1175#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1176 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \ 1177 : "=r" ((unsigned int)(sh)), \ 1178 "=&r" ((unsigned int)(sl)) \ 1179 : "0" ((unsigned int)(ah)), \ 1180 "r" ((unsigned int)(bh)), \ 1181 "1" ((unsigned int)(al)), \ 1182 "rQR" ((unsigned int)(bl))) 1183#define umul_ppmm(xh, xl, m0, m1) \ 1184 do { \ 1185 union {long int __ll; \ 1186 struct {unsigned int __h, __l;} __i; \ 1187 } __xx; \ 1188 unsigned int __m0 = (m0), __m1 = (m1); \ 1189 __asm__ ("mult %S0,%H3" \ 1190 : "=r" (__xx.__i.__h), \ 1191 "=r" (__xx.__i.__l) \ 1192 : "%1" (__m0), \ 1193 "rQR" (__m1)); \ 1194 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \ 1195 (xh) += ((((signed int) __m0 >> 15) & __m1) \ 1196 + (((signed int) __m1 >> 15) & __m0)); \ 1197 } while (0) 1198#endif /* __z8000__ */ 1199 1200#endif /* __GNUC__ */ 1201 1202/* If this machine has no inline assembler, use C macros. */ 1203 1204#if !defined (add_ssaaaa) 1205#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 1206 do { \ 1207 UWtype __x; \ 1208 __x = (al) + (bl); \ 1209 (sh) = (ah) + (bh) + (__x < (al)); \ 1210 (sl) = __x; \ 1211 } while (0) 1212#endif 1213 1214#if !defined (sub_ddmmss) 1215#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 1216 do { \ 1217 UWtype __x; \ 1218 __x = (al) - (bl); \ 1219 (sh) = (ah) - (bh) - (__x > (al)); \ 1220 (sl) = __x; \ 1221 } while (0) 1222#endif 1223 1224/* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of 1225 smul_ppmm. */ 1226#if !defined (umul_ppmm) && defined (smul_ppmm) 1227#define umul_ppmm(w1, w0, u, v) \ 1228 do { \ 1229 UWtype __w1; \ 1230 UWtype __xm0 = (u), __xm1 = (v); \ 1231 smul_ppmm (__w1, w0, __xm0, __xm1); \ 1232 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \ 1233 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \ 1234 } while (0) 1235#endif 1236 1237/* If we still don't have umul_ppmm, define it using plain C. */ 1238#if !defined (umul_ppmm) 1239#define umul_ppmm(w1, w0, u, v) \ 1240 do { \ 1241 UWtype __x0, __x1, __x2, __x3; \ 1242 UHWtype __ul, __vl, __uh, __vh; \ 1243 \ 1244 __ul = __ll_lowpart (u); \ 1245 __uh = __ll_highpart (u); \ 1246 __vl = __ll_lowpart (v); \ 1247 __vh = __ll_highpart (v); \ 1248 \ 1249 __x0 = (UWtype) __ul * __vl; \ 1250 __x1 = (UWtype) __ul * __vh; \ 1251 __x2 = (UWtype) __uh * __vl; \ 1252 __x3 = (UWtype) __uh * __vh; \ 1253 \ 1254 __x1 += __ll_highpart (__x0);/* this can't give carry */ \ 1255 __x1 += __x2; /* but this indeed can */ \ 1256 if (__x1 < __x2) /* did we get it? */ \ 1257 __x3 += __ll_B; /* yes, add it in the proper pos. */ \ 1258 \ 1259 (w1) = __x3 + __ll_highpart (__x1); \ 1260 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ 1261 } while (0) 1262#endif 1263 1264#if !defined (__umulsidi3) 1265#define __umulsidi3(u, v) \ 1266 ({DWunion __w; \ 1267 umul_ppmm (__w.s.high, __w.s.low, u, v); \ 1268 __w.ll; }) 1269#endif 1270 1271/* Define this unconditionally, so it can be used for debugging. */ 1272#define __udiv_qrnnd_c(q, r, n1, n0, d) \ 1273 do { \ 1274 UWtype __d1, __d0, __q1, __q0; \ 1275 UWtype __r1, __r0, __m; \ 1276 __d1 = __ll_highpart (d); \ 1277 __d0 = __ll_lowpart (d); \ 1278 \ 1279 __r1 = (n1) % __d1; \ 1280 __q1 = (n1) / __d1; \ 1281 __m = (UWtype) __q1 * __d0; \ 1282 __r1 = __r1 * __ll_B | __ll_highpart (n0); \ 1283 if (__r1 < __m) \ 1284 { \ 1285 __q1--, __r1 += (d); \ 1286 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ 1287 if (__r1 < __m) \ 1288 __q1--, __r1 += (d); \ 1289 } \ 1290 __r1 -= __m; \ 1291 \ 1292 __r0 = __r1 % __d1; \ 1293 __q0 = __r1 / __d1; \ 1294 __m = (UWtype) __q0 * __d0; \ 1295 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ 1296 if (__r0 < __m) \ 1297 { \ 1298 __q0--, __r0 += (d); \ 1299 if (__r0 >= (d)) \ 1300 if (__r0 < __m) \ 1301 __q0--, __r0 += (d); \ 1302 } \ 1303 __r0 -= __m; \ 1304 \ 1305 (q) = (UWtype) __q1 * __ll_B | __q0; \ 1306 (r) = __r0; \ 1307 } while (0) 1308 1309/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through 1310 __udiv_w_sdiv (defined in libgcc or elsewhere). */ 1311#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd) 1312#define udiv_qrnnd(q, r, nh, nl, d) \ 1313 do { \ 1314 USItype __r; \ 1315 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \ 1316 (r) = __r; \ 1317 } while (0) 1318#endif 1319 1320/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */ 1321#if !defined (udiv_qrnnd) 1322#define UDIV_NEEDS_NORMALIZATION 1 1323#define udiv_qrnnd __udiv_qrnnd_c 1324#endif 1325 1326#if !defined (count_leading_zeros) 1327extern const UQItype __clz_tab[] ATTRIBUTE_HIDDEN; 1328#define count_leading_zeros(count, x) \ 1329 do { \ 1330 UWtype __xr = (x); \ 1331 UWtype __a; \ 1332 \ 1333 if (W_TYPE_SIZE <= 32) \ 1334 { \ 1335 __a = __xr < ((UWtype)1<<2*__BITS4) \ 1336 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \ 1337 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \ 1338 } \ 1339 else \ 1340 { \ 1341 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \ 1342 if (((__xr >> __a) & 0xff) != 0) \ 1343 break; \ 1344 } \ 1345 \ 1346 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \ 1347 } while (0) 1348#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE 1349#endif 1350 1351#if !defined (count_trailing_zeros) 1352/* Define count_trailing_zeros using count_leading_zeros. The latter might be 1353 defined in asm, but if it is not, the C version above is good enough. */ 1354#define count_trailing_zeros(count, x) \ 1355 do { \ 1356 UWtype __ctz_x = (x); \ 1357 UWtype __ctz_c; \ 1358 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \ 1359 (count) = W_TYPE_SIZE - 1 - __ctz_c; \ 1360 } while (0) 1361#endif 1362 1363#ifndef UDIV_NEEDS_NORMALIZATION 1364#define UDIV_NEEDS_NORMALIZATION 0 1365#endif 1366