sparc.h revision 132718
1/* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com). 5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 6 at Cygnus Support. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify 11it under the terms of the GNU General Public License as published by 12the Free Software Foundation; either version 2, or (at your option) 13any later version. 14 15GCC is distributed in the hope that it will be useful, 16but WITHOUT ANY WARRANTY; without even the implied warranty of 17MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18GNU General Public License for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING. If not, write to 22the Free Software Foundation, 59 Temple Place - Suite 330, 23Boston, MA 02111-1307, USA. */ 24 25/* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28/* Target CPU builtins. FIXME: Defining sparc is for the benefit of 29 Solaris only; otherwise just define __sparc__. Sadly the headers 30 are such a mess there is no Solaris-specific header. */ 31#define TARGET_CPU_CPP_BUILTINS() \ 32 do \ 33 { \ 34 builtin_define_std ("sparc"); \ 35 if (TARGET_64BIT) \ 36 { \ 37 builtin_assert ("cpu=sparc64"); \ 38 builtin_assert ("machine=sparc64"); \ 39 } \ 40 else \ 41 { \ 42 builtin_assert ("cpu=sparc"); \ 43 builtin_assert ("machine=sparc"); \ 44 } \ 45 } \ 46 while (0) 47 48/* Specify this in a cover file to provide bi-architecture (32/64) support. */ 49/* #define SPARC_BI_ARCH */ 50 51/* Macro used later in this file to determine default architecture. */ 52#define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 53 54/* TARGET_ARCH{32,64} are the main macros to decide which of the two 55 architectures to compile for. We allow targets to choose compile time or 56 runtime selection. */ 57#ifdef IN_LIBGCC2 58#if defined(__sparcv9) || defined(__arch64__) 59#define TARGET_ARCH32 0 60#else 61#define TARGET_ARCH32 1 62#endif /* sparc64 */ 63#else 64#ifdef SPARC_BI_ARCH 65#define TARGET_ARCH32 (! TARGET_64BIT) 66#else 67#define TARGET_ARCH32 (DEFAULT_ARCH32_P) 68#endif /* SPARC_BI_ARCH */ 69#endif /* IN_LIBGCC2 */ 70#define TARGET_ARCH64 (! TARGET_ARCH32) 71 72/* Code model selection in 64-bit environment. 73 74 The machine mode used for addresses is 32-bit wide: 75 76 TARGET_CM_32: 32-bit address space. 77 It is the code model used when generating 32-bit code. 78 79 The machine mode used for addresses is 64-bit wide: 80 81 TARGET_CM_MEDLOW: 32-bit address space. 82 The executable must be in the low 32 bits of memory. 83 This avoids generating %uhi and %ulo terms. Programs 84 can be statically or dynamically linked. 85 86 TARGET_CM_MEDMID: 44-bit address space. 87 The executable must be in the low 44 bits of memory, 88 and the %[hml]44 terms are used. The text and data 89 segments have a maximum size of 2GB (31-bit span). 90 The maximum offset from any instruction to the label 91 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 92 93 TARGET_CM_MEDANY: 64-bit address space. 94 The text and data segments have a maximum size of 2GB 95 (31-bit span) and may be located anywhere in memory. 96 The maximum offset from any instruction to the label 97 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 98 99 TARGET_CM_EMBMEDANY: 64-bit address space. 100 The text and data segments have a maximum size of 2GB 101 (31-bit span) and may be located anywhere in memory. 102 The global register %g4 contains the start address of 103 the data segment. Programs are statically linked and 104 PIC is not supported. 105 106 Different code models are not supported in 32-bit environment. */ 107 108enum cmodel { 109 CM_32, 110 CM_MEDLOW, 111 CM_MEDMID, 112 CM_MEDANY, 113 CM_EMBMEDANY 114}; 115 116/* Value of -mcmodel specified by user. */ 117extern const char *sparc_cmodel_string; 118/* One of CM_FOO. */ 119extern enum cmodel sparc_cmodel; 120 121/* V9 code model selection. */ 122#define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 123#define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 124#define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 125#define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 126 127#define SPARC_DEFAULT_CMODEL CM_32 128 129/* This is call-clobbered in the normal ABI, but is reserved in the 130 home grown (aka upward compatible) embedded ABI. */ 131#define EMBMEDANY_BASE_REG "%g4" 132 133/* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 134 and specified by the user via --with-cpu=foo. 135 This specifies the cpu implementation, not the architecture size. */ 136/* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 137 capable cpu's. */ 138#define TARGET_CPU_sparc 0 139#define TARGET_CPU_v7 0 /* alias for previous */ 140#define TARGET_CPU_sparclet 1 141#define TARGET_CPU_sparclite 2 142#define TARGET_CPU_v8 3 /* generic v8 implementation */ 143#define TARGET_CPU_supersparc 4 144#define TARGET_CPU_hypersparc 5 145#define TARGET_CPU_sparc86x 6 146#define TARGET_CPU_sparclite86x 6 147#define TARGET_CPU_v9 7 /* generic v9 implementation */ 148#define TARGET_CPU_sparcv9 7 /* alias */ 149#define TARGET_CPU_sparc64 7 /* alias */ 150#define TARGET_CPU_ultrasparc 8 151#define TARGET_CPU_ultrasparc3 9 152 153#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 154 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 155 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 156 157#define CPP_CPU32_DEFAULT_SPEC "" 158#define ASM_CPU32_DEFAULT_SPEC "" 159 160#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 161/* ??? What does Sun's CC pass? */ 162#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 163/* ??? It's not clear how other assemblers will handle this, so by default 164 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 165 is handled in sol2.h. */ 166#define ASM_CPU64_DEFAULT_SPEC "-Av9" 167#endif 168#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 169#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 170#define ASM_CPU64_DEFAULT_SPEC "-Av9a" 171#endif 172#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 173#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 174#define ASM_CPU64_DEFAULT_SPEC "-Av9b" 175#endif 176 177#else 178 179#define CPP_CPU64_DEFAULT_SPEC "" 180#define ASM_CPU64_DEFAULT_SPEC "" 181 182#if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 183 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 184#define CPP_CPU32_DEFAULT_SPEC "" 185#define ASM_CPU32_DEFAULT_SPEC "" 186#endif 187 188#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 189#define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 190#define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 191#endif 192 193#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 194#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 195#define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 196#endif 197 198#if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 199#define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 200#define ASM_CPU32_DEFAULT_SPEC "" 201#endif 202 203#if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 204#define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 205#define ASM_CPU32_DEFAULT_SPEC "" 206#endif 207 208#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 209#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 210#define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 211#endif 212 213#endif 214 215#if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 216 #error Unrecognized value in TARGET_CPU_DEFAULT. 217#endif 218 219#ifdef SPARC_BI_ARCH 220 221#define CPP_CPU_DEFAULT_SPEC \ 222(DEFAULT_ARCH32_P ? "\ 223%{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 224%{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 225" : "\ 226%{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 227%{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 228") 229#define ASM_CPU_DEFAULT_SPEC \ 230(DEFAULT_ARCH32_P ? "\ 231%{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 232%{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 233" : "\ 234%{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 235%{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 236") 237 238#else /* !SPARC_BI_ARCH */ 239 240#define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 241#define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 242 243#endif /* !SPARC_BI_ARCH */ 244 245/* Define macros to distinguish architectures. */ 246 247/* Common CPP definitions used by CPP_SPEC amongst the various targets 248 for handling -mcpu=xxx switches. */ 249#define CPP_CPU_SPEC "\ 250%{msoft-float:-D_SOFT_FLOAT} \ 251%{mcypress:} \ 252%{msparclite:-D__sparclite__} \ 253%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ 254%{mv8:-D__sparc_v8__} \ 255%{msupersparc:-D__supersparc__ -D__sparc_v8__} \ 256%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 257%{mcpu=sparclite:-D__sparclite__} \ 258%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 259%{mcpu=v8:-D__sparc_v8__} \ 260%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 261%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 262%{mcpu=sparclite86x:-D__sparclite86x__} \ 263%{mcpu=v9:-D__sparc_v9__} \ 264%{mcpu=ultrasparc:-D__sparc_v9__} \ 265%{mcpu=ultrasparc3:-D__sparc_v9__} \ 266%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ 267" 268#define CPP_ARCH32_SPEC "" 269#define CPP_ARCH64_SPEC "-D__arch64__" 270 271#define CPP_ARCH_DEFAULT_SPEC \ 272(DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 273 274#define CPP_ARCH_SPEC "\ 275%{m32:%(cpp_arch32)} \ 276%{m64:%(cpp_arch64)} \ 277%{!m32:%{!m64:%(cpp_arch_default)}} \ 278" 279 280/* Macros to distinguish endianness. */ 281#define CPP_ENDIAN_SPEC "\ 282%{mlittle-endian:-D__LITTLE_ENDIAN__} \ 283%{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" 284 285/* Macros to distinguish the particular subtarget. */ 286#define CPP_SUBTARGET_SPEC "" 287 288#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" 289 290/* Prevent error on `-sun4' and `-target sun4' options. */ 291/* This used to translate -dalign to -malign, but that is no good 292 because it can't turn off the usual meaning of making debugging dumps. */ 293/* Translate old style -m<cpu> into new style -mcpu=<cpu>. 294 ??? Delete support for -m<cpu> for 2.9. */ 295 296#define CC1_SPEC "\ 297%{sun4:} %{target:} \ 298%{mcypress:-mcpu=cypress} \ 299%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ 300%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ 301" 302 303/* Override in target specific files. */ 304#define ASM_CPU_SPEC "\ 305%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 306%{msparclite:-Asparclite} \ 307%{mf930:-Asparclite} %{mf934:-Asparclite} \ 308%{mcpu=sparclite:-Asparclite} \ 309%{mcpu=sparclite86x:-Asparclite} \ 310%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 311%{mv8plus:-Av8plus} \ 312%{mcpu=v9:-Av9} \ 313%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 314%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 315%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ 316" 317 318/* Word size selection, among other things. 319 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 320 321#define ASM_ARCH32_SPEC "-32" 322#ifdef HAVE_AS_REGISTER_PSEUDO_OP 323#define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 324#else 325#define ASM_ARCH64_SPEC "-64" 326#endif 327#define ASM_ARCH_DEFAULT_SPEC \ 328(DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 329 330#define ASM_ARCH_SPEC "\ 331%{m32:%(asm_arch32)} \ 332%{m64:%(asm_arch64)} \ 333%{!m32:%{!m64:%(asm_arch_default)}} \ 334" 335 336#ifdef HAVE_AS_RELAX_OPTION 337#define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 338#else 339#define ASM_RELAX_SPEC "" 340#endif 341 342/* Special flags to the Sun-4 assembler when using pipe for input. */ 343 344#define ASM_SPEC "\ 345%{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ 346%(asm_cpu) %(asm_relax)" 347 348#define AS_NEEDS_DASH_FOR_PIPED_INPUT 349 350/* This macro defines names of additional specifications to put in the specs 351 that can be used in various specifications like CC1_SPEC. Its definition 352 is an initializer with a subgrouping for each command option. 353 354 Each subgrouping contains a string constant, that defines the 355 specification name, and a string constant that used by the GCC driver 356 program. 357 358 Do not define this macro if it does not need to do anything. */ 359 360#define EXTRA_SPECS \ 361 { "cpp_cpu", CPP_CPU_SPEC }, \ 362 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 363 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 364 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 365 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 366 { "cpp_arch", CPP_ARCH_SPEC }, \ 367 { "cpp_endian", CPP_ENDIAN_SPEC }, \ 368 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 369 { "asm_cpu", ASM_CPU_SPEC }, \ 370 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 371 { "asm_arch32", ASM_ARCH32_SPEC }, \ 372 { "asm_arch64", ASM_ARCH64_SPEC }, \ 373 { "asm_relax", ASM_RELAX_SPEC }, \ 374 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 375 { "asm_arch", ASM_ARCH_SPEC }, \ 376 SUBTARGET_EXTRA_SPECS 377 378#define SUBTARGET_EXTRA_SPECS 379 380/* Because libgcc can generate references back to libc (via .umul etc.) we have 381 to list libc again after the second libgcc. */ 382#define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 383 384 385#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 386#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 387 388/* ??? This should be 32 bits for v9 but what can we do? */ 389#define WCHAR_TYPE "short unsigned int" 390#define WCHAR_TYPE_SIZE 16 391 392/* Show we can debug even without a frame pointer. */ 393#define CAN_DEBUG_WITHOUT_FP 394 395#define OVERRIDE_OPTIONS sparc_override_options () 396 397/* Generate DBX debugging information. */ 398 399#define DBX_DEBUGGING_INFO 1 400 401/* Run-time compilation parameters selecting different hardware subsets. */ 402 403extern int target_flags; 404 405/* Nonzero if we should generate code to use the fpu. */ 406#define MASK_FPU 1 407#define TARGET_FPU (target_flags & MASK_FPU) 408 409/* Nonzero if we should assume that double pointers might be unaligned. 410 This can happen when linking gcc compiled code with other compilers, 411 because the ABI only guarantees 4 byte alignment. */ 412#define MASK_UNALIGNED_DOUBLES 4 413#define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES) 414 415/* Nonzero means that we should generate code for a v8 sparc. */ 416#define MASK_V8 0x8 417#define TARGET_V8 (target_flags & MASK_V8) 418 419/* Nonzero means that we should generate code for a sparclite. 420 This enables the sparclite specific instructions, but does not affect 421 whether FPU instructions are emitted. */ 422#define MASK_SPARCLITE 0x10 423#define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE) 424 425/* Nonzero if we're compiling for the sparclet. */ 426#define MASK_SPARCLET 0x20 427#define TARGET_SPARCLET (target_flags & MASK_SPARCLET) 428 429/* Nonzero if we're compiling for v9 sparc. 430 Note that v9's can run in 32 bit mode so this doesn't necessarily mean 431 the word size is 64. */ 432#define MASK_V9 0x40 433#define TARGET_V9 (target_flags & MASK_V9) 434 435/* Nonzero to generate code that uses the instructions deprecated in 436 the v9 architecture. This option only applies to v9 systems. */ 437/* ??? This isn't user selectable yet. It's used to enable such insns 438 on 32 bit v9 systems and for the moment they're permanently disabled 439 on 64 bit v9 systems. */ 440#define MASK_DEPRECATED_V8_INSNS 0x80 441#define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS) 442 443/* Mask of all CPU selection flags. */ 444#define MASK_ISA \ 445(MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 446 447/* Nonzero means don't pass `-assert pure-text' to the linker. */ 448#define MASK_IMPURE_TEXT 0x100 449#define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT) 450 451/* Nonzero means that we should generate code using a flat register window 452 model, i.e. no save/restore instructions are generated, which is 453 compatible with normal sparc code. 454 The frame pointer is %i7 instead of %fp. */ 455#define MASK_FLAT 0x200 456#define TARGET_FLAT (target_flags & MASK_FLAT) 457 458/* Nonzero means use the registers that the SPARC ABI reserves for 459 application software. This must be the default to coincide with the 460 setting in FIXED_REGISTERS. */ 461#define MASK_APP_REGS 0x400 462#define TARGET_APP_REGS (target_flags & MASK_APP_REGS) 463 464/* Option to select how quad word floating point is implemented. 465 When TARGET_HARD_QUAD is true, we use the hardware quad instructions. 466 Otherwise, we use the SPARC ABI quad library functions. */ 467#define MASK_HARD_QUAD 0x800 468#define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) 469 470/* Nonzero on little-endian machines. */ 471/* ??? Little endian support currently only exists for sparclet-aout and 472 sparc64-elf configurations. May eventually want to expand the support 473 to all targets, but for now it's kept local to only those two. */ 474#define MASK_LITTLE_ENDIAN 0x1000 475#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN) 476 477/* 0x2000, 0x4000 are unused */ 478 479/* Nonzero if pointers are 64 bits. */ 480#define MASK_PTR64 0x8000 481#define TARGET_PTR64 (target_flags & MASK_PTR64) 482 483/* Nonzero if generating code to run in a 64 bit environment. 484 This is intended to only be used by TARGET_ARCH{32,64} as they are the 485 mechanism used to control compile time or run time selection. */ 486#define MASK_64BIT 0x10000 487#define TARGET_64BIT (target_flags & MASK_64BIT) 488 489/* 0x20000,0x40000 unused */ 490 491/* Nonzero means use a stack bias of 2047. Stack offsets are obtained by 492 adding 2047 to %sp. This option is for v9 only and is the default. */ 493#define MASK_STACK_BIAS 0x80000 494#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) 495 496/* 0x100000,0x200000 unused */ 497 498/* Nonzero means -m{,no-}fpu was passed on the command line. */ 499#define MASK_FPU_SET 0x400000 500#define TARGET_FPU_SET (target_flags & MASK_FPU_SET) 501 502/* Use the UltraSPARC Visual Instruction Set extensions. */ 503#define MASK_VIS 0x1000000 504#define TARGET_VIS (target_flags & MASK_VIS) 505 506/* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of 507 the current out and global registers and Linux 2.2+ as well. */ 508#define MASK_V8PLUS 0x2000000 509#define TARGET_V8PLUS (target_flags & MASK_V8PLUS) 510 511/* Force a the fastest alignment on structures to take advantage of 512 faster copies. */ 513#define MASK_FASTER_STRUCTS 0x4000000 514#define TARGET_FASTER_STRUCTS (target_flags & MASK_FASTER_STRUCTS) 515 516/* Use IEEE quad long double. */ 517#define MASK_LONG_DOUBLE_128 0x8000000 518#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128) 519 520/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. 521 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y 522 to get high 32 bits. False in V8+ or V9 because multiply stores 523 a 64 bit result in a register. */ 524 525#define TARGET_HARD_MUL32 \ 526 ((TARGET_V8 || TARGET_SPARCLITE \ 527 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ 528 && ! TARGET_V8PLUS && TARGET_ARCH32) 529 530#define TARGET_HARD_MUL \ 531 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ 532 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) 533 534 535/* Macro to define tables used to set the flags. 536 This is a list in braces of pairs in braces, 537 each pair being { "NAME", VALUE } 538 where VALUE is the bits to set or minus the bits to clear. 539 An empty string NAME is used to identify the default VALUE. */ 540 541#define TARGET_SWITCHES \ 542 { {"fpu", MASK_FPU | MASK_FPU_SET, \ 543 N_("Use hardware fp") }, \ 544 {"no-fpu", -MASK_FPU, \ 545 N_("Do not use hardware fp") }, \ 546 {"no-fpu", MASK_FPU_SET, NULL, }, \ 547 {"hard-float", MASK_FPU | MASK_FPU_SET, \ 548 N_("Use hardware fp") }, \ 549 {"soft-float", -MASK_FPU, \ 550 N_("Do not use hardware fp") }, \ 551 {"soft-float", MASK_FPU_SET, NULL }, \ 552 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES, \ 553 N_("Assume possible double misalignment") }, \ 554 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES, \ 555 N_("Assume all doubles are aligned") }, \ 556 {"impure-text", MASK_IMPURE_TEXT, \ 557 N_("Pass -assert pure-text to linker") }, \ 558 {"no-impure-text", -MASK_IMPURE_TEXT, \ 559 N_("Do not pass -assert pure-text to linker") }, \ 560 {"flat", MASK_FLAT, \ 561 N_("Use flat register window model") }, \ 562 {"no-flat", -MASK_FLAT, \ 563 N_("Do not use flat register window model") }, \ 564 {"app-regs", MASK_APP_REGS, \ 565 N_("Use ABI reserved registers") }, \ 566 {"no-app-regs", -MASK_APP_REGS, \ 567 N_("Do not use ABI reserved registers") }, \ 568 {"hard-quad-float", MASK_HARD_QUAD, \ 569 N_("Use hardware quad fp instructions") }, \ 570 {"soft-quad-float", -MASK_HARD_QUAD, \ 571 N_("Do not use hardware quad fp instructions") }, \ 572 {"v8plus", MASK_V8PLUS, \ 573 N_("Compile for v8plus ABI") }, \ 574 {"no-v8plus", -MASK_V8PLUS, \ 575 N_("Do not compile for v8plus ABI") }, \ 576 {"vis", MASK_VIS, \ 577 N_("Utilize Visual Instruction Set") }, \ 578 {"no-vis", -MASK_VIS, \ 579 N_("Do not utilize Visual Instruction Set") }, \ 580 /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ 581 {"cypress", 0, \ 582 N_("Optimize for Cypress processors") }, \ 583 {"sparclite", 0, \ 584 N_("Optimize for SPARCLite processors") }, \ 585 {"f930", 0, \ 586 N_("Optimize for F930 processors") }, \ 587 {"f934", 0, \ 588 N_("Optimize for F934 processors") }, \ 589 {"v8", 0, \ 590 N_("Use V8 SPARC ISA") }, \ 591 {"supersparc", 0, \ 592 N_("Optimize for SuperSPARC processors") }, \ 593 /* End of deprecated options. */ \ 594 {"ptr64", MASK_PTR64, \ 595 N_("Pointers are 64-bit") }, \ 596 {"ptr32", -MASK_PTR64, \ 597 N_("Pointers are 32-bit") }, \ 598 {"32", -MASK_64BIT, \ 599 N_("Use 32-bit ABI") }, \ 600 {"64", MASK_64BIT, \ 601 N_("Use 64-bit ABI") }, \ 602 {"stack-bias", MASK_STACK_BIAS, \ 603 N_("Use stack bias") }, \ 604 {"no-stack-bias", -MASK_STACK_BIAS, \ 605 N_("Do not use stack bias") }, \ 606 {"faster-structs", MASK_FASTER_STRUCTS, \ 607 N_("Use structs on stronger alignment for double-word copies") }, \ 608 {"no-faster-structs", -MASK_FASTER_STRUCTS, \ 609 N_("Do not use structs on stronger alignment for double-word copies") }, \ 610 {"relax", 0, \ 611 N_("Optimize tail call instructions in assembler and linker") }, \ 612 {"no-relax", 0, \ 613 N_("Do not optimize tail call instructions in assembler or linker") }, \ 614 SUBTARGET_SWITCHES \ 615 { "", TARGET_DEFAULT, ""}} 616 617/* MASK_APP_REGS must always be the default because that's what 618 FIXED_REGISTERS is set to and -ffixed- is processed before 619 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ 620#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 621 622/* This is meant to be redefined in target specific files. */ 623#define SUBTARGET_SWITCHES 624 625/* Processor type. 626 These must match the values for the cpu attribute in sparc.md. */ 627enum processor_type { 628 PROCESSOR_V7, 629 PROCESSOR_CYPRESS, 630 PROCESSOR_V8, 631 PROCESSOR_SUPERSPARC, 632 PROCESSOR_SPARCLITE, 633 PROCESSOR_F930, 634 PROCESSOR_F934, 635 PROCESSOR_HYPERSPARC, 636 PROCESSOR_SPARCLITE86X, 637 PROCESSOR_SPARCLET, 638 PROCESSOR_TSC701, 639 PROCESSOR_V9, 640 PROCESSOR_ULTRASPARC, 641 PROCESSOR_ULTRASPARC3 642}; 643 644/* This is set from -m{cpu,tune}=xxx. */ 645extern enum processor_type sparc_cpu; 646 647/* Recast the cpu class to be the cpu attribute. 648 Every file includes us, but not every file includes insn-attr.h. */ 649#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 650 651#define TARGET_OPTIONS \ 652{ \ 653 { "cpu=", &sparc_select[1].string, \ 654 N_("Use features of and schedule code for given CPU"), 0}, \ 655 { "tune=", &sparc_select[2].string, \ 656 N_("Schedule code for given CPU"), 0}, \ 657 { "cmodel=", &sparc_cmodel_string, \ 658 N_("Use given SPARC code model"), 0}, \ 659 SUBTARGET_OPTIONS \ 660} 661 662/* This is meant to be redefined in target specific files. */ 663#define SUBTARGET_OPTIONS 664 665/* Support for a compile-time default CPU, et cetera. The rules are: 666 --with-cpu is ignored if -mcpu is specified. 667 --with-tune is ignored if -mtune is specified. 668 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 669 are specified. */ 670#define OPTION_DEFAULT_SPECS \ 671 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 672 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 673 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" } 674 675/* sparc_select[0] is reserved for the default cpu. */ 676struct sparc_cpu_select 677{ 678 const char *string; 679 const char *const name; 680 const int set_tune_p; 681 const int set_arch_p; 682}; 683 684extern struct sparc_cpu_select sparc_select[]; 685 686/* target machine storage layout */ 687 688/* Define this if most significant bit is lowest numbered 689 in instructions that operate on numbered bit-fields. */ 690#define BITS_BIG_ENDIAN 1 691 692/* Define this if most significant byte of a word is the lowest numbered. */ 693#define BYTES_BIG_ENDIAN 1 694 695/* Define this if most significant word of a multiword number is the lowest 696 numbered. */ 697#define WORDS_BIG_ENDIAN 1 698 699/* Define this to set the endianness to use in libgcc2.c, which can 700 not depend on target_flags. */ 701#if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) 702#define LIBGCC2_WORDS_BIG_ENDIAN 0 703#else 704#define LIBGCC2_WORDS_BIG_ENDIAN 1 705#endif 706 707#define MAX_BITS_PER_WORD 64 708 709/* Width of a word, in units (bytes). */ 710#define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 711#ifdef IN_LIBGCC2 712#define MIN_UNITS_PER_WORD UNITS_PER_WORD 713#else 714#define MIN_UNITS_PER_WORD 4 715#endif 716 717/* Now define the sizes of the C data types. */ 718 719#define SHORT_TYPE_SIZE 16 720#define INT_TYPE_SIZE 32 721#define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 722#define LONG_LONG_TYPE_SIZE 64 723#define FLOAT_TYPE_SIZE 32 724#define DOUBLE_TYPE_SIZE 64 725 726#ifdef SPARC_BI_ARCH 727#define MAX_LONG_TYPE_SIZE 64 728#endif 729 730#if 0 731/* ??? This does not work in SunOS 4.x, so it is not enabled here. 732 Instead, it is enabled in sol2.h, because it does work under Solaris. */ 733/* Define for support of TFmode long double. 734 SPARC ABI says that long double is 4 words. */ 735#define LONG_DOUBLE_TYPE_SIZE 128 736#endif 737 738/* Width in bits of a pointer. 739 See also the macro `Pmode' defined below. */ 740#define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 741 742/* If we have to extend pointers (only when TARGET_ARCH64 and not 743 TARGET_PTR64), we want to do it unsigned. This macro does nothing 744 if ptr_mode and Pmode are the same. */ 745#define POINTERS_EXTEND_UNSIGNED 1 746 747/* A macro to update MODE and UNSIGNEDP when an object whose type 748 is TYPE and which has the specified mode and signedness is to be 749 stored in a register. This macro is only called when TYPE is a 750 scalar type. */ 751#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 752if (TARGET_ARCH64 \ 753 && GET_MODE_CLASS (MODE) == MODE_INT \ 754 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 755 (MODE) = DImode; 756 757/* Define this macro if the promotion described by PROMOTE_MODE 758 should also be done for outgoing function arguments. */ 759/* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op 760 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test 761 for this value. */ 762#define PROMOTE_FUNCTION_ARGS 763 764/* Define this macro if the promotion described by PROMOTE_MODE 765 should also be done for the return value of functions. 766 If this macro is defined, FUNCTION_VALUE must perform the same 767 promotions done by PROMOTE_MODE. */ 768/* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op 769 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test 770 for this value. */ 771#define PROMOTE_FUNCTION_RETURN 772 773/* Define this macro if the promotion described by PROMOTE_MODE 774 should _only_ be performed for outgoing function arguments or 775 function return values, as specified by PROMOTE_FUNCTION_ARGS 776 and PROMOTE_FUNCTION_RETURN, respectively. */ 777/* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op 778 for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test 779 for this value. For TARGET_ARCH64 we need it, as we don't have instructions 780 for arithmetic operations which do zero/sign extension at the same time, 781 so without this we end up with a srl/sra after every assignment to an 782 user variable, which means very very bad code. */ 783#define PROMOTE_FOR_CALL_ONLY 784 785/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 786#define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 787 788/* Boundary (in *bits*) on which stack pointer should be aligned. */ 789/* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 790 then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */ 791#define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 792/* Temporary hack until the FIXME above is fixed. This macro is used 793 only in pad_to_arg_alignment in function.c; see the comment there 794 for details about what it does. */ 795#define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 796 797/* ALIGN FRAMES on double word boundaries */ 798 799#define SPARC_STACK_ALIGN(LOC) \ 800 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 801 802/* Allocation boundary (in *bits*) for the code of a function. */ 803#define FUNCTION_BOUNDARY 32 804 805/* Alignment of field after `int : 0' in a structure. */ 806#define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 807 808/* Every structure's size must be a multiple of this. */ 809#define STRUCTURE_SIZE_BOUNDARY 8 810 811/* A bit-field declared as `int' forces `int' alignment for the struct. */ 812#define PCC_BITFIELD_TYPE_MATTERS 1 813 814/* No data type wants to be aligned rounder than this. */ 815#define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 816 817/* The best alignment to use in cases where we have a choice. */ 818#define FASTEST_ALIGNMENT 64 819 820/* Define this macro as an expression for the alignment of a structure 821 (given by STRUCT as a tree node) if the alignment computed in the 822 usual way is COMPUTED and the alignment explicitly specified was 823 SPECIFIED. 824 825 The default is to use SPECIFIED if it is larger; otherwise, use 826 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 827#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 828 (TARGET_FASTER_STRUCTS ? \ 829 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 830 || TREE_CODE (STRUCT) == UNION_TYPE \ 831 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 832 && TYPE_FIELDS (STRUCT) != 0 \ 833 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 834 : MAX ((COMPUTED), (SPECIFIED))) \ 835 : MAX ((COMPUTED), (SPECIFIED))) 836 837/* Make strings word-aligned so strcpy from constants will be faster. */ 838#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 839 ((TREE_CODE (EXP) == STRING_CST \ 840 && (ALIGN) < FASTEST_ALIGNMENT) \ 841 ? FASTEST_ALIGNMENT : (ALIGN)) 842 843/* Make arrays of chars word-aligned for the same reasons. */ 844#define DATA_ALIGNMENT(TYPE, ALIGN) \ 845 (TREE_CODE (TYPE) == ARRAY_TYPE \ 846 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 847 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 848 849/* Set this nonzero if move instructions will actually fail to work 850 when given unaligned data. */ 851#define STRICT_ALIGNMENT 1 852 853/* Things that must be doubleword aligned cannot go in the text section, 854 because the linker fails to align the text section enough! 855 Put them in the data section. This macro is only used in this file. */ 856#define MAX_TEXT_ALIGN 32 857 858/* This forces all variables and constants to the data section when PIC. 859 This is because the SunOS 4 shared library scheme thinks everything in 860 text is a function, and patches the address to point to a loader stub. */ 861/* This is defined to zero for every system which doesn't use the a.out object 862 file format. */ 863#ifndef SUNOS4_SHARED_LIBRARIES 864#define SUNOS4_SHARED_LIBRARIES 0 865#endif 866 867/* Standard register usage. */ 868 869/* Number of actual hardware registers. 870 The hardware registers are assigned numbers for the compiler 871 from 0 to just below FIRST_PSEUDO_REGISTER. 872 All registers that the compiler knows about must be given numbers, 873 even those that are not normally considered general registers. 874 875 SPARC has 32 integer registers and 32 floating point registers. 876 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not 877 accessible. We still account for them to simplify register computations 878 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 879 32+32+32+4 == 100. 880 Register 100 is used as the integer condition code register. 881 Register 101 is used as the soft frame pointer register. */ 882 883#define FIRST_PSEUDO_REGISTER 102 884 885#define SPARC_FIRST_FP_REG 32 886/* Additional V9 fp regs. */ 887#define SPARC_FIRST_V9_FP_REG 64 888#define SPARC_LAST_V9_FP_REG 95 889/* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 890#define SPARC_FIRST_V9_FCC_REG 96 891#define SPARC_LAST_V9_FCC_REG 99 892/* V8 fcc reg. */ 893#define SPARC_FCC_REG 96 894/* Integer CC reg. We don't distinguish %icc from %xcc. */ 895#define SPARC_ICC_REG 100 896 897/* Nonzero if REGNO is an fp reg. */ 898#define SPARC_FP_REG_P(REGNO) \ 899((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 900 901/* Argument passing regs. */ 902#define SPARC_OUTGOING_INT_ARG_FIRST 8 903#define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 904#define SPARC_FP_ARG_FIRST 32 905 906/* 1 for registers that have pervasive standard uses 907 and are not available for the register allocator. 908 909 On non-v9 systems: 910 g1 is free to use as temporary. 911 g2-g4 are reserved for applications. Gcc normally uses them as 912 temporaries, but this can be disabled via the -mno-app-regs option. 913 g5 through g7 are reserved for the operating system. 914 915 On v9 systems: 916 g1,g5 are free to use as temporaries, and are free to use between calls 917 if the call is to an external function via the PLT. 918 g4 is free to use as a temporary in the non-embedded case. 919 g4 is reserved in the embedded case. 920 g2-g3 are reserved for applications. Gcc normally uses them as 921 temporaries, but this can be disabled via the -mno-app-regs option. 922 g6-g7 are reserved for the operating system (or application in 923 embedded case). 924 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 925 currently be a fixed register until this pattern is rewritten. 926 Register 1 is also used when restoring call-preserved registers in large 927 stack frames. 928 929 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 930 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 931*/ 932 933#define FIXED_REGISTERS \ 934 {1, 0, 2, 2, 2, 2, 1, 1, \ 935 0, 0, 0, 0, 0, 0, 1, 0, \ 936 0, 0, 0, 0, 0, 0, 0, 0, \ 937 0, 0, 0, 0, 0, 0, 1, 1, \ 938 \ 939 0, 0, 0, 0, 0, 0, 0, 0, \ 940 0, 0, 0, 0, 0, 0, 0, 0, \ 941 0, 0, 0, 0, 0, 0, 0, 0, \ 942 0, 0, 0, 0, 0, 0, 0, 0, \ 943 \ 944 0, 0, 0, 0, 0, 0, 0, 0, \ 945 0, 0, 0, 0, 0, 0, 0, 0, \ 946 0, 0, 0, 0, 0, 0, 0, 0, \ 947 0, 0, 0, 0, 0, 0, 0, 0, \ 948 \ 949 0, 0, 0, 0, 0, 1} 950 951/* 1 for registers not available across function calls. 952 These must include the FIXED_REGISTERS and also any 953 registers that can be used without being saved. 954 The latter must include the registers where values are returned 955 and the register where structure-value addresses are passed. 956 Aside from that, you can include as many other registers as you like. */ 957 958#define CALL_USED_REGISTERS \ 959 {1, 1, 1, 1, 1, 1, 1, 1, \ 960 1, 1, 1, 1, 1, 1, 1, 1, \ 961 0, 0, 0, 0, 0, 0, 0, 0, \ 962 0, 0, 0, 0, 0, 0, 1, 1, \ 963 \ 964 1, 1, 1, 1, 1, 1, 1, 1, \ 965 1, 1, 1, 1, 1, 1, 1, 1, \ 966 1, 1, 1, 1, 1, 1, 1, 1, \ 967 1, 1, 1, 1, 1, 1, 1, 1, \ 968 \ 969 1, 1, 1, 1, 1, 1, 1, 1, \ 970 1, 1, 1, 1, 1, 1, 1, 1, \ 971 1, 1, 1, 1, 1, 1, 1, 1, \ 972 1, 1, 1, 1, 1, 1, 1, 1, \ 973 \ 974 1, 1, 1, 1, 1, 1} 975 976/* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that 977 they won't be allocated. */ 978 979#define CONDITIONAL_REGISTER_USAGE \ 980do \ 981 { \ 982 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 983 { \ 984 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 985 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 986 } \ 987 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ 988 /* then honor it. */ \ 989 if (TARGET_ARCH32 && fixed_regs[5]) \ 990 fixed_regs[5] = 1; \ 991 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ 992 fixed_regs[5] = 0; \ 993 if (! TARGET_V9) \ 994 { \ 995 int regno; \ 996 for (regno = SPARC_FIRST_V9_FP_REG; \ 997 regno <= SPARC_LAST_V9_FP_REG; \ 998 regno++) \ 999 fixed_regs[regno] = 1; \ 1000 /* %fcc0 is used by v8 and v9. */ \ 1001 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ 1002 regno <= SPARC_LAST_V9_FCC_REG; \ 1003 regno++) \ 1004 fixed_regs[regno] = 1; \ 1005 } \ 1006 if (! TARGET_FPU) \ 1007 { \ 1008 int regno; \ 1009 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ 1010 fixed_regs[regno] = 1; \ 1011 } \ 1012 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ 1013 /* then honor it. Likewise with g3 and g4. */ \ 1014 if (fixed_regs[2] == 2) \ 1015 fixed_regs[2] = ! TARGET_APP_REGS; \ 1016 if (fixed_regs[3] == 2) \ 1017 fixed_regs[3] = ! TARGET_APP_REGS; \ 1018 if (TARGET_ARCH32 && fixed_regs[4] == 2) \ 1019 fixed_regs[4] = ! TARGET_APP_REGS; \ 1020 else if (TARGET_CM_EMBMEDANY) \ 1021 fixed_regs[4] = 1; \ 1022 else if (fixed_regs[4] == 2) \ 1023 fixed_regs[4] = 0; \ 1024 if (TARGET_FLAT) \ 1025 { \ 1026 int regno; \ 1027 /* Let the compiler believe the frame pointer is still \ 1028 %fp, but output it as %i7. */ \ 1029 fixed_regs[31] = 1; \ 1030 reg_names[HARD_FRAME_POINTER_REGNUM] = "%i7"; \ 1031 /* Disable leaf functions */ \ 1032 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); \ 1033 /* Make LEAF_REG_REMAP a noop. */ \ 1034 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ 1035 leaf_reg_remap [regno] = regno; \ 1036 } \ 1037 } \ 1038while (0) 1039 1040/* Return number of consecutive hard regs needed starting at reg REGNO 1041 to hold something of mode MODE. 1042 This is ordinarily the length in words of a value of mode MODE 1043 but can be less for certain modes in special long registers. 1044 1045 On SPARC, ordinary registers hold 32 bits worth; 1046 this means both integer and floating point registers. 1047 On v9, integer regs hold 64 bits worth; floating point regs hold 1048 32 bits worth (this includes the new fp regs as even the odd ones are 1049 included in the hard register count). */ 1050 1051#define HARD_REGNO_NREGS(REGNO, MODE) \ 1052 (TARGET_ARCH64 \ 1053 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ 1054 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 1055 : (GET_MODE_SIZE (MODE) + 3) / 4) \ 1056 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1057 1058/* Due to the ARCH64 discrepancy above we must override this next 1059 macro too. */ 1060#define REGMODE_NATURAL_SIZE(MODE) \ 1061 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) 1062 1063/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 1064 See sparc.c for how we initialize this. */ 1065extern const int *hard_regno_mode_classes; 1066extern int sparc_mode_class[]; 1067 1068/* ??? Because of the funny way we pass parameters we should allow certain 1069 ??? types of float/complex values to be in integer registers during 1070 ??? RTL generation. This only matters on arch32. */ 1071#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1072 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 1073 1074/* Value is 1 if it is a good idea to tie two pseudo registers 1075 when one has mode MODE1 and one has mode MODE2. 1076 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1077 for any hard reg, then this must be 0 for correct output. 1078 1079 For V9: SFmode can't be combined with other float modes, because they can't 1080 be allocated to the %d registers. Also, DFmode won't fit in odd %f 1081 registers, but SFmode will. */ 1082#define MODES_TIEABLE_P(MODE1, MODE2) \ 1083 ((MODE1) == (MODE2) \ 1084 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 1085 && (! TARGET_V9 \ 1086 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ 1087 || (MODE1 != SFmode && MODE2 != SFmode))))) 1088 1089/* Specify the registers used for certain standard purposes. 1090 The values of these macros are register numbers. */ 1091 1092/* SPARC pc isn't overloaded on a register that the compiler knows about. */ 1093/* #define PC_REGNUM */ 1094 1095/* Register to use for pushing function arguments. */ 1096#define STACK_POINTER_REGNUM 14 1097 1098/* The stack bias (amount by which the hardware register is offset by). */ 1099#define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 1100 1101/* Actual top-of-stack address is 92/176 greater than the contents of the 1102 stack pointer register for !v9/v9. That is: 1103 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 1104 address, and 6*4 bytes for the 6 register parameters. 1105 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 1106 parameter regs. */ 1107#define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 1108 1109/* Base register for access to local variables of the function. */ 1110#define HARD_FRAME_POINTER_REGNUM 30 1111 1112/* The soft frame pointer does not have the stack bias applied. */ 1113#define FRAME_POINTER_REGNUM 101 1114 1115/* Given the stack bias, the stack pointer isn't actually aligned. */ 1116#define INIT_EXPANDERS \ 1117 do { \ 1118 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \ 1119 { \ 1120 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ 1121 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ 1122 } \ 1123 } while (0) 1124 1125/* Value should be nonzero if functions must have frame pointers. 1126 Zero means the frame pointer need not be set up (and parms 1127 may be accessed via the stack pointer) in functions that seem suitable. 1128 This is computed in `reload', in reload1.c. 1129 Used in flow.c, global.c, and reload1.c. 1130 1131 Being a non-leaf function does not mean a frame pointer is needed in the 1132 flat window model. However, the debugger won't be able to backtrace through 1133 us with out it. */ 1134#define FRAME_POINTER_REQUIRED \ 1135 (TARGET_FLAT \ 1136 ? (current_function_calls_alloca \ 1137 || !leaf_function_p ()) \ 1138 : ! (leaf_function_p () && only_leaf_regs_used ())) 1139 1140/* Base register for access to arguments of the function. */ 1141#define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 1142 1143/* Register in which static-chain is passed to a function. This must 1144 not be a register used by the prologue. */ 1145#define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 1146 1147/* Register which holds offset table for position-independent 1148 data references. */ 1149 1150#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM) 1151 1152/* Pick a default value we can notice from override_options: 1153 !v9: Default is on. 1154 v9: Default is off. */ 1155 1156#define DEFAULT_PCC_STRUCT_RETURN -1 1157 1158/* SPARC ABI says that quad-precision floats and all structures are returned 1159 in memory. 1160 For v9: unions <= 32 bytes in size are returned in int regs, 1161 structures up to 32 bytes are returned in int and fp regs. */ 1162 1163#define RETURN_IN_MEMORY(TYPE) \ 1164(TARGET_ARCH32 \ 1165 ? (TYPE_MODE (TYPE) == BLKmode \ 1166 || TYPE_MODE (TYPE) == TFmode) \ 1167 : (TYPE_MODE (TYPE) == BLKmode \ 1168 && (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 32)) 1169 1170/* Functions which return large structures get the address 1171 to place the wanted value at offset 64 from the frame. 1172 Must reserve 64 bytes for the in and local registers. 1173 v9: Functions which return large structures get the address to place the 1174 wanted value from an invisible first argument. */ 1175/* Used only in other #defines in this file. */ 1176#define STRUCT_VALUE_OFFSET 64 1177 1178#define STRUCT_VALUE \ 1179 (TARGET_ARCH64 \ 1180 ? 0 \ 1181 : gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \ 1182 STRUCT_VALUE_OFFSET))) 1183 1184#define STRUCT_VALUE_INCOMING \ 1185 (TARGET_ARCH64 \ 1186 ? 0 \ 1187 : gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, \ 1188 STRUCT_VALUE_OFFSET))) 1189 1190/* Define the classes of registers for register constraints in the 1191 machine description. Also define ranges of constants. 1192 1193 One of the classes must always be named ALL_REGS and include all hard regs. 1194 If there is more than one class, another class must be named NO_REGS 1195 and contain no registers. 1196 1197 The name GENERAL_REGS must be the name of a class (or an alias for 1198 another name such as ALL_REGS). This is the class of registers 1199 that is allowed by "g" or "r" in a register constraint. 1200 Also, registers outside this class are allocated only when 1201 instructions express preferences for them. 1202 1203 The classes must be numbered in nondecreasing order; that is, 1204 a larger-numbered class must never be contained completely 1205 in a smaller-numbered class. 1206 1207 For any two classes, it is very desirable that there be another 1208 class that represents their union. */ 1209 1210/* The SPARC has various kinds of registers: general, floating point, 1211 and condition codes [well, it has others as well, but none that we 1212 care directly about]. 1213 1214 For v9 we must distinguish between the upper and lower floating point 1215 registers because the upper ones can't hold SFmode values. 1216 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 1217 satisfying a group need for a class will also satisfy a single need for 1218 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 1219 regs. 1220 1221 It is important that one class contains all the general and all the standard 1222 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 1223 because reg_class_record() will bias the selection in favor of fp regs, 1224 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 1225 because FP_REGS > GENERAL_REGS. 1226 1227 It is also important that one class contain all the general and all the 1228 fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS 1229 but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause 1230 allocate_reload_reg() to bypass it causing an abort because the compiler 1231 thinks it doesn't have a spill reg when in fact it does. 1232 1233 v9 also has 4 floating point condition code registers. Since we don't 1234 have a class that is the union of FPCC_REGS with either of the others, 1235 it is important that it appear first. Otherwise the compiler will die 1236 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 1237 constraints. 1238 1239 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine 1240 may try to use it to hold an SImode value. See register_operand. 1241 ??? Should %fcc[0123] be handled similarly? 1242*/ 1243 1244enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 1245 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 1246 ALL_REGS, LIM_REG_CLASSES }; 1247 1248#define N_REG_CLASSES (int) LIM_REG_CLASSES 1249 1250/* Give names of register classes as strings for dump file. */ 1251 1252#define REG_CLASS_NAMES \ 1253 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 1254 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 1255 "ALL_REGS" } 1256 1257/* Define which registers fit in which classes. 1258 This is an initializer for a vector of HARD_REG_SET 1259 of length N_REG_CLASSES. */ 1260 1261#define REG_CLASS_CONTENTS \ 1262 {{0, 0, 0, 0}, /* NO_REGS */ \ 1263 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 1264 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 1265 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 1266 {0, -1, 0, 0}, /* FP_REGS */ \ 1267 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 1268 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 1269 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 1270 {-1, -1, -1, 0x3f}} /* ALL_REGS */ 1271 1272/* Defines invalid mode changes. Borrowed from pa64-regs.h. 1273 1274 SImode loads to floating-point registers are not zero-extended. 1275 The definition for LOAD_EXTEND_OP specifies that integer loads 1276 narrower than BITS_PER_WORD will be zero-extended. As a result, 1277 we inhibit changes from SImode unless they are to a mode that is 1278 identical in size. */ 1279 1280#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1281 (TARGET_ARCH64 \ 1282 && (FROM) == SImode \ 1283 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1284 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 1285 1286/* The same information, inverted: 1287 Return the class number of the smallest class containing 1288 reg number REGNO. This could be a conditional expression 1289 or could index an array. */ 1290 1291extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 1292 1293#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 1294 1295/* This is the order in which to allocate registers normally. 1296 1297 We put %f0-%f7 last among the float registers, so as to make it more 1298 likely that a pseudo-register which dies in the float return register 1299 area will get allocated to the float return register, thus saving a move 1300 instruction at the end of the function. 1301 1302 Similarly for integer return value registers. 1303 1304 We know in this case that we will not end up with a leaf function. 1305 1306 The register allocator is given the global and out registers first 1307 because these registers are call clobbered and thus less useful to 1308 global register allocation. 1309 1310 Next we list the local and in registers. They are not call clobbered 1311 and thus very useful for global register allocation. We list the input 1312 registers before the locals so that it is more likely the incoming 1313 arguments received in those registers can just stay there and not be 1314 reloaded. */ 1315 1316#define REG_ALLOC_ORDER \ 1317{ 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1318 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1319 15, /* %o7 */ \ 1320 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1321 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 1322 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1323 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1324 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1325 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1326 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1327 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1328 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1329 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1330 96, 97, 98, 99, /* %fcc0-3 */ \ 1331 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ 1332 1333/* This is the order in which to allocate registers for 1334 leaf functions. If all registers can fit in the global and 1335 output registers, then we have the possibility of having a leaf 1336 function. 1337 1338 The macro actually mentioned the input registers first, 1339 because they get renumbered into the output registers once 1340 we know really do have a leaf function. 1341 1342 To be more precise, this register allocation order is used 1343 when %o7 is found to not be clobbered right before register 1344 allocation. Normally, the reason %o7 would be clobbered is 1345 due to a call which could not be transformed into a sibling 1346 call. 1347 1348 As a consequence, it is possible to use the leaf register 1349 allocation order and not end up with a leaf function. We will 1350 not get suboptimal register allocation in that case because by 1351 definition of being potentially leaf, there were no function 1352 calls. Therefore, allocation order within the local register 1353 window is not critical like it is when we do have function calls. */ 1354 1355#define REG_LEAF_ALLOC_ORDER \ 1356{ 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1357 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 1358 15, /* %o7 */ \ 1359 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1360 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1361 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1362 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1363 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1364 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1365 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1366 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1367 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1368 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1369 96, 97, 98, 99, /* %fcc0-3 */ \ 1370 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ 1371 1372#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 1373 1374extern char sparc_leaf_regs[]; 1375#define LEAF_REGISTERS sparc_leaf_regs 1376 1377extern char leaf_reg_remap[]; 1378#define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1379 1380/* The class value for index registers, and the one for base regs. */ 1381#define INDEX_REG_CLASS GENERAL_REGS 1382#define BASE_REG_CLASS GENERAL_REGS 1383 1384/* Local macro to handle the two v9 classes of FP regs. */ 1385#define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1386 1387/* Get reg_class from a letter such as appears in the machine description. 1388 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the 1389 .md file for v8 and v9. 1390 'd' and 'b' are used for single and double precision VIS operations, 1391 if TARGET_VIS. 1392 'h' is used for V8+ 64 bit global and out registers. */ 1393 1394#define REG_CLASS_FROM_LETTER(C) \ 1395(TARGET_V9 \ 1396 ? ((C) == 'f' ? FP_REGS \ 1397 : (C) == 'e' ? EXTRA_FP_REGS \ 1398 : (C) == 'c' ? FPCC_REGS \ 1399 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\ 1400 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\ 1401 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\ 1402 : NO_REGS) \ 1403 : ((C) == 'f' ? FP_REGS \ 1404 : (C) == 'e' ? FP_REGS \ 1405 : (C) == 'c' ? FPCC_REGS \ 1406 : NO_REGS)) 1407 1408/* The letters I, J, K, L and M in a register constraint string 1409 can be used to stand for particular ranges of immediate operands. 1410 This macro defines what the ranges are. 1411 C is the letter, and VALUE is a constant value. 1412 Return 1 if VALUE is in the range specified by C. 1413 1414 `I' is used for the range of constants an insn can actually contain. 1415 `J' is used for the range which is just zero (since that is R0). 1416 `K' is used for constants which can be loaded with a single sethi insn. 1417 `L' is used for the range of constants supported by the movcc insns. 1418 `M' is used for the range of constants supported by the movrcc insns. 1419 `N' is like K, but for constants wider than 32 bits. 1420 `O' is used for the range which is just 4096. */ 1421 1422#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1423#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1424#define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1425/* 10 and 11 bit immediates are only used for a few specific insns. 1426 SMALL_INT is used throughout the port so we continue to use it. */ 1427#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1428/* 13 bit immediate, considering only the low 32 bits */ 1429#define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \ 1430 (INTVAL (X), SImode))) 1431#define SPARC_SETHI_P(X) \ 1432 (((unsigned HOST_WIDE_INT) (X) \ 1433 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1434#define SPARC_SETHI32_P(X) \ 1435 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1436 1437#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1438 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \ 1439 : (C) == 'J' ? (VALUE) == 0 \ 1440 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \ 1441 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ 1442 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ 1443 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \ 1444 : (C) == 'O' ? (VALUE) == 4096 \ 1445 : 0) 1446 1447/* Similar, but for floating constants, and defining letters G and H. 1448 Here VALUE is the CONST_DOUBLE rtx itself. */ 1449 1450#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1451 ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \ 1452 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ 1453 : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \ 1454 : 0) 1455 1456/* Given an rtx X being reloaded into a reg required to be 1457 in class CLASS, return the class of reg to actually use. 1458 In general this is just CLASS; but on some machines 1459 in some cases it is preferable to use a more restrictive class. */ 1460/* - We can't load constants into FP registers. 1461 - We can't load FP constants into integer registers when soft-float, 1462 because there is no soft-float pattern with a r/F constraint. 1463 - We can't load FP constants into integer registers for TFmode unless 1464 it is 0.0L, because there is no movtf pattern with a r/F constraint. 1465 - Try and reload integer constants (symbolic or otherwise) back into 1466 registers directly, rather than having them dumped to memory. */ 1467 1468#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1469 (CONSTANT_P (X) \ 1470 ? ((FP_REG_CLASS_P (CLASS) \ 1471 || (CLASS) == GENERAL_OR_FP_REGS \ 1472 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \ 1473 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1474 && ! TARGET_FPU) \ 1475 || (GET_MODE (X) == TFmode \ 1476 && ! fp_zero_operand (X, TFmode))) \ 1477 ? NO_REGS \ 1478 : (!FP_REG_CLASS_P (CLASS) \ 1479 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ 1480 ? GENERAL_REGS \ 1481 : (CLASS)) \ 1482 : (CLASS)) 1483 1484/* Return the register class of a scratch register needed to load IN into 1485 a register of class CLASS in MODE. 1486 1487 We need a temporary when loading/storing a HImode/QImode value 1488 between memory and the FPU registers. This can happen when combine puts 1489 a paradoxical subreg in a float/fix conversion insn. 1490 1491 We need a temporary when loading/storing a DFmode value between 1492 unaligned memory and the upper FPU registers. */ 1493 1494#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1495 ((FP_REG_CLASS_P (CLASS) \ 1496 && ((MODE) == HImode || (MODE) == QImode) \ 1497 && (GET_CODE (IN) == MEM \ 1498 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1499 && true_regnum (IN) == -1))) \ 1500 ? GENERAL_REGS \ 1501 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1502 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1503 && ! mem_min_alignment ((IN), 8)) \ 1504 ? FP_REGS \ 1505 : (((TARGET_CM_MEDANY \ 1506 && symbolic_operand ((IN), (MODE))) \ 1507 || (TARGET_CM_EMBMEDANY \ 1508 && text_segment_operand ((IN), (MODE)))) \ 1509 && !flag_pic) \ 1510 ? GENERAL_REGS \ 1511 : NO_REGS) 1512 1513#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1514 ((FP_REG_CLASS_P (CLASS) \ 1515 && ((MODE) == HImode || (MODE) == QImode) \ 1516 && (GET_CODE (IN) == MEM \ 1517 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1518 && true_regnum (IN) == -1))) \ 1519 ? GENERAL_REGS \ 1520 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1521 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1522 && ! mem_min_alignment ((IN), 8)) \ 1523 ? FP_REGS \ 1524 : (((TARGET_CM_MEDANY \ 1525 && symbolic_operand ((IN), (MODE))) \ 1526 || (TARGET_CM_EMBMEDANY \ 1527 && text_segment_operand ((IN), (MODE)))) \ 1528 && !flag_pic) \ 1529 ? GENERAL_REGS \ 1530 : NO_REGS) 1531 1532/* On SPARC it is not possible to directly move data between 1533 GENERAL_REGS and FP_REGS. */ 1534#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1535 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1536 1537/* Return the stack location to use for secondary memory needed reloads. 1538 We want to use the reserved location just below the frame pointer. 1539 However, we must ensure that there is a frame, so use assign_stack_local 1540 if the frame size is zero. */ 1541#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1542 (get_frame_size () == 0 \ 1543 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \ 1544 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \ 1545 STARTING_FRAME_OFFSET))) 1546 1547/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 1548 because the movsi and movsf patterns don't handle r/f moves. 1549 For v8 we copy the default definition. */ 1550#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1551 (TARGET_ARCH64 \ 1552 ? (GET_MODE_BITSIZE (MODE) < 32 \ 1553 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1554 : MODE) \ 1555 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1556 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1557 : MODE)) 1558 1559/* Return the maximum number of consecutive registers 1560 needed to represent mode MODE in a register of class CLASS. */ 1561/* On SPARC, this is the size of MODE in words. */ 1562#define CLASS_MAX_NREGS(CLASS, MODE) \ 1563 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1564 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1565 1566/* Stack layout; function entry, exit and calling. */ 1567 1568/* Define the number of register that can hold parameters. 1569 This macro is only used in other macro definitions below and in sparc.c. 1570 MODE is the mode of the argument. 1571 !v9: All args are passed in %o0-%o5. 1572 v9: %o0-%o5 and %f0-%f31 are cumulatively used to pass values. 1573 See the description in sparc.c. */ 1574#define NPARM_REGS(MODE) \ 1575(TARGET_ARCH64 \ 1576 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 6) \ 1577 : 6) 1578 1579/* Define this if pushing a word on the stack 1580 makes the stack pointer a smaller address. */ 1581#define STACK_GROWS_DOWNWARD 1582 1583/* Define this if the nominal address of the stack frame 1584 is at the high-address end of the local variables; 1585 that is, each additional local variable allocated 1586 goes at a more negative offset in the frame. */ 1587#define FRAME_GROWS_DOWNWARD 1588 1589/* Offset within stack frame to start allocating local variables at. 1590 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1591 first local allocated. Otherwise, it is the offset to the BEGINNING 1592 of the first local allocated. */ 1593/* This allows space for one TFmode floating point value. */ 1594#define STARTING_FRAME_OFFSET \ 1595 (TARGET_ARCH64 ? -16 \ 1596 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))) 1597 1598/* If we generate an insn to push BYTES bytes, 1599 this says how many the stack pointer really advances by. 1600 On SPARC, don't define this because there are no push insns. */ 1601/* #define PUSH_ROUNDING(BYTES) */ 1602 1603/* Offset of first parameter from the argument pointer register value. 1604 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1605 even if this function isn't going to use it. 1606 v9: This is 128 for the ins and locals. */ 1607#define FIRST_PARM_OFFSET(FNDECL) \ 1608 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1609 1610/* Offset from the argument pointer register value to the CFA. 1611 This is different from FIRST_PARM_OFFSET because the register window 1612 comes between the CFA and the arguments. */ 1613#define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1614 1615/* When a parameter is passed in a register, stack space is still 1616 allocated for it. 1617 !v9: All 6 possible integer registers have backing store allocated. 1618 v9: Only space for the arguments passed is allocated. */ 1619/* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1620 meaning to the backend. Further, we need to be able to detect if a 1621 varargs/unprototyped function is called, as they may want to spill more 1622 registers than we've provided space. Ugly, ugly. So for now we retain 1623 all 6 slots even for v9. */ 1624#define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1625 1626/* Definitions for register elimination. */ 1627/* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */ 1628 1629#define ELIMINABLE_REGS \ 1630 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1631 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1632 1633/* The way this is structured, we can't eliminate SFP in favor of SP 1634 if the frame pointer is required: we want to use the SFP->HFP elimination 1635 in that case. But the test in update_eliminables doesn't know we are 1636 assuming below that we only do the former elimination. */ 1637#define CAN_ELIMINATE(FROM, TO) \ 1638 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED) 1639 1640#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1641 do { \ 1642 (OFFSET) = 0; \ 1643 if ((TO) == STACK_POINTER_REGNUM) \ 1644 { \ 1645 /* Note, we always pretend that this is a leaf function \ 1646 because if it's not, there's no point in trying to \ 1647 eliminate the frame pointer. If it is a leaf \ 1648 function, we guessed right! */ \ 1649 if (TARGET_FLAT) \ 1650 (OFFSET) = \ 1651 sparc_flat_compute_frame_size (get_frame_size ()); \ 1652 else \ 1653 (OFFSET) = compute_frame_size (get_frame_size (), 1); \ 1654 } \ 1655 (OFFSET) += SPARC_STACK_BIAS; \ 1656 } while (0) 1657 1658/* Keep the stack pointer constant throughout the function. 1659 This is both an optimization and a necessity: longjmp 1660 doesn't behave itself when the stack pointer moves within 1661 the function! */ 1662#define ACCUMULATE_OUTGOING_ARGS 1 1663 1664/* Value is the number of bytes of arguments automatically 1665 popped when returning from a subroutine call. 1666 FUNDECL is the declaration node of the function (as a tree), 1667 FUNTYPE is the data type of the function (as a tree), 1668 or for a library call it is an identifier node for the subroutine name. 1669 SIZE is the number of bytes of arguments passed on the stack. */ 1670 1671#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1672 1673/* Some subroutine macros specific to this machine. 1674 When !TARGET_FPU, put float return values in the general registers, 1675 since we don't have any fp registers. */ 1676#define BASE_RETURN_VALUE_REG(MODE) \ 1677 (TARGET_ARCH64 \ 1678 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ 1679 : (TARGET_FPU && FLOAT_MODE_P (MODE) && (MODE) != TFmode ? 32 : 8)) 1680 1681#define BASE_OUTGOING_VALUE_REG(MODE) \ 1682 (TARGET_ARCH64 \ 1683 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ 1684 : TARGET_FLAT ? 8 : 24) \ 1685 : (TARGET_FPU && FLOAT_MODE_P (MODE) && (MODE) != TFmode ? 32\ 1686 : (TARGET_FLAT ? 8 : 24))) 1687 1688#define BASE_PASSING_ARG_REG(MODE) \ 1689 (TARGET_ARCH64 \ 1690 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 : 8) \ 1691 : 8) 1692 1693/* ??? FIXME -- seems wrong for v9 structure passing... */ 1694#define BASE_INCOMING_ARG_REG(MODE) \ 1695 (TARGET_ARCH64 \ 1696 ? (TARGET_FPU && FLOAT_MODE_P (MODE) ? 32 \ 1697 : TARGET_FLAT ? 8 : 24) \ 1698 : (TARGET_FLAT ? 8 : 24)) 1699 1700/* Define this macro if the target machine has "register windows". This 1701 C expression returns the register number as seen by the called function 1702 corresponding to register number OUT as seen by the calling function. 1703 Return OUT if register number OUT is not an outbound register. */ 1704 1705#define INCOMING_REGNO(OUT) \ 1706 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1707 1708/* Define this macro if the target machine has "register windows". This 1709 C expression returns the register number as seen by the calling function 1710 corresponding to register number IN as seen by the called function. 1711 Return IN if register number IN is not an inbound register. */ 1712 1713#define OUTGOING_REGNO(IN) \ 1714 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1715 1716/* Define this macro if the target machine has register windows. This 1717 C expression returns true if the register is call-saved but is in the 1718 register window. */ 1719 1720#define LOCAL_REGNO(REGNO) \ 1721 (TARGET_FLAT ? 0 : (REGNO) >= 16 && (REGNO) <= 31) 1722 1723/* Define how to find the value returned by a function. 1724 VALTYPE is the data type of the value (as a tree). 1725 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1726 otherwise, FUNC is 0. */ 1727 1728/* On SPARC the value is found in the first "output" register. */ 1729 1730#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1731 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) 1732 1733/* But the called function leaves it in the first "input" register. */ 1734 1735#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1736 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) 1737 1738/* Define how to find the value returned by a library function 1739 assuming the value has mode MODE. */ 1740 1741#define LIBCALL_VALUE(MODE) \ 1742 function_value (NULL_TREE, (MODE), 1) 1743 1744/* 1 if N is a possible register number for a function value 1745 as seen by the caller. 1746 On SPARC, the first "output" reg is used for integer values, 1747 and the first floating point register is used for floating point values. */ 1748 1749#define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1750 1751/* Define the size of space to allocate for the return value of an 1752 untyped_call. */ 1753 1754#define APPLY_RESULT_SIZE 16 1755 1756/* 1 if N is a possible register number for function argument passing. 1757 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1758 1759#define FUNCTION_ARG_REGNO_P(N) \ 1760(TARGET_ARCH64 \ 1761 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ 1762 : ((N) >= 8 && (N) <= 13)) 1763 1764/* Define a data type for recording info about an argument list 1765 during the scan of that argument list. This data type should 1766 hold all necessary information about the function itself 1767 and about the args processed so far, enough to enable macros 1768 such as FUNCTION_ARG to determine where the next arg should go. 1769 1770 On SPARC (!v9), this is a single integer, which is a number of words 1771 of arguments scanned so far (including the invisible argument, 1772 if any, which holds the structure-value-address). 1773 Thus 7 or more means all following args should go on the stack. 1774 1775 For v9, we also need to know whether a prototype is present. */ 1776 1777struct sparc_args { 1778 int words; /* number of words passed so far */ 1779 int prototype_p; /* nonzero if a prototype is present */ 1780 int libcall_p; /* nonzero if a library call */ 1781}; 1782#define CUMULATIVE_ARGS struct sparc_args 1783 1784/* Initialize a variable CUM of type CUMULATIVE_ARGS 1785 for a call to a function whose data type is FNTYPE. 1786 For a library call, FNTYPE is 0. */ 1787 1788#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1789init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1790 1791/* Update the data in CUM to advance over an argument 1792 of mode MODE and data type TYPE. 1793 TYPE is null for libcalls where that information may not be available. */ 1794 1795#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1796function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) 1797 1798/* Nonzero if we do not know how to pass TYPE solely in registers. */ 1799 1800#define MUST_PASS_IN_STACK(MODE,TYPE) \ 1801 ((TYPE) != 0 \ 1802 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1803 || TREE_ADDRESSABLE (TYPE))) 1804 1805/* Determine where to put an argument to a function. 1806 Value is zero to push the argument on the stack, 1807 or a hard register in which to store the argument. 1808 1809 MODE is the argument's machine mode. 1810 TYPE is the data type of the argument (as a tree). 1811 This is null for libcalls where that information may 1812 not be available. 1813 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1814 the preceding args and about the function being called. 1815 NAMED is nonzero if this argument is a named parameter 1816 (otherwise it is an extra parameter matching an ellipsis). */ 1817 1818#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1819function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) 1820 1821/* Define where a function finds its arguments. 1822 This is different from FUNCTION_ARG because of register windows. */ 1823 1824#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1825function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) 1826 1827/* For an arg passed partly in registers and partly in memory, 1828 this is the number of registers used. 1829 For args passed entirely in registers or entirely in memory, zero. */ 1830 1831#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1832function_arg_partial_nregs (& (CUM), (MODE), (TYPE), (NAMED)) 1833 1834/* A C expression that indicates when an argument must be passed by reference. 1835 If nonzero for an argument, a copy of that argument is made in memory and a 1836 pointer to the argument is passed instead of the argument itself. 1837 The pointer is passed in whatever way is appropriate for passing a pointer 1838 to that type. */ 1839 1840#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1841function_arg_pass_by_reference (& (CUM), (MODE), (TYPE), (NAMED)) 1842 1843/* If defined, a C expression which determines whether, and in which direction, 1844 to pad out an argument with extra space. The value should be of type 1845 `enum direction': either `upward' to pad above the argument, 1846 `downward' to pad below, or `none' to inhibit padding. */ 1847 1848#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1849function_arg_padding ((MODE), (TYPE)) 1850 1851/* If defined, a C expression that gives the alignment boundary, in bits, 1852 of an argument with the specified mode and type. If it is not defined, 1853 PARM_BOUNDARY is used for all arguments. 1854 For sparc64, objects requiring 16 byte alignment are passed that way. */ 1855 1856#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1857((TARGET_ARCH64 \ 1858 && (GET_MODE_ALIGNMENT (MODE) == 128 \ 1859 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ 1860 ? 128 : PARM_BOUNDARY) 1861 1862/* Define the information needed to generate branch and scc insns. This is 1863 stored from the compare operation. Note that we can't use "rtx" here 1864 since it hasn't been defined! */ 1865 1866extern GTY(()) rtx sparc_compare_op0; 1867extern GTY(()) rtx sparc_compare_op1; 1868 1869 1870/* Generate the special assembly code needed to tell the assembler whatever 1871 it might need to know about the return value of a function. 1872 1873 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1874 information to the assembler relating to peephole optimization (done in 1875 the assembler). */ 1876 1877#define ASM_DECLARE_RESULT(FILE, RESULT) \ 1878 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1879 1880/* Output the special assembly code needed to tell the assembler some 1881 register is used as global register variable. 1882 1883 SPARC 64bit psABI declares registers %g2 and %g3 as application 1884 registers and %g6 and %g7 as OS registers. Any object using them 1885 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1886 and how they are used (scratch or some global variable). 1887 Linker will then refuse to link together objects which use those 1888 registers incompatibly. 1889 1890 Unless the registers are used for scratch, two different global 1891 registers cannot be declared to the same name, so in the unlikely 1892 case of a global register variable occupying more than one register 1893 we prefix the second and following registers with .gnu.part1. etc. */ 1894 1895extern char sparc_hard_reg_printed[8]; 1896 1897#ifdef HAVE_AS_REGISTER_PSEUDO_OP 1898#define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1899do { \ 1900 if (TARGET_ARCH64) \ 1901 { \ 1902 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ 1903 int reg; \ 1904 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1905 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1906 { \ 1907 if (reg == (REGNO)) \ 1908 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1909 else \ 1910 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1911 reg, reg - (REGNO), (NAME)); \ 1912 sparc_hard_reg_printed[reg] = 1; \ 1913 } \ 1914 } \ 1915} while (0) 1916#endif 1917 1918 1919/* Emit rtl for profiling. */ 1920#define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1921 1922/* All the work done in PROFILE_HOOK, but still required. */ 1923#define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1924 1925/* Set the name of the mcount function for the system. */ 1926#define MCOUNT_FUNCTION "*mcount" 1927 1928/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1929 the stack pointer does not matter. The value is tested only in 1930 functions that have frame pointers. 1931 No definition is equivalent to always zero. */ 1932 1933#define EXIT_IGNORE_STACK \ 1934 (get_frame_size () != 0 \ 1935 || current_function_calls_alloca || current_function_outgoing_args_size) 1936 1937#define DELAY_SLOTS_FOR_EPILOGUE \ 1938 (TARGET_FLAT ? sparc_flat_epilogue_delay_slots () : 1) 1939#define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \ 1940 (TARGET_FLAT ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \ 1941 : eligible_for_epilogue_delay (trial, slots_filled)) 1942 1943/* Define registers used by the epilogue and return instruction. */ 1944#define EPILOGUE_USES(REGNO) \ 1945 (!TARGET_FLAT && REGNO == 31) 1946 1947/* Length in units of the trampoline for entering a nested function. */ 1948 1949#define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1950 1951#define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ 1952 1953/* Emit RTL insns to initialize the variable parts of a trampoline. 1954 FNADDR is an RTX for the address of the function's pure code. 1955 CXT is an RTX for the static chain value for the function. */ 1956 1957#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1958 if (TARGET_ARCH64) \ 1959 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \ 1960 else \ 1961 sparc_initialize_trampoline (TRAMP, FNADDR, CXT) 1962 1963/* Generate necessary RTL for __builtin_saveregs(). */ 1964 1965#define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs () 1966 1967/* Implement `va_start' for varargs and stdarg. */ 1968#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1969 sparc_va_start (valist, nextarg) 1970 1971/* Implement `va_arg'. */ 1972#define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1973 sparc_va_arg (valist, type) 1974 1975/* Define this macro if the location where a function argument is passed 1976 depends on whether or not it is a named argument. 1977 1978 This macro controls how the NAMED argument to FUNCTION_ARG 1979 is set for varargs and stdarg functions. With this macro defined, 1980 the NAMED argument is always true for named arguments, and false for 1981 unnamed arguments. If this is not defined, but SETUP_INCOMING_VARARGS 1982 is defined, then all arguments are treated as named. Otherwise, all named 1983 arguments except the last are treated as named. 1984 For the v9 we want NAMED to mean what it says it means. */ 1985 1986#define STRICT_ARGUMENT_NAMING TARGET_V9 1987 1988/* Generate RTL to flush the register windows so as to make arbitrary frames 1989 available. */ 1990#define SETUP_FRAME_ADDRESSES() \ 1991 emit_insn (gen_flush_register_windows ()) 1992 1993/* Given an rtx for the address of a frame, 1994 return an rtx for the address of the word in the frame 1995 that holds the dynamic chain--the previous frame's address. 1996 ??? -mflat support? */ 1997#define DYNAMIC_CHAIN_ADDRESS(frame) \ 1998 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1999 2000/* The return address isn't on the stack, it is in a register, so we can't 2001 access it from the current frame pointer. We can access it from the 2002 previous frame pointer though by reading a value from the register window 2003 save area. */ 2004#define RETURN_ADDR_IN_PREVIOUS_FRAME 2005 2006/* This is the offset of the return address to the true next instruction to be 2007 executed for the current function. */ 2008#define RETURN_ADDR_OFFSET \ 2009 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct)) 2010 2011/* The current return address is in %i7. The return address of anything 2012 farther back is in the register window save area at [%fp+60]. */ 2013/* ??? This ignores the fact that the actual return address is +8 for normal 2014 returns, and +12 for structure returns. */ 2015#define RETURN_ADDR_RTX(count, frame) \ 2016 ((count == -1) \ 2017 ? gen_rtx_REG (Pmode, 31) \ 2018 : gen_rtx_MEM (Pmode, \ 2019 memory_address (Pmode, plus_constant (frame, \ 2020 15 * UNITS_PER_WORD \ 2021 + SPARC_STACK_BIAS)))) 2022 2023/* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 2024 +12, but always using +8 is close enough for frame unwind purposes. 2025 Actually, just using %o7 is close enough for unwinding, but %o7+8 2026 is something you can return to. */ 2027#define INCOMING_RETURN_ADDR_RTX \ 2028 plus_constant (gen_rtx_REG (word_mode, 15), 8) 2029#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15) 2030 2031/* The offset from the incoming value of %sp to the top of the stack frame 2032 for the current function. On sparc64, we have to account for the stack 2033 bias if present. */ 2034#define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 2035 2036/* Describe how we implement __builtin_eh_return. */ 2037#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 2038#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */ 2039#define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */ 2040 2041/* Select a format to encode pointers in exception handling data. CODE 2042 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2043 true if the symbol may be affected by dynamic relocations. 2044 2045 If assembler and linker properly support .uaword %r_disp32(foo), 2046 then use PC relative 32-bit relocations instead of absolute relocs 2047 for shared libraries. On sparc64, use pc relative 32-bit relocs even 2048 for binaries, to save memory. 2049 2050 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 2051 symbol %r_disp32() is against was not local, but .hidden. In that 2052 case, we have to use DW_EH_PE_absptr for pic personality. */ 2053#ifdef HAVE_AS_SPARC_UA_PCREL 2054#ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 2055#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 2056 (flag_pic \ 2057 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 2058 : ((TARGET_ARCH64 && ! GLOBAL) \ 2059 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 2060 : DW_EH_PE_absptr)) 2061#else 2062#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 2063 (flag_pic \ 2064 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 2065 : ((TARGET_ARCH64 && ! GLOBAL) \ 2066 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 2067 : DW_EH_PE_absptr)) 2068#endif 2069 2070/* Emit a PC-relative relocation. */ 2071#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 2072 do { \ 2073 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 2074 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 2075 assemble_name (FILE, LABEL); \ 2076 fputc (')', FILE); \ 2077 } while (0) 2078#endif 2079 2080/* Addressing modes, and classification of registers for them. */ 2081 2082/* Macros to check register numbers against specific register classes. */ 2083 2084/* These assume that REGNO is a hard or pseudo reg number. 2085 They give nonzero only if REGNO is a hard reg of the suitable class 2086 or a pseudo reg currently allocated to a suitable hard reg. 2087 Since they use reg_renumber, they are safe only once reg_renumber 2088 has been allocated, which happens in local-alloc.c. */ 2089 2090#define REGNO_OK_FOR_INDEX_P(REGNO) \ 2091((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ 2092 || (REGNO) == FRAME_POINTER_REGNUM \ 2093 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 2094 2095#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 2096 2097#define REGNO_OK_FOR_FP_P(REGNO) \ 2098 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 2099 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 2100#define REGNO_OK_FOR_CCFP_P(REGNO) \ 2101 (TARGET_V9 \ 2102 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 2103 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 2104 2105/* Now macros that check whether X is a register and also, 2106 strictly, whether it is in a specified class. 2107 2108 These macros are specific to the SPARC, and may be used only 2109 in code for printing assembler insns and in conditions for 2110 define_optimization. */ 2111 2112/* 1 if X is an fp register. */ 2113 2114#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 2115 2116/* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ 2117#define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) 2118 2119/* Maximum number of registers that can appear in a valid memory address. */ 2120 2121#define MAX_REGS_PER_ADDRESS 2 2122 2123/* Recognize any constant value that is a valid address. 2124 When PIC, we do not accept an address that would require a scratch reg 2125 to load into a register. */ 2126 2127#define CONSTANT_ADDRESS_P(X) constant_address_p (X) 2128 2129/* Define this, so that when PIC, reload won't try to reload invalid 2130 addresses which require two reload registers. */ 2131 2132#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 2133 2134/* Nonzero if the constant value X is a legitimate general operand. 2135 Anything can be made to work except floating point constants. 2136 If TARGET_VIS, 0.0 can be made to work as well. */ 2137 2138#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 2139 2140/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2141 and check its validity for a certain class. 2142 We have two alternate definitions for each of them. 2143 The usual definition accepts all pseudo regs; the other rejects 2144 them unless they have been allocated suitable hard regs. 2145 The symbol REG_OK_STRICT causes the latter definition to be used. 2146 2147 Most source files want to accept pseudo regs in the hope that 2148 they will get allocated to the class that the insn wants them to be in. 2149 Source files for reload pass need to be strict. 2150 After reload, it makes no difference, since pseudo regs have 2151 been eliminated by then. */ 2152 2153/* Optional extra constraints for this machine. 2154 2155 'Q' handles floating point constants which can be moved into 2156 an integer register with a single sethi instruction. 2157 2158 'R' handles floating point constants which can be moved into 2159 an integer register with a single mov instruction. 2160 2161 'S' handles floating point constants which can be moved into 2162 an integer register using a high/lo_sum sequence. 2163 2164 'T' handles memory addresses where the alignment is known to 2165 be at least 8 bytes. 2166 2167 `U' handles all pseudo registers or a hard even numbered 2168 integer register, needed for ldd/std instructions. 2169 2170 'W' handles the memory operand when moving operands in/out 2171 of 'e' constraint floating point registers. */ 2172 2173#ifndef REG_OK_STRICT 2174 2175/* Nonzero if X is a hard reg that can be used as an index 2176 or if it is a pseudo reg. */ 2177#define REG_OK_FOR_INDEX_P(X) \ 2178 (REGNO (X) < 32 \ 2179 || REGNO (X) == FRAME_POINTER_REGNUM \ 2180 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 2181 2182/* Nonzero if X is a hard reg that can be used as a base reg 2183 or if it is a pseudo reg. */ 2184#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) 2185 2186/* 'T', 'U' are for aligned memory loads which aren't needed for arch64. 2187 'W' is like 'T' but is assumed true on arch64. 2188 2189 Remember to accept pseudo-registers for memory constraints if reload is 2190 in progress. */ 2191 2192#define EXTRA_CONSTRAINT(OP, C) \ 2193 sparc_extra_constraint_check(OP, C, 0) 2194 2195#else 2196 2197/* Nonzero if X is a hard reg that can be used as an index. */ 2198#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 2199/* Nonzero if X is a hard reg that can be used as a base reg. */ 2200#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 2201 2202#define EXTRA_CONSTRAINT(OP, C) \ 2203 sparc_extra_constraint_check(OP, C, 1) 2204 2205#endif 2206 2207/* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 2208 2209#ifdef HAVE_AS_OFFSETABLE_LO10 2210#define USE_AS_OFFSETABLE_LO10 1 2211#else 2212#define USE_AS_OFFSETABLE_LO10 0 2213#endif 2214 2215/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2216 that is a valid memory address for an instruction. 2217 The MODE argument is the machine mode for the MEM expression 2218 that wants to use this address. 2219 2220 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 2221 ordinarily. This changes a bit when generating PIC. 2222 2223 If you change this, execute "rm explow.o recog.o reload.o". */ 2224 2225#define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) 2226 2227#define RTX_OK_FOR_BASE_P(X) \ 2228 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 2229 || (GET_CODE (X) == SUBREG \ 2230 && GET_CODE (SUBREG_REG (X)) == REG \ 2231 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 2232 2233#define RTX_OK_FOR_INDEX_P(X) \ 2234 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 2235 || (GET_CODE (X) == SUBREG \ 2236 && GET_CODE (SUBREG_REG (X)) == REG \ 2237 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 2238 2239#define RTX_OK_FOR_OFFSET_P(X) \ 2240 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) 2241 2242#define RTX_OK_FOR_OLO10_P(X) \ 2243 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) 2244 2245#ifdef REG_OK_STRICT 2246#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2247{ \ 2248 if (legitimate_address_p (MODE, X, 1)) \ 2249 goto ADDR; \ 2250} 2251#else 2252#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2253{ \ 2254 if (legitimate_address_p (MODE, X, 0)) \ 2255 goto ADDR; \ 2256} 2257#endif 2258 2259/* Go to LABEL if ADDR (a legitimate address expression) 2260 has an effect that depends on the machine mode it is used for. 2261 2262 In PIC mode, 2263 2264 (mem:HI [%l7+a]) 2265 2266 is not equivalent to 2267 2268 (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) 2269 2270 because [%l7+a+1] is interpreted as the address of (a+1). */ 2271 2272#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2273{ \ 2274 if (flag_pic == 1) \ 2275 { \ 2276 if (GET_CODE (ADDR) == PLUS) \ 2277 { \ 2278 rtx op0 = XEXP (ADDR, 0); \ 2279 rtx op1 = XEXP (ADDR, 1); \ 2280 if (op0 == pic_offset_table_rtx \ 2281 && SYMBOLIC_CONST (op1)) \ 2282 goto LABEL; \ 2283 } \ 2284 } \ 2285} 2286 2287/* Try machine-dependent ways of modifying an illegitimate address 2288 to be legitimate. If we find one, return the new, valid address. 2289 This macro is used in only one place: `memory_address' in explow.c. 2290 2291 OLDX is the address as it was before break_out_memory_refs was called. 2292 In some cases it is useful to look at this to decide what needs to be done. 2293 2294 MODE and WIN are passed so that this macro can use 2295 GO_IF_LEGITIMATE_ADDRESS. 2296 2297 It is always safe for this macro to do nothing. It exists to recognize 2298 opportunities to optimize the output. */ 2299 2300/* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 2301#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2302{ \ 2303 (X) = legitimize_address (X, OLDX, MODE); \ 2304 if (memory_address_p (MODE, X)) \ 2305 goto WIN; \ 2306} 2307 2308/* Try a machine-dependent way of reloading an illegitimate address 2309 operand. If we find one, push the reload and jump to WIN. This 2310 macro is used in only one place: `find_reloads_address' in reload.c. 2311 2312 For SPARC 32, we wish to handle addresses by splitting them into 2313 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. 2314 This cuts the number of extra insns by one. 2315 2316 Do nothing when generating PIC code and the address is a 2317 symbolic operand or requires a scratch register. */ 2318 2319#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2320do { \ 2321 /* Decompose SImode constants into hi+lo_sum. We do have to \ 2322 rerecognize what we produce, so be careful. */ \ 2323 if (CONSTANT_P (X) \ 2324 && (MODE != TFmode || TARGET_ARCH64) \ 2325 && GET_MODE (X) == SImode \ 2326 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ 2327 && ! (flag_pic \ 2328 && (symbolic_operand (X, Pmode) \ 2329 || pic_address_needs_scratch (X))) \ 2330 && sparc_cmodel <= CM_MEDLOW) \ 2331 { \ 2332 X = gen_rtx_LO_SUM (GET_MODE (X), \ 2333 gen_rtx_HIGH (GET_MODE (X), X), X); \ 2334 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 2335 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 2336 OPNUM, TYPE); \ 2337 goto WIN; \ 2338 } \ 2339 /* ??? 64-bit reloads. */ \ 2340} while (0) 2341 2342/* Specify the machine mode that this machine uses 2343 for the index in the tablejump instruction. */ 2344/* If we ever implement any of the full models (such as CM_FULLANY), 2345 this has to be DImode in that case */ 2346#ifdef HAVE_GAS_SUBSECTION_ORDERING 2347#define CASE_VECTOR_MODE \ 2348(! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 2349#else 2350/* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 2351 we have to sign extend which slows things down. */ 2352#define CASE_VECTOR_MODE \ 2353(! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 2354#endif 2355 2356/* Define as C expression which evaluates to nonzero if the tablejump 2357 instruction expects the table to contain offsets from the address of the 2358 table. 2359 Do not define this if the table should contain absolute addresses. */ 2360/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2361 2362/* Define this as 1 if `char' should by default be signed; else as 0. */ 2363#define DEFAULT_SIGNED_CHAR 1 2364 2365/* Max number of bytes we can move from memory to memory 2366 in one reasonably fast instruction. */ 2367#define MOVE_MAX 8 2368 2369#if 0 /* Sun 4 has matherr, so this is no good. */ 2370/* This is the value of the error code EDOM for this machine, 2371 used by the sqrt instruction. */ 2372#define TARGET_EDOM 33 2373 2374/* This is how to refer to the variable errno. */ 2375#define GEN_ERRNO_RTX \ 2376 gen_rtx_MEM (SImode, gen_rtx_SYMBOL_REF (Pmode, "errno")) 2377#endif /* 0 */ 2378 2379/* Define if operations between registers always perform the operation 2380 on the full register even if a narrower mode is specified. */ 2381#define WORD_REGISTER_OPERATIONS 2382 2383/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2384 will either zero-extend or sign-extend. The value of this macro should 2385 be the code that says which one of the two operations is implicitly 2386 done, NIL if none. */ 2387#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2388 2389/* Nonzero if access to memory by bytes is slow and undesirable. 2390 For RISC chips, it means that access to memory by bytes is no 2391 better than access by words when possible, so grab a whole word 2392 and maybe make use of that. */ 2393#define SLOW_BYTE_ACCESS 1 2394 2395/* When a prototype says `char' or `short', really pass an `int'. */ 2396#define PROMOTE_PROTOTYPES (TARGET_ARCH32) 2397 2398/* Define this to be nonzero if shift instructions ignore all but the low-order 2399 few bits. */ 2400#define SHIFT_COUNT_TRUNCATED 1 2401 2402/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2403 is done just by pretending it is already truncated. */ 2404#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2405 2406/* Specify the machine mode used for addresses. */ 2407#define Pmode (TARGET_ARCH64 ? DImode : SImode) 2408 2409/* Generate calls to memcpy, memcmp and memset. */ 2410#define TARGET_MEM_FUNCTIONS 2411 2412/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2413 return the mode to be used for the comparison. For floating-point, 2414 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 2415 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 2416 processing is needed. */ 2417#define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 2418 2419/* Return nonzero if MODE implies a floating point inequality can be 2420 reversed. For SPARC this is always true because we have a full 2421 compliment of ordered and unordered comparisons, but until generic 2422 code knows how to reverse it correctly we keep the old definition. */ 2423#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 2424 2425/* A function address in a call instruction for indexing purposes. */ 2426#define FUNCTION_MODE Pmode 2427 2428/* Define this if addresses of constant functions 2429 shouldn't be put through pseudo regs where they can be cse'd. 2430 Desirable on machines where ordinary constants are expensive 2431 but a CALL with constant address is cheap. */ 2432#define NO_FUNCTION_CSE 2433 2434/* alloca should avoid clobbering the old register save area. */ 2435#define SETJMP_VIA_SAVE_AREA 2436 2437/* The _Q_* comparison libcalls return booleans. */ 2438#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 2439 2440/* Assume by default that the _Qp_* 64-bit libcalls are implemented such 2441 that the inputs are fully consumed before the output memory is clobbered. */ 2442 2443#define TARGET_BUGGY_QP_LIB 0 2444 2445/* Assume by default that we do not have the Solaris-specific conversion 2446 routines nor 64-bit integer multiply and divide routines. */ 2447 2448#define SUN_CONVERSION_LIBFUNCS 0 2449#define DITF_CONVERSION_LIBFUNCS 0 2450#define SUN_INTEGER_MULTIPLY_64 0 2451 2452/* Compute extra cost of moving data between one register class 2453 and another. */ 2454#define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) 2455#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2456 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ 2457 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ 2458 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ 2459 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2460 || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2) 2461 2462/* Provide the cost of a branch. For pre-v9 processors we use 2463 a value of 3 to take into account the potential annulling of 2464 the delay slot (which ends up being a bubble in the pipeline slot) 2465 plus a cycle to take into consideration the instruction cache 2466 effects. 2467 2468 On v9 and later, which have branch prediction facilities, we set 2469 it to the depth of the pipeline as that is the cost of a 2470 mispredicted branch. */ 2471 2472#define BRANCH_COST \ 2473 ((sparc_cpu == PROCESSOR_V9 \ 2474 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 2475 ? 7 \ 2476 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2477 ? 9 : 3)) 2478 2479#define PREFETCH_BLOCK \ 2480 ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2481 || sparc_cpu == PROCESSOR_ULTRASPARC3) \ 2482 ? 64 : 32) 2483 2484#define SIMULTANEOUS_PREFETCHES \ 2485 ((sparc_cpu == PROCESSOR_ULTRASPARC) \ 2486 ? 2 \ 2487 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2488 ? 8 : 3)) 2489 2490/* Control the assembler format that we output. */ 2491 2492/* A C string constant describing how to begin a comment in the target 2493 assembler language. The compiler assumes that the comment will end at 2494 the end of the line. */ 2495 2496#define ASM_COMMENT_START "!" 2497 2498/* Output to assembler file text saying following lines 2499 may contain character constants, extra white space, comments, etc. */ 2500 2501#define ASM_APP_ON "" 2502 2503/* Output to assembler file text saying following lines 2504 no longer contain unusual constructs. */ 2505 2506#define ASM_APP_OFF "" 2507 2508/* ??? Try to make the style consistent here (_OP?). */ 2509 2510#define ASM_FLOAT ".single" 2511#define ASM_DOUBLE ".double" 2512#define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */ 2513 2514/* How to refer to registers in assembler output. 2515 This sequence is indexed by compiler's hard-register-number (see above). */ 2516 2517#define REGISTER_NAMES \ 2518{"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2519 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2520 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2521 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2522 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2523 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2524 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2525 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 2526 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 2527 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 2528 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 2529 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 2530 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" } 2531 2532/* Define additional names for use in asm clobbers and asm declarations. */ 2533 2534#define ADDITIONAL_REGISTER_NAMES \ 2535{{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 2536 2537/* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 2538 can run past this up to a continuation point. Once we used 1500, but 2539 a single entry in C++ can run more than 500 bytes, due to the length of 2540 mangled symbol names. dbxout.c should really be fixed to do 2541 continuations when they are actually needed instead of trying to 2542 guess... */ 2543#define DBX_CONTIN_LENGTH 1000 2544 2545/* This is how to output a command to make the user-level label named NAME 2546 defined for reference from other files. */ 2547 2548/* Globalizing directive for a label. */ 2549#define GLOBAL_ASM_OP "\t.global " 2550 2551/* The prefix to add to user-visible assembler symbols. */ 2552 2553#define USER_LABEL_PREFIX "_" 2554 2555/* This is how to store into the string LABEL 2556 the symbol_ref name of an internal numbered label where 2557 PREFIX is the class of label and NUM is the number within the class. 2558 This is suitable for output with `assemble_name'. */ 2559 2560#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2561 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 2562 2563/* This is how we hook in and defer the case-vector until the end of 2564 the function. */ 2565#define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 2566 sparc_defer_case_vector ((LAB),(VEC), 0) 2567 2568#define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 2569 sparc_defer_case_vector ((LAB),(VEC), 1) 2570 2571/* This is how to output an element of a case-vector that is absolute. */ 2572 2573#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2574do { \ 2575 char label[30]; \ 2576 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 2577 if (CASE_VECTOR_MODE == SImode) \ 2578 fprintf (FILE, "\t.word\t"); \ 2579 else \ 2580 fprintf (FILE, "\t.xword\t"); \ 2581 assemble_name (FILE, label); \ 2582 fputc ('\n', FILE); \ 2583} while (0) 2584 2585/* This is how to output an element of a case-vector that is relative. 2586 (SPARC uses such vectors only when generating PIC.) */ 2587 2588#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2589do { \ 2590 char label[30]; \ 2591 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 2592 if (CASE_VECTOR_MODE == SImode) \ 2593 fprintf (FILE, "\t.word\t"); \ 2594 else \ 2595 fprintf (FILE, "\t.xword\t"); \ 2596 assemble_name (FILE, label); \ 2597 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 2598 fputc ('-', FILE); \ 2599 assemble_name (FILE, label); \ 2600 fputc ('\n', FILE); \ 2601} while (0) 2602 2603/* This is what to output before and after case-vector (both 2604 relative and absolute). If .subsection -1 works, we put case-vectors 2605 at the beginning of the current section. */ 2606 2607#ifdef HAVE_GAS_SUBSECTION_ORDERING 2608 2609#define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 2610 fprintf(FILE, "\t.subsection\t-1\n") 2611 2612#define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 2613 fprintf(FILE, "\t.previous\n") 2614 2615#endif 2616 2617/* This is how to output an assembler line 2618 that says to advance the location counter 2619 to a multiple of 2**LOG bytes. */ 2620 2621#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2622 if ((LOG) != 0) \ 2623 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2624 2625/* This is how to output an assembler line that says to advance 2626 the location counter to a multiple of 2**LOG bytes using the 2627 "nop" instruction as padding. */ 2628#define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ 2629 if ((LOG) != 0) \ 2630 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG))) 2631 2632#define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2633 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2634 2635/* This says how to output an assembler line 2636 to define a global common symbol. */ 2637 2638#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 2639( fputs ("\t.common ", (FILE)), \ 2640 assemble_name ((FILE), (NAME)), \ 2641 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 2642 2643/* This says how to output an assembler line to define a local common 2644 symbol. */ 2645 2646#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 2647( fputs ("\t.reserve ", (FILE)), \ 2648 assemble_name ((FILE), (NAME)), \ 2649 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 2650 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 2651 2652/* A C statement (sans semicolon) to output to the stdio stream 2653 FILE the assembler definition of uninitialized global DECL named 2654 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 2655 Try to use asm_output_aligned_bss to implement this macro. */ 2656 2657#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 2658 do { \ 2659 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 2660 } while (0) 2661 2662#define IDENT_ASM_OP "\t.ident\t" 2663 2664/* Output #ident as a .ident. */ 2665 2666#define ASM_OUTPUT_IDENT(FILE, NAME) \ 2667 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); 2668 2669/* Emit a dtp-relative reference to a TLS variable. */ 2670 2671#ifdef HAVE_AS_TLS 2672#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ 2673 sparc_output_dwarf_dtprel (FILE, SIZE, X) 2674#endif 2675 2676#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2677 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \ 2678 || (CHAR) == '(' || (CHAR) == '_' || (CHAR) == '&') 2679 2680/* Print operand X (an rtx) in assembler syntax to file FILE. 2681 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2682 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2683 2684#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2685 2686/* Print a memory address as an operand to reference that memory location. */ 2687 2688#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2689{ register rtx base, index = 0; \ 2690 int offset = 0; \ 2691 register rtx addr = ADDR; \ 2692 if (GET_CODE (addr) == REG) \ 2693 fputs (reg_names[REGNO (addr)], FILE); \ 2694 else if (GET_CODE (addr) == PLUS) \ 2695 { \ 2696 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2697 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2698 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2699 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2700 else \ 2701 base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2702 if (GET_CODE (base) == LO_SUM) \ 2703 { \ 2704 if (! USE_AS_OFFSETABLE_LO10 \ 2705 || TARGET_ARCH32 \ 2706 || TARGET_CM_MEDMID) \ 2707 abort (); \ 2708 output_operand (XEXP (base, 0), 0); \ 2709 fputs ("+%lo(", FILE); \ 2710 output_address (XEXP (base, 1)); \ 2711 fprintf (FILE, ")+%d", offset); \ 2712 } \ 2713 else \ 2714 { \ 2715 fputs (reg_names[REGNO (base)], FILE); \ 2716 if (index == 0) \ 2717 fprintf (FILE, "%+d", offset); \ 2718 else if (GET_CODE (index) == REG) \ 2719 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 2720 else if (GET_CODE (index) == SYMBOL_REF \ 2721 || GET_CODE (index) == CONST) \ 2722 fputc ('+', FILE), output_addr_const (FILE, index); \ 2723 else abort (); \ 2724 } \ 2725 } \ 2726 else if (GET_CODE (addr) == MINUS \ 2727 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2728 { \ 2729 output_addr_const (FILE, XEXP (addr, 0)); \ 2730 fputs ("-(", FILE); \ 2731 output_addr_const (FILE, XEXP (addr, 1)); \ 2732 fputs ("-.)", FILE); \ 2733 } \ 2734 else if (GET_CODE (addr) == LO_SUM) \ 2735 { \ 2736 output_operand (XEXP (addr, 0), 0); \ 2737 if (TARGET_CM_MEDMID) \ 2738 fputs ("+%l44(", FILE); \ 2739 else \ 2740 fputs ("+%lo(", FILE); \ 2741 output_address (XEXP (addr, 1)); \ 2742 fputc (')', FILE); \ 2743 } \ 2744 else if (flag_pic && GET_CODE (addr) == CONST \ 2745 && GET_CODE (XEXP (addr, 0)) == MINUS \ 2746 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2747 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2748 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 2749 { \ 2750 addr = XEXP (addr, 0); \ 2751 output_addr_const (FILE, XEXP (addr, 0)); \ 2752 /* Group the args of the second CONST in parenthesis. */ \ 2753 fputs ("-(", FILE); \ 2754 /* Skip past the second CONST--it does nothing for us. */\ 2755 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 2756 /* Close the parenthesis. */ \ 2757 fputc (')', FILE); \ 2758 } \ 2759 else \ 2760 { \ 2761 output_addr_const (FILE, addr); \ 2762 } \ 2763} 2764 2765#ifdef HAVE_AS_TLS 2766#define TARGET_TLS 1 2767#else 2768#define TARGET_TLS 0 2769#endif 2770#define TARGET_SUN_TLS TARGET_TLS 2771#define TARGET_GNU_TLS 0 2772 2773/* Define the codes that are matched by predicates in sparc.c. */ 2774 2775#define PREDICATE_CODES \ 2776{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2777{"const1_operand", {CONST_INT}}, \ 2778{"fp_zero_operand", {CONST_DOUBLE}}, \ 2779{"fp_register_operand", {SUBREG, REG}}, \ 2780{"intreg_operand", {SUBREG, REG}}, \ 2781{"fcc_reg_operand", {REG}}, \ 2782{"fcc0_reg_operand", {REG}}, \ 2783{"icc_or_fcc_reg_operand", {REG}}, \ 2784{"restore_operand", {REG}}, \ 2785{"call_operand", {MEM}}, \ 2786{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \ 2787 ADDRESSOF, SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \ 2788{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ 2789{"symbolic_memory_operand", {SUBREG, MEM}}, \ 2790{"label_ref_operand", {LABEL_REF}}, \ 2791{"sp64_medium_pic_operand", {CONST}}, \ 2792{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \ 2793{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \ 2794{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \ 2795{"splittable_symbolic_memory_operand", {MEM}}, \ 2796{"splittable_immediate_memory_operand", {MEM}}, \ 2797{"eq_or_neq", {EQ, NE}}, \ 2798{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \ 2799{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ 2800{"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \ 2801{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \ 2802{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \ 2803{"cc_arithop", {AND, IOR, XOR}}, \ 2804{"cc_arithopn", {AND, IOR}}, \ 2805{"arith_operand", {SUBREG, REG, CONST_INT}}, \ 2806{"arith_add_operand", {SUBREG, REG, CONST_INT}}, \ 2807{"arith11_operand", {SUBREG, REG, CONST_INT}}, \ 2808{"arith10_operand", {SUBREG, REG, CONST_INT}}, \ 2809{"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2810{"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2811{"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2812{"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2813{"small_int", {CONST_INT}}, \ 2814{"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \ 2815{"uns_small_int", {CONST_INT}}, \ 2816{"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \ 2817{"clobbered_register", {REG}}, \ 2818{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \ 2819{"compare_operand", {SUBREG, REG, ZERO_EXTRACT}}, \ 2820{"const64_operand", {CONST_INT, CONST_DOUBLE}}, \ 2821{"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \ 2822{"tgd_symbolic_operand", {SYMBOL_REF}}, \ 2823{"tld_symbolic_operand", {SYMBOL_REF}}, \ 2824{"tie_symbolic_operand", {SYMBOL_REF}}, \ 2825{"tle_symbolic_operand", {SYMBOL_REF}}, 2826 2827/* The number of Pmode words for the setjmp buffer. */ 2828#define JMP_BUF_SIZE 12 2829 2830#define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic) 2831