pentium.md revision 132718
1;; Pentium Scheduling 2;; Copyright (C) 2002 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 59 Temple Place - Suite 330, 19;; Boston, MA 02111-1307, USA. */ 20;; 21;; The Pentium is an in-order core with two integer pipelines. 22 23;; True for insns that behave like prefixed insns on the Pentium. 24(define_attr "pent_prefix" "false,true" 25 (if_then_else (ior (eq_attr "prefix_0f" "1") 26 (ior (eq_attr "prefix_data16" "1") 27 (eq_attr "prefix_rep" "1"))) 28 (const_string "true") 29 (const_string "false"))) 30 31;; Categorize how an instruction slots. 32 33;; The non-MMX Pentium slots an instruction with prefixes on U pipe only, 34;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium 35;; rules, because it results in noticeably better code on non-MMX Pentium 36;; and doesn't hurt much on MMX. (Prefixed instructions are not very 37;; common, so the scheduler usually has a non-prefixed insn to pair). 38 39(define_attr "pent_pair" "uv,pu,pv,np" 40 (cond [(eq_attr "imm_disp" "true") 41 (const_string "np") 42 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec") 43 (and (eq_attr "type" "pop,push") 44 (eq_attr "memory" "!both"))) 45 (if_then_else (eq_attr "pent_prefix" "true") 46 (const_string "pu") 47 (const_string "uv")) 48 (eq_attr "type" "ibr") 49 (const_string "pv") 50 (and (eq_attr "type" "ishift") 51 (match_operand 2 "const_int_operand" "")) 52 (const_string "pu") 53 (and (eq_attr "type" "rotate") 54 (match_operand 2 "const1_operand" "")) 55 (const_string "pu") 56 (and (eq_attr "type" "ishift1") 57 (match_operand 1 "const_int_operand" "")) 58 (const_string "pu") 59 (and (eq_attr "type" "rotate1") 60 (match_operand 1 "const1_operand" "")) 61 (const_string "pu") 62 (and (eq_attr "type" "call") 63 (match_operand 0 "constant_call_address_operand" "")) 64 (const_string "pv") 65 (and (eq_attr "type" "callv") 66 (match_operand 1 "constant_call_address_operand" "")) 67 (const_string "pv") 68 ] 69 (const_string "np"))) 70 71(define_automaton "pentium,pentium_fpu") 72 73;; Pentium do have U and V pipes. Instruction to both pipes 74;; are always issued together, much like on VLIW. 75;; 76;; predecode 77;; / \ 78;; decodeu decodev 79;; / | | 80;; fpu executeu executev 81;; | | | 82;; fpu retire retire 83;; | 84;; fpu 85;; We add dummy "port" pipes allocated only first cycle of 86;; instruction to specify this behavior. 87 88(define_cpu_unit "pentium-portu,pentium-portv" "pentium") 89(define_cpu_unit "pentium-u,pentium-v" "pentium") 90(absence_set "pentium-portu" "pentium-u,pentium-v") 91(presence_set "pentium-portv" "pentium-portu") 92 93;; Floating point instructions can overlap with new issue of integer 94;; instructions. We model only first cycle of FP pipeline, as it is 95;; fully pipelined. 96(define_cpu_unit "pentium-fp" "pentium_fpu") 97 98;; There is non-pipelined multiplier unit used for complex operations. 99(define_cpu_unit "pentium-fmul" "pentium_fpu") 100 101;; Pentium preserves memory ordering, so when load-execute-store 102;; instruction is executed together with other instruction loading 103;; data, the execution of the other instruction is delayed to very 104;; last cycle of first instruction, when data are bypassed. 105;; We model this by allocating "memory" unit when store is pending 106;; and using conflicting load units together. 107 108(define_cpu_unit "pentium-memory" "pentium") 109(define_cpu_unit "pentium-load0" "pentium") 110(define_cpu_unit "pentium-load1" "pentium") 111(absence_set "pentium-load0,pentium-load1" "pentium-memory") 112 113(define_reservation "pentium-load" "(pentium-load0 | pentium-load1)") 114(define_reservation "pentium-np" "(pentium-u + pentium-v)") 115(define_reservation "pentium-uv" "(pentium-u | pentium-v)") 116(define_reservation "pentium-portuv" "(pentium-portu | pentium-portv)") 117(define_reservation "pentium-firstu" "(pentium-u + pentium-portu)") 118(define_reservation "pentium-firstv" "(pentium-v + pentium-portuv)") 119(define_reservation "pentium-firstuv" "(pentium-uv + pentium-portuv)") 120(define_reservation "pentium-firstuload" "(pentium-load + pentium-firstu)") 121(define_reservation "pentium-firstvload" "(pentium-load + pentium-firstv)") 122(define_reservation "pentium-firstuvload" "(pentium-load + pentium-firstuv) 123 | (pentium-firstv,pentium-v, 124 (pentium-load+pentium-firstv))") 125(define_reservation "pentium-firstuboth" "(pentium-load + pentium-firstu 126 + pentium-memory)") 127(define_reservation "pentium-firstvboth" "(pentium-load + pentium-firstv 128 + pentium-memory)") 129(define_reservation "pentium-firstuvboth" "(pentium-load + pentium-firstuv 130 + pentium-memory) 131 | (pentium-firstv,pentium-v, 132 (pentium-load+pentium-firstv))") 133 134;; Few common long latency instructions 135(define_insn_reservation "pent_mul" 11 136 (and (eq_attr "cpu" "pentium") 137 (eq_attr "type" "imul")) 138 "pentium-np*11") 139 140(define_insn_reservation "pent_str" 12 141 (and (eq_attr "cpu" "pentium") 142 (eq_attr "type" "str")) 143 "pentium-np*12") 144 145;; Integer division and some other long latency instruction block all 146;; units, including the FP pipe. There is no value in modeling the 147;; latency of these instructions and not modeling the latency 148;; decreases the size of the DFA. 149(define_insn_reservation "pent_block" 1 150 (and (eq_attr "cpu" "pentium") 151 (eq_attr "type" "idiv")) 152 "pentium-np+pentium-fp") 153 154(define_insn_reservation "pent_cld" 2 155 (and (eq_attr "cpu" "pentium") 156 (eq_attr "type" "cld")) 157 "pentium-np*2") 158 159;; Moves usually have one cycle penalty, but there are exceptions. 160(define_insn_reservation "pent_fmov" 1 161 (and (eq_attr "cpu" "pentium") 162 (and (eq_attr "type" "fmov") 163 (eq_attr "memory" "none,load"))) 164 "(pentium-fp+pentium-np)") 165 166(define_insn_reservation "pent_fpmovxf" 3 167 (and (eq_attr "cpu" "pentium") 168 (and (eq_attr "type" "fmov") 169 (and (eq_attr "memory" "load,store") 170 (eq_attr "mode" "XF")))) 171 "(pentium-fp+pentium-np)*3") 172 173(define_insn_reservation "pent_fpstore" 2 174 (and (eq_attr "cpu" "pentium") 175 (and (eq_attr "type" "fmov") 176 (ior (match_operand 1 "immediate_operand" "") 177 (eq_attr "memory" "store")))) 178 "(pentium-fp+pentium-np)*2") 179 180(define_insn_reservation "pent_imov" 1 181 (and (eq_attr "cpu" "pentium") 182 (eq_attr "type" "imov")) 183 "pentium-firstuv") 184 185;; Push and pop instructions have 1 cycle latency and special 186;; hardware bypass allows them to be paired with other push,pop 187;; and call instructions. 188(define_bypass 0 "pent_push,pent_pop" "pent_push,pent_pop,pent_call") 189(define_insn_reservation "pent_push" 1 190 (and (eq_attr "cpu" "pentium") 191 (and (eq_attr "type" "push") 192 (eq_attr "memory" "store"))) 193 "pentium-firstuv") 194 195(define_insn_reservation "pent_pop" 1 196 (and (eq_attr "cpu" "pentium") 197 (eq_attr "type" "pop,leave")) 198 "pentium-firstuv") 199 200;; Call and branch instruction can execute in either pipe, but 201;; they are only pairable when in the v pipe. 202(define_insn_reservation "pent_call" 10 203 (and (eq_attr "cpu" "pentium") 204 (eq_attr "type" "call,callv")) 205 "pentium-firstv,pentium-v*9") 206 207(define_insn_reservation "pent_branch" 1 208 (and (eq_attr "cpu" "pentium") 209 (eq_attr "type" "ibr")) 210 "pentium-firstv") 211 212;; Floating point instruction dispatch in U pipe, but continue 213;; in FP pipeline allowing other instructions to be executed. 214(define_insn_reservation "pent_fp" 3 215 (and (eq_attr "cpu" "pentium") 216 (eq_attr "type" "fop,fistp")) 217 "(pentium-firstu+pentium-fp),nothing,nothing") 218 219;; First two cycles of fmul are not pipelined. 220(define_insn_reservation "pent_fmul" 3 221 (and (eq_attr "cpu" "pentium") 222 (eq_attr "type" "fmul")) 223 "(pentium-firstuv+pentium-fp+pentium-fmul),pentium-fmul,nothing") 224 225;; Long latency FP instructions overlap with integer instructions, 226;; but only last 2 cycles with FP ones. 227(define_insn_reservation "pent_fdiv" 39 228 (and (eq_attr "cpu" "pentium") 229 (eq_attr "type" "fdiv")) 230 "(pentium-np+pentium-fp+pentium-fmul), 231 (pentium-fp+pentium-fmul)*36,pentium-fmul*2") 232 233(define_insn_reservation "pent_fpspc" 70 234 (and (eq_attr "cpu" "pentium") 235 (eq_attr "type" "fpspc")) 236 "(pentium-np+pentium-fp+pentium-fmul), 237 (pentium-fp+pentium-fmul)*67,pentium-fmul*2") 238 239;; Integer instructions. Load/execute/store takes 3 cycles, 240;; load/execute 2 cycles and execute only one cycle. 241(define_insn_reservation "pent_uv_both" 3 242 (and (eq_attr "cpu" "pentium") 243 (and (eq_attr "pent_pair" "uv") 244 (eq_attr "memory" "both"))) 245 "pentium-firstuvboth,pentium-uv+pentium-memory,pentium-uv") 246 247(define_insn_reservation "pent_u_both" 3 248 (and (eq_attr "cpu" "pentium") 249 (and (eq_attr "pent_pair" "pu") 250 (eq_attr "memory" "both"))) 251 "pentium-firstuboth,pentium-u+pentium-memory,pentium-u") 252 253(define_insn_reservation "pent_v_both" 3 254 (and (eq_attr "cpu" "pentium") 255 (and (eq_attr "pent_pair" "pv") 256 (eq_attr "memory" "both"))) 257 "pentium-firstvboth,pentium-v+pentium-memory,pentium-v") 258 259(define_insn_reservation "pent_np_both" 3 260 (and (eq_attr "cpu" "pentium") 261 (and (eq_attr "pent_pair" "np") 262 (eq_attr "memory" "both"))) 263 "pentium-np,pentium-np,pentium-np") 264 265(define_insn_reservation "pent_uv_load" 2 266 (and (eq_attr "cpu" "pentium") 267 (and (eq_attr "pent_pair" "uv") 268 (eq_attr "memory" "load"))) 269 "pentium-firstuvload,pentium-uv") 270 271(define_insn_reservation "pent_u_load" 2 272 (and (eq_attr "cpu" "pentium") 273 (and (eq_attr "pent_pair" "pu") 274 (eq_attr "memory" "load"))) 275 "pentium-firstuload,pentium-u") 276 277(define_insn_reservation "pent_v_load" 2 278 (and (eq_attr "cpu" "pentium") 279 (and (eq_attr "pent_pair" "pv") 280 (eq_attr "memory" "load"))) 281 "pentium-firstvload,pentium-v") 282 283(define_insn_reservation "pent_np_load" 2 284 (and (eq_attr "cpu" "pentium") 285 (and (eq_attr "pent_pair" "np") 286 (eq_attr "memory" "load"))) 287 "pentium-np,pentium-np") 288 289(define_insn_reservation "pent_uv" 1 290 (and (eq_attr "cpu" "pentium") 291 (and (eq_attr "pent_pair" "uv") 292 (eq_attr "memory" "none"))) 293 "pentium-firstuv") 294 295(define_insn_reservation "pent_u" 1 296 (and (eq_attr "cpu" "pentium") 297 (and (eq_attr "pent_pair" "pu") 298 (eq_attr "memory" "none"))) 299 "pentium-firstu") 300 301(define_insn_reservation "pent_v" 1 302 (and (eq_attr "cpu" "pentium") 303 (and (eq_attr "pent_pair" "pv") 304 (eq_attr "memory" "none"))) 305 "pentium-firstv") 306 307(define_insn_reservation "pent_np" 1 308 (and (eq_attr "cpu" "pentium") 309 (and (eq_attr "pent_pair" "np") 310 (eq_attr "memory" "none"))) 311 "pentium-np") 312 313