k6.md revision 132718
1117395Skan;; AMD K6/K6-2 Scheduling
2117395Skan;; Copyright (C) 2002 ;; Free Software Foundation, Inc.
3117395Skan;;
4132718Skan;; This file is part of GCC.
5117395Skan;;
6132718Skan;; GCC is free software; you can redistribute it and/or modify
7117395Skan;; it under the terms of the GNU General Public License as published by
8117395Skan;; the Free Software Foundation; either version 2, or (at your option)
9117395Skan;; any later version.
10117395Skan;;
11132718Skan;; GCC is distributed in the hope that it will be useful,
12117395Skan;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13117395Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14117395Skan;; GNU General Public License for more details.
15117395Skan;;
16117395Skan;; You should have received a copy of the GNU General Public License
17132718Skan;; along with GCC; see the file COPYING.  If not, write to
18117395Skan;; the Free Software Foundation, 59 Temple Place - Suite 330,
19117395Skan;; Boston, MA 02111-1307, USA.  */
20117395Skan;;
21117395Skan;; The K6 has similar architecture to PPro.  Important difference is, that
22117395Skan;; there are only two decoders and they seems to be much slower than execution
23117395Skan;; units.  So we have to pay much more attention to proper decoding for
24117395Skan;; schedulers.  We share most of scheduler code for PPro in i386.c
25117395Skan;;
26117395Skan;; The fp unit is not pipelined and do one operation per two cycles including
27117395Skan;; the FXCH.
28117395Skan;;
29117395Skan;; alu	  describes both ALU units (ALU-X and ALU-Y).
30117395Skan;; alux   describes X alu unit
31117395Skan;; fpu    describes FPU unit
32117395Skan;; load   describes load unit.
33117395Skan;; branch describes branch unit.
34132718Skan;; store  describes store unit.  This unit is not modelled completely and only
35117395Skan;;        used to model lea operation.  Otherwise it lie outside of the critical
36117395Skan;;        path.
37117395Skan;;
38117395Skan;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
39117395Skan
40117395Skan;; The decoder specification is in the PPro section above!
41117395Skan
42117395Skan;; Shift instructions and certain arithmetic are issued only to X pipe.
43117395Skan(define_function_unit "k6_alux" 1 0
44117395Skan  (and (eq_attr "cpu" "k6")
45117395Skan       (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld"))
46117395Skan  1 1)
47117395Skan
48117395Skan;; The QI mode arithmetic is issued to X pipe only.
49117395Skan(define_function_unit "k6_alux" 1 0
50117395Skan  (and (eq_attr "cpu" "k6")
51117395Skan       (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
52132718Skan	    (eq_attr "mode" "QI")))
53117395Skan  1 1)
54117395Skan
55117395Skan(define_function_unit "k6_alu" 2 0
56117395Skan  (and (eq_attr "cpu" "k6")
57117395Skan       (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
58117395Skan  1 1)
59117395Skan
60117395Skan(define_function_unit "k6_alu" 2 0
61117395Skan  (and (eq_attr "cpu" "k6")
62117395Skan       (and (eq_attr "type" "imov")
63117395Skan       	    (eq_attr "memory" "none")))
64117395Skan  1 1)
65117395Skan
66117395Skan(define_function_unit "k6_branch" 1 0
67117395Skan  (and (eq_attr "cpu" "k6")
68117395Skan       (eq_attr "type" "call,callv,ibr"))
69117395Skan  1 1)
70117395Skan
71117395Skan;; Load unit have two cycle latency, but we take care for it in adjust_cost
72117395Skan(define_function_unit "k6_load" 1 0
73117395Skan  (and (eq_attr "cpu" "k6")
74132718Skan       (ior (eq_attr "type" "pop,leave")
75117395Skan	    (eq_attr "memory" "load,both")))
76117395Skan  1 1)
77117395Skan
78117395Skan(define_function_unit "k6_load" 1 0
79117395Skan  (and (eq_attr "cpu" "k6")
80117395Skan       (and (eq_attr "type" "str")
81117395Skan	    (eq_attr "memory" "load,both")))
82117395Skan  10 10)
83117395Skan
84117395Skan;; Lea have two instructions, so latency is probably 2
85117395Skan(define_function_unit "k6_store" 1 0
86117395Skan  (and (eq_attr "cpu" "k6")
87117395Skan       (eq_attr "type" "lea"))
88117395Skan  2 1)
89117395Skan
90117395Skan(define_function_unit "k6_store" 1 0
91117395Skan  (and (eq_attr "cpu" "k6")
92117395Skan       (eq_attr "type" "str"))
93117395Skan  10 10)
94117395Skan
95117395Skan(define_function_unit "k6_store" 1 0
96117395Skan  (and (eq_attr "cpu" "k6")
97117395Skan       (ior (eq_attr "type" "push")
98117395Skan	    (eq_attr "memory" "store,both")))
99117395Skan  1 1)
100117395Skan
101117395Skan(define_function_unit "k6_fpu" 1 1
102117395Skan  (and (eq_attr "cpu" "k6")
103117395Skan       (eq_attr "type" "fop,fmov,fcmp,fistp"))
104117395Skan  2 2)
105117395Skan
106117395Skan(define_function_unit "k6_fpu" 1 1
107117395Skan  (and (eq_attr "cpu" "k6")
108117395Skan       (eq_attr "type" "fmul"))
109117395Skan  2 2)
110117395Skan
111117395Skan;; ??? Guess
112117395Skan(define_function_unit "k6_fpu" 1 1
113117395Skan  (and (eq_attr "cpu" "k6")
114117395Skan       (eq_attr "type" "fdiv,fpspc"))
115117395Skan  56 56)
116117395Skan
117117395Skan(define_function_unit "k6_alu" 2 0
118117395Skan  (and (eq_attr "cpu" "k6")
119117395Skan       (eq_attr "type" "imul"))
120117395Skan  2 2)
121117395Skan
122117395Skan(define_function_unit "k6_alux" 1 0
123117395Skan  (and (eq_attr "cpu" "k6")
124117395Skan       (eq_attr "type" "imul"))
125117395Skan  2 2)
126117395Skan
127117395Skan;; ??? Guess
128117395Skan(define_function_unit "k6_alu" 2 0
129117395Skan  (and (eq_attr "cpu" "k6")
130117395Skan       (eq_attr "type" "idiv"))
131117395Skan  17 17)
132117395Skan
133117395Skan(define_function_unit "k6_alux" 1 0
134117395Skan  (and (eq_attr "cpu" "k6")
135117395Skan       (eq_attr "type" "idiv"))
136117395Skan  17 17)
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