1117395Skan;; AMD K6/K6-2 Scheduling 2169689Skan;; Copyright (C) 2002, 2004 3169689Skan;; Free Software Foundation, Inc. 4117395Skan;; 5132718Skan;; This file is part of GCC. 6117395Skan;; 7132718Skan;; GCC is free software; you can redistribute it and/or modify 8117395Skan;; it under the terms of the GNU General Public License as published by 9117395Skan;; the Free Software Foundation; either version 2, or (at your option) 10117395Skan;; any later version. 11117395Skan;; 12132718Skan;; GCC is distributed in the hope that it will be useful, 13117395Skan;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14117395Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15117395Skan;; GNU General Public License for more details. 16117395Skan;; 17117395Skan;; You should have received a copy of the GNU General Public License 18132718Skan;; along with GCC; see the file COPYING. If not, write to 19169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20169689Skan;; Boston, MA 02110-1301, USA. 21117395Skan;; 22169689Skan;; The K6 architecture is quite similar to PPro. Important difference is 23169689Skan;; that there are only two decoders and they seems to be much slower than 24169689Skan;; any of the execution units. So we have to pay much more attention to 25169689Skan;; proper scheduling for the decoders. 26169689Skan;; FIXME: We don't do that right now. A good start would be to sort the 27169689Skan;; instructions based on length. 28117395Skan;; 29169689Skan;; This description is based on data from the following documents: 30117395Skan;; 31169689Skan;; "AMD-K6 Processor Data Sheet (Preliminary information)" 32169689Skan;; Advanced Micro Devices, Inc., 1998. 33117395Skan;; 34169689Skan;; "AMD-K6 Processor Code Optimization Application Note" 35169689Skan;; Advanced Micro Devices, Inc., 2000. 36169689Skan;; 37169689Skan;; CPU execution units of the K6: 38169689Skan;; 39169689Skan;; store describes the Store unit. This unit is not modelled 40169689Skan;; completely and it is only used to model lea operation. 41169689Skan;; Otherwise it lies outside of any critical path. 42169689Skan;; load describes the Load unit 43169689Skan;; alux describes the Integer X unit 44169689Skan;; mm describes the Multimedia unit, which shares a pipe 45169689Skan;; with the Integer X unit. This unit is used for MMX, 46169689Skan;; which is not implemented for K6. 47169689Skan;; aluy describes the Integer Y unit 48169689Skan;; fpu describes the FPU unit 49169689Skan;; branch describes the Branch unit 50169689Skan;; 51169689Skan;; The fp unit is not pipelined, and it can only do one operation per two 52169689Skan;; cycles, including fxcg. 53169689Skan;; 54169689Skan;; Generally this is a very poor description, but at least no worse than 55169689Skan;; the old description, and a lot easier to extend to something more 56169689Skan;; reasonable if anyone still cares enough about this architecture in 2004. 57169689Skan;; 58117395Skan;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real. 59117395Skan 60169689Skan(define_automaton "k6_decoder,k6_load_unit,k6_store_unit,k6_integer_units,k6_fpu_unit,k6_branch_unit") 61117395Skan 62169689Skan;; The K6 instruction decoding begins before the on-chip instruction cache is 63169689Skan;; filled. Depending on the length of the instruction, two simple instructions 64169689Skan;; can be decoded in two parallel short decoders, or one complex instruction can 65169689Skan;; be decoded in either the long or the vector decoder. For all practical 66169689Skan;; purposes, the long and vector decoder can be modelled as one decoder. 67169689Skan(define_cpu_unit "k6_decode_short0" "k6_decoder") 68169689Skan(define_cpu_unit "k6_decode_short1" "k6_decoder") 69169689Skan(define_cpu_unit "k6_decode_long" "k6_decoder") 70169689Skan(exclusion_set "k6_decode_long" "k6_decode_short0,k6_decode_short1") 71169689Skan(define_reservation "k6_decode_short" "k6_decode_short0|k6_decode_short1") 72169689Skan(define_reservation "k6_decode_vector" "k6_decode_long") 73117395Skan 74169689Skan(define_cpu_unit "k6_store" "k6_store_unit") 75169689Skan(define_cpu_unit "k6_load" "k6_load_unit") 76169689Skan(define_cpu_unit "k6_alux,k6_aluy" "k6_integer_units") 77169689Skan(define_cpu_unit "k6_fpu" "k6_fpu_unit") 78169689Skan(define_cpu_unit "k6_branch" "k6_branch_unit") 79117395Skan 80169689Skan;; Shift instructions and certain arithmetic are issued only on Integer X. 81169689Skan(define_insn_reservation "k6_alux_only" 1 82169689Skan (and (eq_attr "cpu" "k6") 83169689Skan (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld") 84169689Skan (eq_attr "memory" "none"))) 85169689Skan "k6_decode_short,k6_alux") 86117395Skan 87169689Skan(define_insn_reservation "k6_alux_only_load" 3 88169689Skan (and (eq_attr "cpu" "k6") 89169689Skan (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld") 90169689Skan (eq_attr "memory" "load"))) 91169689Skan "k6_decode_short,k6_load,k6_alux") 92117395Skan 93169689Skan(define_insn_reservation "k6_alux_only_store" 3 94169689Skan (and (eq_attr "cpu" "k6") 95169689Skan (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,cld") 96169689Skan (eq_attr "memory" "store,both,unknown"))) 97169689Skan "k6_decode_long,k6_load,k6_alux,k6_store") 98117395Skan 99169689Skan;; Integer divide and multiply can only be issued on Integer X, too. 100169689Skan(define_insn_reservation "k6_alu_imul" 2 101169689Skan (and (eq_attr "cpu" "k6") 102169689Skan (eq_attr "type" "imul")) 103169689Skan "k6_decode_vector,k6_alux*3") 104117395Skan 105169689Skan(define_insn_reservation "k6_alu_imul_load" 4 106169689Skan (and (eq_attr "cpu" "k6") 107169689Skan (and (eq_attr "type" "imul") 108169689Skan (eq_attr "memory" "load"))) 109169689Skan "k6_decode_vector,k6_load,k6_alux*3") 110117395Skan 111169689Skan(define_insn_reservation "k6_alu_imul_store" 4 112169689Skan (and (eq_attr "cpu" "k6") 113169689Skan (and (eq_attr "type" "imul") 114169689Skan (eq_attr "memory" "store,both,unknown"))) 115169689Skan "k6_decode_vector,k6_load,k6_alux*3,k6_store") 116117395Skan 117169689Skan;; ??? Guessed latencies based on the old pipeline description. 118169689Skan(define_insn_reservation "k6_alu_idiv" 17 119169689Skan (and (eq_attr "cpu" "k6") 120169689Skan (and (eq_attr "type" "idiv") 121169689Skan (eq_attr "memory" "none"))) 122169689Skan "k6_decode_vector,k6_alux*17") 123117395Skan 124169689Skan(define_insn_reservation "k6_alu_idiv_mem" 19 125169689Skan (and (eq_attr "cpu" "k6") 126169689Skan (and (eq_attr "type" "idiv") 127169689Skan (eq_attr "memory" "!none"))) 128169689Skan "k6_decode_vector,k6_load,k6_alux*17") 129117395Skan 130169689Skan;; Basic word and doubleword ALU ops can be issued on both Integer units. 131169689Skan(define_insn_reservation "k6_alu" 1 132169689Skan (and (eq_attr "cpu" "k6") 133169689Skan (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc") 134169689Skan (eq_attr "memory" "none"))) 135169689Skan "k6_decode_short,k6_alux|k6_aluy") 136117395Skan 137169689Skan(define_insn_reservation "k6_alu_load" 3 138169689Skan (and (eq_attr "cpu" "k6") 139169689Skan (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc") 140169689Skan (eq_attr "memory" "load"))) 141169689Skan "k6_decode_short,k6_load,k6_alux|k6_aluy") 142117395Skan 143169689Skan(define_insn_reservation "k6_alu_store" 3 144169689Skan (and (eq_attr "cpu" "k6") 145169689Skan (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc") 146169689Skan (eq_attr "memory" "store,both,unknown"))) 147169689Skan "k6_decode_long,k6_load,k6_alux|k6_aluy,k6_store") 148117395Skan 149169689Skan;; A "load immediate" operation does not require execution at all, 150169689Skan;; it is available immediately after decoding. Special-case this. 151169689Skan(define_insn_reservation "k6_alu_imov" 1 152169689Skan (and (eq_attr "cpu" "k6") 153169689Skan (and (eq_attr "type" "imov") 154169689Skan (and (eq_attr "memory" "none") 155169689Skan (match_operand 1 "nonimmediate_operand")))) 156169689Skan "k6_decode_short,k6_alux|k6_aluy") 157117395Skan 158169689Skan(define_insn_reservation "k6_alu_imov_imm" 0 159169689Skan (and (eq_attr "cpu" "k6") 160169689Skan (and (eq_attr "type" "imov") 161169689Skan (and (eq_attr "memory" "none") 162169689Skan (match_operand 1 "immediate_operand")))) 163169689Skan "k6_decode_short") 164117395Skan 165169689Skan(define_insn_reservation "k6_alu_imov_load" 2 166169689Skan (and (eq_attr "cpu" "k6") 167169689Skan (and (eq_attr "type" "imov") 168169689Skan (eq_attr "memory" "load"))) 169169689Skan "k6_decode_short,k6_load") 170117395Skan 171169689Skan(define_insn_reservation "k6_alu_imov_store" 1 172169689Skan (and (eq_attr "cpu" "k6") 173169689Skan (and (eq_attr "type" "imov") 174169689Skan (eq_attr "memory" "store"))) 175169689Skan "k6_decode_short,k6_store") 176169689Skan 177169689Skan(define_insn_reservation "k6_alu_imov_both" 2 178169689Skan (and (eq_attr "cpu" "k6") 179169689Skan (and (eq_attr "type" "imov") 180169689Skan (eq_attr "memory" "both,unknown"))) 181169689Skan "k6_decode_long,k6_load,k6_alux|k6_aluy") 182169689Skan 183169689Skan;; The branch unit. 184169689Skan(define_insn_reservation "k6_branch_call" 1 185169689Skan (and (eq_attr "cpu" "k6") 186169689Skan (eq_attr "type" "call,callv")) 187169689Skan "k6_decode_vector,k6_branch") 188169689Skan 189169689Skan(define_insn_reservation "k6_branch_branch" 1 190169689Skan (and (eq_attr "cpu" "k6") 191169689Skan (eq_attr "type" "ibr")) 192169689Skan "k6_decode_short,k6_branch") 193169689Skan 194169689Skan;; The load and units have two pipeline stages. The load latency is 195169689Skan;; two cycles. 196169689Skan(define_insn_reservation "k6_load_pop" 3 197169689Skan (and (eq_attr "cpu" "k6") 198169689Skan (ior (eq_attr "type" "pop") 199169689Skan (eq_attr "memory" "load,both"))) 200169689Skan "k6_decode_short,k6_load") 201169689Skan 202169689Skan(define_insn_reservation "k6_load_leave" 5 203169689Skan (and (eq_attr "cpu" "k6") 204169689Skan (eq_attr "type" "leave")) 205169689Skan "k6_decode_long,k6_load,(k6_alux|k6_aluy)*2") 206169689Skan 207169689Skan;; ??? From the old pipeline description. Egad! 208169689Skan;; ??? Apparently we take care of this reservation in adjust_cost. 209169689Skan(define_insn_reservation "k6_load_str" 10 210169689Skan (and (eq_attr "cpu" "k6") 211169689Skan (and (eq_attr "type" "str") 212169689Skan (eq_attr "memory" "load,both"))) 213169689Skan "k6_decode_vector,k6_load*10") 214169689Skan 215169689Skan;; The store unit handles lea and push. It is otherwise unmodelled. 216169689Skan(define_insn_reservation "k6_store_lea" 2 217169689Skan (and (eq_attr "cpu" "k6") 218169689Skan (eq_attr "type" "lea")) 219169689Skan "k6_decode_short,k6_store,k6_alux|k6_aluy") 220169689Skan 221169689Skan(define_insn_reservation "k6_store_push" 2 222169689Skan (and (eq_attr "cpu" "k6") 223169689Skan (ior (eq_attr "type" "push") 224169689Skan (eq_attr "memory" "store,both"))) 225169689Skan "k6_decode_short,k6_store") 226169689Skan 227169689Skan(define_insn_reservation "k6_store_str" 10 228169689Skan (and (eq_attr "cpu" "k6") 229169689Skan (eq_attr "type" "str")) 230169689Skan "k6_store*10") 231169689Skan 232169689Skan;; Most FPU instructions have latency 2 and throughput 2. 233169689Skan(define_insn_reservation "k6_fpu" 2 234169689Skan (and (eq_attr "cpu" "k6") 235169689Skan (and (eq_attr "type" "fop,fmov,fcmp,fistp") 236169689Skan (eq_attr "memory" "none"))) 237169689Skan "k6_decode_vector,k6_fpu*2") 238169689Skan 239169689Skan(define_insn_reservation "k6_fpu_load" 6 240169689Skan (and (eq_attr "cpu" "k6") 241169689Skan (and (eq_attr "type" "fop,fmov,fcmp,fistp") 242169689Skan (eq_attr "memory" "load,both"))) 243169689Skan "k6_decode_short,k6_load,k6_fpu*2") 244169689Skan 245169689Skan(define_insn_reservation "k6_fpu_store" 6 246169689Skan (and (eq_attr "cpu" "k6") 247169689Skan (and (eq_attr "type" "fop,fmov,fcmp,fistp") 248169689Skan (eq_attr "memory" "store"))) 249169689Skan "k6_decode_short,k6_store,k6_fpu*2") 250169689Skan 251169689Skan(define_insn_reservation "k6_fpu_fmul" 2 252169689Skan (and (eq_attr "cpu" "k6") 253169689Skan (and (eq_attr "type" "fmul") 254169689Skan (eq_attr "memory" "none"))) 255169689Skan "k6_decode_short,k6_fpu*2") 256169689Skan 257169689Skan(define_insn_reservation "k6_fpu_fmul_load" 2 258169689Skan (and (eq_attr "cpu" "k6") 259169689Skan (and (eq_attr "type" "fmul") 260169689Skan (eq_attr "memory" "load,both"))) 261169689Skan "k6_decode_short,k6_load,k6_fpu*2") 262169689Skan 263169689Skan;; ??? Guessed latencies from the old pipeline description. 264169689Skan(define_insn_reservation "k6_fpu_expensive" 56 265169689Skan (and (eq_attr "cpu" "k6") 266169689Skan (eq_attr "type" "fdiv,fpspc")) 267169689Skan "k6_decode_short,k6_fpu*56") 268169689Skan 269