athlon.md revision 132718
1233294Sstas;; AMD Athlon Scheduling 2178825Sdfr;; 3233294Sstas;; The Athlon does contain three pipelined FP units, three integer units and 4233294Sstas;; three address generation units. 5233294Sstas;; 6233294Sstas;; The predecode logic is determining boundaries of instructions in the 64 7178825Sdfr;; byte cache line. So the cache line straddling problem of K6 might be issue 8178825Sdfr;; here as well, but it is not noted in the documentation. 9178825Sdfr;; 10178825Sdfr;; Three DirectPath instructions decoders and only one VectorPath decoder 11233294Sstas;; is available. They can decode three DirectPath instructions or one VectorPath 12178825Sdfr;; instruction per cycle. 13178825Sdfr;; Decoded macro instructions are then passed to 72 entry instruction control 14178825Sdfr;; unit, that passes 15233294Sstas;; it to the specialized integer (18 entry) and fp (36 entry) schedulers. 16178825Sdfr;; 17178825Sdfr;; The load/store queue unit is not attached to the schedulers but 18178825Sdfr;; communicates with all the execution units separately instead. 19178825Sdfr 20178825Sdfr(define_attr "athlon_decode" "direct,vector,double" 21233294Sstas (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,leave") 22178825Sdfr (const_string "vector") 23178825Sdfr (and (eq_attr "type" "push") 24178825Sdfr (match_operand 1 "memory_operand" "")) 25178825Sdfr (const_string "vector") 26178825Sdfr (and (eq_attr "type" "fmov") 27178825Sdfr (and (eq_attr "memory" "load,store") 28178825Sdfr (eq_attr "mode" "XF"))) 29178825Sdfr (const_string "vector")] 30178825Sdfr (const_string "direct"))) 31178825Sdfr 32233294Sstas;; 33178825Sdfr;; decode0 decode1 decode2 34178825Sdfr;; \ | / 35178825Sdfr;; instruction control unit (72 entry scheduler) 36178825Sdfr;; | | 37178825Sdfr;; integer scheduler (18) stack map 38178825Sdfr;; / | | | | \ stack rename 39178825Sdfr;; ieu0 agu0 ieu1 agu1 ieu2 agu2 scheduler 40233294Sstas;; | agu0 | agu1 agu2 register file 41178825Sdfr;; | \ | | / | | | 42178825Sdfr;; \ /\ | / fadd fmul fstore 43178825Sdfr;; \ / \ | / fadd fmul fstore 44178825Sdfr;; imul load/store (2x) fadd fmul fstore 45178825Sdfr 46178825Sdfr(define_automaton "athlon,athlon_load,athlon_mult,athlon_fp") 47178825Sdfr(define_cpu_unit "athlon-decode0" "athlon") 48233294Sstas(define_cpu_unit "athlon-decode1" "athlon") 49178825Sdfr(define_cpu_unit "athlon-decode2" "athlon") 50178825Sdfr(define_cpu_unit "athlon-decodev" "athlon") 51233294Sstas;; Model the fact that double decoded instruction may take 2 cycles 52178825Sdfr;; to decode when decoder2 and decoder0 in next cycle 53178825Sdfr;; is used (this is needed to allow troughput of 1.5 double decoded 54233294Sstas;; instructions per cycle). 55178825Sdfr;; 56178825Sdfr;; In order to avoid dependence between reservation of decoder 57178825Sdfr;; and other units, we model decoder as two stage fully pipelined unit 58178825Sdfr;; and only double decoded instruction may occupy unit in the first cycle. 59178825Sdfr;; With this scheme however two double instructions can be issued cycle0. 60233294Sstas;; 61178825Sdfr;; Avoid this by using presence set requiring decoder0 to be allocated 62178825Sdfr;; too. Vector decoded instructions then can't be issued when 63178825Sdfr;; modeled as consuming decoder0+decoder1+decoder2. 64233294Sstas;; We solve that by specialized vector decoder unit and exclusion set. 65178825Sdfr(presence_set "athlon-decode2" "athlon-decode0") 66178825Sdfr(exclusion_set "athlon-decodev" "athlon-decode0,athlon-decode1,athlon-decode2") 67178825Sdfr(define_reservation "athlon-vector" "nothing,athlon-decodev") 68233294Sstas(define_reservation "athlon-direct0" "nothing,athlon-decode0") 69178825Sdfr(define_reservation "athlon-direct" "nothing, 70178825Sdfr (athlon-decode0 | athlon-decode1 71178825Sdfr | athlon-decode2)") 72233294Sstas;; Double instructions behaves like two direct instructions. 73178825Sdfr(define_reservation "athlon-double" "((athlon-decode2, athlon-decode0) 74178825Sdfr | (nothing,(athlon-decode0 + athlon-decode1)) 75178825Sdfr | (nothing,(athlon-decode1 + athlon-decode2)))") 76233294Sstas 77178825Sdfr;; Agu and ieu unit results in extremely large automatons and 78178825Sdfr;; in our approximation they are hardly filled in. Only ieu 79178825Sdfr;; unit can, as issue rate is 3 and agu unit is always used 80233294Sstas;; first in the insn reservations. Skip the models. 81178825Sdfr 82178825Sdfr;(define_cpu_unit "athlon-ieu0" "athlon_ieu") 83178825Sdfr;(define_cpu_unit "athlon-ieu1" "athlon_ieu") 84233294Sstas;(define_cpu_unit "athlon-ieu2" "athlon_ieu") 85178825Sdfr;(define_reservation "athlon-ieu" "(athlon-ieu0 | athlon-ieu1 | athlon-ieu2)") 86178825Sdfr(define_reservation "athlon-ieu" "nothing") 87178825Sdfr(define_cpu_unit "athlon-ieu0" "athlon") 88233294Sstas;(define_cpu_unit "athlon-agu0" "athlon_agu") 89178825Sdfr;(define_cpu_unit "athlon-agu1" "athlon_agu") 90178825Sdfr;(define_cpu_unit "athlon-agu2" "athlon_agu") 91178825Sdfr;(define_reservation "athlon-agu" "(athlon-agu0 | athlon-agu1 | athlon-agu2)") 92233294Sstas(define_reservation "athlon-agu" "nothing") 93178825Sdfr 94178825Sdfr(define_cpu_unit "athlon-mult" "athlon_mult") 95178825Sdfr 96178825Sdfr(define_cpu_unit "athlon-load0" "athlon_load") 97178825Sdfr(define_cpu_unit "athlon-load1" "athlon_load") 98178825Sdfr(define_reservation "athlon-load" "athlon-agu, 99178825Sdfr (athlon-load0 | athlon-load1),nothing") 100178825Sdfr;; 128bit SSE instructions issue two loads at once 101178825Sdfr(define_reservation "athlon-load2" "athlon-agu, 102178825Sdfr (athlon-load0 + athlon-load1),nothing") 103178825Sdfr 104178825Sdfr(define_reservation "athlon-store" "(athlon-load0 | athlon-load1)") 105233294Sstas;; 128bit SSE instructions issue two stores at once 106178825Sdfr(define_reservation "athlon-store2" "(athlon-load0 + athlon-load1)") 107178825Sdfr 108178825Sdfr 109178825Sdfr;; The FP operations start to execute at stage 12 in the pipeline, while 110233294Sstas;; integer operations start to execute at stage 9 for Athlon and 11 for K8 111178825Sdfr;; Compensate the difference for Athlon because it results in significantly 112178825Sdfr;; smaller automata. 113178825Sdfr(define_reservation "athlon-fpsched" "nothing,nothing,nothing") 114178825Sdfr;; The floating point loads. 115178825Sdfr(define_reservation "athlon-fpload" "(athlon-fpsched + athlon-load)") 116233294Sstas(define_reservation "athlon-fpload2" "(athlon-fpsched + athlon-load2)") 117178825Sdfr(define_reservation "athlon-fploadk8" "(athlon-fpsched + athlon-load)") 118178825Sdfr(define_reservation "athlon-fpload2k8" "(athlon-fpsched + athlon-load2)") 119178825Sdfr 120233294Sstas 121178825Sdfr;; The three fp units are fully pipelined with latency of 3 122178825Sdfr(define_cpu_unit "athlon-fadd" "athlon_fp") 123178825Sdfr(define_cpu_unit "athlon-fmul" "athlon_fp") 124178825Sdfr(define_cpu_unit "athlon-fstore" "athlon_fp") 125233294Sstas(define_reservation "athlon-fany" "(athlon-fstore | athlon-fmul | athlon-fadd)") 126178825Sdfr(define_reservation "athlon-faddmul" "(athlon-fmul | athlon-fadd)") 127178825Sdfr 128178825Sdfr;; Vector operations usually consume many of pipes. 129178825Sdfr(define_reservation "athlon-fvector" "(athlon-fadd + athlon-fmul + athlon-fstore)") 130233294Sstas 131178825Sdfr 132178825Sdfr;; Jump instructions are executed in the branch unit completely transparent to us 133178825Sdfr(define_insn_reservation "athlon_branch" 0 134178825Sdfr (and (eq_attr "cpu" "athlon,k8") 135178825Sdfr (eq_attr "type" "ibr")) 136178825Sdfr "athlon-direct,athlon-ieu") 137178825Sdfr(define_insn_reservation "athlon_call" 0 138178825Sdfr (and (eq_attr "cpu" "athlon,k8") 139233294Sstas (eq_attr "type" "call,callv")) 140178825Sdfr "athlon-vector,athlon-ieu") 141178825Sdfr 142178825Sdfr;; Latency of push operation is 3 cycles, but ESP value is available 143178825Sdfr;; earlier 144178825Sdfr(define_insn_reservation "athlon_push" 2 145178825Sdfr (and (eq_attr "cpu" "athlon,k8") 146178825Sdfr (eq_attr "type" "push")) 147178825Sdfr "athlon-direct,athlon-agu,athlon-store") 148178825Sdfr(define_insn_reservation "athlon_pop" 4 149178825Sdfr (and (eq_attr "cpu" "athlon,k8") 150178825Sdfr (eq_attr "type" "pop")) 151178825Sdfr "athlon-vector,athlon-load,athlon-ieu") 152178825Sdfr(define_insn_reservation "athlon_pop_k8" 3 153178825Sdfr (and (eq_attr "cpu" "k8") 154178825Sdfr (eq_attr "type" "pop")) 155233294Sstas "athlon-double,(athlon-ieu+athlon-load)") 156178825Sdfr(define_insn_reservation "athlon_leave" 3 157178825Sdfr (and (eq_attr "cpu" "athlon") 158233294Sstas (eq_attr "type" "leave")) 159178825Sdfr "athlon-vector,(athlon-ieu+athlon-load)") 160233294Sstas(define_insn_reservation "athlon_leave_k8" 3 161178825Sdfr (and (eq_attr "cpu" "k8") 162178825Sdfr (eq_attr "type" "leave")) 163178825Sdfr "athlon-double,(athlon-ieu+athlon-load)") 164233294Sstas 165178825Sdfr;; Lea executes in AGU unit with 2 cycles latency. 166178825Sdfr(define_insn_reservation "athlon_lea" 2 167178825Sdfr (and (eq_attr "cpu" "athlon,k8") 168178825Sdfr (eq_attr "type" "lea")) 169178825Sdfr "athlon-direct,athlon-agu,nothing") 170233294Sstas 171178825Sdfr;; Mul executes in special multiplier unit attached to IEU0 172178825Sdfr(define_insn_reservation "athlon_imul" 5 173178825Sdfr (and (eq_attr "cpu" "athlon") 174233294Sstas (and (eq_attr "type" "imul") 175178825Sdfr (eq_attr "memory" "none,unknown"))) 176178825Sdfr "athlon-vector,athlon-ieu0,athlon-mult,nothing,nothing,athlon-ieu0") 177178825Sdfr;; ??? Widening multiply is vector or double. 178178825Sdfr(define_insn_reservation "athlon_imul_k8_DI" 4 179178825Sdfr (and (eq_attr "cpu" "k8") 180178825Sdfr (and (eq_attr "type" "imul") 181178825Sdfr (and (eq_attr "mode" "DI") 182178825Sdfr (eq_attr "memory" "none,unknown")))) 183178825Sdfr "athlon-direct0,athlon-ieu0,athlon-mult,nothing,athlon-ieu0") 184178825Sdfr(define_insn_reservation "athlon_imul_k8" 3 185178825Sdfr (and (eq_attr "cpu" "k8") 186178825Sdfr (and (eq_attr "type" "imul") 187178825Sdfr (eq_attr "memory" "none,unknown"))) 188178825Sdfr "athlon-direct0,athlon-ieu0,athlon-mult,athlon-ieu0") 189178825Sdfr(define_insn_reservation "athlon_imul_mem" 8 190178825Sdfr (and (eq_attr "cpu" "athlon") 191178825Sdfr (and (eq_attr "type" "imul") 192178825Sdfr (eq_attr "memory" "load,both"))) 193178825Sdfr "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,nothing,athlon-ieu") 194178825Sdfr(define_insn_reservation "athlon_imul_mem_k8_DI" 7 195233294Sstas (and (eq_attr "cpu" "k8") 196178825Sdfr (and (eq_attr "type" "imul") 197178825Sdfr (and (eq_attr "mode" "DI") 198178825Sdfr (eq_attr "memory" "load,both")))) 199178825Sdfr "athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,athlon-ieu") 200178825Sdfr(define_insn_reservation "athlon_imul_mem_k8" 6 201178825Sdfr (and (eq_attr "cpu" "k8") 202178825Sdfr (and (eq_attr "type" "imul") 203233294Sstas (eq_attr "memory" "load,both"))) 204178825Sdfr "athlon-vector,athlon-load,athlon-ieu,athlon-mult,athlon-ieu") 205178825Sdfr 206178825Sdfr;; Idiv can not execute in parallel with other instructions. Dealing with it 207178825Sdfr;; as with short latency vector instruction is good approximation avoiding 208178825Sdfr;; scheduler from trying too hard to can hide it's latency by overlap with 209178825Sdfr;; other instructions. 210233294Sstas;; ??? Experiments show that the idiv can overlap with roughly 6 cycles 211178825Sdfr;; of the other code 212178825Sdfr 213178825Sdfr(define_insn_reservation "athlon_idiv" 6 214178825Sdfr (and (eq_attr "cpu" "athlon,k8") 215178825Sdfr (and (eq_attr "type" "idiv") 216178825Sdfr (eq_attr "memory" "none,unknown"))) 217178825Sdfr "athlon-vector,(athlon-ieu0*6+(athlon-fpsched,athlon-fvector))") 218178825Sdfr(define_insn_reservation "athlon_idiv_mem" 9 219178825Sdfr (and (eq_attr "cpu" "athlon,k8") 220178825Sdfr (and (eq_attr "type" "idiv") 221178825Sdfr (eq_attr "memory" "load,both"))) 222233294Sstas "athlon-vector,((athlon-load,athlon-ieu0*6)+(athlon-fpsched,athlon-fvector))") 223178825Sdfr;; The parallelism of string instructions is not documented. Model it same way 224178825Sdfr;; as idiv to create smaller automata. This probably does not matter much. 225178825Sdfr(define_insn_reservation "athlon_str" 6 226178825Sdfr (and (eq_attr "cpu" "athlon,k8") 227233294Sstas (and (eq_attr "type" "str") 228178825Sdfr (eq_attr "memory" "load,both,store"))) 229178825Sdfr "athlon-vector,athlon-load,athlon-ieu0*6") 230178825Sdfr 231178825Sdfr(define_insn_reservation "athlon_idirect" 1 232178825Sdfr (and (eq_attr "cpu" "athlon,k8") 233178825Sdfr (and (eq_attr "athlon_decode" "direct") 234178825Sdfr (and (eq_attr "unit" "integer,unknown") 235178825Sdfr (eq_attr "memory" "none,unknown")))) 236178825Sdfr "athlon-direct,athlon-ieu") 237178825Sdfr(define_insn_reservation "athlon_ivector" 2 238233294Sstas (and (eq_attr "cpu" "athlon,k8") 239178825Sdfr (and (eq_attr "athlon_decode" "vector") 240178825Sdfr (and (eq_attr "unit" "integer,unknown") 241178825Sdfr (eq_attr "memory" "none,unknown")))) 242178825Sdfr "athlon-vector,athlon-ieu,athlon-ieu") 243233294Sstas(define_insn_reservation "athlon_idirect_loadmov" 3 244178825Sdfr (and (eq_attr "cpu" "athlon,k8") 245178825Sdfr (and (eq_attr "type" "imov") 246178825Sdfr (eq_attr "memory" "load"))) 247233294Sstas "athlon-direct,athlon-load") 248178825Sdfr(define_insn_reservation "athlon_idirect_load" 4 249178825Sdfr (and (eq_attr "cpu" "athlon,k8") 250178825Sdfr (and (eq_attr "athlon_decode" "direct") 251233294Sstas (and (eq_attr "unit" "integer,unknown") 252178825Sdfr (eq_attr "memory" "load")))) 253178825Sdfr "athlon-direct,athlon-load,athlon-ieu") 254178825Sdfr(define_insn_reservation "athlon_ivector_load" 6 255178825Sdfr (and (eq_attr "cpu" "athlon,k8") 256178825Sdfr (and (eq_attr "athlon_decode" "vector") 257178825Sdfr (and (eq_attr "unit" "integer,unknown") 258233294Sstas (eq_attr "memory" "load")))) 259178825Sdfr "athlon-vector,athlon-load,athlon-ieu,athlon-ieu") 260178825Sdfr(define_insn_reservation "athlon_idirect_movstore" 1 261178825Sdfr (and (eq_attr "cpu" "athlon,k8") 262178825Sdfr (and (eq_attr "type" "imov") 263178825Sdfr (eq_attr "memory" "store"))) 264178825Sdfr "athlon-direct,athlon-agu,athlon-store") 265233294Sstas(define_insn_reservation "athlon_idirect_both" 4 266178825Sdfr (and (eq_attr "cpu" "athlon,k8") 267178825Sdfr (and (eq_attr "athlon_decode" "direct") 268178825Sdfr (and (eq_attr "unit" "integer,unknown") 269178825Sdfr (eq_attr "memory" "both")))) 270233294Sstas "athlon-direct,athlon-load, 271178825Sdfr athlon-ieu,athlon-store, 272178825Sdfr athlon-store") 273178825Sdfr(define_insn_reservation "athlon_ivector_both" 6 274233294Sstas (and (eq_attr "cpu" "athlon,k8") 275178825Sdfr (and (eq_attr "athlon_decode" "vector") 276178825Sdfr (and (eq_attr "unit" "integer,unknown") 277178825Sdfr (eq_attr "memory" "both")))) 278178825Sdfr "athlon-vector,athlon-load, 279178825Sdfr athlon-ieu, 280178825Sdfr athlon-ieu, 281233294Sstas athlon-store") 282178825Sdfr(define_insn_reservation "athlon_idirect_store" 1 283178825Sdfr (and (eq_attr "cpu" "athlon,k8") 284178825Sdfr (and (eq_attr "athlon_decode" "direct") 285178825Sdfr (and (eq_attr "unit" "integer,unknown") 286178825Sdfr (eq_attr "memory" "store")))) 287178825Sdfr "athlon-direct,(athlon-ieu+athlon-agu), 288178825Sdfr athlon-store") 289233294Sstas(define_insn_reservation "athlon_ivector_store" 2 290178825Sdfr (and (eq_attr "cpu" "athlon,k8") 291178825Sdfr (and (eq_attr "athlon_decode" "vector") 292178825Sdfr (and (eq_attr "unit" "integer,unknown") 293178825Sdfr (eq_attr "memory" "store")))) 294178825Sdfr "athlon-vector,(athlon-ieu+athlon-agu),athlon-ieu, 295178825Sdfr athlon-store") 296178825Sdfr 297178825Sdfr;; Athlon floatin point unit 298178825Sdfr(define_insn_reservation "athlon_fldxf" 12 299178825Sdfr (and (eq_attr "cpu" "athlon") 300178825Sdfr (and (eq_attr "type" "fmov") 301178825Sdfr (and (eq_attr "memory" "load") 302178825Sdfr (eq_attr "mode" "XF")))) 303178825Sdfr "athlon-vector,athlon-fpload2,athlon-fvector*9") 304178825Sdfr(define_insn_reservation "athlon_fldxf_k8" 13 305178825Sdfr (and (eq_attr "cpu" "k8") 306178825Sdfr (and (eq_attr "type" "fmov") 307178825Sdfr (and (eq_attr "memory" "load") 308178825Sdfr (eq_attr "mode" "XF")))) 309178825Sdfr "athlon-vector,athlon-fpload2k8,athlon-fvector*9") 310233294Sstas;; Assume superforwarding to take place so effective latency of fany op is 0. 311178825Sdfr(define_insn_reservation "athlon_fld" 0 312178825Sdfr (and (eq_attr "cpu" "athlon") 313178825Sdfr (and (eq_attr "type" "fmov") 314233294Sstas (eq_attr "memory" "load"))) 315178825Sdfr "athlon-direct,athlon-fpload,athlon-fany") 316178825Sdfr(define_insn_reservation "athlon_fld_k8" 2 317178825Sdfr (and (eq_attr "cpu" "k8") 318178825Sdfr (and (eq_attr "type" "fmov") 319178825Sdfr (eq_attr "memory" "load"))) 320178825Sdfr "athlon-direct,athlon-fploadk8,athlon-fstore") 321178825Sdfr 322233294Sstas(define_insn_reservation "athlon_fstxf" 10 323178825Sdfr (and (eq_attr "cpu" "athlon") 324178825Sdfr (and (eq_attr "type" "fmov") 325178825Sdfr (and (eq_attr "memory" "store,both") 326178825Sdfr (eq_attr "mode" "XF")))) 327178825Sdfr "athlon-vector,(athlon-fpsched+athlon-agu),(athlon-store2+(athlon-fvector*7))") 328178825Sdfr(define_insn_reservation "athlon_fstxf_k8" 8 329178825Sdfr (and (eq_attr "cpu" "k8") 330178825Sdfr (and (eq_attr "type" "fmov") 331178825Sdfr (and (eq_attr "memory" "store,both") 332178825Sdfr (eq_attr "mode" "XF")))) 333178825Sdfr "athlon-vector,(athlon-fpsched+athlon-agu),(athlon-store2+(athlon-fvector*6))") 334178825Sdfr(define_insn_reservation "athlon_fst" 4 335233294Sstas (and (eq_attr "cpu" "athlon") 336142403Snectar (and (eq_attr "type" "fmov") 337178825Sdfr (eq_attr "memory" "store,both"))) 338178825Sdfr "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)") 339142403Snectar(define_insn_reservation "athlon_fst_k8" 2 340178825Sdfr (and (eq_attr "cpu" "k8") 341142403Snectar (and (eq_attr "type" "fmov") 342178825Sdfr (eq_attr "memory" "store,both"))) 343178825Sdfr "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)") 344178825Sdfr(define_insn_reservation "athlon_fist" 4 345178825Sdfr (and (eq_attr "cpu" "athlon,k8") 346178825Sdfr (eq_attr "type" "fistp")) 347178825Sdfr "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)") 348178825Sdfr(define_insn_reservation "athlon_fmov" 2 349233294Sstas (and (eq_attr "cpu" "athlon,k8") 350178825Sdfr (eq_attr "type" "fmov")) 351178825Sdfr "athlon-direct,athlon-fpsched,athlon-faddmul") 352178825Sdfr(define_insn_reservation "athlon_fadd_load" 4 353178825Sdfr (and (eq_attr "cpu" "athlon") 354178825Sdfr (and (eq_attr "type" "fop") 355178825Sdfr (eq_attr "memory" "load"))) 356178825Sdfr "athlon-direct,athlon-fpload,athlon-fadd") 357178825Sdfr(define_insn_reservation "athlon_fadd_load_k8" 6 358178825Sdfr (and (eq_attr "cpu" "k8") 359178825Sdfr (and (eq_attr "type" "fop") 360178825Sdfr (eq_attr "memory" "load"))) 361233294Sstas "athlon-direct,athlon-fploadk8,athlon-fadd") 362178825Sdfr(define_insn_reservation "athlon_fadd" 4 363178825Sdfr (and (eq_attr "cpu" "athlon,k8") 364178825Sdfr (eq_attr "type" "fop")) 365178825Sdfr "athlon-direct,athlon-fpsched,athlon-fadd") 366233294Sstas(define_insn_reservation "athlon_fmul_load" 4 367178825Sdfr (and (eq_attr "cpu" "athlon") 368178825Sdfr (and (eq_attr "type" "fmul") 369178825Sdfr (eq_attr "memory" "load"))) 370178825Sdfr "athlon-direct,athlon-fpload,athlon-fmul") 371178825Sdfr(define_insn_reservation "athlon_fmul_load_k8" 6 372178825Sdfr (and (eq_attr "cpu" "k8") 373233294Sstas (and (eq_attr "type" "fmul") 374178825Sdfr (eq_attr "memory" "load"))) 375178825Sdfr "athlon-direct,athlon-fploadk8,athlon-fmul") 376178825Sdfr(define_insn_reservation "athlon_fmul" 4 377178825Sdfr (and (eq_attr "cpu" "athlon,k8") 378178825Sdfr (eq_attr "type" "fmul")) 379233294Sstas "athlon-direct,athlon-fpsched,athlon-fmul") 380178825Sdfr(define_insn_reservation "athlon_fsgn" 2 381178825Sdfr (and (eq_attr "cpu" "athlon,k8") 382178825Sdfr (eq_attr "type" "fsgn")) 383178825Sdfr "athlon-direct,athlon-fpsched,athlon-fmul") 384233294Sstas(define_insn_reservation "athlon_fdiv_load" 24 385178825Sdfr (and (eq_attr "cpu" "athlon") 386178825Sdfr (and (eq_attr "type" "fdiv") 387178825Sdfr (eq_attr "memory" "load"))) 388178825Sdfr "athlon-direct,athlon-fpload,athlon-fmul") 389178825Sdfr(define_insn_reservation "athlon_fdiv_load_k8" 13 390233294Sstas (and (eq_attr "cpu" "k8") 391178825Sdfr (and (eq_attr "type" "fdiv") 392178825Sdfr (eq_attr "memory" "load"))) 393178825Sdfr "athlon-direct,athlon-fploadk8,athlon-fmul") 394233294Sstas(define_insn_reservation "athlon_fdiv" 24 395178825Sdfr (and (eq_attr "cpu" "athlon") 396178825Sdfr (eq_attr "type" "fdiv")) 397178825Sdfr "athlon-direct,athlon-fpsched,athlon-fmul") 398178825Sdfr(define_insn_reservation "athlon_fdiv_k8" 11 399178825Sdfr (and (eq_attr "cpu" "k8") 400178825Sdfr (eq_attr "type" "fdiv")) 401178825Sdfr "athlon-direct,athlon-fpsched,athlon-fmul") 402233294Sstas(define_insn_reservation "athlon_fpspc_load" 103 403120945Snectar (and (eq_attr "cpu" "athlon,k8") 404120945Snectar (and (eq_attr "type" "fpspc") 405120945Snectar (eq_attr "memory" "load"))) 406120945Snectar "athlon-vector,athlon-fpload,athlon-fvector") 407233294Sstas(define_insn_reservation "athlon_fpspc" 100 408120945Snectar (and (eq_attr "cpu" "athlon,k8") 409120945Snectar (eq_attr "type" "fpspc")) 410120945Snectar "athlon-vector,athlon-fpsched,athlon-fvector") 411233294Sstas(define_insn_reservation "athlon_fcmov_load" 7 412120945Snectar (and (eq_attr "cpu" "athlon") 413120945Snectar (and (eq_attr "type" "fcmov") 414120945Snectar (eq_attr "memory" "load"))) 415120945Snectar "athlon-vector,athlon-fpload,athlon-fvector") 416120945Snectar(define_insn_reservation "athlon_fcmov" 7 417120945Snectar (and (eq_attr "cpu" "athlon") 418120945Snectar (eq_attr "type" "fcmov")) 419233294Sstas "athlon-vector,athlon-fpsched,athlon-fvector") 420120945Snectar(define_insn_reservation "athlon_fcmov_load_k8" 17 421120945Snectar (and (eq_attr "cpu" "k8") 422120945Snectar (and (eq_attr "type" "fcmov") 423120945Snectar (eq_attr "memory" "load"))) 424120945Snectar "athlon-vector,athlon-fploadk8,athlon-fvector") 425233294Sstas(define_insn_reservation "athlon_fcmov_k8" 15 426120945Snectar (and (eq_attr "cpu" "k8") 427120945Snectar (eq_attr "type" "fcmov")) 428120945Snectar "athlon-vector,athlon-fpsched,athlon-fvector") 429120945Snectar;; fcomi is vector decoded by uses only one pipe. 430120945Snectar(define_insn_reservation "athlon_fcomi_load" 3 431120945Snectar (and (eq_attr "cpu" "athlon") 432120945Snectar (and (eq_attr "type" "fcmp") 433178825Sdfr (and (eq_attr "athlon_decode" "vector") 434178825Sdfr (eq_attr "memory" "load")))) 435178825Sdfr "athlon-vector,athlon-fpload,athlon-fadd") 436178825Sdfr(define_insn_reservation "athlon_fcomi_load_k8" 5 437178825Sdfr (and (eq_attr "cpu" "k8") 438178825Sdfr (and (eq_attr "type" "fcmp") 439178825Sdfr (and (eq_attr "athlon_decode" "vector") 440178825Sdfr (eq_attr "memory" "load")))) 441178825Sdfr "athlon-vector,athlon-fploadk8,athlon-fadd") 442178825Sdfr(define_insn_reservation "athlon_fcomi" 3 443178825Sdfr (and (eq_attr "cpu" "athlon,k8") 444178825Sdfr (and (eq_attr "athlon_decode" "vector") 445178825Sdfr (eq_attr "type" "fcmp"))) 446178825Sdfr "athlon-vector,athlon-fpsched,athlon-fadd") 447178825Sdfr(define_insn_reservation "athlon_fcom_load" 2 448178825Sdfr (and (eq_attr "cpu" "athlon") 449178825Sdfr (and (eq_attr "type" "fcmp") 450178825Sdfr (eq_attr "memory" "load"))) 451178825Sdfr "athlon-direct,athlon-fpload,athlon-fadd") 452120945Snectar(define_insn_reservation "athlon_fcom_load_k8" 4 453120945Snectar (and (eq_attr "cpu" "k8") 454120945Snectar (and (eq_attr "type" "fcmp") 455120945Snectar (eq_attr "memory" "load"))) 456120945Snectar "athlon-direct,athlon-fploadk8,athlon-fadd") 457107207Snectar(define_insn_reservation "athlon_fcom" 2 458107207Snectar (and (eq_attr "cpu" "athlon,k8") 459120945Snectar (eq_attr "type" "fcmp")) 460107207Snectar "athlon-direct,athlon-fpsched,athlon-fadd") 461103423Snectar;; Never seen by the scheduler because we still don't do post reg-stack 462103423Snectar;; scheduling. 463103423Snectar;(define_insn_reservation "athlon_fxch" 2 464103423Snectar; (and (eq_attr "cpu" "athlon,k8") 465103423Snectar; (eq_attr "type" "fxch")) 466103423Snectar; "athlon-direct,athlon-fpsched,athlon-fany") 467103423Snectar 468103423Snectar;; Athlon handle MMX operations in the FPU unit with shorter latencies 469103423Snectar 470103423Snectar(define_insn_reservation "athlon_movlpd_load" 0 471103423Snectar (and (eq_attr "cpu" "athlon") 472103423Snectar (and (eq_attr "type" "ssemov") 473103423Snectar (match_operand:DF 1 "memory_operand" ""))) 474103423Snectar "athlon-direct,athlon-fpload,athlon-fany") 475103423Snectar(define_insn_reservation "athlon_movlpd_load_k8" 2 476103423Snectar (and (eq_attr "cpu" "k8") 477103423Snectar (and (eq_attr "type" "ssemov") 478103423Snectar (match_operand:DF 1 "memory_operand" ""))) 479102644Snectar "athlon-direct,athlon-fploadk8,athlon-fstore") 480102644Snectar(define_insn_reservation "athlon_movaps_load_k8" 2 481102644Snectar (and (eq_attr "cpu" "k8") 482102644Snectar (and (eq_attr "type" "ssemov") 483102644Snectar (and (eq_attr "mode" "V4SF,V2DF,TI") 484102644Snectar (eq_attr "memory" "load")))) 485102644Snectar "athlon-double,athlon-fpload2k8,athlon-fstore,athlon-fstore") 486102644Snectar(define_insn_reservation "athlon_movaps_load" 0 487102644Snectar (and (eq_attr "cpu" "athlon") 488102644Snectar (and (eq_attr "type" "ssemov") 489102644Snectar (and (eq_attr "mode" "V4SF,V2DF,TI") 490102644Snectar (eq_attr "memory" "load")))) 491102644Snectar "athlon-vector,athlon-fpload2,(athlon-fany+athlon-fany)") 49290926Snectar(define_insn_reservation "athlon_movss_load" 1 49390926Snectar (and (eq_attr "cpu" "athlon") 49490926Snectar (and (eq_attr "type" "ssemov") 49590926Snectar (and (eq_attr "mode" "SF,DI") 49690926Snectar (eq_attr "memory" "load")))) 49790926Snectar "athlon-vector,athlon-fpload,(athlon-fany*2)") 49890926Snectar(define_insn_reservation "athlon_movss_load_k8" 1 49990926Snectar (and (eq_attr "cpu" "k8") 50090926Snectar (and (eq_attr "type" "ssemov") 50190926Snectar (and (eq_attr "mode" "SF,DI") 50290926Snectar (eq_attr "memory" "load")))) 50390926Snectar "athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fany)") 50490926Snectar(define_insn_reservation "athlon_mmxsseld" 0 50590926Snectar (and (eq_attr "cpu" "athlon") 50690926Snectar (and (eq_attr "type" "mmxmov,ssemov") 50790926Snectar (eq_attr "memory" "load"))) 50890926Snectar "athlon-direct,athlon-fpload,athlon-fany") 50990926Snectar(define_insn_reservation "athlon_mmxsseld_k8" 2 51090926Snectar (and (eq_attr "cpu" "k8") 51190926Snectar (and (eq_attr "type" "mmxmov,ssemov") 51290926Snectar (eq_attr "memory" "load"))) 51390926Snectar "athlon-direct,athlon-fploadk8,athlon-fstore") 51490926Snectar(define_insn_reservation "athlon_mmxssest" 3 51590926Snectar (and (eq_attr "cpu" "k8") 51690926Snectar (and (eq_attr "type" "mmxmov,ssemov") 51790926Snectar (and (eq_attr "mode" "V4SF,V2DF,TI") 51890926Snectar (eq_attr "memory" "store,both")))) 51990926Snectar "athlon-vector,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)") 52090926Snectar(define_insn_reservation "athlon_mmxssest_k8" 3 52190926Snectar (and (eq_attr "cpu" "k8") 52290926Snectar (and (eq_attr "type" "mmxmov,ssemov") 52390926Snectar (and (eq_attr "mode" "V4SF,V2DF,TI") 52490926Snectar (eq_attr "memory" "store,both")))) 52590926Snectar "athlon-double,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)") 52690926Snectar(define_insn_reservation "athlon_mmxssest_short" 2 52790926Snectar (and (eq_attr "cpu" "athlon,k8") 52890926Snectar (and (eq_attr "type" "mmxmov,ssemov") 52990926Snectar (eq_attr "memory" "store,both"))) 53090926Snectar "athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)") 53190926Snectar(define_insn_reservation "athlon_movaps" 2 53290926Snectar (and (eq_attr "cpu" "k8") 53390926Snectar (and (eq_attr "type" "ssemov") 53490926Snectar (eq_attr "mode" "V4SF,V2DF,TI"))) 53590926Snectar "athlon-double,athlon-fpsched,(athlon-faddmul+athlon-faddmul)") 53690926Snectar(define_insn_reservation "athlon_movaps_k8" 2 53790926Snectar (and (eq_attr "cpu" "athlon") 53890926Snectar (and (eq_attr "type" "ssemov") 53990926Snectar (eq_attr "mode" "V4SF,V2DF,TI"))) 54090926Snectar "athlon-vector,athlon-fpsched,(athlon-faddmul+athlon-faddmul)") 54190926Snectar(define_insn_reservation "athlon_mmxssemov" 2 54290926Snectar (and (eq_attr "cpu" "athlon,k8") 54390926Snectar (eq_attr "type" "mmxmov,ssemov")) 54490926Snectar "athlon-direct,athlon-fpsched,athlon-faddmul") 54590926Snectar(define_insn_reservation "athlon_mmxmul_load" 4 54690926Snectar (and (eq_attr "cpu" "athlon,k8") 54790926Snectar (and (eq_attr "type" "mmxmul") 54890926Snectar (eq_attr "memory" "load"))) 54990926Snectar "athlon-direct,athlon-fpload,athlon-fmul") 55090926Snectar(define_insn_reservation "athlon_mmxmul" 3 55178527Sassar (and (eq_attr "cpu" "athlon,k8") 55278527Sassar (eq_attr "type" "mmxmul")) 55378527Sassar "athlon-direct,athlon-fpsched,athlon-fmul") 55478527Sassar(define_insn_reservation "athlon_mmx_load" 3 55578527Sassar (and (eq_attr "cpu" "athlon,k8") 55678527Sassar (and (eq_attr "unit" "mmx") 55778527Sassar (eq_attr "memory" "load"))) 55878527Sassar "athlon-direct,athlon-fpload,athlon-faddmul") 55978527Sassar(define_insn_reservation "athlon_mmx" 2 56078527Sassar (and (eq_attr "cpu" "athlon,k8") 56178527Sassar (eq_attr "unit" "mmx")) 56278527Sassar "athlon-direct,athlon-fpsched,athlon-faddmul") 56378527Sassar;; SSE operations are handled by the i387 unit as well. The latency 56478527Sassar;; is same as for i387 operations for scalar operations 56578527Sassar 56678527Sassar(define_insn_reservation "athlon_sselog_load" 3 56778527Sassar (and (eq_attr "cpu" "athlon") 56878527Sassar (and (eq_attr "type" "sselog") 56978527Sassar (eq_attr "memory" "load"))) 57078527Sassar "athlon-vector,athlon-fpload2,(athlon-fmul*2)") 57178527Sassar(define_insn_reservation "athlon_sselog_load_k8" 5 57278527Sassar (and (eq_attr "cpu" "k8") 57378527Sassar (and (eq_attr "type" "sselog") 57478527Sassar (eq_attr "memory" "load"))) 57578527Sassar "athlon-double,athlon-fpload2k8,(athlon-fmul*2)") 57678527Sassar(define_insn_reservation "athlon_sselog" 3 57778527Sassar (and (eq_attr "cpu" "athlon") 57878527Sassar (eq_attr "type" "sselog")) 57978527Sassar "athlon-vector,athlon-fpsched,athlon-fmul*2") 58078527Sassar(define_insn_reservation "athlon_sselog_k8" 3 58178527Sassar (and (eq_attr "cpu" "k8") 58278527Sassar (eq_attr "type" "sselog")) 58378527Sassar "athlon-double,athlon-fpsched,athlon-fmul") 58478527Sassar;; ??? pcmp executes in addmul, probably not wortwhile to brother about that. 58578527Sassar(define_insn_reservation "athlon_ssecmp_load" 2 58678527Sassar (and (eq_attr "cpu" "athlon") 58778527Sassar (and (eq_attr "type" "ssecmp") 58878527Sassar (and (eq_attr "mode" "SF,DF,DI") 58978527Sassar (eq_attr "memory" "load")))) 59078527Sassar "athlon-direct,athlon-fpload,athlon-fadd") 59178527Sassar(define_insn_reservation "athlon_ssecmp_load_k8" 4 59278527Sassar (and (eq_attr "cpu" "k8") 59378527Sassar (and (eq_attr "type" "ssecmp") 59472445Sassar (and (eq_attr "mode" "SF,DF,DI,TI") 59572445Sassar (eq_attr "memory" "load")))) 59672445Sassar "athlon-direct,athlon-fploadk8,athlon-fadd") 59772445Sassar(define_insn_reservation "athlon_ssecmp" 2 59872445Sassar (and (eq_attr "cpu" "athlon,k8") 59972445Sassar (and (eq_attr "type" "ssecmp") 60072445Sassar (eq_attr "mode" "SF,DF,DI,TI"))) 60172445Sassar "athlon-direct,athlon-fpsched,athlon-fadd") 60272445Sassar(define_insn_reservation "athlon_ssecmpvector_load" 3 60372445Sassar (and (eq_attr "cpu" "athlon") 60472445Sassar (and (eq_attr "type" "ssecmp") 60572445Sassar (eq_attr "memory" "load"))) 60672445Sassar "athlon-vector,athlon-fpload2,(athlon-fadd*2)") 60772445Sassar(define_insn_reservation "athlon_ssecmpvector_load_k8" 5 60872445Sassar (and (eq_attr "cpu" "k8") 60972445Sassar (and (eq_attr "type" "ssecmp") 61072445Sassar (eq_attr "memory" "load"))) 61172445Sassar "athlon-double,athlon-fpload2k8,(athlon-fadd*2)") 61272445Sassar(define_insn_reservation "athlon_ssecmpvector" 3 61372445Sassar (and (eq_attr "cpu" "athlon") 61472445Sassar (eq_attr "type" "ssecmp")) 61572445Sassar "athlon-vector,athlon-fpsched,(athlon-fadd*2)") 61672445Sassar(define_insn_reservation "athlon_ssecmpvector_k8" 3 61772445Sassar (and (eq_attr "cpu" "k8") 61872445Sassar (eq_attr "type" "ssecmp")) 61972445Sassar "athlon-double,athlon-fpsched,(athlon-fadd*2)") 62072445Sassar(define_insn_reservation "athlon_ssecomi_load" 4 62172445Sassar (and (eq_attr "cpu" "athlon") 62272445Sassar (and (eq_attr "type" "ssecomi") 62372445Sassar (eq_attr "memory" "load"))) 62472445Sassar "athlon-vector,athlon-fpload,athlon-fadd") 62572445Sassar(define_insn_reservation "athlon_ssecomi_load_k8" 6 62672445Sassar (and (eq_attr "cpu" "k8") 62772445Sassar (and (eq_attr "type" "ssecomi") 62872445Sassar (eq_attr "memory" "load"))) 62972445Sassar "athlon-vector,athlon-fploadk8,athlon-fadd") 63072445Sassar(define_insn_reservation "athlon_ssecomi" 4 63172445Sassar (and (eq_attr "cpu" "athlon,k8") 63272445Sassar (eq_attr "type" "ssecmp")) 63372445Sassar "athlon-vector,athlon-fpsched,athlon-fadd") 63472445Sassar(define_insn_reservation "athlon_sseadd_load" 4 63572445Sassar (and (eq_attr "cpu" "athlon") 63672445Sassar (and (eq_attr "type" "sseadd") 63772445Sassar (and (eq_attr "mode" "SF,DF,DI") 63872445Sassar (eq_attr "memory" "load")))) 63972445Sassar "athlon-direct,athlon-fpload,athlon-fadd") 64072445Sassar(define_insn_reservation "athlon_sseadd_load_k8" 6 64172445Sassar (and (eq_attr "cpu" "k8") 64272445Sassar (and (eq_attr "type" "sseadd") 64372445Sassar (and (eq_attr "mode" "SF,DF,DI") 64472445Sassar (eq_attr "memory" "load")))) 64572445Sassar "athlon-direct,athlon-fploadk8,athlon-fadd") 64672445Sassar(define_insn_reservation "athlon_sseadd" 4 64772445Sassar (and (eq_attr "cpu" "athlon,k8") 64872445Sassar (and (eq_attr "type" "sseadd") 64972445Sassar (eq_attr "mode" "SF,DF,DI"))) 65072445Sassar "athlon-direct,athlon-fpsched,athlon-fadd") 65172445Sassar(define_insn_reservation "athlon_sseaddvector_load" 5 65272445Sassar (and (eq_attr "cpu" "athlon") 65372445Sassar (and (eq_attr "type" "sseadd") 65472445Sassar (eq_attr "memory" "load"))) 65572445Sassar "athlon-vector,athlon-fpload2,(athlon-fadd*2)") 65672445Sassar(define_insn_reservation "athlon_sseaddvector_load_k8" 7 65772445Sassar (and (eq_attr "cpu" "k8") 65872445Sassar (and (eq_attr "type" "sseadd") 65972445Sassar (eq_attr "memory" "load"))) 66072445Sassar "athlon-double,athlon-fpload2k8,(athlon-fadd*2)") 66172445Sassar(define_insn_reservation "athlon_sseaddvector" 5 66272445Sassar (and (eq_attr "cpu" "athlon") 66372445Sassar (eq_attr "type" "sseadd")) 66472445Sassar "athlon-vector,athlon-fpsched,(athlon-fadd*2)") 66572445Sassar(define_insn_reservation "athlon_sseaddvector_k8" 5 66672445Sassar (and (eq_attr "cpu" "k8") 66772445Sassar (eq_attr "type" "sseadd")) 66872445Sassar "athlon-double,athlon-fpsched,(athlon-fadd*2)") 66972445Sassar 67072445Sassar;; Conversions behaves very irregularly and the scheduling is critical here. 67172445Sassar;; Take each instruction separately. Assume that the mode is always set to the 67272445Sassar;; destination one and athlon_decode is set to the K8 versions. 67372445Sassar 67472445Sassar;; cvtss2sd 67572445Sassar(define_insn_reservation "athlon_ssecvt_cvtss2sd_load_k8" 4 67672445Sassar (and (eq_attr "cpu" "k8,athlon") 67772445Sassar (and (eq_attr "type" "ssecvt") 67872445Sassar (and (eq_attr "athlon_decode" "direct") 67972445Sassar (and (eq_attr "mode" "DF") 68072445Sassar (eq_attr "memory" "load"))))) 68172445Sassar "athlon-direct,athlon-fploadk8,athlon-fstore") 68272445Sassar(define_insn_reservation "athlon_ssecvt_cvtss2sd" 2 68372445Sassar (and (eq_attr "cpu" "athlon,k8") 68472445Sassar (and (eq_attr "type" "ssecvt") 68572445Sassar (and (eq_attr "athlon_decode" "direct") 68672445Sassar (eq_attr "mode" "DF")))) 68772445Sassar "athlon-direct,athlon-fpsched,athlon-fstore") 68872445Sassar;; cvtps2pd. Model same way the other double decoded FP conversions. 68972445Sassar(define_insn_reservation "athlon_ssecvt_cvtps2pd_load_k8" 5 69072445Sassar (and (eq_attr "cpu" "k8,athlon") 69172445Sassar (and (eq_attr "type" "ssecvt") 69272445Sassar (and (eq_attr "athlon_decode" "double") 69372445Sassar (and (eq_attr "mode" "V2DF,V4SF,TI") 69472445Sassar (eq_attr "memory" "load"))))) 69572445Sassar "athlon-double,athlon-fpload2k8,(athlon-fstore*2)") 69672445Sassar(define_insn_reservation "athlon_ssecvt_cvtps2pd_k8" 3 69772445Sassar (and (eq_attr "cpu" "k8,athlon") 69872445Sassar (and (eq_attr "type" "ssecvt") 69972445Sassar (and (eq_attr "athlon_decode" "double") 70072445Sassar (eq_attr "mode" "V2DF,V4SF,TI")))) 70172445Sassar "athlon-double,athlon-fpsched,athlon-fstore,athlon-fstore") 70272445Sassar;; cvtsi2sd mem,reg is directpath path (cvtsi2sd reg,reg is doublepath) 70372445Sassar;; cvtsi2sd has troughput 1 and is executed in store unit with latency of 6 70472445Sassar(define_insn_reservation "athlon_sseicvt_cvtsi2sd_load" 6 70572445Sassar (and (eq_attr "cpu" "athlon,k8") 70672445Sassar (and (eq_attr "type" "sseicvt") 70772445Sassar (and (eq_attr "athlon_decode" "direct") 70872445Sassar (and (eq_attr "mode" "SF,DF") 70972445Sassar (eq_attr "memory" "load"))))) 71072445Sassar "athlon-direct,athlon-fploadk8,athlon-fstore") 71172445Sassar;; cvtsi2ss mem, reg is doublepath 71272445Sassar(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load" 9 71372445Sassar (and (eq_attr "cpu" "athlon") 71472445Sassar (and (eq_attr "type" "sseicvt") 71572445Sassar (and (eq_attr "athlon_decode" "double") 71672445Sassar (and (eq_attr "mode" "SF,DF") 71772445Sassar (eq_attr "memory" "load"))))) 71872445Sassar "athlon-vector,athlon-fpload,(athlon-fstore*2)") 71972445Sassar(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load_k8" 9 72072445Sassar (and (eq_attr "cpu" "k8") 72172445Sassar (and (eq_attr "type" "sseicvt") 72272445Sassar (and (eq_attr "athlon_decode" "double") 72372445Sassar (and (eq_attr "mode" "SF,DF") 72472445Sassar (eq_attr "memory" "load"))))) 72572445Sassar "athlon-double,athlon-fploadk8,(athlon-fstore*2)") 72672445Sassar;; cvtsi2sd reg,reg is double decoded (vector on Athlon) 72772445Sassar(define_insn_reservation "athlon_sseicvt_cvtsi2sd_k8" 11 72872445Sassar (and (eq_attr "cpu" "k8,athlon") 72972445Sassar (and (eq_attr "type" "sseicvt") 73072445Sassar (and (eq_attr "athlon_decode" "double") 73172445Sassar (and (eq_attr "mode" "SF,DF") 73272445Sassar (eq_attr "memory" "none"))))) 73372445Sassar "athlon-double,athlon-fploadk8,athlon-fstore") 73472445Sassar;; cvtsi2ss reg, reg is doublepath 73572445Sassar(define_insn_reservation "athlon_sseicvt_cvtsi2ss" 14 73672445Sassar (and (eq_attr "cpu" "athlon,k8") 73772445Sassar (and (eq_attr "type" "sseicvt") 73872445Sassar (and (eq_attr "athlon_decode" "vector") 73972445Sassar (and (eq_attr "mode" "SF,DF") 74072445Sassar (eq_attr "memory" "none"))))) 74172445Sassar "athlon-vector,athlon-fploadk8,(athlon-fvector*2)") 74272445Sassar;; cvtsd2ss mem,reg is doublepath, troughput unknown, latency 9 74372445Sassar(define_insn_reservation "athlon_ssecvt_cvtsd2ss_load_k8" 9 74472445Sassar (and (eq_attr "cpu" "k8,athlon") 74572445Sassar (and (eq_attr "type" "ssecvt") 74672445Sassar (and (eq_attr "athlon_decode" "double") 74772445Sassar (and (eq_attr "mode" "SF") 74872445Sassar (eq_attr "memory" "load"))))) 74972445Sassar "athlon-double,athlon-fploadk8,(athlon-fstore*3)") 75072445Sassar;; cvtsd2ss reg,reg is vectorpath, troughput unknown, latency 12 75172445Sassar(define_insn_reservation "athlon_ssecvt_cvtsd2ss" 12 75272445Sassar (and (eq_attr "cpu" "athlon,k8") 75372445Sassar (and (eq_attr "type" "ssecvt") 75472445Sassar (and (eq_attr "athlon_decode" "vector") 75572445Sassar (and (eq_attr "mode" "SF") 75672445Sassar (eq_attr "memory" "none"))))) 75772445Sassar "athlon-vector,athlon-fpsched,(athlon-fvector*3)") 75872445Sassar(define_insn_reservation "athlon_ssecvt_cvtpd2ps_load_k8" 8 75972445Sassar (and (eq_attr "cpu" "athlon,k8") 76072445Sassar (and (eq_attr "type" "ssecvt") 76172445Sassar (and (eq_attr "athlon_decode" "vector") 76272445Sassar (and (eq_attr "mode" "V4SF,V2DF,TI") 76372445Sassar (eq_attr "memory" "load"))))) 76472445Sassar "athlon-double,athlon-fpload2k8,(athlon-fstore*3)") 76572445Sassar;; cvtpd2ps mem,reg is vectorpath, troughput unknown, latency 10 76672445Sassar;; ??? Why it is fater than cvtsd2ss? 76772445Sassar(define_insn_reservation "athlon_ssecvt_cvtpd2ps" 8 76872445Sassar (and (eq_attr "cpu" "athlon,k8") 76972445Sassar (and (eq_attr "type" "ssecvt") 77072445Sassar (and (eq_attr "athlon_decode" "vector") 77172445Sassar (and (eq_attr "mode" "V4SF,V2DF,TI") 77272445Sassar (eq_attr "memory" "none"))))) 77372445Sassar "athlon-vector,athlon-fpsched,athlon-fvector*2") 77472445Sassar;; cvtsd2si mem,reg is doublepath, troughput 1, latency 9 77572445Sassar(define_insn_reservation "athlon_secvt_cvtsX2si_load" 9 77672445Sassar (and (eq_attr "cpu" "athlon,k8") 77772445Sassar (and (eq_attr "type" "sseicvt") 77872445Sassar (and (eq_attr "athlon_decode" "vector") 77972445Sassar (and (eq_attr "mode" "SI,DI") 78072445Sassar (eq_attr "memory" "load"))))) 78172445Sassar "athlon-vector,athlon-fploadk8,athlon-fvector") 78272445Sassar;; cvtsd2si reg,reg is doublepath, troughput 1, latency 9 78372445Sassar(define_insn_reservation "athlon_ssecvt_cvtsX2si" 9 78472445Sassar (and (eq_attr "cpu" "athlon") 78572445Sassar (and (eq_attr "type" "sseicvt") 78672445Sassar (and (eq_attr "athlon_decode" "double") 78772445Sassar (and (eq_attr "mode" "SI,DI") 78872445Sassar (eq_attr "memory" "none"))))) 78972445Sassar "athlon-vector,athlon-fpsched,athlon-fvector") 79072445Sassar(define_insn_reservation "athlon_ssecvt_cvtsX2si_k8" 9 79172445Sassar (and (eq_attr "cpu" "k8") 79272445Sassar (and (eq_attr "type" "sseicvt") 79372445Sassar (and (eq_attr "athlon_decode" "double") 79472445Sassar (and (eq_attr "mode" "SI,DI") 79572445Sassar (eq_attr "memory" "none"))))) 79672445Sassar "athlon-double,athlon-fpsched,athlon-fstore") 79772445Sassar 79872445Sassar 79972445Sassar(define_insn_reservation "athlon_ssemul_load" 4 80072445Sassar (and (eq_attr "cpu" "athlon") 80172445Sassar (and (eq_attr "type" "ssemul") 80272445Sassar (and (eq_attr "mode" "SF,DF") 80372445Sassar (eq_attr "memory" "load")))) 80472445Sassar "athlon-direct,athlon-fpload,athlon-fmul") 80572445Sassar(define_insn_reservation "athlon_ssemul_load_k8" 6 80672445Sassar (and (eq_attr "cpu" "k8") 80772445Sassar (and (eq_attr "type" "ssemul") 80872445Sassar (and (eq_attr "mode" "SF,DF") 80972445Sassar (eq_attr "memory" "load")))) 81072445Sassar "athlon-direct,athlon-fploadk8,athlon-fmul") 81172445Sassar(define_insn_reservation "athlon_ssemul" 4 81272445Sassar (and (eq_attr "cpu" "athlon,k8") 81372445Sassar (and (eq_attr "type" "ssemul") 81472445Sassar (eq_attr "mode" "SF,DF"))) 81572445Sassar "athlon-direct,athlon-fpsched,athlon-fmul") 81672445Sassar(define_insn_reservation "athlon_ssemulvector_load" 5 81772445Sassar (and (eq_attr "cpu" "athlon") 81872445Sassar (and (eq_attr "type" "ssemul") 81972445Sassar (eq_attr "memory" "load"))) 82072445Sassar "athlon-vector,athlon-fpload2,(athlon-fmul*2)") 82172445Sassar(define_insn_reservation "athlon_ssemulvector_load_k8" 7 82272445Sassar (and (eq_attr "cpu" "k8") 82372445Sassar (and (eq_attr "type" "ssemul") 82472445Sassar (eq_attr "memory" "load"))) 82572445Sassar "athlon-double,athlon-fpload2k8,(athlon-fmul*2)") 82672445Sassar(define_insn_reservation "athlon_ssemulvector" 5 82757422Smarkm (and (eq_attr "cpu" "athlon") 82857422Smarkm (eq_attr "type" "ssemul")) 82957422Smarkm "athlon-vector,athlon-fpsched,(athlon-fmul*2)") 83057422Smarkm(define_insn_reservation "athlon_ssemulvector_k8" 5 83157422Smarkm (and (eq_attr "cpu" "k8") 83257416Smarkm (eq_attr "type" "ssemul")) 83357416Smarkm "athlon-double,athlon-fpsched,(athlon-fmul*2)") 83457416Smarkm;; divsd timings. divss is faster 83557416Smarkm(define_insn_reservation "athlon_ssediv_load" 20 83657416Smarkm (and (eq_attr "cpu" "athlon") 83755682Smarkm (and (eq_attr "type" "ssediv") 83855682Smarkm (and (eq_attr "mode" "SF,DF") 83955682Smarkm (eq_attr "memory" "load")))) 84055682Smarkm "athlon-direct,athlon-fpload,athlon-fmul*17") 84155682Smarkm(define_insn_reservation "athlon_ssediv_load_k8" 22 84255682Smarkm (and (eq_attr "cpu" "k8") 84355682Smarkm (and (eq_attr "type" "ssediv") 84455682Smarkm (and (eq_attr "mode" "SF,DF") 84555682Smarkm (eq_attr "memory" "load")))) 84655682Smarkm "athlon-direct,athlon-fploadk8,athlon-fmul*17") 84755682Smarkm(define_insn_reservation "athlon_ssediv" 20 84855682Smarkm (and (eq_attr "cpu" "athlon,k8") 84955682Smarkm (and (eq_attr "type" "ssediv") 85055682Smarkm (eq_attr "mode" "SF,DF"))) 85155682Smarkm "athlon-direct,athlon-fpsched,athlon-fmul*17") 85255682Smarkm(define_insn_reservation "athlon_ssedivvector_load" 39 85355682Smarkm (and (eq_attr "cpu" "athlon") 85455682Smarkm (and (eq_attr "type" "ssediv") 85555682Smarkm (eq_attr "memory" "load"))) 85655682Smarkm "athlon-vector,athlon-fpload2,athlon-fmul*34") 85755682Smarkm(define_insn_reservation "athlon_ssedivvector_load_k8" 35 85855682Smarkm (and (eq_attr "cpu" "k8") 85955682Smarkm (and (eq_attr "type" "ssediv") 86055682Smarkm (eq_attr "memory" "load"))) 86155682Smarkm "athlon-double,athlon-fpload2k8,athlon-fmul*34") 86255682Smarkm(define_insn_reservation "athlon_ssedivvector" 39 86355682Smarkm (and (eq_attr "cpu" "athlon") 86455682Smarkm (eq_attr "type" "ssediv")) 86555682Smarkm "athlon-vector,athlon-fmul*34") 86655682Smarkm(define_insn_reservation "athlon_ssedivvector_k8" 39 86755682Smarkm (and (eq_attr "cpu" "k8") 86855682Smarkm (eq_attr "type" "ssediv")) 86955682Smarkm "athlon-double,athlon-fmul*34") 87055682Smarkm