1132718Skan;; Patterns for the Intel Wireless MMX technology architecture. 2169689Skan;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc. 3132718Skan;; Contributed by Red Hat. 4132718Skan 5132718Skan;; This file is part of GCC. 6132718Skan 7132718Skan;; GCC is free software; you can redistribute it and/or modify it under 8132718Skan;; the terms of the GNU General Public License as published by the Free 9132718Skan;; Software Foundation; either version 2, or (at your option) any later 10132718Skan;; version. 11132718Skan 12132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 13132718Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14132718Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15132718Skan;; License for more details. 16132718Skan 17132718Skan;; You should have received a copy of the GNU General Public License 18132718Skan;; along with GCC; see the file COPYING. If not, write to 19169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20169689Skan;; Boston, MA 02110-1301, USA. 21132718Skan 22132718Skan(define_insn "iwmmxt_iordi3" 23132718Skan [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 24132718Skan (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r") 25132718Skan (match_operand:DI 2 "register_operand" "y,r,r")))] 26132718Skan "TARGET_REALLY_IWMMXT" 27132718Skan "@ 28132718Skan wor%?\\t%0, %1, %2 29132718Skan # 30132718Skan #" 31132718Skan [(set_attr "predicable" "yes") 32132718Skan (set_attr "length" "4,8,8")]) 33132718Skan 34132718Skan(define_insn "iwmmxt_xordi3" 35132718Skan [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 36132718Skan (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r") 37132718Skan (match_operand:DI 2 "register_operand" "y,r,r")))] 38132718Skan "TARGET_REALLY_IWMMXT" 39132718Skan "@ 40132718Skan wxor%?\\t%0, %1, %2 41132718Skan # 42132718Skan #" 43132718Skan [(set_attr "predicable" "yes") 44132718Skan (set_attr "length" "4,8,8")]) 45132718Skan 46132718Skan(define_insn "iwmmxt_anddi3" 47132718Skan [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 48132718Skan (and:DI (match_operand:DI 1 "register_operand" "%y,0,r") 49132718Skan (match_operand:DI 2 "register_operand" "y,r,r")))] 50132718Skan "TARGET_REALLY_IWMMXT" 51132718Skan "@ 52132718Skan wand%?\\t%0, %1, %2 53132718Skan # 54132718Skan #" 55132718Skan [(set_attr "predicable" "yes") 56132718Skan (set_attr "length" "4,8,8")]) 57132718Skan 58132718Skan(define_insn "iwmmxt_nanddi3" 59132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 60132718Skan (and:DI (match_operand:DI 1 "register_operand" "y") 61132718Skan (not:DI (match_operand:DI 2 "register_operand" "y"))))] 62132718Skan "TARGET_REALLY_IWMMXT" 63132718Skan "wandn%?\\t%0, %1, %2" 64132718Skan [(set_attr "predicable" "yes")]) 65132718Skan 66132718Skan(define_insn "*iwmmxt_arm_movdi" 67169689Skan [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy") 68169689Skan (match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))] 69169689Skan "TARGET_REALLY_IWMMXT 70169689Skan && ( register_operand (operands[0], DImode) 71169689Skan || register_operand (operands[1], DImode))" 72132718Skan "* 73132718Skan{ 74132718Skan switch (which_alternative) 75132718Skan { 76132718Skan default: 77132718Skan return output_move_double (operands); 78169689Skan case 0: 79169689Skan return \"#\"; 80132718Skan case 3: 81132718Skan return \"wmov%?\\t%0,%1\"; 82132718Skan case 4: 83132718Skan return \"tmcrr%?\\t%0,%Q1,%R1\"; 84132718Skan case 5: 85132718Skan return \"tmrrc%?\\t%Q0,%R0,%1\"; 86132718Skan case 6: 87132718Skan return \"wldrd%?\\t%0,%1\"; 88132718Skan case 7: 89132718Skan return \"wstrd%?\\t%1,%0\"; 90132718Skan } 91132718Skan}" 92132718Skan [(set_attr "length" "8,8,8,4,4,4,4,4") 93169689Skan (set_attr "type" "*,load1,store2,*,*,*,*,*") 94132718Skan (set_attr "pool_range" "*,1020,*,*,*,*,*,*") 95132718Skan (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")] 96132718Skan) 97132718Skan 98132718Skan(define_insn "*iwmmxt_movsi_insn" 99169689Skan [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z") 100169689Skan (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,Uy,z,z"))] 101132718Skan "TARGET_REALLY_IWMMXT 102132718Skan && ( register_operand (operands[0], SImode) 103132718Skan || register_operand (operands[1], SImode))" 104132718Skan "* 105132718Skan switch (which_alternative) 106132718Skan { 107132718Skan case 0: return \"mov\\t%0, %1\"; 108132718Skan case 1: return \"mvn\\t%0, #%B1\"; 109132718Skan case 2: return \"ldr\\t%0, %1\"; 110132718Skan case 3: return \"str\\t%1, %0\"; 111132718Skan case 4: return \"tmcr\\t%0, %1\"; 112132718Skan case 5: return \"tmrc\\t%0, %1\"; 113132718Skan case 6: return arm_output_load_gr (operands); 114132718Skan case 7: return \"wstrw\\t%1, %0\"; 115132718Skan default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\"; 116132718Skan }" 117169689Skan [(set_attr "type" "*,*,load1,store1,*,*,load1,store1,*") 118132718Skan (set_attr "length" "*,*,*, *,*,*, 16, *,8") 119132718Skan (set_attr "pool_range" "*,*,4096, *,*,*,1024, *,*") 120132718Skan (set_attr "neg_pool_range" "*,*,4084, *,*,*, *, 1012,*") 121132718Skan ;; Note - the "predicable" attribute is not allowed to have alternatives. 122132718Skan ;; Since the wSTRw wCx instruction is not predicable, we cannot support 123132718Skan ;; predicating any of the alternatives in this template. Instead, 124132718Skan ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn. 125132718Skan (set_attr "predicable" "no") 126132718Skan ;; Also - we have to pretend that these insns clobber the condition code 127132718Skan ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize 128132718Skan ;; them. 129132718Skan (set_attr "conds" "clob")] 130132718Skan) 131132718Skan 132132718Skan;; Because iwmmxt_movsi_insn is not predicable, we provide the 133132718Skan;; cond_exec version explicitly, with appropriate constraints. 134132718Skan 135132718Skan(define_insn "*cond_iwmmxt_movsi_insn" 136132718Skan [(cond_exec 137132718Skan (match_operator 2 "arm_comparison_operator" 138132718Skan [(match_operand 3 "cc_register" "") 139132718Skan (const_int 0)]) 140132718Skan (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r") 141132718Skan (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))] 142132718Skan "TARGET_REALLY_IWMMXT 143132718Skan && ( register_operand (operands[0], SImode) 144132718Skan || register_operand (operands[1], SImode))" 145132718Skan "* 146132718Skan switch (which_alternative) 147132718Skan { 148132718Skan case 0: return \"mov%?\\t%0, %1\"; 149132718Skan case 1: return \"mvn%?\\t%0, #%B1\"; 150132718Skan case 2: return \"ldr%?\\t%0, %1\"; 151132718Skan case 3: return \"str%?\\t%1, %0\"; 152132718Skan case 4: return \"tmcr%?\\t%0, %1\"; 153132718Skan default: return \"tmrc%?\\t%0, %1\"; 154132718Skan }" 155169689Skan [(set_attr "type" "*,*,load1,store1,*,*") 156132718Skan (set_attr "pool_range" "*,*,4096, *,*,*") 157132718Skan (set_attr "neg_pool_range" "*,*,4084, *,*,*")] 158132718Skan) 159132718Skan 160132718Skan(define_insn "movv8qi_internal" 161132718Skan [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") 162169689Skan (match_operand:V8QI 1 "general_operand" "y,y,mi,y,r,mi"))] 163132718Skan "TARGET_REALLY_IWMMXT" 164132718Skan "* 165132718Skan switch (which_alternative) 166132718Skan { 167132718Skan case 0: return \"wmov%?\\t%0, %1\"; 168132718Skan case 1: return \"wstrd%?\\t%1, %0\"; 169132718Skan case 2: return \"wldrd%?\\t%0, %1\"; 170132718Skan case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; 171132718Skan case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; 172132718Skan default: return output_move_double (operands); 173132718Skan }" 174132718Skan [(set_attr "predicable" "yes") 175132718Skan (set_attr "length" "4, 4, 4,4,4, 8") 176169689Skan (set_attr "type" "*,store1,load1,*,*,load1") 177132718Skan (set_attr "pool_range" "*, *, 256,*,*, 256") 178132718Skan (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) 179132718Skan 180132718Skan(define_insn "movv4hi_internal" 181132718Skan [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") 182169689Skan (match_operand:V4HI 1 "general_operand" "y,y,mi,y,r,mi"))] 183132718Skan "TARGET_REALLY_IWMMXT" 184132718Skan "* 185132718Skan switch (which_alternative) 186132718Skan { 187132718Skan case 0: return \"wmov%?\\t%0, %1\"; 188132718Skan case 1: return \"wstrd%?\\t%1, %0\"; 189132718Skan case 2: return \"wldrd%?\\t%0, %1\"; 190132718Skan case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; 191132718Skan case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; 192132718Skan default: return output_move_double (operands); 193132718Skan }" 194132718Skan [(set_attr "predicable" "yes") 195132718Skan (set_attr "length" "4, 4, 4,4,4, 8") 196169689Skan (set_attr "type" "*,store1,load1,*,*,load1") 197132718Skan (set_attr "pool_range" "*, *, 256,*,*, 256") 198132718Skan (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) 199132718Skan 200132718Skan(define_insn "movv2si_internal" 201132718Skan [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") 202169689Skan (match_operand:V2SI 1 "general_operand" "y,y,mi,y,r,mi"))] 203132718Skan "TARGET_REALLY_IWMMXT" 204132718Skan "* 205132718Skan switch (which_alternative) 206132718Skan { 207132718Skan case 0: return \"wmov%?\\t%0, %1\"; 208132718Skan case 1: return \"wstrd%?\\t%1, %0\"; 209132718Skan case 2: return \"wldrd%?\\t%0, %1\"; 210132718Skan case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; 211132718Skan case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; 212132718Skan default: return output_move_double (operands); 213132718Skan }" 214132718Skan [(set_attr "predicable" "yes") 215132718Skan (set_attr "length" "4, 4, 4,4,4, 24") 216169689Skan (set_attr "type" "*,store1,load1,*,*,load1") 217132718Skan (set_attr "pool_range" "*, *, 256,*,*, 256") 218132718Skan (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) 219132718Skan 220132718Skan;; This pattern should not be needed. It is to match a 221132718Skan;; wierd case generated by GCC when no optimizations are 222132718Skan;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/ 223132718Skan;; compile/simd-5.c at -O0). The mode for operands[1] is 224132718Skan;; deliberately omitted. 225132718Skan(define_insn "movv2si_internal_2" 226132718Skan [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r") 227169689Skan (match_operand 1 "immediate_operand" "mi"))] 228132718Skan "TARGET_REALLY_IWMMXT" 229132718Skan "* return output_move_double (operands);" 230132718Skan [(set_attr "predicable" "yes") 231132718Skan (set_attr "length" "8") 232169689Skan (set_attr "type" "load1") 233132718Skan (set_attr "pool_range" "256") 234132718Skan (set_attr "neg_pool_range" "244")]) 235132718Skan 236132718Skan;; Vector add/subtract 237132718Skan 238132718Skan(define_insn "addv8qi3" 239132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 240132718Skan (plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 241132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 242132718Skan "TARGET_REALLY_IWMMXT" 243132718Skan "waddb%?\\t%0, %1, %2" 244132718Skan [(set_attr "predicable" "yes")]) 245132718Skan 246132718Skan(define_insn "addv4hi3" 247132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 248132718Skan (plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 249132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 250132718Skan "TARGET_REALLY_IWMMXT" 251132718Skan "waddh%?\\t%0, %1, %2" 252132718Skan [(set_attr "predicable" "yes")]) 253132718Skan 254132718Skan(define_insn "addv2si3" 255132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 256132718Skan (plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 257132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 258132718Skan "TARGET_REALLY_IWMMXT" 259132718Skan "waddw%?\\t%0, %1, %2" 260132718Skan [(set_attr "predicable" "yes")]) 261132718Skan 262132718Skan(define_insn "ssaddv8qi3" 263132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 264132718Skan (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 265132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 266132718Skan "TARGET_REALLY_IWMMXT" 267132718Skan "waddbss%?\\t%0, %1, %2" 268132718Skan [(set_attr "predicable" "yes")]) 269132718Skan 270132718Skan(define_insn "ssaddv4hi3" 271132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 272132718Skan (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 273132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 274132718Skan "TARGET_REALLY_IWMMXT" 275132718Skan "waddhss%?\\t%0, %1, %2" 276132718Skan [(set_attr "predicable" "yes")]) 277132718Skan 278132718Skan(define_insn "ssaddv2si3" 279132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 280132718Skan (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 281132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 282132718Skan "TARGET_REALLY_IWMMXT" 283132718Skan "waddwss%?\\t%0, %1, %2" 284132718Skan [(set_attr "predicable" "yes")]) 285132718Skan 286132718Skan(define_insn "usaddv8qi3" 287132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 288132718Skan (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 289132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 290132718Skan "TARGET_REALLY_IWMMXT" 291132718Skan "waddbus%?\\t%0, %1, %2" 292132718Skan [(set_attr "predicable" "yes")]) 293132718Skan 294132718Skan(define_insn "usaddv4hi3" 295132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 296132718Skan (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 297132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 298132718Skan "TARGET_REALLY_IWMMXT" 299132718Skan "waddhus%?\\t%0, %1, %2" 300132718Skan [(set_attr "predicable" "yes")]) 301132718Skan 302132718Skan(define_insn "usaddv2si3" 303132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 304132718Skan (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 305132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 306132718Skan "TARGET_REALLY_IWMMXT" 307132718Skan "waddwus%?\\t%0, %1, %2" 308132718Skan [(set_attr "predicable" "yes")]) 309132718Skan 310132718Skan(define_insn "subv8qi3" 311132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 312132718Skan (minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 313132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 314132718Skan "TARGET_REALLY_IWMMXT" 315132718Skan "wsubb%?\\t%0, %1, %2" 316132718Skan [(set_attr "predicable" "yes")]) 317132718Skan 318132718Skan(define_insn "subv4hi3" 319132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 320132718Skan (minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 321132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 322132718Skan "TARGET_REALLY_IWMMXT" 323132718Skan "wsubh%?\\t%0, %1, %2" 324132718Skan [(set_attr "predicable" "yes")]) 325132718Skan 326132718Skan(define_insn "subv2si3" 327132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 328132718Skan (minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 329132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 330132718Skan "TARGET_REALLY_IWMMXT" 331132718Skan "wsubw%?\\t%0, %1, %2" 332132718Skan [(set_attr "predicable" "yes")]) 333132718Skan 334132718Skan(define_insn "sssubv8qi3" 335132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 336132718Skan (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 337132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 338132718Skan "TARGET_REALLY_IWMMXT" 339132718Skan "wsubbss%?\\t%0, %1, %2" 340132718Skan [(set_attr "predicable" "yes")]) 341132718Skan 342132718Skan(define_insn "sssubv4hi3" 343132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 344132718Skan (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 345132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 346132718Skan "TARGET_REALLY_IWMMXT" 347132718Skan "wsubhss%?\\t%0, %1, %2" 348132718Skan [(set_attr "predicable" "yes")]) 349132718Skan 350132718Skan(define_insn "sssubv2si3" 351132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 352132718Skan (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 353132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 354132718Skan "TARGET_REALLY_IWMMXT" 355132718Skan "wsubwss%?\\t%0, %1, %2" 356132718Skan [(set_attr "predicable" "yes")]) 357132718Skan 358132718Skan(define_insn "ussubv8qi3" 359132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 360132718Skan (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 361132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 362132718Skan "TARGET_REALLY_IWMMXT" 363132718Skan "wsubbus%?\\t%0, %1, %2" 364132718Skan [(set_attr "predicable" "yes")]) 365132718Skan 366132718Skan(define_insn "ussubv4hi3" 367132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 368132718Skan (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 369132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 370132718Skan "TARGET_REALLY_IWMMXT" 371132718Skan "wsubhus%?\\t%0, %1, %2" 372132718Skan [(set_attr "predicable" "yes")]) 373132718Skan 374132718Skan(define_insn "ussubv2si3" 375132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 376132718Skan (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 377132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 378132718Skan "TARGET_REALLY_IWMMXT" 379132718Skan "wsubwus%?\\t%0, %1, %2" 380132718Skan [(set_attr "predicable" "yes")]) 381132718Skan 382132718Skan(define_insn "mulv4hi3" 383132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 384132718Skan (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") 385132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 386132718Skan "TARGET_REALLY_IWMMXT" 387132718Skan "wmulul%?\\t%0, %1, %2" 388132718Skan [(set_attr "predicable" "yes")]) 389132718Skan 390132718Skan(define_insn "smulv4hi3_highpart" 391132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 392132718Skan (truncate:V4HI 393132718Skan (lshiftrt:V4SI 394132718Skan (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) 395132718Skan (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) 396132718Skan (const_int 16))))] 397132718Skan "TARGET_REALLY_IWMMXT" 398132718Skan "wmulsm%?\\t%0, %1, %2" 399132718Skan [(set_attr "predicable" "yes")]) 400132718Skan 401132718Skan(define_insn "umulv4hi3_highpart" 402132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 403132718Skan (truncate:V4HI 404132718Skan (lshiftrt:V4SI 405132718Skan (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) 406132718Skan (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) 407132718Skan (const_int 16))))] 408132718Skan "TARGET_REALLY_IWMMXT" 409132718Skan "wmulum%?\\t%0, %1, %2" 410132718Skan [(set_attr "predicable" "yes")]) 411132718Skan 412132718Skan(define_insn "iwmmxt_wmacs" 413132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 414132718Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 415132718Skan (match_operand:V4HI 2 "register_operand" "y") 416132718Skan (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))] 417132718Skan "TARGET_REALLY_IWMMXT" 418132718Skan "wmacs%?\\t%0, %2, %3" 419132718Skan [(set_attr "predicable" "yes")]) 420132718Skan 421132718Skan(define_insn "iwmmxt_wmacsz" 422132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 423132718Skan (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") 424132718Skan (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))] 425132718Skan "TARGET_REALLY_IWMMXT" 426132718Skan "wmacsz%?\\t%0, %1, %2" 427132718Skan [(set_attr "predicable" "yes")]) 428132718Skan 429132718Skan(define_insn "iwmmxt_wmacu" 430132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 431132718Skan (unspec:DI [(match_operand:DI 1 "register_operand" "0") 432132718Skan (match_operand:V4HI 2 "register_operand" "y") 433132718Skan (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))] 434132718Skan "TARGET_REALLY_IWMMXT" 435132718Skan "wmacu%?\\t%0, %2, %3" 436132718Skan [(set_attr "predicable" "yes")]) 437132718Skan 438132718Skan(define_insn "iwmmxt_wmacuz" 439132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 440132718Skan (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") 441132718Skan (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))] 442132718Skan "TARGET_REALLY_IWMMXT" 443132718Skan "wmacuz%?\\t%0, %1, %2" 444132718Skan [(set_attr "predicable" "yes")]) 445132718Skan 446132718Skan;; Same as xordi3, but don't show input operands so that we don't think 447132718Skan;; they are live. 448132718Skan(define_insn "iwmmxt_clrdi" 449132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 450132718Skan (unspec:DI [(const_int 0)] UNSPEC_CLRDI))] 451132718Skan "TARGET_REALLY_IWMMXT" 452132718Skan "wxor%?\\t%0, %0, %0" 453132718Skan [(set_attr "predicable" "yes")]) 454132718Skan 455132718Skan;; Seems like cse likes to generate these, so we have to support them. 456132718Skan 457132718Skan(define_insn "*iwmmxt_clrv8qi" 458132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 459132718Skan (const_vector:V8QI [(const_int 0) (const_int 0) 460132718Skan (const_int 0) (const_int 0) 461132718Skan (const_int 0) (const_int 0) 462132718Skan (const_int 0) (const_int 0)]))] 463132718Skan "TARGET_REALLY_IWMMXT" 464132718Skan "wxor%?\\t%0, %0, %0" 465132718Skan [(set_attr "predicable" "yes")]) 466132718Skan 467132718Skan(define_insn "*iwmmxt_clrv4hi" 468132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 469132718Skan (const_vector:V4HI [(const_int 0) (const_int 0) 470132718Skan (const_int 0) (const_int 0)]))] 471132718Skan "TARGET_REALLY_IWMMXT" 472132718Skan "wxor%?\\t%0, %0, %0" 473132718Skan [(set_attr "predicable" "yes")]) 474132718Skan 475132718Skan(define_insn "*iwmmxt_clrv2si" 476132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 477132718Skan (const_vector:V2SI [(const_int 0) (const_int 0)]))] 478132718Skan "TARGET_REALLY_IWMMXT" 479132718Skan "wxor%?\\t%0, %0, %0" 480132718Skan [(set_attr "predicable" "yes")]) 481132718Skan 482132718Skan;; Unsigned averages/sum of absolute differences 483132718Skan 484132718Skan(define_insn "iwmmxt_uavgrndv8qi3" 485132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 486132718Skan (ashiftrt:V8QI 487132718Skan (plus:V8QI (plus:V8QI 488132718Skan (match_operand:V8QI 1 "register_operand" "y") 489132718Skan (match_operand:V8QI 2 "register_operand" "y")) 490132718Skan (const_vector:V8QI [(const_int 1) 491132718Skan (const_int 1) 492132718Skan (const_int 1) 493132718Skan (const_int 1) 494132718Skan (const_int 1) 495132718Skan (const_int 1) 496132718Skan (const_int 1) 497132718Skan (const_int 1)])) 498132718Skan (const_int 1)))] 499132718Skan "TARGET_REALLY_IWMMXT" 500132718Skan "wavg2br%?\\t%0, %1, %2" 501132718Skan [(set_attr "predicable" "yes")]) 502132718Skan 503132718Skan(define_insn "iwmmxt_uavgrndv4hi3" 504132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 505132718Skan (ashiftrt:V4HI 506132718Skan (plus:V4HI (plus:V4HI 507132718Skan (match_operand:V4HI 1 "register_operand" "y") 508132718Skan (match_operand:V4HI 2 "register_operand" "y")) 509132718Skan (const_vector:V4HI [(const_int 1) 510132718Skan (const_int 1) 511132718Skan (const_int 1) 512132718Skan (const_int 1)])) 513132718Skan (const_int 1)))] 514132718Skan "TARGET_REALLY_IWMMXT" 515132718Skan "wavg2hr%?\\t%0, %1, %2" 516132718Skan [(set_attr "predicable" "yes")]) 517132718Skan 518132718Skan 519132718Skan(define_insn "iwmmxt_uavgv8qi3" 520132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 521132718Skan (ashiftrt:V8QI (plus:V8QI 522132718Skan (match_operand:V8QI 1 "register_operand" "y") 523132718Skan (match_operand:V8QI 2 "register_operand" "y")) 524132718Skan (const_int 1)))] 525132718Skan "TARGET_REALLY_IWMMXT" 526132718Skan "wavg2b%?\\t%0, %1, %2" 527132718Skan [(set_attr "predicable" "yes")]) 528132718Skan 529132718Skan(define_insn "iwmmxt_uavgv4hi3" 530132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 531132718Skan (ashiftrt:V4HI (plus:V4HI 532132718Skan (match_operand:V4HI 1 "register_operand" "y") 533132718Skan (match_operand:V4HI 2 "register_operand" "y")) 534132718Skan (const_int 1)))] 535132718Skan "TARGET_REALLY_IWMMXT" 536132718Skan "wavg2h%?\\t%0, %1, %2" 537132718Skan [(set_attr "predicable" "yes")]) 538132718Skan 539132718Skan(define_insn "iwmmxt_psadbw" 540132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 541132718Skan (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 542132718Skan (match_operand:V8QI 2 "register_operand" "y"))))] 543132718Skan "TARGET_REALLY_IWMMXT" 544132718Skan "psadbw%?\\t%0, %1, %2" 545132718Skan [(set_attr "predicable" "yes")]) 546132718Skan 547132718Skan 548132718Skan;; Insert/extract/shuffle 549132718Skan 550132718Skan(define_insn "iwmmxt_tinsrb" 551132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 552132718Skan (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0") 553132718Skan (vec_duplicate:V8QI 554132718Skan (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r"))) 555132718Skan (match_operand:SI 3 "immediate_operand" "i")))] 556132718Skan "TARGET_REALLY_IWMMXT" 557132718Skan "tinsrb%?\\t%0, %2, %3" 558132718Skan [(set_attr "predicable" "yes")]) 559132718Skan 560132718Skan(define_insn "iwmmxt_tinsrh" 561132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 562132718Skan (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0") 563132718Skan (vec_duplicate:V4HI 564132718Skan (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r"))) 565132718Skan (match_operand:SI 3 "immediate_operand" "i")))] 566132718Skan "TARGET_REALLY_IWMMXT" 567132718Skan "tinsrh%?\\t%0, %2, %3" 568132718Skan [(set_attr "predicable" "yes")]) 569132718Skan 570132718Skan(define_insn "iwmmxt_tinsrw" 571132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 572132718Skan (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0") 573132718Skan (vec_duplicate:V2SI 574132718Skan (match_operand:SI 2 "nonimmediate_operand" "r")) 575132718Skan (match_operand:SI 3 "immediate_operand" "i")))] 576132718Skan "TARGET_REALLY_IWMMXT" 577132718Skan "tinsrw%?\\t%0, %2, %3" 578132718Skan [(set_attr "predicable" "yes")]) 579132718Skan 580132718Skan(define_insn "iwmmxt_textrmub" 581132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 582132718Skan (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") 583132718Skan (parallel 584132718Skan [(match_operand:SI 2 "immediate_operand" "i")]))))] 585132718Skan "TARGET_REALLY_IWMMXT" 586132718Skan "textrmub%?\\t%0, %1, %2" 587132718Skan [(set_attr "predicable" "yes")]) 588132718Skan 589132718Skan(define_insn "iwmmxt_textrmsb" 590132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 591132718Skan (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") 592132718Skan (parallel 593132718Skan [(match_operand:SI 2 "immediate_operand" "i")]))))] 594132718Skan "TARGET_REALLY_IWMMXT" 595132718Skan "textrmsb%?\\t%0, %1, %2" 596132718Skan [(set_attr "predicable" "yes")]) 597132718Skan 598132718Skan(define_insn "iwmmxt_textrmuh" 599132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 600132718Skan (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") 601132718Skan (parallel 602132718Skan [(match_operand:SI 2 "immediate_operand" "i")]))))] 603132718Skan "TARGET_REALLY_IWMMXT" 604132718Skan "textrmuh%?\\t%0, %1, %2" 605132718Skan [(set_attr "predicable" "yes")]) 606132718Skan 607132718Skan(define_insn "iwmmxt_textrmsh" 608132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 609132718Skan (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") 610132718Skan (parallel 611132718Skan [(match_operand:SI 2 "immediate_operand" "i")]))))] 612132718Skan "TARGET_REALLY_IWMMXT" 613132718Skan "textrmsh%?\\t%0, %1, %2" 614132718Skan [(set_attr "predicable" "yes")]) 615132718Skan 616132718Skan;; There are signed/unsigned variants of this instruction, but they are 617132718Skan;; pointless. 618132718Skan(define_insn "iwmmxt_textrmw" 619132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 620132718Skan (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 621132718Skan (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] 622132718Skan "TARGET_REALLY_IWMMXT" 623132718Skan "textrmsw%?\\t%0, %1, %2" 624132718Skan [(set_attr "predicable" "yes")]) 625132718Skan 626132718Skan(define_insn "iwmmxt_wshufh" 627132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 628132718Skan (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 629132718Skan (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))] 630132718Skan "TARGET_REALLY_IWMMXT" 631132718Skan "wshufh%?\\t%0, %1, %2" 632132718Skan [(set_attr "predicable" "yes")]) 633132718Skan 634132718Skan;; Mask-generating comparisons 635132718Skan;; 636132718Skan;; Note - you cannot use patterns like these here: 637132718Skan;; 638132718Skan;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>))) 639132718Skan;; 640132718Skan;; Because GCC will assume that the truth value (1 or 0) is installed 641132718Skan;; into the entire destination vector, (with the '1' going into the least 642132718Skan;; significant element of the vector). This is not how these instructions 643132718Skan;; behave. 644132718Skan;; 645132718Skan;; Unfortunately the current patterns are illegal. They are SET insns 646132718Skan;; without a SET in them. They work in most cases for ordinary code 647132718Skan;; generation, but there are circumstances where they can cause gcc to fail. 648132718Skan;; XXX - FIXME. 649132718Skan 650132718Skan(define_insn "eqv8qi3" 651132718Skan [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 652132718Skan (match_operand:V8QI 1 "register_operand" "y") 653132718Skan (match_operand:V8QI 2 "register_operand" "y")] 654132718Skan VUNSPEC_WCMP_EQ)] 655132718Skan "TARGET_REALLY_IWMMXT" 656132718Skan "wcmpeqb%?\\t%0, %1, %2" 657132718Skan [(set_attr "predicable" "yes")]) 658132718Skan 659132718Skan(define_insn "eqv4hi3" 660132718Skan [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 661132718Skan (match_operand:V4HI 1 "register_operand" "y") 662132718Skan (match_operand:V4HI 2 "register_operand" "y")] 663132718Skan VUNSPEC_WCMP_EQ)] 664132718Skan "TARGET_REALLY_IWMMXT" 665132718Skan "wcmpeqh%?\\t%0, %1, %2" 666132718Skan [(set_attr "predicable" "yes")]) 667132718Skan 668132718Skan(define_insn "eqv2si3" 669132718Skan [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y") 670132718Skan (match_operand:V2SI 1 "register_operand" "y") 671132718Skan (match_operand:V2SI 2 "register_operand" "y")] 672132718Skan VUNSPEC_WCMP_EQ)] 673132718Skan "TARGET_REALLY_IWMMXT" 674132718Skan "wcmpeqw%?\\t%0, %1, %2" 675132718Skan [(set_attr "predicable" "yes")]) 676132718Skan 677132718Skan(define_insn "gtuv8qi3" 678132718Skan [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 679132718Skan (match_operand:V8QI 1 "register_operand" "y") 680132718Skan (match_operand:V8QI 2 "register_operand" "y")] 681132718Skan VUNSPEC_WCMP_GTU)] 682132718Skan "TARGET_REALLY_IWMMXT" 683132718Skan "wcmpgtub%?\\t%0, %1, %2" 684132718Skan [(set_attr "predicable" "yes")]) 685132718Skan 686132718Skan(define_insn "gtuv4hi3" 687132718Skan [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 688132718Skan (match_operand:V4HI 1 "register_operand" "y") 689132718Skan (match_operand:V4HI 2 "register_operand" "y")] 690132718Skan VUNSPEC_WCMP_GTU)] 691132718Skan "TARGET_REALLY_IWMMXT" 692132718Skan "wcmpgtuh%?\\t%0, %1, %2" 693132718Skan [(set_attr "predicable" "yes")]) 694132718Skan 695132718Skan(define_insn "gtuv2si3" 696132718Skan [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") 697132718Skan (match_operand:V2SI 1 "register_operand" "y") 698132718Skan (match_operand:V2SI 2 "register_operand" "y")] 699132718Skan VUNSPEC_WCMP_GTU)] 700132718Skan "TARGET_REALLY_IWMMXT" 701132718Skan "wcmpgtuw%?\\t%0, %1, %2" 702132718Skan [(set_attr "predicable" "yes")]) 703132718Skan 704132718Skan(define_insn "gtv8qi3" 705132718Skan [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 706132718Skan (match_operand:V8QI 1 "register_operand" "y") 707132718Skan (match_operand:V8QI 2 "register_operand" "y")] 708132718Skan VUNSPEC_WCMP_GT)] 709132718Skan "TARGET_REALLY_IWMMXT" 710132718Skan "wcmpgtsb%?\\t%0, %1, %2" 711132718Skan [(set_attr "predicable" "yes")]) 712132718Skan 713132718Skan(define_insn "gtv4hi3" 714132718Skan [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 715132718Skan (match_operand:V4HI 1 "register_operand" "y") 716132718Skan (match_operand:V4HI 2 "register_operand" "y")] 717132718Skan VUNSPEC_WCMP_GT)] 718132718Skan "TARGET_REALLY_IWMMXT" 719132718Skan "wcmpgtsh%?\\t%0, %1, %2" 720132718Skan [(set_attr "predicable" "yes")]) 721132718Skan 722132718Skan(define_insn "gtv2si3" 723132718Skan [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") 724132718Skan (match_operand:V2SI 1 "register_operand" "y") 725132718Skan (match_operand:V2SI 2 "register_operand" "y")] 726132718Skan VUNSPEC_WCMP_GT)] 727132718Skan "TARGET_REALLY_IWMMXT" 728132718Skan "wcmpgtsw%?\\t%0, %1, %2" 729132718Skan [(set_attr "predicable" "yes")]) 730132718Skan 731132718Skan;; Max/min insns 732132718Skan 733132718Skan(define_insn "smaxv8qi3" 734132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 735132718Skan (smax:V8QI (match_operand:V8QI 1 "register_operand" "y") 736132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 737132718Skan "TARGET_REALLY_IWMMXT" 738132718Skan "wmaxsb%?\\t%0, %1, %2" 739132718Skan [(set_attr "predicable" "yes")]) 740132718Skan 741132718Skan(define_insn "umaxv8qi3" 742132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 743132718Skan (umax:V8QI (match_operand:V8QI 1 "register_operand" "y") 744132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 745132718Skan "TARGET_REALLY_IWMMXT" 746132718Skan "wmaxub%?\\t%0, %1, %2" 747132718Skan [(set_attr "predicable" "yes")]) 748132718Skan 749132718Skan(define_insn "smaxv4hi3" 750132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 751132718Skan (smax:V4HI (match_operand:V4HI 1 "register_operand" "y") 752132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 753132718Skan "TARGET_REALLY_IWMMXT" 754132718Skan "wmaxsh%?\\t%0, %1, %2" 755132718Skan [(set_attr "predicable" "yes")]) 756132718Skan 757132718Skan(define_insn "umaxv4hi3" 758132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 759132718Skan (umax:V4HI (match_operand:V4HI 1 "register_operand" "y") 760132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 761132718Skan "TARGET_REALLY_IWMMXT" 762132718Skan "wmaxuh%?\\t%0, %1, %2" 763132718Skan [(set_attr "predicable" "yes")]) 764132718Skan 765132718Skan(define_insn "smaxv2si3" 766132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 767132718Skan (smax:V2SI (match_operand:V2SI 1 "register_operand" "y") 768132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 769132718Skan "TARGET_REALLY_IWMMXT" 770132718Skan "wmaxsw%?\\t%0, %1, %2" 771132718Skan [(set_attr "predicable" "yes")]) 772132718Skan 773132718Skan(define_insn "umaxv2si3" 774132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 775132718Skan (umax:V2SI (match_operand:V2SI 1 "register_operand" "y") 776132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 777132718Skan "TARGET_REALLY_IWMMXT" 778132718Skan "wmaxuw%?\\t%0, %1, %2" 779132718Skan [(set_attr "predicable" "yes")]) 780132718Skan 781132718Skan(define_insn "sminv8qi3" 782132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 783132718Skan (smin:V8QI (match_operand:V8QI 1 "register_operand" "y") 784132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 785132718Skan "TARGET_REALLY_IWMMXT" 786132718Skan "wminsb%?\\t%0, %1, %2" 787132718Skan [(set_attr "predicable" "yes")]) 788132718Skan 789132718Skan(define_insn "uminv8qi3" 790132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 791132718Skan (umin:V8QI (match_operand:V8QI 1 "register_operand" "y") 792132718Skan (match_operand:V8QI 2 "register_operand" "y")))] 793132718Skan "TARGET_REALLY_IWMMXT" 794132718Skan "wminub%?\\t%0, %1, %2" 795132718Skan [(set_attr "predicable" "yes")]) 796132718Skan 797132718Skan(define_insn "sminv4hi3" 798132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 799132718Skan (smin:V4HI (match_operand:V4HI 1 "register_operand" "y") 800132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 801132718Skan "TARGET_REALLY_IWMMXT" 802132718Skan "wminsh%?\\t%0, %1, %2" 803132718Skan [(set_attr "predicable" "yes")]) 804132718Skan 805132718Skan(define_insn "uminv4hi3" 806132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 807132718Skan (umin:V4HI (match_operand:V4HI 1 "register_operand" "y") 808132718Skan (match_operand:V4HI 2 "register_operand" "y")))] 809132718Skan "TARGET_REALLY_IWMMXT" 810132718Skan "wminuh%?\\t%0, %1, %2" 811132718Skan [(set_attr "predicable" "yes")]) 812132718Skan 813132718Skan(define_insn "sminv2si3" 814132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 815132718Skan (smin:V2SI (match_operand:V2SI 1 "register_operand" "y") 816132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 817132718Skan "TARGET_REALLY_IWMMXT" 818132718Skan "wminsw%?\\t%0, %1, %2" 819132718Skan [(set_attr "predicable" "yes")]) 820132718Skan 821132718Skan(define_insn "uminv2si3" 822132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 823132718Skan (umin:V2SI (match_operand:V2SI 1 "register_operand" "y") 824132718Skan (match_operand:V2SI 2 "register_operand" "y")))] 825132718Skan "TARGET_REALLY_IWMMXT" 826132718Skan "wminuw%?\\t%0, %1, %2" 827132718Skan [(set_attr "predicable" "yes")]) 828132718Skan 829132718Skan;; Pack/unpack insns. 830132718Skan 831132718Skan(define_insn "iwmmxt_wpackhss" 832132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 833132718Skan (vec_concat:V8QI 834132718Skan (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) 835132718Skan (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] 836132718Skan "TARGET_REALLY_IWMMXT" 837132718Skan "wpackhss%?\\t%0, %1, %2" 838132718Skan [(set_attr "predicable" "yes")]) 839132718Skan 840132718Skan(define_insn "iwmmxt_wpackwss" 841132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 842132718Skan (vec_concat:V4HI 843132718Skan (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) 844132718Skan (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] 845132718Skan "TARGET_REALLY_IWMMXT" 846132718Skan "wpackwss%?\\t%0, %1, %2" 847132718Skan [(set_attr "predicable" "yes")]) 848132718Skan 849132718Skan(define_insn "iwmmxt_wpackdss" 850132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 851132718Skan (vec_concat:V2SI 852132718Skan (ss_truncate:SI (match_operand:DI 1 "register_operand" "y")) 853132718Skan (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] 854132718Skan "TARGET_REALLY_IWMMXT" 855132718Skan "wpackdss%?\\t%0, %1, %2" 856132718Skan [(set_attr "predicable" "yes")]) 857132718Skan 858132718Skan(define_insn "iwmmxt_wpackhus" 859132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 860132718Skan (vec_concat:V8QI 861132718Skan (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) 862132718Skan (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] 863132718Skan "TARGET_REALLY_IWMMXT" 864132718Skan "wpackhus%?\\t%0, %1, %2" 865132718Skan [(set_attr "predicable" "yes")]) 866132718Skan 867132718Skan(define_insn "iwmmxt_wpackwus" 868132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 869132718Skan (vec_concat:V4HI 870132718Skan (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) 871132718Skan (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] 872132718Skan "TARGET_REALLY_IWMMXT" 873132718Skan "wpackwus%?\\t%0, %1, %2" 874132718Skan [(set_attr "predicable" "yes")]) 875132718Skan 876132718Skan(define_insn "iwmmxt_wpackdus" 877132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 878132718Skan (vec_concat:V2SI 879132718Skan (us_truncate:SI (match_operand:DI 1 "register_operand" "y")) 880132718Skan (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] 881132718Skan "TARGET_REALLY_IWMMXT" 882132718Skan "wpackdus%?\\t%0, %1, %2" 883132718Skan [(set_attr "predicable" "yes")]) 884132718Skan 885132718Skan 886132718Skan(define_insn "iwmmxt_wunpckihb" 887132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 888132718Skan (vec_merge:V8QI 889132718Skan (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") 890132718Skan (parallel [(const_int 4) 891132718Skan (const_int 0) 892132718Skan (const_int 5) 893132718Skan (const_int 1) 894132718Skan (const_int 6) 895132718Skan (const_int 2) 896132718Skan (const_int 7) 897132718Skan (const_int 3)])) 898132718Skan (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 899132718Skan (parallel [(const_int 0) 900132718Skan (const_int 4) 901132718Skan (const_int 1) 902132718Skan (const_int 5) 903132718Skan (const_int 2) 904132718Skan (const_int 6) 905132718Skan (const_int 3) 906132718Skan (const_int 7)])) 907132718Skan (const_int 85)))] 908132718Skan "TARGET_REALLY_IWMMXT" 909132718Skan "wunpckihb%?\\t%0, %1, %2" 910132718Skan [(set_attr "predicable" "yes")]) 911132718Skan 912132718Skan(define_insn "iwmmxt_wunpckihh" 913132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 914132718Skan (vec_merge:V4HI 915132718Skan (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") 916132718Skan (parallel [(const_int 0) 917132718Skan (const_int 2) 918132718Skan (const_int 1) 919132718Skan (const_int 3)])) 920132718Skan (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 921132718Skan (parallel [(const_int 2) 922132718Skan (const_int 0) 923132718Skan (const_int 3) 924132718Skan (const_int 1)])) 925132718Skan (const_int 5)))] 926132718Skan "TARGET_REALLY_IWMMXT" 927132718Skan "wunpckihh%?\\t%0, %1, %2" 928132718Skan [(set_attr "predicable" "yes")]) 929132718Skan 930132718Skan(define_insn "iwmmxt_wunpckihw" 931132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 932132718Skan (vec_merge:V2SI 933132718Skan (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") 934132718Skan (parallel [(const_int 0) 935132718Skan (const_int 1)])) 936132718Skan (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") 937132718Skan (parallel [(const_int 1) 938132718Skan (const_int 0)])) 939132718Skan (const_int 1)))] 940132718Skan "TARGET_REALLY_IWMMXT" 941132718Skan "wunpckihw%?\\t%0, %1, %2" 942132718Skan [(set_attr "predicable" "yes")]) 943132718Skan 944132718Skan(define_insn "iwmmxt_wunpckilb" 945132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 946132718Skan (vec_merge:V8QI 947132718Skan (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") 948132718Skan (parallel [(const_int 0) 949132718Skan (const_int 4) 950132718Skan (const_int 1) 951132718Skan (const_int 5) 952132718Skan (const_int 2) 953132718Skan (const_int 6) 954132718Skan (const_int 3) 955132718Skan (const_int 7)])) 956132718Skan (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 957132718Skan (parallel [(const_int 4) 958132718Skan (const_int 0) 959132718Skan (const_int 5) 960132718Skan (const_int 1) 961132718Skan (const_int 6) 962132718Skan (const_int 2) 963132718Skan (const_int 7) 964132718Skan (const_int 3)])) 965132718Skan (const_int 85)))] 966132718Skan "TARGET_REALLY_IWMMXT" 967132718Skan "wunpckilb%?\\t%0, %1, %2" 968132718Skan [(set_attr "predicable" "yes")]) 969132718Skan 970132718Skan(define_insn "iwmmxt_wunpckilh" 971132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 972132718Skan (vec_merge:V4HI 973132718Skan (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") 974132718Skan (parallel [(const_int 2) 975132718Skan (const_int 0) 976132718Skan (const_int 3) 977132718Skan (const_int 1)])) 978132718Skan (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 979132718Skan (parallel [(const_int 0) 980132718Skan (const_int 2) 981132718Skan (const_int 1) 982132718Skan (const_int 3)])) 983132718Skan (const_int 5)))] 984132718Skan "TARGET_REALLY_IWMMXT" 985132718Skan "wunpckilh%?\\t%0, %1, %2" 986132718Skan [(set_attr "predicable" "yes")]) 987132718Skan 988132718Skan(define_insn "iwmmxt_wunpckilw" 989132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 990132718Skan (vec_merge:V2SI 991132718Skan (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") 992132718Skan (parallel [(const_int 1) 993132718Skan (const_int 0)])) 994132718Skan (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") 995132718Skan (parallel [(const_int 0) 996132718Skan (const_int 1)])) 997132718Skan (const_int 1)))] 998132718Skan "TARGET_REALLY_IWMMXT" 999132718Skan "wunpckilw%?\\t%0, %1, %2" 1000132718Skan [(set_attr "predicable" "yes")]) 1001132718Skan 1002132718Skan(define_insn "iwmmxt_wunpckehub" 1003132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1004132718Skan (zero_extend:V4HI 1005132718Skan (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1006132718Skan (parallel [(const_int 4) (const_int 5) 1007132718Skan (const_int 6) (const_int 7)]))))] 1008132718Skan "TARGET_REALLY_IWMMXT" 1009132718Skan "wunpckehub%?\\t%0, %1" 1010132718Skan [(set_attr "predicable" "yes")]) 1011132718Skan 1012132718Skan(define_insn "iwmmxt_wunpckehuh" 1013132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1014132718Skan (zero_extend:V2SI 1015132718Skan (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1016132718Skan (parallel [(const_int 2) (const_int 3)]))))] 1017132718Skan "TARGET_REALLY_IWMMXT" 1018132718Skan "wunpckehuh%?\\t%0, %1" 1019132718Skan [(set_attr "predicable" "yes")]) 1020132718Skan 1021132718Skan(define_insn "iwmmxt_wunpckehuw" 1022132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1023132718Skan (zero_extend:DI 1024132718Skan (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1025132718Skan (parallel [(const_int 1)]))))] 1026132718Skan "TARGET_REALLY_IWMMXT" 1027132718Skan "wunpckehuw%?\\t%0, %1" 1028132718Skan [(set_attr "predicable" "yes")]) 1029132718Skan 1030132718Skan(define_insn "iwmmxt_wunpckehsb" 1031132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1032132718Skan (sign_extend:V4HI 1033132718Skan (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1034132718Skan (parallel [(const_int 4) (const_int 5) 1035132718Skan (const_int 6) (const_int 7)]))))] 1036132718Skan "TARGET_REALLY_IWMMXT" 1037132718Skan "wunpckehsb%?\\t%0, %1" 1038132718Skan [(set_attr "predicable" "yes")]) 1039132718Skan 1040132718Skan(define_insn "iwmmxt_wunpckehsh" 1041132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1042132718Skan (sign_extend:V2SI 1043132718Skan (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1044132718Skan (parallel [(const_int 2) (const_int 3)]))))] 1045132718Skan "TARGET_REALLY_IWMMXT" 1046132718Skan "wunpckehsh%?\\t%0, %1" 1047132718Skan [(set_attr "predicable" "yes")]) 1048132718Skan 1049132718Skan(define_insn "iwmmxt_wunpckehsw" 1050132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1051132718Skan (sign_extend:DI 1052132718Skan (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1053132718Skan (parallel [(const_int 1)]))))] 1054132718Skan "TARGET_REALLY_IWMMXT" 1055132718Skan "wunpckehsw%?\\t%0, %1" 1056132718Skan [(set_attr "predicable" "yes")]) 1057132718Skan 1058132718Skan(define_insn "iwmmxt_wunpckelub" 1059132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1060132718Skan (zero_extend:V4HI 1061132718Skan (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1062132718Skan (parallel [(const_int 0) (const_int 1) 1063132718Skan (const_int 2) (const_int 3)]))))] 1064132718Skan "TARGET_REALLY_IWMMXT" 1065132718Skan "wunpckelub%?\\t%0, %1" 1066132718Skan [(set_attr "predicable" "yes")]) 1067132718Skan 1068132718Skan(define_insn "iwmmxt_wunpckeluh" 1069132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1070132718Skan (zero_extend:V2SI 1071132718Skan (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1072132718Skan (parallel [(const_int 0) (const_int 1)]))))] 1073132718Skan "TARGET_REALLY_IWMMXT" 1074132718Skan "wunpckeluh%?\\t%0, %1" 1075132718Skan [(set_attr "predicable" "yes")]) 1076132718Skan 1077132718Skan(define_insn "iwmmxt_wunpckeluw" 1078132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1079132718Skan (zero_extend:DI 1080132718Skan (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1081132718Skan (parallel [(const_int 0)]))))] 1082132718Skan "TARGET_REALLY_IWMMXT" 1083132718Skan "wunpckeluw%?\\t%0, %1" 1084132718Skan [(set_attr "predicable" "yes")]) 1085132718Skan 1086132718Skan(define_insn "iwmmxt_wunpckelsb" 1087132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1088132718Skan (sign_extend:V4HI 1089132718Skan (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1090132718Skan (parallel [(const_int 0) (const_int 1) 1091132718Skan (const_int 2) (const_int 3)]))))] 1092132718Skan "TARGET_REALLY_IWMMXT" 1093132718Skan "wunpckelsb%?\\t%0, %1" 1094132718Skan [(set_attr "predicable" "yes")]) 1095132718Skan 1096132718Skan(define_insn "iwmmxt_wunpckelsh" 1097132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1098132718Skan (sign_extend:V2SI 1099132718Skan (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1100132718Skan (parallel [(const_int 0) (const_int 1)]))))] 1101132718Skan "TARGET_REALLY_IWMMXT" 1102132718Skan "wunpckelsh%?\\t%0, %1" 1103132718Skan [(set_attr "predicable" "yes")]) 1104132718Skan 1105132718Skan(define_insn "iwmmxt_wunpckelsw" 1106132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1107132718Skan (sign_extend:DI 1108132718Skan (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1109132718Skan (parallel [(const_int 0)]))))] 1110132718Skan "TARGET_REALLY_IWMMXT" 1111132718Skan "wunpckelsw%?\\t%0, %1" 1112132718Skan [(set_attr "predicable" "yes")]) 1113132718Skan 1114132718Skan;; Shifts 1115132718Skan 1116132718Skan(define_insn "rorv4hi3" 1117132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1118132718Skan (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") 1119132718Skan (match_operand:SI 2 "register_operand" "z")))] 1120132718Skan "TARGET_REALLY_IWMMXT" 1121132718Skan "wrorhg%?\\t%0, %1, %2" 1122132718Skan [(set_attr "predicable" "yes")]) 1123132718Skan 1124132718Skan(define_insn "rorv2si3" 1125132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1126132718Skan (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") 1127132718Skan (match_operand:SI 2 "register_operand" "z")))] 1128132718Skan "TARGET_REALLY_IWMMXT" 1129132718Skan "wrorwg%?\\t%0, %1, %2" 1130132718Skan [(set_attr "predicable" "yes")]) 1131132718Skan 1132132718Skan(define_insn "rordi3" 1133132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1134132718Skan (rotatert:DI (match_operand:DI 1 "register_operand" "y") 1135132718Skan (match_operand:SI 2 "register_operand" "z")))] 1136132718Skan "TARGET_REALLY_IWMMXT" 1137132718Skan "wrordg%?\\t%0, %1, %2" 1138132718Skan [(set_attr "predicable" "yes")]) 1139132718Skan 1140132718Skan(define_insn "ashrv4hi3" 1141132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1142132718Skan (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1143132718Skan (match_operand:SI 2 "register_operand" "z")))] 1144132718Skan "TARGET_REALLY_IWMMXT" 1145132718Skan "wsrahg%?\\t%0, %1, %2" 1146132718Skan [(set_attr "predicable" "yes")]) 1147132718Skan 1148132718Skan(define_insn "ashrv2si3" 1149132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1150132718Skan (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1151132718Skan (match_operand:SI 2 "register_operand" "z")))] 1152132718Skan "TARGET_REALLY_IWMMXT" 1153132718Skan "wsrawg%?\\t%0, %1, %2" 1154132718Skan [(set_attr "predicable" "yes")]) 1155132718Skan 1156169689Skan(define_insn "ashrdi3_iwmmxt" 1157132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1158132718Skan (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") 1159132718Skan (match_operand:SI 2 "register_operand" "z")))] 1160132718Skan "TARGET_REALLY_IWMMXT" 1161132718Skan "wsradg%?\\t%0, %1, %2" 1162132718Skan [(set_attr "predicable" "yes")]) 1163132718Skan 1164132718Skan(define_insn "lshrv4hi3" 1165132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1166132718Skan (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1167132718Skan (match_operand:SI 2 "register_operand" "z")))] 1168132718Skan "TARGET_REALLY_IWMMXT" 1169132718Skan "wsrlhg%?\\t%0, %1, %2" 1170132718Skan [(set_attr "predicable" "yes")]) 1171132718Skan 1172132718Skan(define_insn "lshrv2si3" 1173132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1174132718Skan (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1175132718Skan (match_operand:SI 2 "register_operand" "z")))] 1176132718Skan "TARGET_REALLY_IWMMXT" 1177132718Skan "wsrlwg%?\\t%0, %1, %2" 1178132718Skan [(set_attr "predicable" "yes")]) 1179132718Skan 1180169689Skan(define_insn "lshrdi3_iwmmxt" 1181132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1182132718Skan (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") 1183132718Skan (match_operand:SI 2 "register_operand" "z")))] 1184132718Skan "TARGET_REALLY_IWMMXT" 1185132718Skan "wsrldg%?\\t%0, %1, %2" 1186132718Skan [(set_attr "predicable" "yes")]) 1187132718Skan 1188132718Skan(define_insn "ashlv4hi3" 1189132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1190132718Skan (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") 1191132718Skan (match_operand:SI 2 "register_operand" "z")))] 1192132718Skan "TARGET_REALLY_IWMMXT" 1193132718Skan "wsllhg%?\\t%0, %1, %2" 1194132718Skan [(set_attr "predicable" "yes")]) 1195132718Skan 1196132718Skan(define_insn "ashlv2si3" 1197132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1198132718Skan (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") 1199132718Skan (match_operand:SI 2 "register_operand" "z")))] 1200132718Skan "TARGET_REALLY_IWMMXT" 1201132718Skan "wsllwg%?\\t%0, %1, %2" 1202132718Skan [(set_attr "predicable" "yes")]) 1203132718Skan 1204132718Skan(define_insn "ashldi3_iwmmxt" 1205132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1206132718Skan (ashift:DI (match_operand:DI 1 "register_operand" "y") 1207132718Skan (match_operand:SI 2 "register_operand" "z")))] 1208132718Skan "TARGET_REALLY_IWMMXT" 1209132718Skan "wslldg%?\\t%0, %1, %2" 1210132718Skan [(set_attr "predicable" "yes")]) 1211132718Skan 1212132718Skan(define_insn "rorv4hi3_di" 1213132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1214132718Skan (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") 1215132718Skan (match_operand:DI 2 "register_operand" "y")))] 1216132718Skan "TARGET_REALLY_IWMMXT" 1217132718Skan "wrorh%?\\t%0, %1, %2" 1218132718Skan [(set_attr "predicable" "yes")]) 1219132718Skan 1220132718Skan(define_insn "rorv2si3_di" 1221132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1222132718Skan (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") 1223132718Skan (match_operand:DI 2 "register_operand" "y")))] 1224132718Skan "TARGET_REALLY_IWMMXT" 1225132718Skan "wrorw%?\\t%0, %1, %2" 1226132718Skan [(set_attr "predicable" "yes")]) 1227132718Skan 1228132718Skan(define_insn "rordi3_di" 1229132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1230132718Skan (rotatert:DI (match_operand:DI 1 "register_operand" "y") 1231132718Skan (match_operand:DI 2 "register_operand" "y")))] 1232132718Skan "TARGET_REALLY_IWMMXT" 1233132718Skan "wrord%?\\t%0, %1, %2" 1234132718Skan [(set_attr "predicable" "yes")]) 1235132718Skan 1236132718Skan(define_insn "ashrv4hi3_di" 1237132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1238132718Skan (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1239132718Skan (match_operand:DI 2 "register_operand" "y")))] 1240132718Skan "TARGET_REALLY_IWMMXT" 1241132718Skan "wsrah%?\\t%0, %1, %2" 1242132718Skan [(set_attr "predicable" "yes")]) 1243132718Skan 1244132718Skan(define_insn "ashrv2si3_di" 1245132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1246132718Skan (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1247132718Skan (match_operand:DI 2 "register_operand" "y")))] 1248132718Skan "TARGET_REALLY_IWMMXT" 1249132718Skan "wsraw%?\\t%0, %1, %2" 1250132718Skan [(set_attr "predicable" "yes")]) 1251132718Skan 1252132718Skan(define_insn "ashrdi3_di" 1253132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1254132718Skan (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") 1255132718Skan (match_operand:DI 2 "register_operand" "y")))] 1256132718Skan "TARGET_REALLY_IWMMXT" 1257132718Skan "wsrad%?\\t%0, %1, %2" 1258132718Skan [(set_attr "predicable" "yes")]) 1259132718Skan 1260132718Skan(define_insn "lshrv4hi3_di" 1261132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1262132718Skan (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1263132718Skan (match_operand:DI 2 "register_operand" "y")))] 1264132718Skan "TARGET_REALLY_IWMMXT" 1265132718Skan "wsrlh%?\\t%0, %1, %2" 1266132718Skan [(set_attr "predicable" "yes")]) 1267132718Skan 1268132718Skan(define_insn "lshrv2si3_di" 1269132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1270132718Skan (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1271132718Skan (match_operand:DI 2 "register_operand" "y")))] 1272132718Skan "TARGET_REALLY_IWMMXT" 1273132718Skan "wsrlw%?\\t%0, %1, %2" 1274132718Skan [(set_attr "predicable" "yes")]) 1275132718Skan 1276132718Skan(define_insn "lshrdi3_di" 1277132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1278132718Skan (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") 1279132718Skan (match_operand:DI 2 "register_operand" "y")))] 1280132718Skan "TARGET_REALLY_IWMMXT" 1281132718Skan "wsrld%?\\t%0, %1, %2" 1282132718Skan [(set_attr "predicable" "yes")]) 1283132718Skan 1284132718Skan(define_insn "ashlv4hi3_di" 1285132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1286132718Skan (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") 1287132718Skan (match_operand:DI 2 "register_operand" "y")))] 1288132718Skan "TARGET_REALLY_IWMMXT" 1289132718Skan "wsllh%?\\t%0, %1, %2" 1290132718Skan [(set_attr "predicable" "yes")]) 1291132718Skan 1292132718Skan(define_insn "ashlv2si3_di" 1293132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1294132718Skan (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") 1295132718Skan (match_operand:DI 2 "register_operand" "y")))] 1296132718Skan "TARGET_REALLY_IWMMXT" 1297132718Skan "wsllw%?\\t%0, %1, %2" 1298132718Skan [(set_attr "predicable" "yes")]) 1299132718Skan 1300132718Skan(define_insn "ashldi3_di" 1301132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1302132718Skan (ashift:DI (match_operand:DI 1 "register_operand" "y") 1303132718Skan (match_operand:DI 2 "register_operand" "y")))] 1304132718Skan "TARGET_REALLY_IWMMXT" 1305132718Skan "wslld%?\\t%0, %1, %2" 1306132718Skan [(set_attr "predicable" "yes")]) 1307132718Skan 1308132718Skan(define_insn "iwmmxt_wmadds" 1309132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1310132718Skan (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1311132718Skan (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))] 1312132718Skan "TARGET_REALLY_IWMMXT" 1313132718Skan "wmadds%?\\t%0, %1, %2" 1314132718Skan [(set_attr "predicable" "yes")]) 1315132718Skan 1316132718Skan(define_insn "iwmmxt_wmaddu" 1317132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1318132718Skan (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1319132718Skan (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))] 1320132718Skan "TARGET_REALLY_IWMMXT" 1321132718Skan "wmaddu%?\\t%0, %1, %2" 1322132718Skan [(set_attr "predicable" "yes")]) 1323132718Skan 1324132718Skan(define_insn "iwmmxt_tmia" 1325132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1326132718Skan (plus:DI (match_operand:DI 1 "register_operand" "0") 1327132718Skan (mult:DI (sign_extend:DI 1328132718Skan (match_operand:SI 2 "register_operand" "r")) 1329132718Skan (sign_extend:DI 1330132718Skan (match_operand:SI 3 "register_operand" "r")))))] 1331132718Skan "TARGET_REALLY_IWMMXT" 1332132718Skan "tmia%?\\t%0, %2, %3" 1333132718Skan [(set_attr "predicable" "yes")]) 1334132718Skan 1335132718Skan(define_insn "iwmmxt_tmiaph" 1336132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1337132718Skan (plus:DI (match_operand:DI 1 "register_operand" "0") 1338132718Skan (plus:DI 1339132718Skan (mult:DI (sign_extend:DI 1340132718Skan (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1341132718Skan (sign_extend:DI 1342132718Skan (truncate:HI (match_operand:SI 3 "register_operand" "r")))) 1343132718Skan (mult:DI (sign_extend:DI 1344132718Skan (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16)))) 1345132718Skan (sign_extend:DI 1346132718Skan (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))] 1347132718Skan "TARGET_REALLY_IWMMXT" 1348132718Skan "tmiaph%?\\t%0, %2, %3" 1349132718Skan [(set_attr "predicable" "yes")]) 1350132718Skan 1351132718Skan(define_insn "iwmmxt_tmiabb" 1352132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1353132718Skan (plus:DI (match_operand:DI 1 "register_operand" "0") 1354132718Skan (mult:DI (sign_extend:DI 1355132718Skan (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1356132718Skan (sign_extend:DI 1357132718Skan (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] 1358132718Skan "TARGET_REALLY_IWMMXT" 1359132718Skan "tmiabb%?\\t%0, %2, %3" 1360132718Skan [(set_attr "predicable" "yes")]) 1361132718Skan 1362132718Skan(define_insn "iwmmxt_tmiatb" 1363132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1364132718Skan (plus:DI (match_operand:DI 1 "register_operand" "0") 1365132718Skan (mult:DI (sign_extend:DI 1366132718Skan (truncate:HI (ashiftrt:SI 1367132718Skan (match_operand:SI 2 "register_operand" "r") 1368132718Skan (const_int 16)))) 1369132718Skan (sign_extend:DI 1370132718Skan (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] 1371132718Skan "TARGET_REALLY_IWMMXT" 1372132718Skan "tmiatb%?\\t%0, %2, %3" 1373132718Skan [(set_attr "predicable" "yes")]) 1374132718Skan 1375132718Skan(define_insn "iwmmxt_tmiabt" 1376132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1377132718Skan (plus:DI (match_operand:DI 1 "register_operand" "0") 1378132718Skan (mult:DI (sign_extend:DI 1379132718Skan (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1380132718Skan (sign_extend:DI 1381132718Skan (truncate:HI (ashiftrt:SI 1382132718Skan (match_operand:SI 3 "register_operand" "r") 1383132718Skan (const_int 16)))))))] 1384132718Skan "TARGET_REALLY_IWMMXT" 1385132718Skan "tmiabt%?\\t%0, %2, %3" 1386132718Skan [(set_attr "predicable" "yes")]) 1387132718Skan 1388132718Skan(define_insn "iwmmxt_tmiatt" 1389132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1390132718Skan (plus:DI (match_operand:DI 1 "register_operand" "0") 1391132718Skan (mult:DI (sign_extend:DI 1392132718Skan (truncate:HI (ashiftrt:SI 1393132718Skan (match_operand:SI 2 "register_operand" "r") 1394132718Skan (const_int 16)))) 1395132718Skan (sign_extend:DI 1396132718Skan (truncate:HI (ashiftrt:SI 1397132718Skan (match_operand:SI 3 "register_operand" "r") 1398132718Skan (const_int 16)))))))] 1399132718Skan "TARGET_REALLY_IWMMXT" 1400132718Skan "tmiatt%?\\t%0, %2, %3" 1401132718Skan [(set_attr "predicable" "yes")]) 1402132718Skan 1403132718Skan(define_insn "iwmmxt_tbcstqi" 1404132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 1405132718Skan (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))] 1406132718Skan "TARGET_REALLY_IWMMXT" 1407132718Skan "tbcstb%?\\t%0, %1" 1408132718Skan [(set_attr "predicable" "yes")]) 1409132718Skan 1410132718Skan(define_insn "iwmmxt_tbcsthi" 1411132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1412132718Skan (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))] 1413132718Skan "TARGET_REALLY_IWMMXT" 1414132718Skan "tbcsth%?\\t%0, %1" 1415132718Skan [(set_attr "predicable" "yes")]) 1416132718Skan 1417132718Skan(define_insn "iwmmxt_tbcstsi" 1418132718Skan [(set (match_operand:V2SI 0 "register_operand" "=y") 1419132718Skan (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))] 1420132718Skan "TARGET_REALLY_IWMMXT" 1421132718Skan "tbcstw%?\\t%0, %1" 1422132718Skan [(set_attr "predicable" "yes")]) 1423132718Skan 1424132718Skan(define_insn "iwmmxt_tmovmskb" 1425132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 1426132718Skan (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1427132718Skan "TARGET_REALLY_IWMMXT" 1428132718Skan "tmovmskb%?\\t%0, %1" 1429132718Skan [(set_attr "predicable" "yes")]) 1430132718Skan 1431132718Skan(define_insn "iwmmxt_tmovmskh" 1432132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 1433132718Skan (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1434132718Skan "TARGET_REALLY_IWMMXT" 1435132718Skan "tmovmskh%?\\t%0, %1" 1436132718Skan [(set_attr "predicable" "yes")]) 1437132718Skan 1438132718Skan(define_insn "iwmmxt_tmovmskw" 1439132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 1440132718Skan (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1441132718Skan "TARGET_REALLY_IWMMXT" 1442132718Skan "tmovmskw%?\\t%0, %1" 1443132718Skan [(set_attr "predicable" "yes")]) 1444132718Skan 1445132718Skan(define_insn "iwmmxt_waccb" 1446132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1447132718Skan (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))] 1448132718Skan "TARGET_REALLY_IWMMXT" 1449132718Skan "waccb%?\\t%0, %1" 1450132718Skan [(set_attr "predicable" "yes")]) 1451132718Skan 1452132718Skan(define_insn "iwmmxt_wacch" 1453132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1454132718Skan (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))] 1455132718Skan "TARGET_REALLY_IWMMXT" 1456132718Skan "wacch%?\\t%0, %1" 1457132718Skan [(set_attr "predicable" "yes")]) 1458132718Skan 1459132718Skan(define_insn "iwmmxt_waccw" 1460132718Skan [(set (match_operand:DI 0 "register_operand" "=y") 1461132718Skan (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))] 1462132718Skan "TARGET_REALLY_IWMMXT" 1463132718Skan "waccw%?\\t%0, %1" 1464132718Skan [(set_attr "predicable" "yes")]) 1465132718Skan 1466132718Skan(define_insn "iwmmxt_walign" 1467132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y,y") 1468132718Skan (subreg:V8QI (ashiftrt:TI 1469132718Skan (subreg:TI (vec_concat:V16QI 1470132718Skan (match_operand:V8QI 1 "register_operand" "y,y") 1471132718Skan (match_operand:V8QI 2 "register_operand" "y,y")) 0) 1472132718Skan (mult:SI 1473132718Skan (match_operand:SI 3 "nonmemory_operand" "i,z") 1474132718Skan (const_int 8))) 0))] 1475132718Skan "TARGET_REALLY_IWMMXT" 1476132718Skan "@ 1477132718Skan waligni%?\\t%0, %1, %2, %3 1478132718Skan walignr%U3%?\\t%0, %1, %2" 1479132718Skan [(set_attr "predicable" "yes")]) 1480132718Skan 1481132718Skan(define_insn "iwmmxt_tmrc" 1482132718Skan [(set (match_operand:SI 0 "register_operand" "=r") 1483132718Skan (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] 1484132718Skan VUNSPEC_TMRC))] 1485132718Skan "TARGET_REALLY_IWMMXT" 1486132718Skan "tmrc%?\\t%0, %w1" 1487132718Skan [(set_attr "predicable" "yes")]) 1488132718Skan 1489132718Skan(define_insn "iwmmxt_tmcr" 1490132718Skan [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i") 1491132718Skan (match_operand:SI 1 "register_operand" "r")] 1492132718Skan VUNSPEC_TMCR)] 1493132718Skan "TARGET_REALLY_IWMMXT" 1494132718Skan "tmcr%?\\t%w0, %1" 1495132718Skan [(set_attr "predicable" "yes")]) 1496132718Skan 1497132718Skan(define_insn "iwmmxt_wsadb" 1498132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 1499132718Skan (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 1500132718Skan (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))] 1501132718Skan "TARGET_REALLY_IWMMXT" 1502132718Skan "wsadb%?\\t%0, %1, %2" 1503132718Skan [(set_attr "predicable" "yes")]) 1504132718Skan 1505132718Skan(define_insn "iwmmxt_wsadh" 1506132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1507132718Skan (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1508132718Skan (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))] 1509132718Skan "TARGET_REALLY_IWMMXT" 1510132718Skan "wsadh%?\\t%0, %1, %2" 1511132718Skan [(set_attr "predicable" "yes")]) 1512132718Skan 1513132718Skan(define_insn "iwmmxt_wsadbz" 1514132718Skan [(set (match_operand:V8QI 0 "register_operand" "=y") 1515132718Skan (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 1516132718Skan (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))] 1517132718Skan "TARGET_REALLY_IWMMXT" 1518132718Skan "wsadbz%?\\t%0, %1, %2" 1519132718Skan [(set_attr "predicable" "yes")]) 1520132718Skan 1521132718Skan(define_insn "iwmmxt_wsadhz" 1522132718Skan [(set (match_operand:V4HI 0 "register_operand" "=y") 1523132718Skan (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1524132718Skan (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))] 1525132718Skan "TARGET_REALLY_IWMMXT" 1526132718Skan "wsadhz%?\\t%0, %1, %2" 1527132718Skan [(set_attr "predicable" "yes")]) 1528132718Skan 1529