constraints.md revision 169689
1279377Simp;; Constraint definitions for ARM and Thumb 2279377Simp;; Copyright (C) 2006 Free Software Foundation, Inc. 3279377Simp;; Contributed by ARM Ltd. 4279377Simp 5279377Simp;; This file is part of GCC. 6279377Simp 7279377Simp;; GCC is free software; you can redistribute it and/or modify it 8279377Simp;; under the terms of the GNU General Public License as published 9279377Simp;; by the Free Software Foundation; either version 2, or (at your 10279377Simp;; option) any later version. 11279377Simp 12279377Simp;; GCC is distributed in the hope that it will be useful, but WITHOUT 13279377Simp;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14279377Simp;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15279377Simp;; License for more details. 16279377Simp 17279377Simp;; You should have received a copy of the GNU General Public License 18279377Simp;; along with GCC; see the file COPYING. If not, write to 19279377Simp;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20279377Simp;; Boston, MA 02110-1301, USA. 21279377Simp 22279377Simp;; The following register constraints have been used: 23279377Simp;; - in ARM state: f, v, w, y, z 24279377Simp;; - in Thumb state: h, k, b 25279377Simp;; - in both states: l, c 26279377Simp;; In ARM state, 'l' is an alias for 'r' 27279377Simp 28279377Simp;; The following normal constraints have been used: 29279377Simp;; in ARM state: G, H, I, J, K, L, M 30279377Simp;; in Thumb state: I, J, K, L, M, N, O 31279377Simp 32279377Simp;; The following multi-letter normal constraints have been used: 33279377Simp;; in ARM state: Da, Db, Dc 34279377Simp 35279377Simp;; The following memory constraints have been used: 36279377Simp;; in ARM state: Q, Uq, Uv, Uy 37279377Simp 38279377Simp 39279377Simp(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS" 40279377Simp "Legacy FPA registers @code{f0}-@code{f7}.") 41279377Simp 42279377Simp(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS" 43279377Simp "The Cirrus Maverick co-processor registers.") 44279377Simp 45279377Simp(define_register_constraint "w" "TARGET_ARM ? VFP_REGS : NO_REGS" 46279377Simp "The VFP registers @code{s0}-@code{s31}.") 47279377Simp 48279377Simp(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS" 49279377Simp "The Intel iWMMX co-processor registers.") 50279377Simp 51279377Simp(define_register_constraint "z" 52279377Simp "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS" 53279377Simp "The Intel iWMMX GR registers.") 54279377Simp 55279377Simp(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS" 56279377Simp "In Thumb state the core registers @code{r0}-@code{r7}.") 57279377Simp 58279377Simp(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS" 59279377Simp "In Thumb state the core registers @code{r8}-@code{r15}.") 60279377Simp 61279377Simp(define_register_constraint "k" "TARGET_THUMB ? STACK_REG : NO_REGS" 62279377Simp "@internal 63279377Simp Thumb only. The stack register.") 64279377Simp 65279377Simp(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" 66279377Simp "@internal 67279377Simp Thumb only. The union of the low registers and the stack register.") 68279377Simp 69279377Simp(define_register_constraint "c" "CC_REG" 70279377Simp "@internal The condition code register.") 71279377Simp 72279377Simp(define_constraint "I" 73279377Simp "In ARM state a constant that can be used as an immediate value in a Data 74279377Simp Processing instruction. In Thumb state a constant in the range 0-255." 75279377Simp (and (match_code "const_int") 76279377Simp (match_test "TARGET_ARM ? const_ok_for_arm (ival) 77279377Simp : ival >= 0 && ival <= 255"))) 78279377Simp 79279377Simp(define_constraint "J" 80279377Simp "In ARM state a constant in the range @minus{}4095-4095. In Thumb state 81279377Simp a constant in the range @minus{}255-@minus{}1." 82279377Simp (and (match_code "const_int") 83279377Simp (match_test "TARGET_ARM ? (ival >= -4095 && ival <= 4095) 84279377Simp : (ival >= -255 && ival <= -1)"))) 85279377Simp 86279377Simp(define_constraint "K" 87279377Simp "In ARM state a constant that satisfies the @code{I} constraint if inverted. 88279377Simp In Thumb state a constant that satisfies the @code{I} constraint multiplied 89279377Simp by any power of 2." 90279377Simp (and (match_code "const_int") 91279377Simp (match_test "TARGET_ARM ? const_ok_for_arm (~ival) 92279377Simp : thumb_shiftable_const (ival)"))) 93279377Simp 94279377Simp(define_constraint "L" 95279377Simp "In ARM state a constant that satisfies the @code{I} constraint if negated. 96279377Simp In Thumb state a constant in the range @minus{}7-7." 97279377Simp (and (match_code "const_int") 98279377Simp (match_test "TARGET_ARM ? const_ok_for_arm (-ival) 99279377Simp : (ival >= -7 && ival <= 7)"))) 100279377Simp 101279377Simp;; The ARM state version is internal... 102279377Simp;; @internal In ARM state a constant in the range 0-32 or any power of 2. 103279377Simp(define_constraint "M" 104279377Simp "In Thumb state a constant that is a multiple of 4 in the range 0-1020." 105279377Simp (and (match_code "const_int") 106279377Simp (match_test "TARGET_ARM ? ((ival >= 0 && ival <= 32) 107279377Simp || ((ival & (ival - 1)) == 0)) 108279377Simp : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))"))) 109279377Simp 110279377Simp(define_constraint "N" 111279377Simp "In Thumb state a constant in the range 0-31." 112279377Simp (and (match_code "const_int") 113279377Simp (match_test "TARGET_THUMB && ival >= 0 && ival <= 31"))) 114279377Simp 115279377Simp(define_constraint "O" 116279377Simp "In Thumb state a constant that is a multiple of 4 in the range 117279377Simp @minus{}508-508." 118279377Simp (and (match_code "const_int") 119279377Simp (match_test "TARGET_THUMB && ival >= -508 && ival <= 508 120279377Simp && ((ival & 3) == 0)"))) 121279377Simp 122279377Simp(define_constraint "G" 123279377Simp "In ARM state a valid FPA immediate constant." 124279377Simp (and (match_code "const_double") 125279377Simp (match_test "TARGET_ARM && arm_const_double_rtx (op)"))) 126279377Simp 127279377Simp(define_constraint "H" 128279377Simp "In ARM state a valid FPA immediate constant when negated." 129279377Simp (and (match_code "const_double") 130279377Simp (match_test "TARGET_ARM && neg_const_double_rtx_ok_for_fpa (op)"))) 131279377Simp 132279377Simp(define_constraint "Da" 133279377Simp "@internal 134279377Simp In ARM state a const_int, const_double or const_vector that can 135279377Simp be generated with two Data Processing insns." 136279377Simp (and (match_code "const_double,const_int,const_vector") 137279377Simp (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 2"))) 138279377Simp 139279377Simp(define_constraint "Db" 140279377Simp "@internal 141279377Simp In ARM state a const_int, const_double or const_vector that can 142279377Simp be generated with three Data Processing insns." 143279377Simp (and (match_code "const_double,const_int,const_vector") 144279377Simp (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 3"))) 145279377Simp 146279377Simp(define_constraint "Dc" 147279377Simp "@internal 148279377Simp In ARM state a const_int, const_double or const_vector that can 149279377Simp be generated with four Data Processing insns. This pattern is disabled 150279377Simp if optimizing for space or when we have load-delay slots to fill." 151279377Simp (and (match_code "const_double,const_int,const_vector") 152279377Simp (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 4 153279377Simp && !(optimize_size || arm_ld_sched)"))) 154279377Simp 155279377Simp(define_memory_constraint "Uv" 156279377Simp "@internal 157279377Simp In ARM state a valid VFP load/store address." 158279377Simp (and (match_code "mem") 159279377Simp (match_test "TARGET_ARM && arm_coproc_mem_operand (op, FALSE)"))) 160279377Simp 161279377Simp(define_memory_constraint "Uy" 162279377Simp "@internal 163279377Simp In ARM state a valid iWMMX load/store address." 164279377Simp (and (match_code "mem") 165279377Simp (match_test "TARGET_ARM && arm_coproc_mem_operand (op, TRUE)"))) 166279377Simp 167279377Simp(define_memory_constraint "Uq" 168279377Simp "@internal 169279377Simp In ARM state an address valid in ldrsb instructions." 170279377Simp (and (match_code "mem") 171279377Simp (match_test "TARGET_ARM 172279377Simp && arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 173279377Simp SIGN_EXTEND, 0)"))) 174279377Simp 175279377Simp(define_memory_constraint "Q" 176279377Simp "@internal 177279377Simp In ARM state an address that is a single base register." 178279377Simp (and (match_code "mem") 179279377Simp (match_test "REG_P (XEXP (op, 0))"))) 180279377Simp 181279377Simp;; We used to have constraint letters for S and R in ARM state, but 182279377Simp;; all uses of these now appear to have been removed. 183279377Simp 184279377Simp;; Additionally, we used to have a Q constraint in Thumb state, but 185279377Simp;; this wasn't really a valid memory constraint. Again, all uses of 186279377Simp;; this now seem to have been removed. 187279377Simp