cirrus.md revision 132718
1;; Cirrus EP9312 "Maverick" ARM floating point co-processor description. 2;; Copyright (C) 2003 Free Software Foundation, Inc. 3;; Contributed by Red Hat. 4;; Written by Aldy Hernandez (aldyh@redhat.com) 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 2, or (at your option) 11;; any later version. 12 13;; GCC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING. If not, write to 20;; the Free Software Foundation, 59 Temple Place - Suite 330, 21;; Boston, MA 02111-1307, USA. 22 23 24; Cirrus types for invalid insn combinations 25; not Not a cirrus insn 26; normal Any Cirrus insn not covered by the special cases below 27; double cfldrd, cfldr64, cfstrd, cfstr64 28; compare cfcmps, cfcmpd, cfcmp32, cfcmp64 29; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr 30(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not")) 31 32 33(define_insn "cirrus_adddi3" 34 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 35 (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") 36 (match_operand:DI 2 "cirrus_fp_register" "v")))] 37 "TARGET_ARM && TARGET_CIRRUS" 38 "cfadd64%?\\t%V0, %V1, %V2" 39 [(set_attr "type" "mav_farith") 40 (set_attr "cirrus" "normal")] 41) 42 43(define_insn "*cirrus_addsi3" 44 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 45 (plus:SI (match_operand:SI 1 "cirrus_fp_register" "v") 46 (match_operand:SI 2 "cirrus_fp_register" "v")))] 47 "TARGET_ARM && TARGET_CIRRUS && 0" 48 "cfadd32%?\\t%V0, %V1, %V2" 49 [(set_attr "type" "mav_farith") 50 (set_attr "cirrus" "normal")] 51) 52 53(define_insn "*cirrus_addsf3" 54 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 55 (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v") 56 (match_operand:SF 2 "cirrus_fp_register" "v")))] 57 "TARGET_ARM && TARGET_CIRRUS" 58 "cfadds%?\\t%V0, %V1, %V2" 59 [(set_attr "type" "mav_farith") 60 (set_attr "cirrus" "normal")] 61) 62 63(define_insn "*cirrus_adddf3" 64 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 65 (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v") 66 (match_operand:DF 2 "cirrus_fp_register" "v")))] 67 "TARGET_ARM && TARGET_CIRRUS" 68 "cfaddd%?\\t%V0, %V1, %V2" 69 [(set_attr "type" "mav_farith") 70 (set_attr "cirrus" "normal")] 71) 72 73(define_insn "cirrus_subdi3" 74 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 75 (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") 76 (match_operand:DI 2 "cirrus_fp_register" "v")))] 77 "TARGET_ARM && TARGET_CIRRUS" 78 "cfsub64%?\\t%V0, %V1, %V2" 79 [(set_attr "type" "mav_farith") 80 (set_attr "cirrus" "normal")] 81) 82 83(define_insn "*cirrus_subsi3_insn" 84 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 85 (minus:SI (match_operand:SI 1 "cirrus_fp_register" "v") 86 (match_operand:SI 2 "cirrus_fp_register" "v")))] 87 "TARGET_ARM && TARGET_CIRRUS && 0" 88 "cfsub32%?\\t%V0, %V1, %V2" 89 [(set_attr "type" "mav_farith") 90 (set_attr "cirrus" "normal")] 91) 92 93(define_insn "*cirrus_subsf3" 94 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 95 (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v") 96 (match_operand:SF 2 "cirrus_fp_register" "v")))] 97 "TARGET_ARM && TARGET_CIRRUS" 98 "cfsubs%?\\t%V0, %V1, %V2" 99 [(set_attr "type" "mav_farith") 100 (set_attr "cirrus" "normal")] 101) 102 103(define_insn "*cirrus_subdf3" 104 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 105 (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v") 106 (match_operand:DF 2 "cirrus_fp_register" "v")))] 107 "TARGET_ARM && TARGET_CIRRUS" 108 "cfsubd%?\\t%V0, %V1, %V2" 109 [(set_attr "type" "mav_farith") 110 (set_attr "cirrus" "normal")] 111) 112 113(define_insn "*cirrus_mulsi3" 114 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 115 (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") 116 (match_operand:SI 1 "cirrus_fp_register" "v")))] 117 "TARGET_ARM && TARGET_CIRRUS && 0" 118 "cfmul32%?\\t%V0, %V1, %V2" 119 [(set_attr "type" "mav_farith") 120 (set_attr "cirrus" "normal")] 121) 122 123(define_insn "muldi3" 124 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 125 (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") 126 (match_operand:DI 1 "cirrus_fp_register" "v")))] 127 "TARGET_ARM && TARGET_CIRRUS" 128 "cfmul64%?\\t%V0, %V1, %V2" 129 [(set_attr "type" "mav_dmult") 130 (set_attr "cirrus" "normal")] 131) 132 133(define_insn "*cirrus_mulsi3addsi" 134 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 135 (plus:SI 136 (mult:SI (match_operand:SI 1 "cirrus_fp_register" "v") 137 (match_operand:SI 2 "cirrus_fp_register" "v")) 138 (match_operand:SI 3 "cirrus_fp_register" "0")))] 139 "TARGET_ARM && TARGET_CIRRUS && 0" 140 "cfmac32%?\\t%V0, %V1, %V2" 141 [(set_attr "type" "mav_farith") 142 (set_attr "cirrus" "normal")] 143) 144 145;; Cirrus SI multiply-subtract 146(define_insn "*cirrus_mulsi3subsi" 147 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 148 (minus:SI 149 (match_operand:SI 1 "cirrus_fp_register" "0") 150 (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") 151 (match_operand:SI 3 "cirrus_fp_register" "v"))))] 152 "0 && TARGET_ARM && TARGET_CIRRUS" 153 "cfmsc32%?\\t%V0, %V2, %V3" 154 [(set_attr "type" "mav_farith") 155 (set_attr "cirrus" "normal")] 156) 157 158(define_insn "*cirrus_mulsf3" 159 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 160 (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v") 161 (match_operand:SF 2 "cirrus_fp_register" "v")))] 162 "TARGET_ARM && TARGET_CIRRUS" 163 "cfmuls%?\\t%V0, %V1, %V2" 164 [(set_attr "type" "mav_farith") 165 (set_attr "cirrus" "normal")] 166) 167 168(define_insn "*cirrus_muldf3" 169 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 170 (mult:DF (match_operand:DF 1 "cirrus_fp_register" "v") 171 (match_operand:DF 2 "cirrus_fp_register" "v")))] 172 "TARGET_ARM && TARGET_CIRRUS" 173 "cfmuld%?\\t%V0, %V1, %V2" 174 [(set_attr "type" "mav_dmult") 175 (set_attr "cirrus" "normal")] 176) 177 178(define_insn "cirrus_ashl_const" 179 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 180 (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v") 181 (match_operand:SI 2 "cirrus_shift_const" "")))] 182 "TARGET_ARM && TARGET_CIRRUS && 0" 183 "cfsh32%?\\t%V0, %V1, #%s2" 184 [(set_attr "cirrus" "normal")] 185) 186 187(define_insn "cirrus_ashiftrt_const" 188 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 189 (ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v") 190 (match_operand:SI 2 "cirrus_shift_const" "")))] 191 "TARGET_ARM && TARGET_CIRRUS && 0" 192 "cfsh32%?\\t%V0, %V1, #-%s2" 193 [(set_attr "cirrus" "normal")] 194) 195 196(define_insn "cirrus_ashlsi3" 197 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 198 (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v") 199 (match_operand:SI 2 "register_operand" "r")))] 200 "TARGET_ARM && TARGET_CIRRUS && 0" 201 "cfrshl32%?\\t%V1, %V0, %s2" 202 [(set_attr "cirrus" "normal")] 203) 204 205(define_insn "ashldi3_cirrus" 206 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 207 (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") 208 (match_operand:SI 2 "register_operand" "r")))] 209 "TARGET_ARM && TARGET_CIRRUS" 210 "cfrshl64%?\\t%V1, %V0, %s2" 211 [(set_attr "cirrus" "normal")] 212) 213 214(define_insn "cirrus_ashldi_const" 215 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 216 (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") 217 (match_operand:SI 2 "cirrus_shift_const" "")))] 218 "TARGET_ARM && TARGET_CIRRUS" 219 "cfsh64%?\\t%V0, %V1, #%s2" 220 [(set_attr "cirrus" "normal")] 221) 222 223(define_insn "cirrus_ashiftrtdi_const" 224 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 225 (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") 226 (match_operand:SI 2 "cirrus_shift_const" "")))] 227 "TARGET_ARM && TARGET_CIRRUS" 228 "cfsh64%?\\t%V0, %V1, #-%s2" 229 [(set_attr "cirrus" "normal")] 230) 231 232(define_insn "*cirrus_absdi2" 233 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 234 (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] 235 "TARGET_ARM && TARGET_CIRRUS" 236 "cfabs64%?\\t%V0, %V1" 237 [(set_attr "cirrus" "normal")] 238) 239 240;; This doesn't really clobber ``cc''. Fixme: aldyh. 241(define_insn "*cirrus_negdi2" 242 [(set (match_operand:DI 0 "cirrus_fp_register" "=v") 243 (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) 244 (clobber (reg:CC CC_REGNUM))] 245 "TARGET_ARM && TARGET_CIRRUS" 246 "cfneg64%?\\t%V0, %V1" 247 [(set_attr "cirrus" "normal")] 248) 249 250(define_insn "*cirrus_negsi2" 251 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 252 (neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))] 253 "TARGET_ARM && TARGET_CIRRUS && 0" 254 "cfneg32%?\\t%V0, %V1" 255 [(set_attr "cirrus" "normal")] 256) 257 258(define_insn "*cirrus_negsf2" 259 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 260 (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] 261 "TARGET_ARM && TARGET_CIRRUS" 262 "cfnegs%?\\t%V0, %V1" 263 [(set_attr "cirrus" "normal")] 264) 265 266(define_insn "*cirrus_negdf2" 267 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 268 (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] 269 "TARGET_ARM && TARGET_CIRRUS" 270 "cfnegd%?\\t%V0, %V1" 271 [(set_attr "cirrus" "normal")] 272) 273 274;; This doesn't really clobber the condition codes either. 275(define_insn "*cirrus_abssi2" 276 [(set (match_operand:SI 0 "cirrus_fp_register" "=v") 277 (abs:SI (match_operand:SI 1 "cirrus_fp_register" "v"))) 278 (clobber (reg:CC CC_REGNUM))] 279 "TARGET_ARM && TARGET_CIRRUS && 0" 280 "cfabs32%?\\t%V0, %V1" 281 [(set_attr "cirrus" "normal")] 282) 283 284(define_insn "*cirrus_abssf2" 285 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 286 (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] 287 "TARGET_ARM && TARGET_CIRRUS" 288 "cfabss%?\\t%V0, %V1" 289 [(set_attr "cirrus" "normal")] 290) 291 292(define_insn "*cirrus_absdf2" 293 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 294 (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] 295 "TARGET_ARM && TARGET_CIRRUS" 296 "cfabsd%?\\t%V0, %V1" 297 [(set_attr "cirrus" "normal")] 298) 299 300;; Convert Cirrus-SI to Cirrus-SF 301(define_insn "cirrus_floatsisf2" 302 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 303 (float:SF (match_operand:SI 1 "s_register_operand" "r"))) 304 (clobber (match_scratch:DF 2 "=v"))] 305 "TARGET_ARM && TARGET_CIRRUS" 306 "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" 307 [(set_attr "length" "8") 308 (set_attr "cirrus" "move")] 309) 310 311(define_insn "cirrus_floatsidf2" 312 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 313 (float:DF (match_operand:SI 1 "s_register_operand" "r"))) 314 (clobber (match_scratch:DF 2 "=v"))] 315 "TARGET_ARM && TARGET_CIRRUS" 316 "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" 317 [(set_attr "length" "8") 318 (set_attr "cirrus" "move")] 319) 320 321(define_insn "floatdisf2" 322 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 323 (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] 324 "TARGET_ARM && TARGET_CIRRUS" 325 "cfcvt64s%?\\t%V0, %V1" 326 [(set_attr "cirrus" "normal")]) 327 328(define_insn "floatdidf2" 329 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 330 (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] 331 "TARGET_ARM && TARGET_CIRRUS" 332 "cfcvt64d%?\\t%V0, %V1" 333 [(set_attr "cirrus" "normal")]) 334 335(define_insn "cirrus_truncsfsi2" 336 [(set (match_operand:SI 0 "s_register_operand" "=r") 337 (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) 338 (clobber (match_scratch:DF 2 "=v"))] 339 "TARGET_ARM && TARGET_CIRRUS" 340 "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" 341 [(set_attr "length" "8") 342 (set_attr "cirrus" "normal")] 343) 344 345(define_insn "cirrus_truncdfsi2" 346 [(set (match_operand:SI 0 "s_register_operand" "=r") 347 (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) 348 (clobber (match_scratch:DF 2 "=v"))] 349 "TARGET_ARM && TARGET_CIRRUS" 350 "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" 351 [(set_attr "length" "8")] 352) 353 354(define_insn "*cirrus_truncdfsf2" 355 [(set (match_operand:SF 0 "cirrus_fp_register" "=v") 356 (float_truncate:SF 357 (match_operand:DF 1 "cirrus_fp_register" "v")))] 358 "TARGET_ARM && TARGET_CIRRUS" 359 "cfcvtds%?\\t%V0, %V1" 360 [(set_attr "cirrus" "normal")] 361) 362 363(define_insn "*cirrus_extendsfdf2" 364 [(set (match_operand:DF 0 "cirrus_fp_register" "=v") 365 (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))] 366 "TARGET_ARM && TARGET_CIRRUS" 367 "cfcvtsd%?\\t%V0, %V1" 368 [(set_attr "cirrus" "normal")] 369) 370 371(define_insn "*cirrus_arm_movdi" 372 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") 373 (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,m,v,v"))] 374 "TARGET_ARM && TARGET_CIRRUS" 375 "* 376 { 377 switch (which_alternative) 378 { 379 case 0: 380 case 1: 381 case 2: 382 return (output_move_double (operands)); 383 384 case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\"; 385 case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\"; 386 387 case 5: return \"cfldr64%?\\t%V0, %1\"; 388 case 6: return \"cfstr64%?\\t%V1, %0\"; 389 390 /* Shifting by 0 will just copy %1 into %0. */ 391 case 7: return \"cfsh64%?\\t%V0, %V1, #0\"; 392 393 default: abort (); 394 } 395 }" 396 [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4") 397 (set_attr "type" " *,load,store2, *, *, load,store2, *") 398 (set_attr "pool_range" " *,1020, *, *, *, *, *, *") 399 (set_attr "neg_pool_range" " *,1012, *, *, *, *, *, *") 400 (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")] 401) 402 403;; Cirrus SI values have been outlawed. Look in arm.h for the comment 404;; on HARD_REGNO_MODE_OK. 405 406(define_insn "*cirrus_arm_movsi_insn" 407 [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,*v,r,*v,T,*v") 408 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,*v,T,*v,*v"))] 409 "TARGET_ARM && TARGET_CIRRUS && 0 410 && (register_operand (operands[0], SImode) 411 || register_operand (operands[1], SImode))" 412 "@ 413 mov%?\\t%0, %1 414 mvn%?\\t%0, #%B1 415 ldr%?\\t%0, %1 416 str%?\\t%1, %0 417 cfmv64lr%?\\t%Z0, %1 418 cfmvr64l%?\\t%0, %Z1 419 cfldr32%?\\t%V0, %1 420 cfstr32%?\\t%V1, %0 421 cfsh32%?\\t%V0, %V1, #0" 422 [(set_attr "type" "*, *, load,store1, *, *, load,store1, *") 423 (set_attr "pool_range" "*, *, 4096, *, *, *, 1024, *, *") 424 (set_attr "neg_pool_range" "*, *, 4084, *, *, *, 1012, *, *") 425 (set_attr "cirrus" "not,not, not, not,move,normal,normal,normal,normal")] 426) 427 428(define_insn "*cirrus_movsf_hard_insn" 429 [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") 430 (match_operand:SF 1 "general_operand" "v,m,r,v,v,r,mE,r"))] 431 "TARGET_ARM && TARGET_CIRRUS 432 && (GET_CODE (operands[0]) != MEM 433 || register_operand (operands[1], SFmode))" 434 "@ 435 cfcpys%?\\t%V0, %V1 436 cfldrs%?\\t%V0, %1 437 cfmvsr%?\\t%V0, %1 438 cfmvrs%?\\t%0, %V1 439 cfstrs%?\\t%V1, %0 440 mov%?\\t%0, %1 441 ldr%?\\t%0, %1\\t%@ float 442 str%?\\t%1, %0\\t%@ float" 443 [(set_attr "length" " *, *, *, *, *, 4, 4, 4") 444 (set_attr "type" " *, load, *, *,store1, *,load,store1") 445 (set_attr "pool_range" " *, *, *, *, *, *,4096, *") 446 (set_attr "neg_pool_range" " *, *, *, *, *, *,4084, *") 447 (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] 448) 449 450(define_insn "*cirrus_movdf_hard_insn" 451 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") 452 (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,m,r,v,v"))] 453 "TARGET_ARM 454 && TARGET_CIRRUS 455 && (GET_CODE (operands[0]) != MEM 456 || register_operand (operands[1], DFmode))" 457 "* 458 { 459 switch (which_alternative) 460 { 461 case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; 462 case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; 463 case 2: case 3: case 4: return output_move_double (operands); 464 case 5: return \"cfcpyd%?\\t%V0, %V1\"; 465 case 6: return \"cfldrd%?\\t%V0, %1\"; 466 case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; 467 case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; 468 case 9: return \"cfstrd%?\\t%V1, %0\"; 469 default: abort (); 470 } 471 }" 472 [(set_attr "type" "load,store2, *,store2,load, *, load, *, *,store2") 473 (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") 474 (set_attr "pool_range" " *, *, *, *, 252, *, *, *, *, *") 475 (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *, *, *") 476 (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] 477) 478 479