ChangeLog.gcc43 revision 255107
1101172Srwatson2007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r23479) 2101172Srwatson 3101172Srwatson PR preprocessor/23479 4101172Srwatson * doc/extend.texi: Document the 0b-prefixed binary integer 5101172Srwatson constant extension. 6101172Srwatson 7101172Srwatson2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 8101172Srwatson 9101172Srwatson * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 10 'AMD Family 10 core'. 11 122007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 13 14 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 15 and athlon64-sse3 as improved versions of k8, opteron and athlon64 16 with SSE3 instruction set support. 17 * doc/invoke.texi: Likewise. 18 192007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 20 21 * config/i386/i386.c (override_options): Tuning 32-byte loop 22 alignment for amdfam10 architecture. Increasing the max loop 23 alignment to 24 bytes. 24 252007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 26 27 PR tree-optimization/24689 28 PR tree-optimization/31307 29 * fold-const.c (operand_equal_p): Compare INTEGER_CST array 30 indices by value. 31 * gimplify.c (canonicalize_addr_expr): To be consistent with 32 gimplify_compound_lval only set operands two and three of 33 ARRAY_REFs if they are not gimple_min_invariant. This makes 34 it never at this place. 35 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 36 372007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 38 39 * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 40 412007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 42 43 * config.gcc: Accept barcelona as a variant of amdfam10. 44 * config/i386/i386.c (override_options): Likewise. 45 * doc/invoke.texi: Likewise. 46 472007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 48 49 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 50 (bit_SSE4a): New. 51 522007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 53 54 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 55 conditional to __SSE2__. 56 (Entries below should have been added to first ChangeLog 57 entry for amdfam10 dated 2007-02-05) 58 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 59 defined. 60 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 61 defined. 62 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 63 defined. 64 652007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 66 67 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 68 692007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 70 71 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 72 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 73 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 74 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 75 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 76 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 77 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 78 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 79 802007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 81 82 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 83 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 84 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 85 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 86 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 87 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 88 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 89 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 90 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 91 umuldi3_highpart_rex64, umulsi3_highpart_insn, 92 umulsi3_highpart_zext, smuldi3_highpart_rex64, 93 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 94 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 95 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 96 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 97 sqrtextenddfxf2_i387): Added amdfam10_decode. 98 99 * config/i386/athlon.md (athlon_idirect_amdfam10, 100 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 101 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 102 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 103 athlon_ivector_store_amdfam10): New define_insn_reservation. 104 (athlon_idirect_loadmov, athlon_idirect_movstore): Added 105 amdfam10. 106 1072007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 108 109 * config/i386/athlon.md (athlon_call_amdfam10, 110 athlon_pop_amdfam10, athlon_lea_amdfam10): New 111 define_insn_reservation. 112 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 113 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 114 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 115 1162007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 117 118 * config/i386/athlon.md (athlon_sseld_amdfam10, 119 athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 120 athlon_mmxssest_short_amdfam10): New define_insn_reservation. 121 1222007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 123 124 * config/i386/athlon.md (athlon_sseins_amdfam10): New 125 define_insn_reservation. 126 * config/i386/i386.md (sseins): Added sseins to define_attr type 127 and define_attr unit. 128 * config/i386/sse.md: Set type attribute to sseins for insertq 129 and insertqi. 130 1312007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 132 133 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 134 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 135 ssecomi_load_amdfam10, ssecomi_amdfam10, 136 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 137 define_insn_reservation. 138 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 139 1402007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 141 142 * config/i386/athlon.md (cvtss2sd_load_amdfam10, 143 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 144 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 145 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 146 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 147 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 148 define_insn_reservation. 149 150 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 151 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 152 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 153 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 154 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 155 1562007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 157 158 * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 159 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 160 athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 161 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 162 athlon_ssemul_load_k8): Added amdfam10. 163 1642007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 165 166 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 167 (x86_sse_unaligned_move_optimal): New variable. 168 169 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 170 m_AMDFAM10. 171 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 172 for unaligned vector SSE double/single precision loads for AMDFAM10. 173 1742007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 175 176 * config/i386/i386.h (TARGET_AMDFAM10): New macro. 177 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 178 Define TARGET_CPU_DEFAULT_amdfam10. 179 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 180 (processor_type): Add PROCESSOR_AMDFAM10. 181 182 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 183 processor_type in config/i386/i386.h. 184 Enable imul peepholes for TARGET_AMDFAM10. 185 186 * config.gcc: Add support for --with-cpu option for amdfam10. 187 188 * config/i386/i386.c (amdfam10_cost): New variable. 189 (m_AMDFAM10): New macro. 190 (m_ATHLON_K8_AMDFAM10): New macro. 191 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 192 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 193 x86_promote_QImode, x86_integer_DFmode_moves, 194 x86_partial_reg_dependency, x86_memory_mismatch_stall, 195 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 196 x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 197 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 198 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 199 Enable/disable for amdfam10. 200 (override_options): Add amdfam10_cost to processor_target_table. 201 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 202 processor_alias_table. 203 (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 204 (ix86_adjust_cost): Add code for amdfam10. 205 2062007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 207 208 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 209 instruction set feature flag. Add new (-mpopcnt) flag for popcnt 210 instruction. Add new SSE4A (-msse4a) instruction set feature flag. 211 * config/i386/i386.h: Add builtin definition for SSE4A. 212 * config/i386/i386.md: Add support for ABM instructions 213 (popcnt and lzcnt). 214 * config/i386/sse.md: Add support for SSE4A instructions 215 (movntss, movntsd, extrq, insertq). 216 * config/i386/i386.c: Add support for ABM and SSE4A builtins. 217 Add -march=amdfam10 flag. 218 * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 219 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 220 and amdfam10. 221 * doc/extend.texi: Add documentation for SSE4A builtins. 222 2232007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 224 225 * config/i386/i386.h (x86_cmpxchg16b): Remove const. 226 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 227 * config/i386/i386.c (x86_cmpxchg16b): Remove const. 228 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 229 for CPUs that have PTA_CX16 set. 230 2312007-01-17 Eric Christopher <echristo@apple.com> (r120846) 232 233 * config.gcc: Support core2 processor. 234 2352006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 236 237 PR target/30040 238 * config/i386/driver-i386.c (bit_SSSE3): New. 239 2402006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 241 242 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 243 and m_GENERIC64. 244 2452006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 246 247 * doc/invoke.texi (core2): Add item. 248 249 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 250 macros. 251 (TARGET_CPU_CPP_BUILTINS): Add code for core2. 252 (TARGET_CPU_DEFAULT_generic): Change value. 253 (TARGET_CPU_DEFAULT_NAMES): Add core2. 254 (processor_type): Add new constant PROCESSOR_CORE2. 255 256 * config/i386/i386.md (cpu): Add core2. 257 258 * config/i386/i386.c (core2_cost): New initialized variable. 259 (m_CORE2): New macro. 260 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 261 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 262 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 263 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 264 x86_partial_reg_dependency, x86_memory_mismatch_stall, 265 x86_accumulate_outgoing_args, x86_prologue_using_move, 266 x86_epilogue_using_move, x86_arch_always_fancy_math_387, 267 x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 268 x86_use_incdec, x86_four_jump_limit, x86_schedule, 269 x86_pad_returns): Add m_CORE2. 270 (override_options): Add entries for Core2. 271 (ix86_issue_rate): Add case for Core2. 272 2732006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 274 275 * config/i386/i386.h (TARGET_GEODE): 276 (TARGET_CPU_CPP_BUILTINS): Add code for geode. 277 (TARGET_CPU_DEFAULT_geode): New macro. 278 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 279 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 280 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 281 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 282 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 283 the macro values. 284 (TARGET_CPU_DEFAULT_NAMES): Add geode. 285 (processor_type): Add PROCESSOR_GEODE. 286 287 * config/i386/i386.md: Include geode.md. 288 (cpu): Add geode. 289 290 * config/i386/i386.c (geode_cost): New initialized global 291 variable. 292 (m_GEODE, m_K6_GEODE): New macros. 293 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 294 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 295 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 296 x86_schedule): Use m_K6_GEODE instead of m_K6. 297 (x86_movx, x86_cmove): Set up m_GEODE. 298 (x86_integer_DFmode_moves): Clear m_GEODE. 299 (processor_target_table): Add entry for geode. 300 (processor_alias_table): Ditto. 301 302 * config/i386/geode.md: New file. 303 304 * doc/invoke.texi: Add entry about geode processor. 305 3062006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 307 308 PR middle-end/28796 309 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 310 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 311 for deciding optimizations in consistency with fold-const.c 312 (fold_builtin_unordered_cmp): Likewise. 313 3142006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 315 316 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 317 (x86_64-*-*): Likewise. 318 319 * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 320 (override_options): Check SSSE3. 321 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 322 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 323 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 324 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 325 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 326 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 327 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 328 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 329 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 330 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 331 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 332 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 333 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 334 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 335 IX86_BUILTIN_PABSD128. 336 (bdesc_2arg): Add SSSE3. 337 (bdesc_1arg): Likewise. 338 (ix86_init_mmx_sse_builtins): Support SSSE3. 339 (ix86_expand_builtin): Likewise. 340 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 341 342 * config/i386/i386.md (UNSPEC_PSHUFB): New. 343 (UNSPEC_PSIGN): Likewise. 344 (UNSPEC_PALIGNR): Likewise. 345 Include mmx.md before sse.md. 346 347 * config/i386/i386.opt: Add -mssse3. 348 349 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 350 (ssse3_phaddwv4hi3): Likewise. 351 (ssse3_phadddv4si3): Likewise. 352 (ssse3_phadddv2si3): Likewise. 353 (ssse3_phaddswv8hi3): Likewise. 354 (ssse3_phaddswv4hi3): Likewise. 355 (ssse3_phsubwv8hi3): Likewise. 356 (ssse3_phsubwv4hi3): Likewise. 357 (ssse3_phsubdv4si3): Likewise. 358 (ssse3_phsubdv2si3): Likewise. 359 (ssse3_phsubswv8hi3): Likewise. 360 (ssse3_phsubswv4hi3): Likewise. 361 (ssse3_pmaddubswv8hi3): Likewise. 362 (ssse3_pmaddubswv4hi3): Likewise. 363 (ssse3_pmulhrswv8hi3): Likewise. 364 (ssse3_pmulhrswv4hi3): Likewise. 365 (ssse3_pshufbv16qi3): Likewise. 366 (ssse3_pshufbv8qi3): Likewise. 367 (ssse3_psign<mode>3): Likewise. 368 (ssse3_psign<mode>3): Likewise. 369 (ssse3_palignrti): Likewise. 370 (ssse3_palignrdi): Likewise. 371 (abs<mode>2): Likewise. 372 (abs<mode>2): Likewise. 373 374 * config/i386/tmmintrin.h: New file. 375 376 * doc/extend.texi: Document SSSE3 built-in functions. 377 378 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 379 3802006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 381 382 * config/i386/tmmintrin.h: Remove the duplicated content. 383 3842006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 385 386 PR tree-optimization/3511 387 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 388 got new invariant arguments during PHI translation. 389 3902006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 391 392 * builtins.c (fold_builtin_classify): Fix typo. 393 394