ChangeLog.gcc43 revision 259268
1259268Spfg2007-08-08 Andrew Haley <aph@redhat.com> (r128087) 2255107Spfg 3259268Spfg * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New. 4259268Spfg * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New. 5259268Spfg * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New. 6259268Spfg 7259268Spfg2007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346) 8259268Spfg 9255107Spfg PR preprocessor/23479 10255107Spfg * doc/extend.texi: Document the 0b-prefixed binary integer 11255107Spfg constant extension. 12255107Spfg 13259268Spfg2007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037) 14259268Spfg 15259268Spfg * postreload-gcse.c (reg_changed_after_insn_p): New function. 16259268Spfg (oprs_unchanged_p): Use it to check all registers in a REG. 17259268Spfg (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE. 18259268Spfg (reg_set_between_after_reload_p): Delete. 19259268Spfg (reg_used_between_after_reload_p): Likewise. 20259268Spfg (reg_set_or_used_since_bb_start): Likewise. 21259268Spfg (eliminate_partially_redundant_load): Use reg_changed_after_insn_p 22259268Spfg and reg_used_between_p instead of reg_set_or_used_since_bb_start. 23259268Spfg Use reg_set_between_p instead of reg_set_between_after_reload_p. 24259268Spfg * rtlanal.c (reg_set_p): Check whether REG overlaps 25259268Spfg regs_invalidated_by_call, rather than just checking the 26259268Spfg membership of REGNO (REG). 27259268Spfg 28259268Spfg2007-05-03 Ian Lance Taylor <iant@google.com> (r124381) 29259268Spfg 30259268Spfg * config/rs6000/rs6000.c (rs6000_override_options): Don't set 31259268Spfg MASK_PPC_GFXOPT for 8540 or 8548. 32259268Spfg 33251212Spfg2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 34251212Spfg 35251212Spfg * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 36251212Spfg 'AMD Family 10 core'. 37251212Spfg 38221282Smm2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 39221282Smm 40221282Smm * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 41221282Smm and athlon64-sse3 as improved versions of k8, opteron and athlon64 42221282Smm with SSE3 instruction set support. 43221282Smm * doc/invoke.texi: Likewise. 44221282Smm 45251212Spfg2007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 46251212Spfg 47251212Spfg * config/i386/i386.c (override_options): Tuning 32-byte loop 48251212Spfg alignment for amdfam10 architecture. Increasing the max loop 49251212Spfg alignment to 24 bytes. 50251212Spfg 51259268Spfg2007-04-16 Lawrence Crowl <crowl@google.com> 52259268Spfg 53259268Spfg * doc/invoke.texi (Debugging Options): Add documentation for the 54259268Spfg -femit-struct-debug options -femit-struct-debug-baseonly, 55259268Spfg -femit-struct-debug-reduced, and 56259268Spfg -femit-struct-debug-detailed[=...]. 57259268Spfg 58259268Spfg * c-opts.c (c_common_handle_option): Add 59259268Spfg OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced, 60259268Spfg and OPT_femit_struct_debug_detailed_. 61259268Spfg * c.opt: Add specifications for 62259268Spfg -femit-struct-debug-baseonly, -femit-struct-debug-reduced, 63259268Spfg and -femit-struct-debug-detailed[=...]. 64259268Spfg * opts.c (set_struct_debug_option): Parse the 65259268Spfg -femit-struct-debug-... options. 66259268Spfg * opts.c (matches_main_base, main_input_basename, 67259268Spfg main_input_baselength, base_of_path, matches_main_base): Add 68259268Spfg variables and functions to compare header base name to compilation 69259268Spfg unit base name. 70259268Spfg * opts.c (should_emit_struct_debug): Add to determine to emit a 71259268Spfg structure based on the option. 72259268Spfg (dump_struct_debug) Also disabled function to debug this 73259268Spfg function. 74259268Spfg * opts.c (handle_options): Save the base name of the 75259268Spfg compilation unit. 76259268Spfg 77259268Spfg * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define. 78259268Spfg (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add. 79259268Spfg This hook indicates if a type is generic. Set it by default 80259268Spfg to "never generic". 81259268Spfg * langhooks.h (struct lang_hooks_for_types): Add a new hook 82259268Spfg to determine if a struct type is generic or not. 83259268Spfg * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook. 84259268Spfg * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook. 85259268Spfg * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook 86259268Spfg with live C++ hook. 87259268Spfg 88259268Spfg * flags.h (enum debug_info_usage): Add an enumeration to describe 89259268Spfg a program's use of a structure type. 90259268Spfg * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter 91259268Spfg to indicate the program's usage of the type. Filter structs based 92259268Spfg on the -femit-struct-debug-... specification. 93259268Spfg (gen_type_die): Split into two routines, gen_type_die and 94259268Spfg gen_type_die_with_usage. gen_type_die is now a wrapper 95259268Spfg that assumes direct usage. 96259268Spfg (gen_type_die_with_usage): Replace calls to gen_type_die 97259268Spfg with gen_type_die_with_usage adding the program usage of 98259268Spfg the referenced type. 99259268Spfg (dwarf2out_imported_module_or_decl): Suppress struct debug 100259268Spfg information using should_emit_struct_debug when appropriate. 101259268Spfg 102237406Spfg2007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 103237406Spfg 104237406Spfg PR tree-optimization/24689 105237406Spfg PR tree-optimization/31307 106237406Spfg * fold-const.c (operand_equal_p): Compare INTEGER_CST array 107237406Spfg indices by value. 108237406Spfg * gimplify.c (canonicalize_addr_expr): To be consistent with 109237406Spfg gimplify_compound_lval only set operands two and three of 110237406Spfg ARRAY_REFs if they are not gimple_min_invariant. This makes 111237406Spfg it never at this place. 112237406Spfg * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 113237406Spfg 114221282Smm2007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 115221282Smm 116221282Smm * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 117221282Smm 118251212Spfg2007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 119251212Spfg 120251212Spfg * config.gcc: Accept barcelona as a variant of amdfam10. 121251212Spfg * config/i386/i386.c (override_options): Likewise. 122251212Spfg * doc/invoke.texi: Likewise. 123251212Spfg 124259268Spfg2007-03-12 Seongbae Park <seongbae.park@gmail.com> 125259268Spfg 126259268Spfg * c-decl.c (warn_variable_length_array): New function. 127259268Spfg Refactored from grokdeclarator to handle warn_vla 128259268Spfg and handle unnamed array case. 129259268Spfg (grokdeclarator): Refactored VLA warning case. 130259268Spfg * c.opt (Wvla): New flag. 131259268Spfg 132259268Spfg2007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 133259268Spfg 134259268Spfg * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 135259268Spfg the *_DIV_EXPR codes correctly with overflow infinities. 136259268Spfg 137251212Spfg2007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 138251212Spfg 139251212Spfg * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 140251212Spfg (bit_SSE4a): New. 141251212Spfg 142221282Smm2007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 143221282Smm 144221282Smm * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 145221282Smm conditional to __SSE2__. 146221282Smm (Entries below should have been added to first ChangeLog 147221282Smm entry for amdfam10 dated 2007-02-05) 148221282Smm * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 149221282Smm defined. 150221282Smm * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 151221282Smm defined. 152221282Smm * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 153221282Smm defined. 154221282Smm 155221282Smm2007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 156221282Smm 157221282Smm * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 158221282Smm 159251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 160251212Spfg 161251212Spfg * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 162251212Spfg athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 163251212Spfg athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 164251212Spfg athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 165251212Spfg athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 166251212Spfg athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 167251212Spfg athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 168251212Spfg athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 169251212Spfg 170251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 171251212Spfg 172251212Spfg * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 173251212Spfg cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 174251212Spfg swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 175251212Spfg fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 176251212Spfg x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 177251212Spfg floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 178251212Spfg floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 179251212Spfg mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 180251212Spfg umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 181251212Spfg umuldi3_highpart_rex64, umulsi3_highpart_insn, 182251212Spfg umulsi3_highpart_zext, smuldi3_highpart_rex64, 183251212Spfg smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 184251212Spfg x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 185251212Spfg sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 186251212Spfg sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 187251212Spfg sqrtextenddfxf2_i387): Added amdfam10_decode. 188251212Spfg 189251212Spfg * config/i386/athlon.md (athlon_idirect_amdfam10, 190251212Spfg athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 191251212Spfg athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 192251212Spfg athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 193251212Spfg athlon_ivector_store_amdfam10): New define_insn_reservation. 194251212Spfg (athlon_idirect_loadmov, athlon_idirect_movstore): Added 195251212Spfg amdfam10. 196251212Spfg 197251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 198251212Spfg 199251212Spfg * config/i386/athlon.md (athlon_call_amdfam10, 200251212Spfg athlon_pop_amdfam10, athlon_lea_amdfam10): New 201251212Spfg define_insn_reservation. 202251212Spfg (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 203251212Spfg athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 204251212Spfg athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 205251212Spfg 206251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 207251212Spfg 208251212Spfg * config/i386/athlon.md (athlon_sseld_amdfam10, 209251212Spfg athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 210251212Spfg athlon_mmxssest_short_amdfam10): New define_insn_reservation. 211251212Spfg 212251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 213251212Spfg 214251212Spfg * config/i386/athlon.md (athlon_sseins_amdfam10): New 215251212Spfg define_insn_reservation. 216251212Spfg * config/i386/i386.md (sseins): Added sseins to define_attr type 217251212Spfg and define_attr unit. 218251212Spfg * config/i386/sse.md: Set type attribute to sseins for insertq 219251212Spfg and insertqi. 220251212Spfg 221251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 222251212Spfg 223251212Spfg * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 224251212Spfg ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 225251212Spfg ssecomi_load_amdfam10, ssecomi_amdfam10, 226251212Spfg sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 227251212Spfg define_insn_reservation. 228251212Spfg (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 229251212Spfg 230251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 231251212Spfg 232251212Spfg * config/i386/athlon.md (cvtss2sd_load_amdfam10, 233251212Spfg cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 234251212Spfg cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 235251212Spfg cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 236251212Spfg cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 237251212Spfg cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 238251212Spfg define_insn_reservation. 239251212Spfg 240251212Spfg * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 241251212Spfg cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 242251212Spfg cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 243251212Spfg cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 244251212Spfg cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 245251212Spfg 246251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 247251212Spfg 248251212Spfg * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 249251212Spfg athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 250251212Spfg athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 251251212Spfg (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 252251212Spfg athlon_ssemul_load_k8): Added amdfam10. 253251212Spfg 254251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 255251212Spfg 256251212Spfg * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 257251212Spfg (x86_sse_unaligned_move_optimal): New variable. 258251212Spfg 259251212Spfg * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 260251212Spfg m_AMDFAM10. 261251212Spfg (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 262251212Spfg for unaligned vector SSE double/single precision loads for AMDFAM10. 263251212Spfg 264251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 265251212Spfg 266251212Spfg * config/i386/i386.h (TARGET_AMDFAM10): New macro. 267251212Spfg (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 268251212Spfg Define TARGET_CPU_DEFAULT_amdfam10. 269251212Spfg (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 270251212Spfg (processor_type): Add PROCESSOR_AMDFAM10. 271251212Spfg 272251212Spfg * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 273251212Spfg processor_type in config/i386/i386.h. 274251212Spfg Enable imul peepholes for TARGET_AMDFAM10. 275251212Spfg 276251212Spfg * config.gcc: Add support for --with-cpu option for amdfam10. 277251212Spfg 278251212Spfg * config/i386/i386.c (amdfam10_cost): New variable. 279251212Spfg (m_AMDFAM10): New macro. 280251212Spfg (m_ATHLON_K8_AMDFAM10): New macro. 281251212Spfg (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 282251212Spfg x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 283251212Spfg x86_promote_QImode, x86_integer_DFmode_moves, 284251212Spfg x86_partial_reg_dependency, x86_memory_mismatch_stall, 285251212Spfg x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 286251212Spfg x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 287251212Spfg x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 288251212Spfg x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 289251212Spfg Enable/disable for amdfam10. 290251212Spfg (override_options): Add amdfam10_cost to processor_target_table. 291251212Spfg Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 292251212Spfg processor_alias_table. 293251212Spfg (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 294251212Spfg (ix86_adjust_cost): Add code for amdfam10. 295251212Spfg 296251212Spfg2007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 297251212Spfg 298251212Spfg * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 299251212Spfg instruction set feature flag. Add new (-mpopcnt) flag for popcnt 300251212Spfg instruction. Add new SSE4A (-msse4a) instruction set feature flag. 301251212Spfg * config/i386/i386.h: Add builtin definition for SSE4A. 302251212Spfg * config/i386/i386.md: Add support for ABM instructions 303251212Spfg (popcnt and lzcnt). 304251212Spfg * config/i386/sse.md: Add support for SSE4A instructions 305251212Spfg (movntss, movntsd, extrq, insertq). 306251212Spfg * config/i386/i386.c: Add support for ABM and SSE4A builtins. 307251212Spfg Add -march=amdfam10 flag. 308251212Spfg * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 309251212Spfg * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 310251212Spfg and amdfam10. 311251212Spfg * doc/extend.texi: Add documentation for SSE4A builtins. 312251212Spfg 313251212Spfg2007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 314251212Spfg 315251212Spfg * config/i386/i386.h (x86_cmpxchg16b): Remove const. 316251212Spfg (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 317251212Spfg * config/i386/i386.c (x86_cmpxchg16b): Remove const. 318251212Spfg (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 319251212Spfg for CPUs that have PTA_CX16 set. 320251212Spfg 321221282Smm2007-01-17 Eric Christopher <echristo@apple.com> (r120846) 322221282Smm 323221282Smm * config.gcc: Support core2 processor. 324221282Smm 325259268Spfg2006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 326259268Spfg 327259268Spfg PR c++/19564 328259268Spfg PR c++/19756 329259268Spfg * c-typeck.c (parser_build_binary_op): Move parentheses warnings 330259268Spfg to warn_about_parentheses in c-common.c. 331259268Spfg * c-common.c (warn_about_parentheses): New function. 332259268Spfg * c-common.h (warn_about_parentheses): Declare. 333259268Spfg * doc/invoke.texi (Warning Options): Update -Wparentheses 334259268Spfg description. 335259268Spfg 336221282Smm2006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 337221282Smm 338221282Smm PR target/30040 339221282Smm * config/i386/driver-i386.c (bit_SSSE3): New. 340221282Smm 341251212Spfg2006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 342251212Spfg 343251212Spfg * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 344251212Spfg and m_GENERIC64. 345251212Spfg 346221282Smm2006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 347221282Smm 348221282Smm * doc/invoke.texi (core2): Add item. 349221282Smm 350221282Smm * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 351221282Smm macros. 352221282Smm (TARGET_CPU_CPP_BUILTINS): Add code for core2. 353221282Smm (TARGET_CPU_DEFAULT_generic): Change value. 354221282Smm (TARGET_CPU_DEFAULT_NAMES): Add core2. 355221282Smm (processor_type): Add new constant PROCESSOR_CORE2. 356221282Smm 357221282Smm * config/i386/i386.md (cpu): Add core2. 358221282Smm 359221282Smm * config/i386/i386.c (core2_cost): New initialized variable. 360221282Smm (m_CORE2): New macro. 361221282Smm (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 362221282Smm x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 363221282Smm x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 364221282Smm x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 365221282Smm x86_partial_reg_dependency, x86_memory_mismatch_stall, 366221282Smm x86_accumulate_outgoing_args, x86_prologue_using_move, 367221282Smm x86_epilogue_using_move, x86_arch_always_fancy_math_387, 368221282Smm x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 369221282Smm x86_use_incdec, x86_four_jump_limit, x86_schedule, 370221282Smm x86_pad_returns): Add m_CORE2. 371221282Smm (override_options): Add entries for Core2. 372221282Smm (ix86_issue_rate): Add case for Core2. 373221282Smm 374259268Spfg2006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356) 375259268Spfg 376259268Spfg * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on 377259268Spfg inline static functions in c99 mode. 378259268Spfg 379259268Spfg PR 16622 380259268Spfg * doc/extend.texi (Inline): Update. 381259268Spfg * c-tree.h (struct language_function): Remove field 'extern_inline'. 382259268Spfg * c-decl.c (current_extern_inline): Delete. 383259268Spfg (pop_scope): Adjust test for an undefined nested function. 384259268Spfg Add warning about undeclared inline function. 385259268Spfg (diagnose_mismatched_decls): Update comments. Disallow overriding 386259268Spfg of inline functions in a translation unit in C99. Allow inline 387259268Spfg declarations in C99 at any time. 388259268Spfg (merge_decls): Boolize variables. Handle C99 'extern inline' 389259268Spfg semantics. 390259268Spfg (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle 391259268Spfg C99 inline semantics. 392259268Spfg (start_function): Don't clear current_extern_inline. Don't set 393259268Spfg DECL_EXTERNAL. 394259268Spfg (c_push_function_context): Don't push current_extern_inline. 395259268Spfg (c_pop_function_context): Don't restore current_extern_inline. 396259268Spfg 397259268Spfg PR 11377 398259268Spfg * c-typeck.c (build_external_ref): Warn about static variables 399259268Spfg used in extern inline functions. 400259268Spfg * c-decl.c (start_decl): Warn about static variables declared 401259268Spfg in extern inline functions. 402259268Spfg 403221282Smm2006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 404221282Smm 405221282Smm * config/i386/i386.h (TARGET_GEODE): 406221282Smm (TARGET_CPU_CPP_BUILTINS): Add code for geode. 407221282Smm (TARGET_CPU_DEFAULT_geode): New macro. 408221282Smm (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 409221282Smm TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 410221282Smm TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 411221282Smm TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 412221282Smm TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 413221282Smm the macro values. 414221282Smm (TARGET_CPU_DEFAULT_NAMES): Add geode. 415221282Smm (processor_type): Add PROCESSOR_GEODE. 416221282Smm 417221282Smm * config/i386/i386.md: Include geode.md. 418221282Smm (cpu): Add geode. 419221282Smm 420221282Smm * config/i386/i386.c (geode_cost): New initialized global 421221282Smm variable. 422221282Smm (m_GEODE, m_K6_GEODE): New macros. 423221282Smm (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 424221282Smm x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 425221282Smm x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 426221282Smm x86_schedule): Use m_K6_GEODE instead of m_K6. 427221282Smm (x86_movx, x86_cmove): Set up m_GEODE. 428221282Smm (x86_integer_DFmode_moves): Clear m_GEODE. 429221282Smm (processor_target_table): Add entry for geode. 430221282Smm (processor_alias_table): Ditto. 431221282Smm 432221282Smm * config/i386/geode.md: New file. 433221282Smm 434221282Smm * doc/invoke.texi: Add entry about geode processor. 435237021Spfg 436237406Spfg2006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 437228756Spfg 438228756Spfg PR middle-end/28796 439228756Spfg * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 440228756Spfg and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 441228756Spfg for deciding optimizations in consistency with fold-const.c 442228756Spfg (fold_builtin_unordered_cmp): Likewise. 443228756Spfg 444221282Smm2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 445221282Smm 446221282Smm * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 447221282Smm (x86_64-*-*): Likewise. 448221282Smm 449221282Smm * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 450221282Smm (override_options): Check SSSE3. 451221282Smm (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 452221282Smm IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 453221282Smm IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 454221282Smm IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 455221282Smm IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 456221282Smm IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 457221282Smm IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 458221282Smm IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 459221282Smm IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 460221282Smm IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 461221282Smm IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 462221282Smm IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 463221282Smm IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 464221282Smm IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 465221282Smm IX86_BUILTIN_PABSD128. 466221282Smm (bdesc_2arg): Add SSSE3. 467221282Smm (bdesc_1arg): Likewise. 468221282Smm (ix86_init_mmx_sse_builtins): Support SSSE3. 469221282Smm (ix86_expand_builtin): Likewise. 470221282Smm * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 471221282Smm 472221282Smm * config/i386/i386.md (UNSPEC_PSHUFB): New. 473221282Smm (UNSPEC_PSIGN): Likewise. 474221282Smm (UNSPEC_PALIGNR): Likewise. 475221282Smm Include mmx.md before sse.md. 476221282Smm 477221282Smm * config/i386/i386.opt: Add -mssse3. 478221282Smm 479221282Smm * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 480221282Smm (ssse3_phaddwv4hi3): Likewise. 481221282Smm (ssse3_phadddv4si3): Likewise. 482221282Smm (ssse3_phadddv2si3): Likewise. 483221282Smm (ssse3_phaddswv8hi3): Likewise. 484221282Smm (ssse3_phaddswv4hi3): Likewise. 485221282Smm (ssse3_phsubwv8hi3): Likewise. 486221282Smm (ssse3_phsubwv4hi3): Likewise. 487221282Smm (ssse3_phsubdv4si3): Likewise. 488221282Smm (ssse3_phsubdv2si3): Likewise. 489221282Smm (ssse3_phsubswv8hi3): Likewise. 490221282Smm (ssse3_phsubswv4hi3): Likewise. 491221282Smm (ssse3_pmaddubswv8hi3): Likewise. 492221282Smm (ssse3_pmaddubswv4hi3): Likewise. 493221282Smm (ssse3_pmulhrswv8hi3): Likewise. 494221282Smm (ssse3_pmulhrswv4hi3): Likewise. 495221282Smm (ssse3_pshufbv16qi3): Likewise. 496221282Smm (ssse3_pshufbv8qi3): Likewise. 497221282Smm (ssse3_psign<mode>3): Likewise. 498221282Smm (ssse3_psign<mode>3): Likewise. 499221282Smm (ssse3_palignrti): Likewise. 500221282Smm (ssse3_palignrdi): Likewise. 501221282Smm (abs<mode>2): Likewise. 502221282Smm (abs<mode>2): Likewise. 503221282Smm 504221282Smm * config/i386/tmmintrin.h: New file. 505221282Smm 506221282Smm * doc/extend.texi: Document SSSE3 built-in functions. 507221282Smm 508221282Smm * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 509233923Spfg 510251212Spfg2006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 511250550Spfg 512250550Spfg * config/i386/tmmintrin.h: Remove the duplicated content. 513250550Spfg 514237406Spfg2006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 515233923Spfg 516237406Spfg PR tree-optimization/3511 517237406Spfg * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 518237406Spfg got new invariant arguments during PHI translation. 519237406Spfg 520237406Spfg2006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 521237406Spfg 522233923Spfg * builtins.c (fold_builtin_classify): Fix typo. 523233923Spfg 524