199461Sobrien/* s390-opc.c -- S390 opcode list 2218822Sdim Copyright 2000, 2001, 2003 Free Software Foundation, Inc. 399461Sobrien Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). 499461Sobrien 599461Sobrien This file is part of GDB, GAS, and the GNU binutils. 699461Sobrien 799461Sobrien This program is free software; you can redistribute it and/or modify 899461Sobrien it under the terms of the GNU General Public License as published by 999461Sobrien the Free Software Foundation; either version 2 of the License, or 1099461Sobrien (at your option) any later version. 1199461Sobrien 1299461Sobrien This program is distributed in the hope that it will be useful, 1399461Sobrien but WITHOUT ANY WARRANTY; without even the implied warranty of 1499461Sobrien MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1599461Sobrien GNU General Public License for more details. 1699461Sobrien 1799461Sobrien You should have received a copy of the GNU General Public License 1899461Sobrien along with this program; if not, write to the Free Software 19218822Sdim Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 20218822Sdim 02110-1301, USA. */ 2199461Sobrien 2299461Sobrien#include <stdio.h> 2399461Sobrien#include "ansidecl.h" 2499461Sobrien#include "opcode/s390.h" 2599461Sobrien 2699461Sobrien/* This file holds the S390 opcode table. The opcode table 2799461Sobrien includes almost all of the extended instruction mnemonics. This 2899461Sobrien permits the disassembler to use them, and simplifies the assembler 2999461Sobrien logic, at the cost of increasing the table size. The table is 3099461Sobrien strictly constant data, so the compiler should be able to put it in 3199461Sobrien the .text section. 3299461Sobrien 3399461Sobrien This file also holds the operand table. All knowledge about 3499461Sobrien inserting operands into instructions and vice-versa is kept in this 3599461Sobrien file. */ 3699461Sobrien 3799461Sobrien/* The operands table. 3899461Sobrien The fields are bits, shift, insert, extract, flags. */ 3999461Sobrien 4099461Sobrienconst struct s390_operand s390_operands[] = 4199461Sobrien{ 4299461Sobrien#define UNUSED 0 4399461Sobrien { 0, 0, 0 }, /* Indicates the end of the operand list */ 4499461Sobrien 4599461Sobrien#define R_8 1 /* GPR starting at position 8 */ 4699461Sobrien { 4, 8, S390_OPERAND_GPR }, 4799461Sobrien#define R_12 2 /* GPR starting at position 12 */ 4899461Sobrien { 4, 12, S390_OPERAND_GPR }, 4999461Sobrien#define R_16 3 /* GPR starting at position 16 */ 5099461Sobrien { 4, 16, S390_OPERAND_GPR }, 5199461Sobrien#define R_20 4 /* GPR starting at position 20 */ 5299461Sobrien { 4, 20, S390_OPERAND_GPR }, 5399461Sobrien#define R_24 5 /* GPR starting at position 24 */ 5499461Sobrien { 4, 24, S390_OPERAND_GPR }, 5599461Sobrien#define R_28 6 /* GPR starting at position 28 */ 5699461Sobrien { 4, 28, S390_OPERAND_GPR }, 5799461Sobrien#define R_32 7 /* GPR starting at position 32 */ 5899461Sobrien { 4, 32, S390_OPERAND_GPR }, 5999461Sobrien 6099461Sobrien#define F_8 8 /* FPR starting at position 8 */ 6199461Sobrien { 4, 8, S390_OPERAND_FPR }, 6299461Sobrien#define F_12 9 /* FPR starting at position 12 */ 6399461Sobrien { 4, 12, S390_OPERAND_FPR }, 6499461Sobrien#define F_16 10 /* FPR starting at position 16 */ 6599461Sobrien { 4, 16, S390_OPERAND_FPR }, 6699461Sobrien#define F_20 11 /* FPR starting at position 16 */ 6799461Sobrien { 4, 16, S390_OPERAND_FPR }, 6899461Sobrien#define F_24 12 /* FPR starting at position 24 */ 6999461Sobrien { 4, 24, S390_OPERAND_FPR }, 7099461Sobrien#define F_28 13 /* FPR starting at position 28 */ 7199461Sobrien { 4, 28, S390_OPERAND_FPR }, 7299461Sobrien#define F_32 14 /* FPR starting at position 32 */ 7399461Sobrien { 4, 32, S390_OPERAND_FPR }, 7499461Sobrien 7599461Sobrien#define A_8 15 /* Access reg. starting at position 8 */ 7699461Sobrien { 4, 8, S390_OPERAND_AR }, 7799461Sobrien#define A_12 16 /* Access reg. starting at position 12 */ 7899461Sobrien { 4, 12, S390_OPERAND_AR }, 7999461Sobrien#define A_24 17 /* Access reg. starting at position 24 */ 8099461Sobrien { 4, 24, S390_OPERAND_AR }, 8199461Sobrien#define A_28 18 /* Access reg. starting at position 28 */ 8299461Sobrien { 4, 28, S390_OPERAND_AR }, 8399461Sobrien 8499461Sobrien#define C_8 19 /* Control reg. starting at position 8 */ 8599461Sobrien { 4, 8, S390_OPERAND_CR }, 8699461Sobrien#define C_12 20 /* Control reg. starting at position 12 */ 8799461Sobrien { 4, 12, S390_OPERAND_CR }, 8899461Sobrien 8999461Sobrien#define B_16 21 /* Base register starting at position 16 */ 9099461Sobrien { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR }, 9199461Sobrien#define B_32 22 /* Base register starting at position 32 */ 9299461Sobrien { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR }, 9399461Sobrien 9499461Sobrien#define X_12 23 /* Index register starting at position 12 */ 9599461Sobrien { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR }, 9699461Sobrien 9799461Sobrien#define D_20 24 /* Displacement starting at position 20 */ 9899461Sobrien { 12, 20, S390_OPERAND_DISP }, 9999461Sobrien#define D_36 25 /* Displacement starting at position 36 */ 10099461Sobrien { 12, 36, S390_OPERAND_DISP }, 101130561Sobrien#define D20_20 26 /* 20 bit displacement starting at 20 */ 102130561Sobrien { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, 10399461Sobrien 104130561Sobrien#define L4_8 27 /* 4 bit length starting at position 8 */ 10599461Sobrien { 4, 8, S390_OPERAND_LENGTH }, 106130561Sobrien#define L4_12 28 /* 4 bit length starting at position 12 */ 10799461Sobrien { 4, 12, S390_OPERAND_LENGTH }, 108130561Sobrien#define L8_8 29 /* 8 bit length starting at position 8 */ 10999461Sobrien { 8, 8, S390_OPERAND_LENGTH }, 11099461Sobrien 111130561Sobrien#define U4_8 30 /* 4 bit unsigned value starting at 8 */ 11299461Sobrien { 4, 8, 0 }, 113130561Sobrien#define U4_12 31 /* 4 bit unsigned value starting at 12 */ 11499461Sobrien { 4, 12, 0 }, 115130561Sobrien#define U4_16 32 /* 4 bit unsigned value starting at 16 */ 11699461Sobrien { 4, 16, 0 }, 117130561Sobrien#define U4_20 33 /* 4 bit unsigned value starting at 20 */ 11899461Sobrien { 4, 20, 0 }, 119130561Sobrien#define U8_8 34 /* 8 bit unsigned value starting at 8 */ 12099461Sobrien { 8, 8, 0 }, 121130561Sobrien#define U8_16 35 /* 8 bit unsigned value starting at 16 */ 12299461Sobrien { 8, 16, 0 }, 123130561Sobrien#define I16_16 36 /* 16 bit signed value starting at 16 */ 12499461Sobrien { 16, 16, S390_OPERAND_SIGNED }, 125130561Sobrien#define U16_16 37 /* 16 bit unsigned value starting at 16 */ 12699461Sobrien { 16, 16, 0 }, 127130561Sobrien#define J16_16 38 /* PC relative jump offset at 16 */ 12899461Sobrien { 16, 16, S390_OPERAND_PCREL }, 129130561Sobrien#define J32_16 39 /* PC relative long offset at 16 */ 130218822Sdim { 32, 16, S390_OPERAND_PCREL }, 131218822Sdim#define I32_16 40 /* 32 bit signed value starting at 16 */ 132218822Sdim { 32, 16, S390_OPERAND_SIGNED }, 133218822Sdim#define U32_16 41 /* 32 bit unsigned value starting at 16 */ 134218822Sdim { 32, 16, 0 }, 135218822Sdim#define M_16 42 /* 4 bit optional mask starting at 16 */ 136218822Sdim { 4, 16, S390_OPERAND_OPTIONAL }, 137218822Sdim#define RO_28 43 /* optional GPR starting at position 28 */ 138218822Sdim { 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) } 139218822Sdim 14099461Sobrien}; 14199461Sobrien 14299461Sobrien 14399461Sobrien/* Macros used to form opcodes. */ 14499461Sobrien 14599461Sobrien/* 8/16/48 bit opcodes. */ 14699461Sobrien#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } 14799461Sobrien#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } 14899461Sobrien#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ 14999461Sobrien (x >> 16) & 255, (x >> 8) & 255, x & 255} 15099461Sobrien 15199461Sobrien/* The new format of the INSTR_x_y and MASK_x_y defines is based 15299461Sobrien on the following rules: 15399461Sobrien 1) the middle part of the definition (x in INSTR_x_y) is the official 15499461Sobrien names of the instruction format that you can find in the principals 15599461Sobrien of operation. 15699461Sobrien 2) the last part of the definition (y in INSTR_x_y) gives you an idea 15799461Sobrien which operands the binary represenation of the instruction has. 15899461Sobrien The meanings of the letters in y are: 15999461Sobrien a - access register 16099461Sobrien c - control register 16199461Sobrien d - displacement, 12 bit 16299461Sobrien f - floating pointer register 163218822Sdim i - signed integer, 4, 8, 16 or 32 bit 16499461Sobrien l - length, 4 or 8 bit 16599461Sobrien p - pc relative 16699461Sobrien r - general purpose register 167218822Sdim u - unsigned integer, 4, 8, 16 or 32 bit 168218822Sdim m - mode field, 4 bit 16999461Sobrien 0 - operand skipped. 17099461Sobrien The order of the letters reflects the layout of the format in 17199461Sobrien storage and not the order of the paramaters of the instructions. 17299461Sobrien The use of the letters is not a 100% match with the PoP but it is 17399461Sobrien quite close. 17499461Sobrien 17599461Sobrien For example the instruction "mvo" is defined in the PoP as follows: 17699461Sobrien 17799461Sobrien MVO D1(L1,B1),D2(L2,B2) [SS] 17899461Sobrien 17999461Sobrien -------------------------------------- 18099461Sobrien | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | 18199461Sobrien -------------------------------------- 18299461Sobrien 0 8 12 16 20 32 36 18399461Sobrien 18499461Sobrien The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ 18599461Sobrien 18699461Sobrien#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ 18799461Sobrien#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ 18899461Sobrien#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ 18999461Sobrien#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ 19099461Sobrien#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ 191218822Sdim#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ 192218822Sdim#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ 19399461Sobrien#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ 19499461Sobrien#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ 19599461Sobrien#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ 19699461Sobrien#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ 19799461Sobrien#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ 19899461Sobrien#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ 19999461Sobrien#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ 20099461Sobrien#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ 20199461Sobrien#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ 20299461Sobrien#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ 20399461Sobrien#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ 20499461Sobrien#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ 20599461Sobrien#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ 20699461Sobrien#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ 20799461Sobrien#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ 208218822Sdim#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ 209218822Sdim/* Actually efpc and sfpc do not take an optional operand. 210218822Sdim This is just a workaround for existing code e.g. glibc. */ 211218822Sdim#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ 21299461Sobrien#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ 213218822Sdim#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ 214218822Sdim#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ 21599461Sobrien#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ 21699461Sobrien#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ 217130561Sobrien#define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ 218218822Sdim#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ 219218822Sdim#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ 220218822Sdim#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ 221218822Sdim#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ 222218822Sdim#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ 223218822Sdim#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ 22499461Sobrien#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ 22599461Sobrien#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ 22699461Sobrien#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ 22799461Sobrien#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ 22899461Sobrien#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ 22999461Sobrien#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ 230218822Sdim#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ 23199461Sobrien#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ 232218822Sdim#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ 23399461Sobrien#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ 234130561Sobrien#define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ 23599461Sobrien#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ 236130561Sobrien#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ 237130561Sobrien#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ 238130561Sobrien#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ 239218822Sdim#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ 24099461Sobrien#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ 24199461Sobrien#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ 24299461Sobrien#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ 24399461Sobrien#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ 24499461Sobrien#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ 24599461Sobrien#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ 24699461Sobrien#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ 24799461Sobrien#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ 24899461Sobrien#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ 249130561Sobrien#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ 250130561Sobrien#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ 25199461Sobrien#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ 25299461Sobrien#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ 25399461Sobrien#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ 25499461Sobrien#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ 25599461Sobrien#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ 256130561Sobrien#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ 25799461Sobrien#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ 25899461Sobrien#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ 259218822Sdim#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ 26099461Sobrien#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ 26199461Sobrien#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ 26299461Sobrien#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ 26399461Sobrien#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ 26499461Sobrien#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ 26599461Sobrien#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ 26699461Sobrien#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ 267218822Sdim#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ 26899461Sobrien 26999461Sobrien#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 27099461Sobrien#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 27199461Sobrien#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 27299461Sobrien#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 27399461Sobrien#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 274218822Sdim#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 275218822Sdim#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 27699461Sobrien#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 27799461Sobrien#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 27899461Sobrien#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 27999461Sobrien#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 28099461Sobrien#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 28199461Sobrien#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 28299461Sobrien#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } 28399461Sobrien#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 28499461Sobrien#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 28599461Sobrien#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 28699461Sobrien#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 28799461Sobrien#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } 28899461Sobrien#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 28999461Sobrien#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 29099461Sobrien#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 291218822Sdim#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 292218822Sdim#define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } 29399461Sobrien#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 294218822Sdim#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 295218822Sdim#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 29699461Sobrien#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 29799461Sobrien#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 298130561Sobrien#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 29999461Sobrien#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 300218822Sdim#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 301218822Sdim#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 302218822Sdim#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } 303218822Sdim#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 304218822Sdim#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 30599461Sobrien#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 30699461Sobrien#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 30799461Sobrien#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 30899461Sobrien#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 30999461Sobrien#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 31099461Sobrien#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 311218822Sdim#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } 31299461Sobrien#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 313218822Sdim#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 31499461Sobrien#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 315130561Sobrien#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 31699461Sobrien#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 31799461Sobrien#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 31899461Sobrien#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 31999461Sobrien#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 32099461Sobrien#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 32199461Sobrien#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 322130561Sobrien#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 323130561Sobrien#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 324130561Sobrien#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 325218822Sdim#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 32699461Sobrien#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 32799461Sobrien#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 32899461Sobrien#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 32999461Sobrien#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 330130561Sobrien#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 331130561Sobrien#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 33299461Sobrien#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } 33399461Sobrien#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 33499461Sobrien#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 33599461Sobrien#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 33699461Sobrien#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 337130561Sobrien#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } 33899461Sobrien#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 33999461Sobrien#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 340218822Sdim#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 34199461Sobrien#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 34299461Sobrien#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 34399461Sobrien#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 34499461Sobrien#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 34599461Sobrien#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } 34699461Sobrien#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } 34799461Sobrien#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } 348218822Sdim#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } 34999461Sobrien 35099461Sobrien/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ 35199461Sobrien 35299461Sobrienconst struct s390_opcode s390_opformats[] = 35399461Sobrien { 354130561Sobrien { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, 355130561Sobrien { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, 356130561Sobrien { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, 357130561Sobrien { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, 358218822Sdim { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 }, 359130561Sobrien { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, 360130561Sobrien { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, 361130561Sobrien { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, 362130561Sobrien { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, 363130561Sobrien { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, 364130561Sobrien { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, 365130561Sobrien { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, 366130561Sobrien { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, 367130561Sobrien { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, 368130561Sobrien { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, 369130561Sobrien { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, 370130561Sobrien { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, 371130561Sobrien { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, 372130561Sobrien { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, 373130561Sobrien { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, 374130561Sobrien { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, 375218822Sdim { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 }, 37699461Sobrien}; 37799461Sobrien 37899461Sobrienconst int s390_num_opformats = 37999461Sobrien sizeof (s390_opformats) / sizeof (s390_opformats[0]); 38099461Sobrien 38199461Sobrien#include "s390-opc.tab" 382