arm-dis.c revision 285830
1184610Salfred/* Instruction printing code for the ARM 2184610Salfred Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 3184610Salfred 2007, Free Software Foundation, Inc. 4184610Salfred Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) 5184610Salfred Modification by James G. Smith (jsmith@cygnus.co.uk) 6189002Sed 7184610Salfred This file is part of libopcodes. 8184610Salfred 9184610Salfred This program is free software; you can redistribute it and/or modify it under 10184610Salfred the terms of the GNU General Public License as published by the Free 11184610Salfred Software Foundation; either version 2 of the License, or (at your option) 12184610Salfred any later version. 13184610Salfred 14184610Salfred This program is distributed in the hope that it will be useful, but WITHOUT 15184610Salfred ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16184610Salfred FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17184610Salfred more details. 18184610Salfred 19184610Salfred You should have received a copy of the GNU General Public License 20184610Salfred along with this program; if not, write to the Free Software 21184610Salfred Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 22184610Salfred 23184610Salfred#include "sysdep.h" 24184610Salfred 25184610Salfred#include "dis-asm.h" 26184610Salfred#include "opcode/arm.h" 27184610Salfred#include "opintl.h" 28184610Salfred#include "safe-ctype.h" 29184610Salfred#include "floatformat.h" 30184610Salfred 31184610Salfred/* FIXME: This shouldn't be done here. */ 32184610Salfred#include "coff/internal.h" 33184610Salfred#include "libcoff.h" 34184610Salfred#include "elf-bfd.h" 35184610Salfred#include "elf/internal.h" 36184610Salfred#include "elf/arm.h" 37184610Salfred 38184610Salfred/* FIXME: Belongs in global header. */ 39184610Salfred#ifndef strneq 40184610Salfred#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) 41184610Salfred#endif 42184610Salfred 43184610Salfred#ifndef NUM_ELEM 44184610Salfred#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) 45184610Salfred#endif 46184610Salfred 47184610Salfredstruct opcode32 48184610Salfred{ 49184610Salfred unsigned long arch; /* Architecture defining this insn. */ 50184610Salfred unsigned long value, mask; /* Recognise insn if (op&mask)==value. */ 51184610Salfred const char *assembler; /* How to disassemble this insn. */ 52184610Salfred}; 53184610Salfred 54184610Salfredstruct opcode16 55184610Salfred{ 56184610Salfred unsigned long arch; /* Architecture defining this insn. */ 57184610Salfred unsigned short value, mask; /* Recognise insn if (op&mask)==value. */ 58184610Salfred const char *assembler; /* How to disassemble this insn. */ 59184610Salfred}; 60184610Salfred 61184610Salfred/* print_insn_coprocessor recognizes the following format control codes: 62184610Salfred 63184610Salfred %% % 64184610Salfred 65184610Salfred %c print condition code (always bits 28-31 in ARM mode) 66184610Salfred %q print shifter argument 67184610Salfred %u print condition code (unconditional in ARM mode) 68184610Salfred %A print address for ldc/stc/ldf/stf instruction 69184610Salfred %B print vstm/vldm register list 70184610Salfred %C print vstr/vldr address operand 71184610Salfred %I print cirrus signed shift immediate: bits 0..3|4..6 72184610Salfred %F print the COUNT field of a LFM/SFM instruction. 73184610Salfred %P print floating point precision in arithmetic insn 74184610Salfred %Q print floating point precision in ldf/stf insn 75184610Salfred %R print floating point rounding mode 76184610Salfred 77184610Salfred %<bitfield>r print as an ARM register 78184610Salfred %<bitfield>d print the bitfield in decimal 79184610Salfred %<bitfield>k print immediate for VFPv3 conversion instruction 80184610Salfred %<bitfield>x print the bitfield in hex 81184610Salfred %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 82184610Salfred %<bitfield>f print a floating point constant if >7 else a 83184610Salfred floating point register 84184610Salfred %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us 85184610Salfred %<bitfield>g print as an iWMMXt 64-bit register 86184610Salfred %<bitfield>G print as an iWMMXt general purpose or control register 87184610Salfred %<bitfield>D print as a NEON D register 88184610Salfred %<bitfield>Q print as a NEON Q register 89184610Salfred 90184610Salfred %y<code> print a single precision VFP reg. 91184610Salfred Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair 92184610Salfred %z<code> print a double precision VFP reg 93184610Salfred Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list 94184610Salfred 95184610Salfred %<bitfield>'c print specified char iff bitfield is all ones 96189002Sed %<bitfield>`c print specified char iff bitfield is all zeroes 97184610Salfred %<bitfield>?ab... select from array of values in big endian order 98184610Salfred 99184610Salfred %L print as an iWMMXt N/M width field. 100184610Salfred %Z print the Immediate of a WSHUFH instruction. 101184610Salfred %l like 'A' except use byte offsets for 'B' & 'H' 102184610Salfred versions. 103184610Salfred %i print 5-bit immediate in bits 8,3..0 104184610Salfred (print "32" when 0) 105194677Sthompsa %r print register offset address for wldt/wstr instruction 106194677Sthompsa*/ 107194677Sthompsa 108194677Sthompsa/* Common coprocessor opcodes shared between Arm and Thumb-2. */ 109194677Sthompsa 110194677Sthompsastatic const struct opcode32 coprocessor_opcodes[] = 111194677Sthompsa{ 112194677Sthompsa /* XScale instructions. */ 113194677Sthompsa {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, 114194677Sthompsa {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, 115194677Sthompsa {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, 116194677Sthompsa {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, 117194677Sthompsa {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, 118194677Sthompsa 119194677Sthompsa /* Intel Wireless MMX technology instructions. */ 120194677Sthompsa#define FIRST_IWMMXT_INSN 0x0e130130 121194677Sthompsa#define IWMMXT_INSN_COUNT 73 122194677Sthompsa {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, 123194677Sthompsa {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, 124194677Sthompsa {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, 125194677Sthompsa {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, 126194677Sthompsa {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, 127196826Strasz {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, 128188746Sthompsa {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, 129184610Salfred {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, 130200886Sthompsa {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, 131200886Sthompsa {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, 132184610Salfred {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, 133184610Salfred {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, 134184610Salfred {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, 135184610Salfred {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, 136184610Salfred {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, 137184610Salfred {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, 138184610Salfred {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, 139184610Salfred {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 140184610Salfred {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, 141194677Sthompsa {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, 142194677Sthompsa {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, 143184610Salfred {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, 144184610Salfred {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, 145184610Salfred {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, 146184610Salfred {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, 147184610Salfred {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 148184610Salfred {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 149207077Sthompsa {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, 150184610Salfred {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, 151184610Salfred {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, 152184610Salfred {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, 153184610Salfred {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, 154184610Salfred {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, 155184610Salfred {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 156184610Salfred {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, 157184610Salfred {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 158184610Salfred {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 159184610Salfred {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 160184610Salfred {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, 161184610Salfred {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, 162184610Salfred {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, 163184610Salfred {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, 164184610Salfred {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, 165184610Salfred {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, 166184610Salfred {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 167184610Salfred {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, 168184610Salfred {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, 169184610Salfred {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 170184610Salfred {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, 171184610Salfred {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 172184610Salfred {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, 173184610Salfred {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, 174184610Salfred {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, 175184610Salfred {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, 176184610Salfred {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 177192502Sthompsa {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 178192502Sthompsa {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, 179184610Salfred {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 180199675Sthompsa {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 181199675Sthompsa {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, 182184610Salfred {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, 183184610Salfred {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, 184184610Salfred {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, 185184610Salfred {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, 186184610Salfred {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, 187184610Salfred {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, 188184610Salfred {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, 189184610Salfred {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 190184610Salfred {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, 191184610Salfred {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, 192184610Salfred {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, 193184610Salfred {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, 194184610Salfred {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 195184610Salfred {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, 196184610Salfred {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, 197184610Salfred 198184610Salfred /* Floating point coprocessor (FPA) instructions */ 199184610Salfred {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 200184610Salfred {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 201184610Salfred {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 202184610Salfred {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 203184610Salfred {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 204184610Salfred {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 205184610Salfred {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 206184610Salfred {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 207184610Salfred {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 208184610Salfred {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 209184610Salfred {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 210184610Salfred {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 211184610Salfred {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 212184610Salfred {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 213184610Salfred {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 214184610Salfred {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 215184610Salfred {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 216184610Salfred {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 217184610Salfred {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 218184610Salfred {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 219184610Salfred {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 220184610Salfred {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 221184610Salfred {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 222184610Salfred {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 223184610Salfred {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 224184610Salfred {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 225184610Salfred {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 226184610Salfred {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 227184610Salfred {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 228184610Salfred {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 229184610Salfred {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 230184610Salfred {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 231184610Salfred {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 232184610Salfred {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 233184610Salfred {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 234184610Salfred {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 235184610Salfred {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 236184610Salfred {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 237184610Salfred {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 238184610Salfred {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 239184610Salfred {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 240184610Salfred {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 241184610Salfred {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 242184610Salfred 243184610Salfred /* Register load/store */ 244184610Salfred {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"}, 245184610Salfred {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"}, 246184610Salfred {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, 247184610Salfred {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, 248184610Salfred {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"}, 249184610Salfred {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"}, 250184610Salfred 251184610Salfred /* Data transfer between ARM and NEON registers */ 252184610Salfred {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, 253184610Salfred {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, 254184610Salfred {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, 255184610Salfred {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, 256184610Salfred {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, 257184610Salfred {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, 258184610Salfred {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, 259184610Salfred {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, 260184610Salfred {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, 261184610Salfred {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, 262184610Salfred {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, 263184610Salfred {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, 264184610Salfred {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, 265184610Salfred {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, 266184610Salfred 267184610Salfred /* Floating point coprocessor (VFP) instructions */ 268184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"}, 269184610Salfred {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, 270184610Salfred {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, 271184610Salfred {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"}, 272184610Salfred {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"}, 273184610Salfred {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, 274184610Salfred {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, 275184610Salfred {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, 276184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, 277184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, 278184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"}, 279184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"}, 280184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, 281184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, 282184610Salfred {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, 283184610Salfred {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"}, 284184610Salfred {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"}, 285184610Salfred {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"}, 286184610Salfred {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"}, 287184610Salfred {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"}, 288184610Salfred {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"}, 289184610Salfred {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"}, 290184610Salfred {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"}, 291184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"}, 292184610Salfred {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"}, 293184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"}, 294184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"}, 295184610Salfred {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"}, 296184610Salfred {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"}, 297184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"}, 298184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"}, 299184610Salfred {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"}, 300184610Salfred {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"}, 301184610Salfred {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"}, 302184610Salfred {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"}, 303184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"}, 304184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"}, 305184610Salfred {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"}, 306184610Salfred {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"}, 307184610Salfred {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"}, 308184610Salfred {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"}, 309184610Salfred {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"}, 310184610Salfred {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"}, 311184610Salfred {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"}, 312184610Salfred {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"}, 313184610Salfred {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"}, 314184610Salfred {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"}, 315184610Salfred {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"}, 316200886Sthompsa {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"}, 317184610Salfred {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"}, 318184610Salfred {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"}, 319184610Salfred {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"}, 320200886Sthompsa {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"}, 321200886Sthompsa {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"}, 322184610Salfred {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"}, 323184610Salfred {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"}, 324184610Salfred {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"}, 325184610Salfred {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"}, 326184610Salfred {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"}, 327200886Sthompsa {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"}, 328184610Salfred {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"}, 329184610Salfred {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"}, 330184610Salfred {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"}, 331184610Salfred {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"}, 332184610Salfred {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"}, 333184610Salfred {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"}, 334184610Salfred {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"}, 335184610Salfred {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"}, 336184610Salfred {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"}, 337184610Salfred {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"}, 338184610Salfred {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"}, 339184610Salfred {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"}, 340184610Salfred {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"}, 341184610Salfred {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"}, 342184610Salfred {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"}, 343184610Salfred {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"}, 344184610Salfred {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"}, 345184610Salfred {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"}, 346184610Salfred {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"}, 347184610Salfred {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"}, 348184610Salfred {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"}, 349184610Salfred {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"}, 350184610Salfred {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"}, 351184610Salfred 352184610Salfred /* Cirrus coprocessor instructions. */ 353184610Salfred {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 354184610Salfred {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, 355184610Salfred {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 356184610Salfred {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 357184610Salfred {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 358184610Salfred {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, 359184610Salfred {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 360184610Salfred {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, 361184610Salfred {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 362184610Salfred {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, 363184610Salfred {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 364184610Salfred {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, 365184610Salfred {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 366184610Salfred {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, 367184610Salfred {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 368184610Salfred {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, 369184610Salfred {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, 370184610Salfred {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, 371184610Salfred {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, 372184610Salfred {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, 373184610Salfred {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, 374184610Salfred {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, 375184610Salfred {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, 376184610Salfred {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, 377184610Salfred {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, 378184610Salfred {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, 379184610Salfred {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, 380184610Salfred {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, 381184610Salfred {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, 382184610Salfred {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, 383184610Salfred {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, 384184610Salfred {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, 385184610Salfred {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, 386184610Salfred {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, 387184610Salfred {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, 388184610Salfred {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, 389184610Salfred {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, 390184610Salfred {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, 391184610Salfred {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, 392184610Salfred {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, 393184610Salfred {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, 394184610Salfred {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, 395184610Salfred {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, 396184610Salfred {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, 397184610Salfred {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, 398184610Salfred {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, 399184610Salfred {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, 400184610Salfred {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, 401184610Salfred {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, 402184610Salfred {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, 403184610Salfred {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, 404184610Salfred {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, 405192984Sthompsa {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, 406184610Salfred {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, 407192984Sthompsa {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, 408184610Salfred {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, 409184610Salfred {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, 410184610Salfred {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, 411184610Salfred {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, 412184610Salfred {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, 413184610Salfred {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, 414184610Salfred {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, 415184610Salfred {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 416200886Sthompsa {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 417200886Sthompsa {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 418184610Salfred {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 419184610Salfred {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, 420184610Salfred {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, 421184610Salfred {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, 422184610Salfred {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, 423184610Salfred {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, 424184610Salfred {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, 425184610Salfred {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 426184610Salfred {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 427200886Sthompsa {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 428200886Sthompsa {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 429184610Salfred {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 430200886Sthompsa {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, 431184610Salfred {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 432184610Salfred {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 433184610Salfred {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 434184610Salfred {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, 435184610Salfred {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 436184610Salfred {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, 437184610Salfred 438184610Salfred /* Generic coprocessor instructions */ 439193045Sthompsa {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 440193045Sthompsa {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 441193045Sthompsa {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 442193045Sthompsa {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 443193045Sthompsa {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 444193045Sthompsa {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, 445193045Sthompsa {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, 446193045Sthompsa 447193045Sthompsa /* V6 coprocessor instructions */ 448193045Sthompsa {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 449193045Sthompsa {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, 450193045Sthompsa 451193045Sthompsa /* V5 coprocessor instructions */ 452193045Sthompsa {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 453193045Sthompsa {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, 454193045Sthompsa {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 455193045Sthompsa {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 456193045Sthompsa {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 457193045Sthompsa 458193045Sthompsa {0, 0, 0, 0} 459184610Salfred}; 460185948Sthompsa 461185948Sthompsa/* Neon opcode table: This does not encode the top byte -- that is 462185948Sthompsa checked by the print_insn_neon routine, as it depends on whether we are 463192984Sthompsa doing thumb32 or arm32 disassembly. */ 464194677Sthompsa 465185948Sthompsa/* print_insn_neon recognizes the following format control codes: 466185948Sthompsa 467185948Sthompsa %% % 468185948Sthompsa 469192984Sthompsa %c print condition code 470194677Sthompsa %A print v{st,ld}[1234] operands 471185948Sthompsa %B print v{st,ld}[1234] any one operands 472185948Sthompsa %C print v{st,ld}[1234] single->all operands 473185948Sthompsa %D print scalar 474185948Sthompsa %E print vmov, vmvn, vorr, vbic encoded constant 475185948Sthompsa %F print vtbl,vtbx register list 476185948Sthompsa 477185948Sthompsa %<bitfield>r print as an ARM register 478185948Sthompsa %<bitfield>d print the bitfield in decimal 479185948Sthompsa %<bitfield>e print the 2^N - bitfield in decimal 480185948Sthompsa %<bitfield>D print as a NEON D register 481185948Sthompsa %<bitfield>Q print as a NEON Q register 482185948Sthompsa %<bitfield>R print as a NEON D or Q register 483185948Sthompsa %<bitfield>Sn print byte scaled width limited by n 484185948Sthompsa %<bitfield>Tn print short scaled width limited by n 485185948Sthompsa %<bitfield>Un print long scaled width limited by n 486185948Sthompsa 487185948Sthompsa %<bitfield>'c print specified char iff bitfield is all ones 488185948Sthompsa %<bitfield>`c print specified char iff bitfield is all zeroes 489185948Sthompsa %<bitfield>?ab... select from array of values in big endian order */ 490184610Salfred 491207077Sthompsastatic const struct opcode32 neon_opcodes[] = 492185948Sthompsa{ 493185948Sthompsa /* Extract */ 494185948Sthompsa {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 495185948Sthompsa {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, 496185948Sthompsa 497184610Salfred /* Move data element to all lanes */ 498184610Salfred {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, 499194099Sthompsa {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, 500184610Salfred {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, 501184610Salfred 502184610Salfred /* Table lookup */ 503184610Salfred {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, 504184610Salfred {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, 505192984Sthompsa 506190734Sthompsa /* Two registers, miscellaneous */ 507190734Sthompsa {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, 508190734Sthompsa {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, 509184610Salfred {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, 510184610Salfred {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, 511184610Salfred {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, 512184610Salfred {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, 513184610Salfred {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, 514184610Salfred {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 515192984Sthompsa {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, 516190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, 517190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, 518190734Sthompsa {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 519184610Salfred {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, 520184610Salfred {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 521184610Salfred {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 522184610Salfred {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 523184610Salfred {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 524184610Salfred {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, 525192984Sthompsa {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 526190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, 527190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 528190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 529184610Salfred {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, 530184610Salfred {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 531184610Salfred {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 532184610Salfred {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 533184610Salfred {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 534184610Salfred {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, 535190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 536190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, 537190734Sthompsa {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 538184610Salfred {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, 539184610Salfred {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, 540184610Salfred 541184610Salfred /* Three registers of the same length */ 542184610Salfred {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 543184610Salfred {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 544190734Sthompsa {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 545190734Sthompsa {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 546190734Sthompsa {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 547190734Sthompsa {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 548184610Salfred {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 549184610Salfred {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, 550184610Salfred {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 551184610Salfred {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 552184610Salfred {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 553184610Salfred {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 554192984Sthompsa {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 555190734Sthompsa {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 556190734Sthompsa {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 557184610Salfred {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 558184610Salfred {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 559184610Salfred {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 560184610Salfred {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 561184610Salfred {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 562184610Salfred {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 563190734Sthompsa {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 564190734Sthompsa {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 565190734Sthompsa {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 566190734Sthompsa {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 567184610Salfred {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, 568184610Salfred {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 569184610Salfred {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 570184610Salfred {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 571184610Salfred {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 572184610Salfred {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 573192984Sthompsa {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 574190734Sthompsa {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 575190734Sthompsa {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 576184610Salfred {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, 577184610Salfred {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 578184610Salfred {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 579184610Salfred {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 580184610Salfred {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 581184610Salfred {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, 582190734Sthompsa {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 583190734Sthompsa {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 584190734Sthompsa {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 585190734Sthompsa {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 586184610Salfred {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 587184610Salfred {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, 588184610Salfred {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 589194099Sthompsa {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 590184610Salfred {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 591184610Salfred {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 592184610Salfred {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 593184610Salfred {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 594184610Salfred {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, 595192984Sthompsa 596184610Salfred /* One register and an immediate value */ 597190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, 598190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, 599190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, 600184610Salfred {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, 601184610Salfred {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, 602184610Salfred {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, 603184610Salfred {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, 604184610Salfred {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, 605184610Salfred {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, 606192984Sthompsa {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, 607190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, 608190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, 609190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, 610184610Salfred 611184610Salfred /* Two registers and a shift amount */ 612184610Salfred {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 613184610Salfred {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 614184610Salfred {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 615184610Salfred {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 616192984Sthompsa {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 617190734Sthompsa {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, 618190734Sthompsa {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, 619190734Sthompsa {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 620184610Salfred {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 621184610Salfred {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 622184610Salfred {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, 623184610Salfred {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, 624184610Salfred {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, 625184610Salfred {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 626192984Sthompsa {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 627184610Salfred {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 628190734Sthompsa {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, 629190734Sthompsa {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, 630184610Salfred {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 631184610Salfred {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 632184610Salfred {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 633184610Salfred {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, 634184610Salfred {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, 635184610Salfred {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 636190734Sthompsa {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 637190734Sthompsa {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 638190734Sthompsa {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, 639190734Sthompsa {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, 640184610Salfred {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, 641184610Salfred {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, 642184610Salfred {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 643184610Salfred {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 644184610Salfred {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 645184610Salfred {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, 646192984Sthompsa {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, 647190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 648190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 649184610Salfred {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 650184610Salfred {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, 651184610Salfred {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 652184610Salfred {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, 653184610Salfred {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, 654184610Salfred {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, 655190734Sthompsa {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 656190734Sthompsa {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 657190734Sthompsa {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 658190734Sthompsa {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, 659184610Salfred {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, 660184610Salfred {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 661184610Salfred {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, 662184610Salfred {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, 663184610Salfred {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, 664184610Salfred {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 665192984Sthompsa {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 666190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 667190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, 668184610Salfred {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, 669184610Salfred {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, 670184610Salfred 671184610Salfred /* Three registers of different lengths */ 672184610Salfred {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 673184610Salfred {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 674203145Sthompsa {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 675190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 676190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 677190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 678184610Salfred {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 679184610Salfred {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, 680184610Salfred {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 681184610Salfred {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 682184610Salfred {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 683184610Salfred {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, 684192984Sthompsa {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 685190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 686190734Sthompsa {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 687184610Salfred {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 688184610Salfred {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, 689184610Salfred 690184610Salfred /* Two registers and a scalar */ 691184610Salfred {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 692184610Salfred {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 693184610Salfred {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 694184610Salfred {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 695184610Salfred {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 696184610Salfred {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 697184610Salfred {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 698184610Salfred {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, 699184610Salfred {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 700184610Salfred {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 701184610Salfred {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, 702184610Salfred {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 703184610Salfred {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 704184610Salfred {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 705184610Salfred {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 706184610Salfred {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 707184610Salfred {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, 708184610Salfred {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 709184610Salfred {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, 710184610Salfred {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 711184610Salfred {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 712184610Salfred {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, 713184610Salfred 714184610Salfred /* Element and structure load/store */ 715189275Sthompsa {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, 716188942Sthompsa {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, 717184610Salfred {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, 718212122Sthompsa {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, 719184610Salfred {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, 720184610Salfred {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 721184610Salfred {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 722184610Salfred {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 723184610Salfred {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, 724192052Sthompsa {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 725192984Sthompsa {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 726192052Sthompsa {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 727192984Sthompsa {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, 728192052Sthompsa {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, 729192052Sthompsa {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, 730192052Sthompsa {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, 731192052Sthompsa {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, 732192052Sthompsa {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, 733194228Sthompsa {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, 734192052Sthompsa 735192052Sthompsa {0,0 ,0, 0} 736192052Sthompsa}; 737192052Sthompsa 738192052Sthompsa/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially 739192052Sthompsa ordered: they must be searched linearly from the top to obtain a correct 740192052Sthompsa match. */ 741192052Sthompsa 742192052Sthompsa/* print_insn_arm recognizes the following format control codes: 743192052Sthompsa 744192052Sthompsa %% % 745192052Sthompsa 746192052Sthompsa %a print address for ldr/str instruction 747192052Sthompsa %s print address for ldr/str halfword/signextend instruction 748192052Sthompsa %b print branch destination 749192052Sthompsa %c print condition code (always bits 28-31) 750192052Sthompsa %m print register mask for ldm/stm instruction 751192052Sthompsa %o print operand2 (immediate or register + shift) 752192052Sthompsa %p print 'p' iff bits 12-15 are 15 753192052Sthompsa %t print 't' iff bit 21 set and bit 24 clear 754192052Sthompsa %B print arm BLX(1) destination 755192052Sthompsa %C print the PSR sub type. 756192052Sthompsa %U print barrier type. 757192052Sthompsa %P print address for pli instruction. 758192052Sthompsa 759192052Sthompsa %<bitfield>r print as an ARM register 760192052Sthompsa %<bitfield>d print the bitfield in decimal 761192052Sthompsa %<bitfield>W print the bitfield plus one in decimal 762192052Sthompsa %<bitfield>x print the bitfield in hex 763192052Sthompsa %<bitfield>X print the bitfield as 1 hex digit without leading "0x" 764192052Sthompsa 765192052Sthompsa %<bitfield>'c print specified char iff bitfield is all ones 766192052Sthompsa %<bitfield>`c print specified char iff bitfield is all zeroes 767192052Sthompsa %<bitfield>?ab... select from array of values in big endian order 768192052Sthompsa 769192052Sthompsa %e print arm SMI operand (bits 0..7,8..19). 770192052Sthompsa %E print the LSB and WIDTH fields of a BFI or BFC instruction. 771192052Sthompsa %V print the 16-bit immediate field of a MOVT or MOVW instruction. */ 772192052Sthompsa 773192052Sthompsastatic const struct opcode32 arm_opcodes[] = 774184610Salfred{ 775200886Sthompsa /* ARM instructions. */ 776184610Salfred {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, 777184610Salfred {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, 778192984Sthompsa {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"}, 779184610Salfred {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 780184610Salfred {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"}, 781200886Sthompsa {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 782200886Sthompsa {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 783184610Salfred 784192052Sthompsa /* V7 instructions. */ 785184610Salfred {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, 786200886Sthompsa {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, 787184610Salfred {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, 788200886Sthompsa {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, 789200886Sthompsa {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, 790200886Sthompsa 791200886Sthompsa /* ARM V6T2 instructions. */ 792200886Sthompsa {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, 793200886Sthompsa {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, 794200886Sthompsa {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 795200886Sthompsa {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"}, 796200886Sthompsa {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"}, 797200886Sthompsa {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, 798184610Salfred {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, 799200886Sthompsa {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, 800200886Sthompsa {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, 801200886Sthompsa 802200886Sthompsa /* ARM V6Z instructions. */ 803200886Sthompsa {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, 804200886Sthompsa 805200886Sthompsa /* ARM V6K instructions. */ 806200886Sthompsa {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, 807200886Sthompsa {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"}, 808200886Sthompsa {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"}, 809200886Sthompsa {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"}, 810200886Sthompsa {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"}, 811200886Sthompsa {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"}, 812200886Sthompsa {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"}, 813200886Sthompsa 814200886Sthompsa /* ARM V6K NOP hints. */ 815200886Sthompsa {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, 816200886Sthompsa {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, 817184610Salfred {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, 818184610Salfred {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, 819200886Sthompsa {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, 820200886Sthompsa 821200886Sthompsa /* ARM V6 instructions. */ 822200886Sthompsa {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, 823184610Salfred {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, 824184610Salfred {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, 825200886Sthompsa {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, 826200886Sthompsa {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, 827200886Sthompsa {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, 828200886Sthompsa {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"}, 829200886Sthompsa {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"}, 830200886Sthompsa {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"}, 831200886Sthompsa {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, 832200886Sthompsa {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, 833200886Sthompsa {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, 834200886Sthompsa {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 835200886Sthompsa {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, 836200886Sthompsa {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, 837200886Sthompsa {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 838200886Sthompsa {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, 839200886Sthompsa {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, 840200886Sthompsa {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, 841200886Sthompsa {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, 842200886Sthompsa {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, 843200886Sthompsa {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 844200886Sthompsa {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, 845200886Sthompsa {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, 846200886Sthompsa {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 847200886Sthompsa {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, 848200886Sthompsa {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, 849200886Sthompsa {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, 850200886Sthompsa {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, 851200886Sthompsa {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, 852200886Sthompsa {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 853200886Sthompsa {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, 854200886Sthompsa {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, 855200886Sthompsa {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 856200886Sthompsa {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, 857200886Sthompsa {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, 858184610Salfred {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 859200886Sthompsa {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, 860200886Sthompsa {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, 861184610Salfred {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, 862184610Salfred {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, 863184610Salfred {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, 864184610Salfred {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, 865184610Salfred {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, 866184610Salfred {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, 867192984Sthompsa {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, 868184610Salfred {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, 869184610Salfred {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, 870192499Sthompsa {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, 871184610Salfred {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, 872184610Salfred {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"}, 873184610Salfred {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"}, 874184610Salfred {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"}, 875184610Salfred {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"}, 876184610Salfred {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"}, 877184610Salfred {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"}, 878184610Salfred {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"}, 879184610Salfred {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"}, 880184610Salfred {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"}, 881184610Salfred {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"}, 882184610Salfred {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"}, 883184610Salfred {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"}, 884184610Salfred {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"}, 885184610Salfred {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"}, 886192984Sthompsa {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"}, 887184610Salfred {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"}, 888192984Sthompsa {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"}, 889184610Salfred {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"}, 890184610Salfred {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"}, 891184610Salfred {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"}, 892184610Salfred {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"}, 893184610Salfred {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"}, 894184610Salfred {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"}, 895184610Salfred {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"}, 896184610Salfred {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, 897184610Salfred {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 898184610Salfred {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 899184610Salfred {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 900184610Salfred {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, 901184610Salfred {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 902184610Salfred {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 903184610Salfred {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 904184610Salfred {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, 905184610Salfred {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 906194228Sthompsa {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 907184610Salfred {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 908188415Sthompsa {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, 909188415Sthompsa {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 910188415Sthompsa {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 911184610Salfred {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 912184610Salfred {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, 913194228Sthompsa {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 914184610Salfred {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 915184610Salfred {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, 916184610Salfred {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, 917184610Salfred {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, 918184610Salfred {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, 919184610Salfred {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, 920184610Salfred {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, 921207077Sthompsa {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, 922184610Salfred {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, 923184610Salfred {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, 924184610Salfred {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 925184610Salfred {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 926184610Salfred {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 927184610Salfred {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 928184610Salfred {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, 929184610Salfred {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 930184610Salfred {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 931184610Salfred {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, 932184610Salfred {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, 933184610Salfred {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"}, 934184610Salfred {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"}, 935184610Salfred {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, 936184610Salfred {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, 937184610Salfred {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 938184610Salfred {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, 939184610Salfred {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 940184610Salfred {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, 941184610Salfred {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"}, 942184610Salfred {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"}, 943184610Salfred {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, 944184610Salfred 945184610Salfred /* V5J instruction. */ 946184610Salfred {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, 947184610Salfred 948184610Salfred /* V5 Instructions. */ 949184610Salfred {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, 950184610Salfred {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, 951184610Salfred {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, 952184610Salfred {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, 953184610Salfred 954184610Salfred /* V5E "El Segundo" Instructions. */ 955184610Salfred {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, 956184610Salfred {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, 957184610Salfred {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, 958184610Salfred {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 959184610Salfred {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 960184610Salfred {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 961184610Salfred {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 962184610Salfred 963184610Salfred {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 964194228Sthompsa {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, 965184610Salfred 966184610Salfred {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 967184610Salfred {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 968184610Salfred {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 969184610Salfred {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, 970184610Salfred 971184610Salfred {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, 972184610Salfred {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, 973184610Salfred {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, 974184610Salfred {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, 975184610Salfred 976184610Salfred {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, 977194228Sthompsa {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, 978184610Salfred 979188415Sthompsa {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, 980184610Salfred {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, 981184610Salfred {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, 982184610Salfred {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, 983184610Salfred 984184610Salfred /* ARM Instructions. */ 985184610Salfred {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"}, 986194228Sthompsa {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"}, 987184610Salfred {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"}, 988203145Sthompsa {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, 989184610Salfred {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, 990184610Salfred {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, 991184610Salfred {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"}, 992184610Salfred {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, 993184610Salfred {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, 994184610Salfred {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, 995184610Salfred {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, 996184610Salfred {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, 997184610Salfred {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"}, 998184610Salfred {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"}, 999194228Sthompsa {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"}, 1000184610Salfred {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"}, 1001184610Salfred {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, 1002184610Salfred {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, 1003184610Salfred {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, 1004184610Salfred {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"}, 1005184610Salfred {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"}, 1006184610Salfred {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"}, 1007184610Salfred {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, 1008184610Salfred {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"}, 1009184610Salfred {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, 1010184610Salfred {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"}, 1011184610Salfred {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, 1012184610Salfred {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"}, 1013184610Salfred {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"}, 1014184610Salfred {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"}, 1015184610Salfred {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"}, 1016184610Salfred {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, 1017184610Salfred {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"}, 1018184610Salfred {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, 1019184610Salfred {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"}, 1020184610Salfred {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, 1021184610Salfred {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, 1022184610Salfred {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"}, 1023184610Salfred {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, 1024184610Salfred {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 1025184610Salfred {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, 1026184610Salfred 1027184610Salfred /* The rest. */ 1028184610Salfred {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"}, 1029184610Salfred {0, 0x00000000, 0x00000000, 0} 1030194228Sthompsa}; 1031184610Salfred 1032184610Salfred/* print_insn_thumb16 recognizes the following format control codes: 1033184610Salfred 1034184610Salfred %S print Thumb register (bits 3..5 as high number if bit 6 set) 1035184610Salfred %D print Thumb register (bits 0..2 as high number if bit 7 set) 1036184610Salfred %<bitfield>I print bitfield as a signed decimal 1037184610Salfred (top bit of range being the sign bit) 1038184610Salfred %N print Thumb register mask (with LR) 1039184610Salfred %O print Thumb register mask (with PC) 1040184610Salfred %M print Thumb register mask 1041184610Salfred %b print CZB's 6-bit unsigned branch destination 1042184610Salfred %s print Thumb right-shift immediate (6..10; 0 == 32). 1043184610Salfred %c print the condition code 1044184610Salfred %C print the condition code, or "s" if not conditional 1045184610Salfred %x print warning if conditional an not at end of IT block" 1046184610Salfred %X print "\t; unpredictable <IT:code>" if conditional 1047184610Salfred %I print IT instruction suffix and operands 1048184610Salfred %<bitfield>r print bitfield as an ARM register 1049184610Salfred %<bitfield>d print bitfield as a decimal 1050184610Salfred %<bitfield>H print (bitfield * 2) as a decimal 1051184610Salfred %<bitfield>W print (bitfield * 4) as a decimal 1052184610Salfred %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol 1053184610Salfred %<bitfield>B print Thumb branch destination (signed displacement) 1054184610Salfred %<bitfield>c print bitfield as a condition code 1055184610Salfred %<bitnum>'c print specified char iff bit is one 1056184610Salfred %<bitnum>?ab print a if bit is one else print b. */ 1057184610Salfred 1058194228Sthompsastatic const struct opcode16 thumb_opcodes[] = 1059184610Salfred{ 1060184610Salfred /* Thumb instructions. */ 1061188415Sthompsa 1062184610Salfred /* ARM V6K no-argument instructions. */ 1063184610Salfred {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, 1064184610Salfred {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, 1065184610Salfred {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"}, 1066188415Sthompsa {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"}, 1067184610Salfred {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"}, 1068199061Sthompsa {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, 1069184610Salfred 1070184610Salfred /* ARM V6T2 instructions. */ 1071184610Salfred {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, 1072184610Salfred {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, 1073184610Salfred {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"}, 1074184610Salfred 1075184610Salfred /* ARM V6. */ 1076192984Sthompsa {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, 1077193045Sthompsa {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, 1078184610Salfred {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, 1079184610Salfred {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, 1080184610Salfred {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, 1081184610Salfred {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, 1082184610Salfred {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"}, 1083184610Salfred {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, 1084184610Salfred {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, 1085184610Salfred {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, 1086184610Salfred {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, 1087184610Salfred 1088184610Salfred /* ARM V5 ISA extends Thumb. */ 1089184610Salfred {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ 1090194228Sthompsa /* This is BLX(2). BLX(1) is a 32-bit instruction. */ 1091184610Salfred {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ 1092184610Salfred /* ARM V4T ISA (Thumb v1). */ 1093184610Salfred {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"}, 1094184610Salfred /* Format 4. */ 1095184610Salfred {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, 1096184610Salfred {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, 1097184610Salfred {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, 1098184610Salfred {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, 1099184610Salfred {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, 1100184610Salfred {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, 1101184610Salfred {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, 1102184610Salfred {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, 1103184610Salfred {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, 1104184610Salfred {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, 1105184610Salfred {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, 1106184610Salfred {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, 1107184610Salfred {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, 1108194228Sthompsa {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, 1109184610Salfred {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, 1110184610Salfred {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, 1111184610Salfred /* format 13 */ 1112184610Salfred {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, 1113184610Salfred {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, 1114184610Salfred /* format 5 */ 1115184610Salfred {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"}, 1116184610Salfred {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"}, 1117184610Salfred {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"}, 1118184610Salfred {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"}, 1119184610Salfred /* format 14 */ 1120184610Salfred {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"}, 1121184610Salfred {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"}, 1122194228Sthompsa /* format 2 */ 1123184610Salfred {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, 1124184610Salfred {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, 1125184610Salfred {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, 1126184610Salfred {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, 1127184610Salfred /* format 8 */ 1128184610Salfred {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, 1129184610Salfred {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, 1130184610Salfred {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, 1131188415Sthompsa /* format 7 */ 1132184610Salfred {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 1133184610Salfred {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, 1134184610Salfred /* format 1 */ 1135184610Salfred {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, 1136184610Salfred {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, 1137184610Salfred {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, 1138184610Salfred /* format 3 */ 1139184610Salfred {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, 1140184610Salfred {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, 1141184610Salfred {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, 1142184610Salfred {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, 1143184610Salfred /* format 6 */ 1144184610Salfred {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ 1145194677Sthompsa /* format 9 */ 1146184610Salfred {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, 1147194677Sthompsa {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, 1148184610Salfred {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, 1149194677Sthompsa {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, 1150184610Salfred /* format 10 */ 1151184610Salfred {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, 1152194677Sthompsa {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, 1153184610Salfred /* format 11 */ 1154184610Salfred {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, 1155184610Salfred {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, 1156184610Salfred /* format 12 */ 1157184610Salfred {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"}, 1158184610Salfred {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, 1159184610Salfred /* format 15 */ 1160184610Salfred {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, 1161184610Salfred {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"}, 1162194677Sthompsa /* format 17 */ 1163184610Salfred {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, 1164194677Sthompsa /* format 16 */ 1165192984Sthompsa {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"}, 1166194677Sthompsa {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, 1167184610Salfred /* format 18 */ 1168184610Salfred {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, 1169184610Salfred 1170184610Salfred /* The E800 .. FFFF range is unconditionally redirected to the 1171184610Salfred 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs 1172184610Salfred are processed via that table. Thus, we can never encounter a 1173184610Salfred bare "second half of BL/BLX(1)" instruction here. */ 1174184610Salfred {ARM_EXT_V1, 0x0000, 0x0000, "undefined"}, 1175184610Salfred {0, 0, 0, 0} 1176184610Salfred}; 1177184610Salfred 1178184610Salfred/* Thumb32 opcodes use the same table structure as the ARM opcodes. 1179184610Salfred We adopt the convention that hw1 is the high 16 bits of .value and 1180184610Salfred .mask, hw2 the low 16 bits. 1181184610Salfred 1182184610Salfred print_insn_thumb32 recognizes the following format control codes: 1183184610Salfred 1184184610Salfred %% % 1185184610Salfred 1186184610Salfred %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0] 1187184610Salfred %M print a modified 12-bit immediate (same location) 1188184610Salfred %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0] 1189184610Salfred %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4] 1190184610Salfred %S print a possibly-shifted Rm 1191184610Salfred 1192184610Salfred %a print the address of a plain load/store 1193184610Salfred %w print the width and signedness of a core load/store 1194184610Salfred %m print register mask for ldm/stm 1195184610Salfred 1196184610Salfred %E print the lsb and width fields of a bfc/bfi instruction 1197194677Sthompsa %F print the lsb and width fields of a sbfx/ubfx instruction 1198194677Sthompsa %b print a conditional branch offset 1199184610Salfred %B print an unconditional branch offset 1200194677Sthompsa %s print the shift field of an SSAT instruction 1201194677Sthompsa %R print the rotation field of an SXT instruction 1202194228Sthompsa %U print barrier type. 1203184610Salfred %P print address for pli instruction. 1204184610Salfred %c print the condition code 1205184610Salfred %x print warning if conditional an not at end of IT block" 1206194677Sthompsa %X print "\t; unpredictable <IT:code>" if conditional 1207184610Salfred 1208184610Salfred %<bitfield>d print bitfield in decimal 1209184610Salfred %<bitfield>W print bitfield*4 in decimal 1210184610Salfred %<bitfield>r print bitfield as an ARM register 1211184610Salfred %<bitfield>c print bitfield as a condition code 1212184610Salfred 1213194677Sthompsa %<bitfield>'c print specified char iff bitfield is all ones 1214184610Salfred %<bitfield>`c print specified char iff bitfield is all zeroes 1215184610Salfred %<bitfield>?ab... select from array of values in big endian order 1216194677Sthompsa 1217184610Salfred With one exception at the bottom (done because BL and BLX(1) need 1218184610Salfred to come dead last), this table was machine-sorted first in 1219184610Salfred decreasing order of number of bits set in the mask, then in 1220194677Sthompsa increasing numeric order of mask, then in increasing numeric order 1221184610Salfred of opcode. This order is not the clearest for a human reader, but 1222184610Salfred is guaranteed never to catch a special-case bit pattern with a more 1223194677Sthompsa general mask, which is important, because this instruction encoding 1224184610Salfred makes heavy use of special-case bit patterns. */ 1225184610Salfredstatic const struct opcode32 thumb32_opcodes[] = 1226184610Salfred{ 1227192984Sthompsa /* V7 instructions. */ 1228194677Sthompsa {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, 1229184610Salfred {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, 1230194677Sthompsa {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, 1231184610Salfred {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, 1232184610Salfred {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, 1233184610Salfred {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, 1234184610Salfred {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, 1235184610Salfred 1236184610Salfred /* Instructions defined in the basic V6T2 set. */ 1237184610Salfred {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, 1238184610Salfred {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, 1239194228Sthompsa {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, 1240184610Salfred {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, 1241184610Salfred {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"}, 1242184610Salfred {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, 1243184610Salfred 1244184610Salfred {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, 1245194677Sthompsa {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, 1246184610Salfred {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, 1247184610Salfred {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, 1248184610Salfred {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, 1249184610Salfred {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, 1250184610Salfred {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"}, 1251184610Salfred {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, 1252194677Sthompsa {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, 1253184610Salfred {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, 1254194677Sthompsa {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, 1255184610Salfred {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, 1256194677Sthompsa {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, 1257184610Salfred {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, 1258184610Salfred {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, 1259184610Salfred {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, 1260184610Salfred {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, 1261184610Salfred {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, 1262184610Salfred {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, 1263184610Salfred {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, 1264184610Salfred {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, 1265184610Salfred {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, 1266184610Salfred {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, 1267184610Salfred {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, 1268184610Salfred {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, 1269184610Salfred {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, 1270184610Salfred {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, 1271184610Salfred {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, 1272184610Salfred {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, 1273184610Salfred {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, 1274184610Salfred {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, 1275184610Salfred {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, 1276184610Salfred {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, 1277184610Salfred {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, 1278184610Salfred {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, 1279184610Salfred {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, 1280184610Salfred {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, 1281184610Salfred {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, 1282184610Salfred {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, 1283184610Salfred {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, 1284184610Salfred {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, 1285184610Salfred {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, 1286184610Salfred {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, 1287184610Salfred {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, 1288184610Salfred {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, 1289184610Salfred {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, 1290184610Salfred {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1291184610Salfred {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1292184610Salfred {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1293184610Salfred {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1294184610Salfred {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1295184610Salfred {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"}, 1296184610Salfred {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, 1297184610Salfred {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, 1298184610Salfred {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, 1299184610Salfred {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, 1300184610Salfred {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, 1301184610Salfred {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, 1302184610Salfred {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, 1303184610Salfred {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, 1304184610Salfred {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, 1305184610Salfred {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, 1306184610Salfred {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, 1307184610Salfred {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, 1308184610Salfred {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, 1309184610Salfred {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, 1310184610Salfred {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1311184610Salfred {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1312184610Salfred {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1313184610Salfred {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1314184610Salfred {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1315184610Salfred {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"}, 1316184610Salfred {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, 1317184610Salfred {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, 1318184610Salfred {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1319184610Salfred {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1320194677Sthompsa {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1321194677Sthompsa {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, 1322194677Sthompsa {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, 1323184610Salfred {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, 1324194228Sthompsa {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, 1325184610Salfred {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, 1326184610Salfred {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 1327184610Salfred {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, 1328184610Salfred {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, 1329194677Sthompsa {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 1330184610Salfred {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, 1331184610Salfred {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 1332184610Salfred {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, 1333184610Salfred {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 1334184610Salfred {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, 1335184610Salfred {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, 1336194677Sthompsa {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, 1337184610Salfred {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, 1338194677Sthompsa {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, 1339194677Sthompsa {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, 1340194677Sthompsa {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, 1341194677Sthompsa {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, 1342194677Sthompsa {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, 1343194677Sthompsa {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, 1344184610Salfred {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, 1345194677Sthompsa {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, 1346194677Sthompsa {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, 1347184610Salfred {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, 1348184610Salfred {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1349194677Sthompsa {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1350194677Sthompsa {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1351194677Sthompsa {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1352194677Sthompsa {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1353194677Sthompsa {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1354194677Sthompsa {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1355194677Sthompsa {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1356184610Salfred {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, 1357194677Sthompsa {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, 1358184610Salfred {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, 1359184610Salfred {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, 1360184610Salfred {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, 1361184610Salfred {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1362184610Salfred {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1363184610Salfred {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1364184610Salfred {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1365184610Salfred {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1366184610Salfred {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1367184610Salfred {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1368184610Salfred {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, 1369184610Salfred {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, 1370184610Salfred {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, 1371184610Salfred {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, 1372194677Sthompsa {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, 1373184610Salfred {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, 1374194677Sthompsa {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, 1375194677Sthompsa {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, 1376194677Sthompsa {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, 1377194677Sthompsa {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, 1378194677Sthompsa {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, 1379194677Sthompsa {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, 1380194228Sthompsa {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, 1381184610Salfred {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, 1382184610Salfred {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, 1383184610Salfred {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, 1384194677Sthompsa {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, 1385194677Sthompsa {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, 1386184610Salfred {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, 1387184610Salfred {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, 1388184610Salfred {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, 1389184610Salfred {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, 1390184610Salfred {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, 1391184610Salfred {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, 1392184610Salfred {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, 1393184610Salfred {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, 1394184610Salfred {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, 1395194677Sthompsa {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, 1396184610Salfred {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, 1397184610Salfred {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, 1398194677Sthompsa {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, 1399184610Salfred {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, 1400184610Salfred {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, 1401184610Salfred {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, 1402194677Sthompsa {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, 1403184610Salfred {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, 1404194677Sthompsa {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, 1405194677Sthompsa {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, 1406194677Sthompsa {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, 1407194677Sthompsa {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, 1408194677Sthompsa {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, 1409194677Sthompsa {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, 1410184610Salfred {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, 1411194677Sthompsa {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, 1412194677Sthompsa {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, 1413184610Salfred {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, 1414184610Salfred {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, 1415194677Sthompsa {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, 1416194677Sthompsa 1417194677Sthompsa /* Filter out Bcc with cond=E or F, which are used for other instructions. */ 1418184610Salfred {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, 1419194677Sthompsa {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, 1420184610Salfred {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, 1421184610Salfred {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, 1422184610Salfred 1423184610Salfred /* These have been 32-bit since the invention of Thumb. */ 1424184610Salfred {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"}, 1425184610Salfred {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, 1426184610Salfred 1427184610Salfred /* Fallback. */ 1428184610Salfred {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"}, 1429184610Salfred {0, 0, 0, 0} 1430184610Salfred}; 1431184610Salfred 1432184610Salfredstatic const char *const arm_conditional[] = 1433184610Salfred{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 1434194677Sthompsa "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; 1435184610Salfred 1436194677Sthompsastatic const char *const arm_fp_const[] = 1437194677Sthompsa{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; 1438194677Sthompsa 1439194677Sthompsastatic const char *const arm_shift[] = 1440194677Sthompsa{"lsl", "lsr", "asr", "ror"}; 1441194677Sthompsa 1442194677Sthompsatypedef struct 1443194677Sthompsa{ 1444184610Salfred const char *name; 1445194228Sthompsa const char *description; 1446184610Salfred const char *reg_names[16]; 1447184610Salfred} 1448184610Salfredarm_regname; 1449194677Sthompsa 1450194677Sthompsastatic const arm_regname regnames[] = 1451184610Salfred{ 1452184610Salfred { "raw" , "Select raw register names", 1453184610Salfred { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, 1454184610Salfred { "gcc", "Select register names used by GCC", 1455184610Salfred { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, 1456184610Salfred { "std", "Select register names used in ARM's ISA documentation", 1457184610Salfred { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, 1458184610Salfred { "apcs", "Select register names used in the APCS", 1459184610Salfred { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, 1460194677Sthompsa { "atpcs", "Select register names used in the ATPCS", 1461184610Salfred { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, 1462184610Salfred { "special-atpcs", "Select special register names used in the ATPCS", 1463194677Sthompsa { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, 1464184610Salfred}; 1465184610Salfred 1466184610Salfredstatic const char *const iwmmxt_wwnames[] = 1467194677Sthompsa{"b", "h", "w", "d"}; 1468184610Salfred 1469194677Sthompsastatic const char *const iwmmxt_wwssnames[] = 1470184610Salfred{"b", "bus", "bc", "bss", 1471194677Sthompsa "h", "hus", "hc", "hss", 1472184610Salfred "w", "wus", "wc", "wss", 1473194677Sthompsa "d", "dus", "dc", "dss" 1474184610Salfred}; 1475194677Sthompsa 1476194677Sthompsastatic const char *const iwmmxt_regnames[] = 1477184610Salfred{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", 1478184610Salfred "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" 1479184610Salfred}; 1480184610Salfred 1481184610Salfredstatic const char *const iwmmxt_cregnames[] = 1482184610Salfred{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", 1483184610Salfred "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" 1484184610Salfred}; 1485184610Salfred 1486184610Salfred/* Default to GCC register name set. */ 1487194677Sthompsastatic unsigned int regname_selected = 1; 1488184610Salfred 1489184610Salfred#define NUM_ARM_REGNAMES NUM_ELEM (regnames) 1490194677Sthompsa#define arm_regnames regnames[regname_selected].reg_names 1491194677Sthompsa 1492184610Salfredstatic bfd_boolean force_thumb = FALSE; 1493184610Salfred 1494184610Salfred/* Current IT instruction state. This contains the same state as the IT 1495184610Salfred bits in the CPSR. */ 1496184610Salfredstatic unsigned int ifthen_state; 1497189905Sthompsa/* IT state for the next instruction. */ 1498184610Salfredstatic unsigned int ifthen_next_state; 1499184610Salfred/* The address of the insn for which the IT state is valid. */ 1500184610Salfredstatic bfd_vma ifthen_address; 1501184610Salfred#define IFTHEN_COND ((ifthen_state >> 4) & 0xf) 1502184610Salfred 1503184610Salfred/* Cached mapping symbol state. */ 1504184610Salfredenum map_type { 1505184610Salfred MAP_ARM, 1506184610Salfred MAP_THUMB, 1507184610Salfred MAP_DATA 1508184610Salfred}; 1509184610Salfred 1510184610Salfredenum map_type last_type; 1511184610Salfredint last_mapping_sym = -1; 1512184610Salfredbfd_vma last_mapping_addr = 0; 1513184610Salfred 1514184610Salfred 1515184610Salfred/* Functions. */ 1516184610Salfredint 1517184610Salfredget_arm_regname_num_options (void) 1518184610Salfred{ 1519184610Salfred return NUM_ARM_REGNAMES; 1520184610Salfred} 1521184610Salfred 1522184610Salfredint 1523184610Salfredset_arm_regname_option (int option) 1524184610Salfred{ 1525184610Salfred int old = regname_selected; 1526184610Salfred regname_selected = option; 1527184610Salfred return old; 1528184610Salfred} 1529184610Salfred 1530184610Salfredint 1531184610Salfredget_arm_regnames (int option, const char **setname, const char **setdescription, 1532184610Salfred const char *const **register_names) 1533184610Salfred{ 1534184610Salfred *setname = regnames[option].name; 1535184610Salfred *setdescription = regnames[option].description; 1536184610Salfred *register_names = regnames[option].reg_names; 1537184610Salfred return 16; 1538184610Salfred} 1539184610Salfred 1540184610Salfred/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?. 1541184610Salfred Returns pointer to following character of the format string and 1542184610Salfred fills in *VALUEP and *WIDTHP with the extracted value and number of 1543184610Salfred bits extracted. WIDTHP can be NULL. */ 1544184610Salfred 1545184610Salfredstatic const char * 1546184610Salfredarm_decode_bitfield (const char *ptr, unsigned long insn, 1547184610Salfred unsigned long *valuep, int *widthp) 1548184610Salfred{ 1549184610Salfred unsigned long value = 0; 1550184610Salfred int width = 0; 1551184610Salfred 1552184610Salfred do 1553184610Salfred { 1554184610Salfred int start, end; 1555184610Salfred int bits; 1556184610Salfred 1557184610Salfred for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) 1558184610Salfred start = start * 10 + *ptr - '0'; 1559184610Salfred if (*ptr == '-') 1560184610Salfred for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) 1561184610Salfred end = end * 10 + *ptr - '0'; 1562184610Salfred else 1563184610Salfred end = start; 1564194677Sthompsa bits = end - start; 1565194228Sthompsa if (bits < 0) 1566184610Salfred abort (); 1567184610Salfred value |= ((insn >> start) & ((2ul << bits) - 1)) << width; 1568184610Salfred width += bits + 1; 1569184610Salfred } 1570184610Salfred while (*ptr++ == ','); 1571194677Sthompsa *valuep = value; 1572184610Salfred if (widthp) 1573194677Sthompsa *widthp = width; 1574184610Salfred return ptr - 1; 1575194677Sthompsa} 1576184610Salfred 1577184610Salfredstatic void 1578184610Salfredarm_decode_shift (long given, fprintf_ftype func, void *stream, 1579184610Salfred int print_shift) 1580184610Salfred{ 1581184610Salfred func (stream, "%s", arm_regnames[given & 0xf]); 1582184610Salfred 1583184610Salfred if ((given & 0xff0) != 0) 1584184610Salfred { 1585184610Salfred if ((given & 0x10) == 0) 1586184610Salfred { 1587184610Salfred int amount = (given & 0xf80) >> 7; 1588184610Salfred int shift = (given & 0x60) >> 5; 1589184610Salfred 1590184610Salfred if (amount == 0) 1591184610Salfred { 1592184610Salfred if (shift == 3) 1593184610Salfred { 1594184610Salfred func (stream, ", rrx"); 1595184610Salfred return; 1596184610Salfred } 1597184610Salfred 1598184610Salfred amount = 32; 1599184610Salfred } 1600184610Salfred 1601184610Salfred if (print_shift) 1602184610Salfred func (stream, ", %s #%d", arm_shift[shift], amount); 1603184610Salfred else 1604184610Salfred func (stream, ", #%d", amount); 1605184610Salfred } 1606184610Salfred else if (print_shift) 1607184610Salfred func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], 1608184610Salfred arm_regnames[(given & 0xf00) >> 8]); 1609184610Salfred else 1610194228Sthompsa func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); 1611184610Salfred } 1612184610Salfred} 1613184610Salfred 1614184610Salfred/* Print one coprocessor instruction on INFO->STREAM. 1615184610Salfred Return TRUE if the instuction matched, FALSE if this is not a 1616184610Salfred recognised coprocessor instruction. */ 1617184610Salfred 1618184610Salfredstatic bfd_boolean 1619184610Salfredprint_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, 1620192984Sthompsa bfd_boolean thumb) 1621193045Sthompsa{ 1622184610Salfred const struct opcode32 *insn; 1623184610Salfred void *stream = info->stream; 1624184610Salfred fprintf_ftype func = info->fprintf_func; 1625184610Salfred unsigned long mask; 1626184610Salfred unsigned long value; 1627184610Salfred int cond; 1628184610Salfred 1629184610Salfred for (insn = coprocessor_opcodes; insn->assembler; insn++) 1630184610Salfred { 1631184610Salfred if (insn->value == FIRST_IWMMXT_INSN 1632194228Sthompsa && info->mach != bfd_mach_arm_XScale 1633184610Salfred && info->mach != bfd_mach_arm_iWMMXt 1634184610Salfred && info->mach != bfd_mach_arm_iWMMXt2) 1635184610Salfred insn = insn + IWMMXT_INSN_COUNT; 1636184610Salfred 1637184610Salfred mask = insn->mask; 1638194228Sthompsa value = insn->value; 1639184610Salfred if (thumb) 1640184610Salfred { 1641184610Salfred /* The high 4 bits are 0xe for Arm conditional instructions, and 1642184610Salfred 0xe for arm unconditional instructions. The rest of the 1643184610Salfred encoding is the same. */ 1644184610Salfred mask |= 0xf0000000; 1645184610Salfred value |= 0xe0000000; 1646184610Salfred if (ifthen_state) 1647184610Salfred cond = IFTHEN_COND; 1648184610Salfred else 1649184610Salfred cond = 16; 1650184610Salfred } 1651184610Salfred else 1652184610Salfred { 1653184610Salfred /* Only match unconditional instuctions against unconditional 1654184610Salfred patterns. */ 1655184610Salfred if ((given & 0xf0000000) == 0xf0000000) 1656184610Salfred { 1657184610Salfred mask |= 0xf0000000; 1658184610Salfred cond = 16; 1659184610Salfred } 1660184610Salfred else 1661184610Salfred { 1662184610Salfred cond = (given >> 28) & 0xf; 1663184610Salfred if (cond == 0xe) 1664184610Salfred cond = 16; 1665184610Salfred } 1666194677Sthompsa } 1667184610Salfred if ((given & mask) == value) 1668194677Sthompsa { 1669192984Sthompsa const char *c; 1670194677Sthompsa 1671184610Salfred for (c = insn->assembler; *c; c++) 1672184610Salfred { 1673184610Salfred if (*c == '%') 1674184610Salfred { 1675184610Salfred switch (*++c) 1676184610Salfred { 1677184610Salfred case '%': 1678203145Sthompsa func (stream, "%%"); 1679184610Salfred break; 1680184610Salfred 1681184610Salfred case 'A': 1682184610Salfred func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 1683184610Salfred 1684184610Salfred if ((given & (1 << 24)) != 0) 1685184610Salfred { 1686184610Salfred int offset = given & 0xff; 1687184610Salfred 1688184610Salfred if (offset) 1689184610Salfred func (stream, ", #%s%d]%s", 1690184610Salfred ((given & 0x00800000) == 0 ? "-" : ""), 1691184610Salfred offset * 4, 1692184610Salfred ((given & 0x00200000) != 0 ? "!" : "")); 1693184610Salfred else 1694184610Salfred func (stream, "]"); 1695184610Salfred } 1696184610Salfred else 1697184610Salfred { 1698184610Salfred int offset = given & 0xff; 1699184610Salfred 1700184610Salfred func (stream, "]"); 1701184610Salfred 1702184610Salfred if (given & (1 << 21)) 1703184610Salfred { 1704184610Salfred if (offset) 1705184610Salfred func (stream, ", #%s%d", 1706184610Salfred ((given & 0x00800000) == 0 ? "-" : ""), 1707184610Salfred offset * 4); 1708184610Salfred } 1709184610Salfred else 1710184610Salfred func (stream, ", {%d}", offset); 1711184610Salfred } 1712184610Salfred break; 1713184610Salfred 1714184610Salfred case 'B': 1715184610Salfred { 1716194677Sthompsa int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); 1717194677Sthompsa int offset = (given >> 1) & 0x3f; 1718194677Sthompsa 1719194677Sthompsa if (offset == 1) 1720184610Salfred func (stream, "{d%d}", regno); 1721194677Sthompsa else if (regno + offset > 32) 1722194677Sthompsa func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); 1723194677Sthompsa else 1724194228Sthompsa func (stream, "{d%d-d%d}", regno, regno + offset - 1); 1725203145Sthompsa } 1726184610Salfred break; 1727184610Salfred 1728203145Sthompsa case 'C': 1729203145Sthompsa { 1730203145Sthompsa int rn = (given >> 16) & 0xf; 1731203145Sthompsa int offset = (given & 0xff) * 4; 1732203145Sthompsa int add = (given >> 23) & 1; 1733184610Salfred 1734184610Salfred func (stream, "[%s", arm_regnames[rn]); 1735184610Salfred 1736184610Salfred if (offset) 1737184610Salfred { 1738194677Sthompsa if (!add) 1739184610Salfred offset = -offset; 1740184610Salfred func (stream, ", #%d", offset); 1741194677Sthompsa } 1742184610Salfred func (stream, "]"); 1743184610Salfred if (rn == 15) 1744184610Salfred { 1745194677Sthompsa func (stream, "\t; "); 1746184610Salfred /* FIXME: Unsure if info->bytes_per_chunk is the 1747194677Sthompsa right thing to use here. */ 1748184610Salfred info->print_address_func (offset + pc 1749184610Salfred + info->bytes_per_chunk * 2, info); 1750184610Salfred } 1751184610Salfred } 1752184610Salfred break; 1753194677Sthompsa 1754184610Salfred case 'c': 1755184610Salfred func (stream, "%s", arm_conditional[cond]); 1756184610Salfred break; 1757194677Sthompsa 1758184610Salfred case 'I': 1759184610Salfred /* Print a Cirrus/DSP shift immediate. */ 1760194677Sthompsa /* Immediates are 7bit signed ints with bits 0..3 in 1761184610Salfred bits 0..3 of opcode and bits 4..6 in bits 5..7 1762184610Salfred of opcode. */ 1763184610Salfred { 1764192984Sthompsa int imm; 1765194677Sthompsa 1766184610Salfred imm = (given & 0xf) | ((given & 0xe0) >> 1); 1767194677Sthompsa 1768184610Salfred /* Is ``imm'' a negative number? */ 1769184610Salfred if (imm & 0x40) 1770184610Salfred imm |= (-1 << 7); 1771184610Salfred 1772184610Salfred func (stream, "%d", imm); 1773184610Salfred } 1774184610Salfred 1775184610Salfred break; 1776184610Salfred 1777203145Sthompsa case 'F': 1778184610Salfred switch (given & 0x00408000) 1779184610Salfred { 1780194228Sthompsa case 0: 1781184610Salfred func (stream, "4"); 1782184610Salfred break; 1783203145Sthompsa case 0x8000: 1784184610Salfred func (stream, "1"); 1785184610Salfred break; 1786194677Sthompsa case 0x00400000: 1787203145Sthompsa func (stream, "2"); 1788184610Salfred break; 1789184610Salfred default: 1790184610Salfred func (stream, "3"); 1791184610Salfred } 1792184610Salfred break; 1793194677Sthompsa 1794184610Salfred case 'P': 1795194677Sthompsa switch (given & 0x00080080) 1796184610Salfred { 1797192984Sthompsa case 0: 1798194677Sthompsa func (stream, "s"); 1799184610Salfred break; 1800184610Salfred case 0x80: 1801184610Salfred func (stream, "d"); 1802184610Salfred break; 1803184610Salfred case 0x00080000: 1804184610Salfred func (stream, "e"); 1805184610Salfred break; 1806184610Salfred default: 1807184610Salfred func (stream, _("<illegal precision>")); 1808184610Salfred break; 1809184610Salfred } 1810203145Sthompsa break; 1811184610Salfred case 'Q': 1812184610Salfred switch (given & 0x00408000) 1813184610Salfred { 1814184610Salfred case 0: 1815184610Salfred func (stream, "s"); 1816184610Salfred break; 1817184610Salfred case 0x8000: 1818184610Salfred func (stream, "d"); 1819184610Salfred break; 1820184610Salfred case 0x00400000: 1821184610Salfred func (stream, "e"); 1822184610Salfred break; 1823184610Salfred default: 1824184610Salfred func (stream, "p"); 1825184610Salfred break; 1826184610Salfred } 1827184610Salfred break; 1828184610Salfred case 'R': 1829184610Salfred switch (given & 0x60) 1830184610Salfred { 1831194677Sthompsa case 0: 1832194677Sthompsa break; 1833194677Sthompsa case 0x20: 1834194677Sthompsa func (stream, "p"); 1835184610Salfred break; 1836184610Salfred case 0x40: 1837194677Sthompsa func (stream, "m"); 1838194677Sthompsa break; 1839194677Sthompsa default: 1840194677Sthompsa func (stream, "z"); 1841184610Salfred break; 1842184610Salfred } 1843184610Salfred break; 1844184610Salfred 1845184610Salfred case '0': case '1': case '2': case '3': case '4': 1846184610Salfred case '5': case '6': case '7': case '8': case '9': 1847194228Sthompsa { 1848184610Salfred int width; 1849203145Sthompsa unsigned long value; 1850184610Salfred 1851184610Salfred c = arm_decode_bitfield (c, given, &value, &width); 1852194677Sthompsa 1853203145Sthompsa switch (*c) 1854203145Sthompsa { 1855203145Sthompsa case 'r': 1856184610Salfred func (stream, "%s", arm_regnames[value]); 1857184610Salfred break; 1858184610Salfred case 'D': 1859184610Salfred func (stream, "d%ld", value); 1860194677Sthompsa break; 1861184610Salfred case 'Q': 1862194677Sthompsa if (value & 1) 1863194677Sthompsa func (stream, "<illegal reg q%ld.5>", value >> 1); 1864194677Sthompsa else 1865194677Sthompsa func (stream, "q%ld", value >> 1); 1866194677Sthompsa break; 1867194677Sthompsa case 'd': 1868184610Salfred func (stream, "%ld", value); 1869194677Sthompsa break; 1870194677Sthompsa case 'k': 1871184610Salfred { 1872184610Salfred int from = (given & (1 << 7)) ? 32 : 16; 1873194677Sthompsa func (stream, "%ld", from - value); 1874194677Sthompsa } 1875194677Sthompsa break; 1876194677Sthompsa 1877194677Sthompsa case 'f': 1878194677Sthompsa if (value > 7) 1879194677Sthompsa func (stream, "#%s", arm_fp_const[value & 7]); 1880184610Salfred else 1881194677Sthompsa func (stream, "f%ld", value); 1882184610Salfred break; 1883184610Salfred 1884184610Salfred case 'w': 1885184610Salfred if (width == 2) 1886184610Salfred func (stream, "%s", iwmmxt_wwnames[value]); 1887184610Salfred else 1888184610Salfred func (stream, "%s", iwmmxt_wwssnames[value]); 1889184610Salfred break; 1890184610Salfred 1891203145Sthompsa case 'g': 1892184610Salfred func (stream, "%s", iwmmxt_regnames[value]); 1893184610Salfred break; 1894184610Salfred case 'G': 1895184610Salfred func (stream, "%s", iwmmxt_cregnames[value]); 1896194677Sthompsa break; 1897184610Salfred 1898194677Sthompsa case 'x': 1899194677Sthompsa func (stream, "0x%lx", value); 1900194677Sthompsa break; 1901194677Sthompsa 1902194677Sthompsa case '`': 1903194677Sthompsa c++; 1904194228Sthompsa if (value == 0) 1905203145Sthompsa func (stream, "%c", *c); 1906184610Salfred break; 1907184610Salfred case '\'': 1908194677Sthompsa c++; 1909184610Salfred if (value == ((1ul << width) - 1)) 1910194677Sthompsa func (stream, "%c", *c); 1911184610Salfred break; 1912184610Salfred case '?': 1913184610Salfred func (stream, "%c", c[(1 << width) - (int)value]); 1914203145Sthompsa c += 1 << width; 1915184610Salfred break; 1916184610Salfred default: 1917184610Salfred abort (); 1918184610Salfred } 1919184610Salfred break; 1920194677Sthompsa 1921184610Salfred case 'y': 1922184610Salfred case 'z': 1923194677Sthompsa { 1924184610Salfred int single = *c++ == 'y'; 1925184610Salfred int regno; 1926184610Salfred 1927194677Sthompsa switch (*c) 1928184610Salfred { 1929194677Sthompsa case '4': /* Sm pair */ 1930194677Sthompsa func (stream, "{"); 1931194677Sthompsa /* Fall through. */ 1932194677Sthompsa case '0': /* Sm, Dm */ 1933194677Sthompsa regno = given & 0x0000000f; 1934194677Sthompsa if (single) 1935184610Salfred { 1936194677Sthompsa regno <<= 1; 1937194677Sthompsa regno += (given >> 5) & 1; 1938184610Salfred } 1939184610Salfred else 1940194677Sthompsa regno += ((given >> 5) & 1) << 4; 1941194677Sthompsa break; 1942194677Sthompsa 1943184610Salfred case '1': /* Sd, Dd */ 1944194677Sthompsa regno = (given >> 12) & 0x0000000f; 1945184610Salfred if (single) 1946184610Salfred { 1947184610Salfred regno <<= 1; 1948184610Salfred regno += (given >> 22) & 1; 1949184610Salfred } 1950184610Salfred else 1951184610Salfred regno += ((given >> 22) & 1) << 4; 1952184610Salfred break; 1953184610Salfred 1954203145Sthompsa case '2': /* Sn, Dn */ 1955184610Salfred regno = (given >> 16) & 0x0000000f; 1956184610Salfred if (single) 1957184610Salfred { 1958184610Salfred regno <<= 1; 1959194677Sthompsa regno += (given >> 7) & 1; 1960184610Salfred } 1961194677Sthompsa else 1962194677Sthompsa regno += ((given >> 7) & 1) << 4; 1963194677Sthompsa break; 1964194677Sthompsa 1965194677Sthompsa case '3': /* List */ 1966194677Sthompsa func (stream, "{"); 1967194677Sthompsa regno = (given >> 12) & 0x0000000f; 1968194677Sthompsa if (single) 1969184610Salfred { 1970194228Sthompsa regno <<= 1; 1971203145Sthompsa regno += (given >> 22) & 1; 1972184610Salfred } 1973184610Salfred else 1974194677Sthompsa regno += ((given >> 22) & 1) << 4; 1975184610Salfred break; 1976194677Sthompsa 1977184610Salfred default: 1978184610Salfred abort (); 1979184610Salfred } 1980203145Sthompsa 1981184610Salfred func (stream, "%c%d", single ? 's' : 'd', regno); 1982184610Salfred 1983184610Salfred if (*c == '3') 1984184610Salfred { 1985184610Salfred int count = given & 0xff; 1986194677Sthompsa 1987184610Salfred if (single == 0) 1988184610Salfred count >>= 1; 1989194677Sthompsa 1990184610Salfred if (--count) 1991184610Salfred { 1992184610Salfred func (stream, "-%c%d", 1993194677Sthompsa single ? 's' : 'd', 1994184610Salfred regno + count); 1995194677Sthompsa } 1996184610Salfred 1997194677Sthompsa func (stream, "}"); 1998184610Salfred } 1999184610Salfred else if (*c == '4') 2000194677Sthompsa func (stream, ", %c%d}", single ? 's' : 'd', 2001184610Salfred regno + 1); 2002194677Sthompsa } 2003194677Sthompsa break; 2004184610Salfred 2005184610Salfred case 'L': 2006184610Salfred switch (given & 0x00400100) 2007194677Sthompsa { 2008184610Salfred case 0x00000000: func (stream, "b"); break; 2009184610Salfred case 0x00400000: func (stream, "h"); break; 2010194677Sthompsa case 0x00000100: func (stream, "w"); break; 2011194677Sthompsa case 0x00400100: func (stream, "d"); break; 2012184610Salfred default: 2013184610Salfred break; 2014184610Salfred } 2015184610Salfred break; 2016184610Salfred 2017184610Salfred case 'Z': 2018184610Salfred { 2019184610Salfred int value; 2020184610Salfred /* given (20, 23) | given (0, 3) */ 2021184610Salfred value = ((given >> 16) & 0xf0) | (given & 0xf); 2022184610Salfred func (stream, "%d", value); 2023184610Salfred } 2024184610Salfred break; 2025184610Salfred 2026184610Salfred case 'l': 2027184610Salfred /* This is like the 'A' operator, except that if 2028184610Salfred the width field "M" is zero, then the offset is 2029184610Salfred *not* multiplied by four. */ 2030184610Salfred { 2031184610Salfred int offset = given & 0xff; 2032184610Salfred int multiplier = (given & 0x00000100) ? 4 : 1; 2033184610Salfred 2034184610Salfred func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 2035184610Salfred 2036184610Salfred if (offset) 2037184610Salfred { 2038184610Salfred if ((given & 0x01000000) != 0) 2039184610Salfred func (stream, ", #%s%d]%s", 2040184610Salfred ((given & 0x00800000) == 0 ? "-" : ""), 2041203145Sthompsa offset * multiplier, 2042184610Salfred ((given & 0x00200000) != 0 ? "!" : "")); 2043184610Salfred else 2044184610Salfred func (stream, "], #%s%d", 2045184610Salfred ((given & 0x00800000) == 0 ? "-" : ""), 2046184610Salfred offset * multiplier); 2047184610Salfred } 2048184610Salfred else 2049184610Salfred func (stream, "]"); 2050184610Salfred } 2051184610Salfred break; 2052184610Salfred 2053184610Salfred case 'r': 2054184610Salfred { 2055184610Salfred int imm4 = (given >> 4) & 0xf; 2056184610Salfred int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1); 2057184610Salfred int ubit = (given >> 23) & 1; 2058184610Salfred const char *rm = arm_regnames [given & 0xf]; 2059184610Salfred const char *rn = arm_regnames [(given >> 16) & 0xf]; 2060184610Salfred 2061184610Salfred switch (puw_bits) 2062184610Salfred { 2063184610Salfred case 1: 2064184610Salfred /* fall through */ 2065184610Salfred case 3: 2066203145Sthompsa func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 2067184610Salfred if (imm4) 2068184610Salfred func (stream, ", lsl #%d", imm4); 2069184610Salfred break; 2070184610Salfred 2071184610Salfred case 4: 2072184610Salfred /* fall through */ 2073184610Salfred case 5: 2074194677Sthompsa /* fall through */ 2075194228Sthompsa case 6: 2076203145Sthompsa /* fall through */ 2077184610Salfred case 7: 2078184610Salfred func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 2079184610Salfred if (imm4 > 0) 2080194677Sthompsa func (stream, ", lsl #%d", imm4); 2081194677Sthompsa func (stream, "]"); 2082203145Sthompsa if (puw_bits == 5 || puw_bits == 7) 2083184610Salfred func (stream, "!"); 2084184610Salfred break; 2085184610Salfred 2086184610Salfred default: 2087184610Salfred func (stream, "INVALID"); 2088184610Salfred } 2089184610Salfred } 2090184610Salfred break; 2091184610Salfred 2092184610Salfred case 'i': 2093184610Salfred { 2094184610Salfred long imm5; 2095184610Salfred imm5 = ((given & 0x100) >> 4) | (given & 0xf); 2096184610Salfred func (stream, "%ld", (imm5 == 0) ? 32 : imm5); 2097184610Salfred } 2098184610Salfred break; 2099184610Salfred 2100184610Salfred default: 2101184610Salfred abort (); 2102184610Salfred } 2103184610Salfred } 2104184610Salfred } 2105184610Salfred else 2106184610Salfred func (stream, "%c", *c); 2107184610Salfred } 2108184610Salfred return TRUE; 2109184610Salfred } 2110184610Salfred } 2111184610Salfred return FALSE; 2112184610Salfred} 2113188415Sthompsa 2114184610Salfredstatic void 2115184610Salfredprint_arm_address (bfd_vma pc, struct disassemble_info *info, long given) 2116184610Salfred{ 2117184610Salfred void *stream = info->stream; 2118184610Salfred fprintf_ftype func = info->fprintf_func; 2119184610Salfred 2120184610Salfred if (((given & 0x000f0000) == 0x000f0000) 2121184610Salfred && ((given & 0x02000000) == 0)) 2122184610Salfred { 2123184610Salfred int offset = given & 0xfff; 2124184610Salfred 2125188415Sthompsa func (stream, "[pc"); 2126184610Salfred 2127184610Salfred if (given & 0x01000000) 2128184610Salfred { 2129184610Salfred if ((given & 0x00800000) == 0) 2130188415Sthompsa offset = - offset; 2131184610Salfred 2132184610Salfred /* Pre-indexed. */ 2133184610Salfred func (stream, ", #%d]", offset); 2134184610Salfred 2135184610Salfred offset += pc + 8; 2136188415Sthompsa 2137184610Salfred /* Cope with the possibility of write-back 2138184610Salfred being used. Probably a very dangerous thing 2139184610Salfred for the programmer to do, but who are we to 2140184610Salfred argue ? */ 2141184610Salfred if (given & 0x00200000) 2142184610Salfred func (stream, "!"); 2143188415Sthompsa } 2144184610Salfred else 2145184610Salfred { 2146184610Salfred /* Post indexed. */ 2147184610Salfred func (stream, "], #%d", offset); 2148184610Salfred 2149184610Salfred /* ie ignore the offset. */ 2150184610Salfred offset = pc + 8; 2151184610Salfred } 2152184610Salfred 2153184610Salfred func (stream, "\t; "); 2154184610Salfred info->print_address_func (offset, info); 2155184610Salfred } 2156184610Salfred else 2157184610Salfred { 2158184610Salfred func (stream, "[%s", 2159184610Salfred arm_regnames[(given >> 16) & 0xf]); 2160184610Salfred if ((given & 0x01000000) != 0) 2161184610Salfred { 2162184610Salfred if ((given & 0x02000000) == 0) 2163184610Salfred { 2164184610Salfred int offset = given & 0xfff; 2165184610Salfred if (offset) 2166184610Salfred func (stream, ", #%s%d", 2167188415Sthompsa (((given & 0x00800000) == 0) 2168184610Salfred ? "-" : ""), offset); 2169184610Salfred } 2170184610Salfred else 2171188415Sthompsa { 2172184610Salfred func (stream, ", %s", 2173199816Sthompsa (((given & 0x00800000) == 0) 2174184610Salfred ? "-" : "")); 2175184610Salfred arm_decode_shift (given, func, stream, 1); 2176184610Salfred } 2177184610Salfred 2178184610Salfred func (stream, "]%s", 2179184610Salfred ((given & 0x00200000) != 0) ? "!" : ""); 2180184610Salfred } 2181184610Salfred else 2182184610Salfred { 2183184610Salfred if ((given & 0x02000000) == 0) 2184184610Salfred { 2185184610Salfred int offset = given & 0xfff; 2186184610Salfred if (offset) 2187184610Salfred func (stream, "], #%s%d", 2188184610Salfred (((given & 0x00800000) == 0) 2189198307Sthompsa ? "-" : ""), offset); 2190198307Sthompsa else 2191198307Sthompsa func (stream, "]"); 2192184610Salfred } 2193184610Salfred else 2194184610Salfred { 2195184610Salfred func (stream, "], %s", 2196184610Salfred (((given & 0x00800000) == 0) 2197188415Sthompsa ? "-" : "")); 2198184610Salfred arm_decode_shift (given, func, stream, 1); 2199184610Salfred } 2200184610Salfred } 2201184610Salfred } 2202184610Salfred} 2203184610Salfred 2204184610Salfred/* Print one neon instruction on INFO->STREAM. 2205184610Salfred Return TRUE if the instuction matched, FALSE if this is not a 2206184610Salfred recognised neon instruction. */ 2207184610Salfred 2208184610Salfredstatic bfd_boolean 2209184610Salfredprint_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) 2210184610Salfred{ 2211184610Salfred const struct opcode32 *insn; 2212184610Salfred void *stream = info->stream; 2213184610Salfred fprintf_ftype func = info->fprintf_func; 2214184610Salfred 2215184610Salfred if (thumb) 2216184610Salfred { 2217184610Salfred if ((given & 0xef000000) == 0xef000000) 2218184610Salfred { 2219184610Salfred /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */ 2220184610Salfred unsigned long bit28 = given & (1 << 28); 2221184610Salfred 2222184610Salfred given &= 0x00ffffff; 2223184610Salfred if (bit28) 2224184610Salfred given |= 0xf3000000; 2225184610Salfred else 2226184610Salfred given |= 0xf2000000; 2227184610Salfred } 2228184610Salfred else if ((given & 0xff000000) == 0xf9000000) 2229184610Salfred given ^= 0xf9000000 ^ 0xf4000000; 2230184610Salfred else 2231184610Salfred return FALSE; 2232184610Salfred } 2233184610Salfred 2234184610Salfred for (insn = neon_opcodes; insn->assembler; insn++) 2235184610Salfred { 2236184610Salfred if ((given & insn->mask) == insn->value) 2237184610Salfred { 2238184610Salfred const char *c; 2239184610Salfred 2240184610Salfred for (c = insn->assembler; *c; c++) 2241184610Salfred { 2242184610Salfred if (*c == '%') 2243184610Salfred { 2244184610Salfred switch (*++c) 2245184610Salfred { 2246184610Salfred case '%': 2247184610Salfred func (stream, "%%"); 2248184610Salfred break; 2249184610Salfred 2250184610Salfred case 'c': 2251184610Salfred if (thumb && ifthen_state) 2252184610Salfred func (stream, "%s", arm_conditional[IFTHEN_COND]); 2253184610Salfred break; 2254184610Salfred 2255184610Salfred case 'A': 2256184610Salfred { 2257184610Salfred static const unsigned char enc[16] = 2258184610Salfred { 2259184610Salfred 0x4, 0x14, /* st4 0,1 */ 2260184610Salfred 0x4, /* st1 2 */ 2261184610Salfred 0x4, /* st2 3 */ 2262184610Salfred 0x3, /* st3 4 */ 2263184610Salfred 0x13, /* st3 5 */ 2264184610Salfred 0x3, /* st1 6 */ 2265184610Salfred 0x1, /* st1 7 */ 2266184610Salfred 0x2, /* st2 8 */ 2267184610Salfred 0x12, /* st2 9 */ 2268184610Salfred 0x2, /* st1 10 */ 2269184610Salfred 0, 0, 0, 0, 0 2270184610Salfred }; 2271184610Salfred int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 2272184610Salfred int rn = ((given >> 16) & 0xf); 2273184610Salfred int rm = ((given >> 0) & 0xf); 2274184610Salfred int align = ((given >> 4) & 0x3); 2275184610Salfred int type = ((given >> 8) & 0xf); 2276184610Salfred int n = enc[type] & 0xf; 2277184610Salfred int stride = (enc[type] >> 4) + 1; 2278184610Salfred int ix; 2279184610Salfred 2280184610Salfred func (stream, "{"); 2281184610Salfred if (stride > 1) 2282184610Salfred for (ix = 0; ix != n; ix++) 2283184610Salfred func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); 2284184610Salfred else if (n == 1) 2285184610Salfred func (stream, "d%d", rd); 2286184610Salfred else 2287184610Salfred func (stream, "d%d-d%d", rd, rd + n - 1); 2288184610Salfred func (stream, "}, [%s", arm_regnames[rn]); 2289184610Salfred if (align) 2290184610Salfred func (stream, ", :%d", 32 << align); 2291184610Salfred func (stream, "]"); 2292184610Salfred if (rm == 0xd) 2293184610Salfred func (stream, "!"); 2294184610Salfred else if (rm != 0xf) 2295184610Salfred func (stream, ", %s", arm_regnames[rm]); 2296184610Salfred } 2297184610Salfred break; 2298184610Salfred 2299184610Salfred case 'B': 2300184610Salfred { 2301184610Salfred int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 2302184610Salfred int rn = ((given >> 16) & 0xf); 2303184610Salfred int rm = ((given >> 0) & 0xf); 2304184610Salfred int idx_align = ((given >> 4) & 0xf); 2305184610Salfred int align = 0; 2306184610Salfred int size = ((given >> 10) & 0x3); 2307184610Salfred int idx = idx_align >> (size + 1); 2308184610Salfred int length = ((given >> 8) & 3) + 1; 2309196826Strasz int stride = 1; 2310196826Strasz int i; 2311196826Strasz 2312196826Strasz if (length > 1 && size > 0) 2313196826Strasz stride = (idx_align & (1 << size)) ? 2 : 1; 2314196826Strasz 2315196826Strasz switch (length) 2316196826Strasz { 2317196826Strasz case 1: 2318196826Strasz { 2319196826Strasz int amask = (1 << size) - 1; 2320196826Strasz if ((idx_align & (1 << size)) != 0) 2321196826Strasz return FALSE; 2322196826Strasz if (size > 0) 2323196826Strasz { 2324196826Strasz if ((idx_align & amask) == amask) 2325196826Strasz align = 8 << size; 2326196826Strasz else if ((idx_align & amask) != 0) 2327196826Strasz return FALSE; 2328196826Strasz } 2329196826Strasz } 2330196826Strasz break; 2331184610Salfred 2332184610Salfred case 2: 2333184610Salfred if (size == 2 && (idx_align & 2) != 0) 2334184610Salfred return FALSE; 2335184610Salfred align = (idx_align & 1) ? 16 << size : 0; 2336184610Salfred break; 2337184610Salfred 2338184610Salfred case 3: 2339184610Salfred if ((size == 2 && (idx_align & 3) != 0) 2340184610Salfred || (idx_align & 1) != 0) 2341184610Salfred return FALSE; 2342184610Salfred break; 2343184610Salfred 2344184610Salfred case 4: 2345184610Salfred if (size == 2) 2346184610Salfred { 2347184610Salfred if ((idx_align & 3) == 3) 2348184610Salfred return FALSE; 2349184610Salfred align = (idx_align & 3) * 64; 2350184610Salfred } 2351184610Salfred else 2352184610Salfred align = (idx_align & 1) ? 32 << size : 0; 2353184610Salfred break; 2354184610Salfred 2355184610Salfred default: 2356184610Salfred abort (); 2357184610Salfred } 2358184610Salfred 2359184610Salfred func (stream, "{"); 2360184610Salfred for (i = 0; i < length; i++) 2361184610Salfred func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", 2362184610Salfred rd + i * stride, idx); 2363184610Salfred func (stream, "}, [%s", arm_regnames[rn]); 2364184610Salfred if (align) 2365184610Salfred func (stream, ", :%d", align); 2366184610Salfred func (stream, "]"); 2367184610Salfred if (rm == 0xd) 2368184610Salfred func (stream, "!"); 2369184610Salfred else if (rm != 0xf) 2370184610Salfred func (stream, ", %s", arm_regnames[rm]); 2371184610Salfred } 2372184610Salfred break; 2373184610Salfred 2374184610Salfred case 'C': 2375184610Salfred { 2376184610Salfred int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); 2377184610Salfred int rn = ((given >> 16) & 0xf); 2378184610Salfred int rm = ((given >> 0) & 0xf); 2379184610Salfred int align = ((given >> 4) & 0x1); 2380184610Salfred int size = ((given >> 6) & 0x3); 2381184610Salfred int type = ((given >> 8) & 0x3); 2382184610Salfred int n = type + 1; 2383184610Salfred int stride = ((given >> 5) & 0x1); 2384184610Salfred int ix; 2385184610Salfred 2386184610Salfred if (stride && (n == 1)) 2387184610Salfred n++; 2388184610Salfred else 2389184610Salfred stride++; 2390184610Salfred 2391184610Salfred func (stream, "{"); 2392184610Salfred if (stride > 1) 2393184610Salfred for (ix = 0; ix != n; ix++) 2394184610Salfred func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); 2395184610Salfred else if (n == 1) 2396184610Salfred func (stream, "d%d[]", rd); 2397184610Salfred else 2398184610Salfred func (stream, "d%d[]-d%d[]", rd, rd + n - 1); 2399184610Salfred func (stream, "}, [%s", arm_regnames[rn]); 2400184610Salfred if (align) 2401184610Salfred { 2402184610Salfred int align = (8 * (type + 1)) << size; 2403184610Salfred if (type == 3) 2404184610Salfred align = (size > 1) ? align >> 1 : align; 2405184610Salfred if (type == 2 || (type == 0 && !size)) 2406184610Salfred func (stream, ", :<bad align %d>", align); 2407184610Salfred else 2408184610Salfred func (stream, ", :%d", align); 2409184610Salfred } 2410184610Salfred func (stream, "]"); 2411184610Salfred if (rm == 0xd) 2412184610Salfred func (stream, "!"); 2413184610Salfred else if (rm != 0xf) 2414194228Sthompsa func (stream, ", %s", arm_regnames[rm]); 2415184610Salfred } 2416184610Salfred break; 2417184610Salfred 2418184610Salfred case 'D': 2419184610Salfred { 2420184610Salfred int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); 2421184610Salfred int size = (given >> 20) & 3; 2422184610Salfred int reg = raw_reg & ((4 << size) - 1); 2423184610Salfred int ix = raw_reg >> size >> 2; 2424184610Salfred 2425184610Salfred func (stream, "d%d[%d]", reg, ix); 2426184610Salfred } 2427184610Salfred break; 2428184610Salfred 2429184610Salfred case 'E': 2430184610Salfred /* Neon encoded constant for mov, mvn, vorr, vbic */ 2431184610Salfred { 2432184610Salfred int bits = 0; 2433184610Salfred int cmode = (given >> 8) & 0xf; 2434184610Salfred int op = (given >> 5) & 0x1; 2435184610Salfred unsigned long value = 0, hival = 0; 2436184610Salfred unsigned shift; 2437184610Salfred int size = 0; 2438184610Salfred int isfloat = 0; 2439184610Salfred 2440184610Salfred bits |= ((given >> 24) & 1) << 7; 2441184610Salfred bits |= ((given >> 16) & 7) << 4; 2442184610Salfred bits |= ((given >> 0) & 15) << 0; 2443184610Salfred 2444184610Salfred if (cmode < 8) 2445184610Salfred { 2446184610Salfred shift = (cmode >> 1) & 3; 2447184610Salfred value = (unsigned long)bits << (8 * shift); 2448184610Salfred size = 32; 2449184610Salfred } 2450184610Salfred else if (cmode < 12) 2451184610Salfred { 2452184610Salfred shift = (cmode >> 1) & 1; 2453184610Salfred value = (unsigned long)bits << (8 * shift); 2454184610Salfred size = 16; 2455184610Salfred } 2456184610Salfred else if (cmode < 14) 2457184610Salfred { 2458184610Salfred shift = (cmode & 1) + 1; 2459184610Salfred value = (unsigned long)bits << (8 * shift); 2460184610Salfred value |= (1ul << (8 * shift)) - 1; 2461184610Salfred size = 32; 2462184610Salfred } 2463184610Salfred else if (cmode == 14) 2464184610Salfred { 2465184610Salfred if (op) 2466184610Salfred { 2467184610Salfred /* bit replication into bytes */ 2468184610Salfred int ix; 2469184610Salfred unsigned long mask; 2470184610Salfred 2471184610Salfred value = 0; 2472184610Salfred hival = 0; 2473184610Salfred for (ix = 7; ix >= 0; ix--) 2474184610Salfred { 2475184610Salfred mask = ((bits >> ix) & 1) ? 0xff : 0; 2476184610Salfred if (ix <= 3) 2477184610Salfred value = (value << 8) | mask; 2478184610Salfred else 2479184610Salfred hival = (hival << 8) | mask; 2480184610Salfred } 2481184610Salfred size = 64; 2482184610Salfred } 2483184610Salfred else 2484184610Salfred { 2485184610Salfred /* byte replication */ 2486184610Salfred value = (unsigned long)bits; 2487184610Salfred size = 8; 2488184610Salfred } 2489184610Salfred } 2490184610Salfred else if (!op) 2491184610Salfred { 2492184610Salfred /* floating point encoding */ 2493184610Salfred int tmp; 2494184610Salfred 2495184610Salfred value = (unsigned long)(bits & 0x7f) << 19; 2496184610Salfred value |= (unsigned long)(bits & 0x80) << 24; 2497184610Salfred tmp = bits & 0x40 ? 0x3c : 0x40; 2498184610Salfred value |= (unsigned long)tmp << 24; 2499184610Salfred size = 32; 2500184610Salfred isfloat = 1; 2501184610Salfred } 2502184610Salfred else 2503188415Sthompsa { 2504184610Salfred func (stream, "<illegal constant %.8x:%x:%x>", 2505184610Salfred bits, cmode, op); 2506184610Salfred size = 32; 2507184610Salfred break; 2508184610Salfred } 2509184610Salfred switch (size) 2510184610Salfred { 2511184610Salfred case 8: 2512184610Salfred func (stream, "#%ld\t; 0x%.2lx", value, value); 2513184610Salfred break; 2514184610Salfred 2515184610Salfred case 16: 2516184610Salfred func (stream, "#%ld\t; 0x%.4lx", value, value); 2517184610Salfred break; 2518184610Salfred 2519194677Sthompsa case 32: 2520184610Salfred if (isfloat) 2521184610Salfred { 2522184610Salfred unsigned char valbytes[4]; 2523184610Salfred double fvalue; 2524184610Salfred 2525184610Salfred /* Do this a byte at a time so we don't have to 2526184610Salfred worry about the host's endianness. */ 2527184610Salfred valbytes[0] = value & 0xff; 2528184610Salfred valbytes[1] = (value >> 8) & 0xff; 2529184610Salfred valbytes[2] = (value >> 16) & 0xff; 2530184610Salfred valbytes[3] = (value >> 24) & 0xff; 2531184610Salfred 2532184610Salfred floatformat_to_double 2533184610Salfred (&floatformat_ieee_single_little, valbytes, 2534184610Salfred &fvalue); 2535184610Salfred 2536184610Salfred func (stream, "#%.7g\t; 0x%.8lx", fvalue, 2537184610Salfred value); 2538184610Salfred } 2539184610Salfred else 2540184610Salfred func (stream, "#%ld\t; 0x%.8lx", 2541184610Salfred (long) ((value & 0x80000000) 2542184610Salfred ? value | ~0xffffffffl : value), value); 2543184610Salfred break; 2544184610Salfred 2545184610Salfred case 64: 2546196826Strasz func (stream, "#0x%.8lx%.8lx", hival, value); 2547196826Strasz break; 2548196826Strasz 2549196826Strasz default: 2550196826Strasz abort (); 2551196826Strasz } 2552196826Strasz } 2553196826Strasz break; 2554196826Strasz 2555196826Strasz case 'F': 2556196826Strasz { 2557196826Strasz int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); 2558196826Strasz int num = (given >> 8) & 0x3; 2559196826Strasz 2560196826Strasz if (!num) 2561196826Strasz func (stream, "{d%d}", regno); 2562196826Strasz else if (num + regno >= 32) 2563196826Strasz func (stream, "{d%d-<overflow reg d%d}", regno, regno + num); 2564196826Strasz else 2565196826Strasz func (stream, "{d%d-d%d}", regno, regno + num); 2566196826Strasz } 2567196826Strasz break; 2568196826Strasz 2569184610Salfred 2570184610Salfred case '0': case '1': case '2': case '3': case '4': 2571184610Salfred case '5': case '6': case '7': case '8': case '9': 2572184610Salfred { 2573184610Salfred int width; 2574184610Salfred unsigned long value; 2575184610Salfred 2576184610Salfred c = arm_decode_bitfield (c, given, &value, &width); 2577184610Salfred 2578184610Salfred switch (*c) 2579184610Salfred { 2580184610Salfred case 'r': 2581184610Salfred func (stream, "%s", arm_regnames[value]); 2582184610Salfred break; 2583184610Salfred case 'd': 2584184610Salfred func (stream, "%ld", value); 2585184610Salfred break; 2586184610Salfred case 'e': 2587184610Salfred func (stream, "%ld", (1ul << width) - value); 2588184610Salfred break; 2589184610Salfred 2590184610Salfred case 'S': 2591184610Salfred case 'T': 2592184610Salfred case 'U': 2593184610Salfred /* various width encodings */ 2594184610Salfred { 2595184610Salfred int base = 8 << (*c - 'S'); /* 8,16 or 32 */ 2596184610Salfred int limit; 2597184610Salfred unsigned low, high; 2598203146Sthompsa 2599203146Sthompsa c++; 2600203146Sthompsa if (*c >= '0' && *c <= '9') 2601203146Sthompsa limit = *c - '0'; 2602203146Sthompsa else if (*c >= 'a' && *c <= 'f') 2603203146Sthompsa limit = *c - 'a' + 10; 2604184610Salfred else 2605203146Sthompsa abort (); 2606203146Sthompsa low = limit >> 2; 2607203146Sthompsa high = limit & 3; 2608203146Sthompsa 2609203146Sthompsa if (value < low || value > high) 2610203146Sthompsa func (stream, "<illegal width %d>", base << value); 2611184610Salfred else 2612184610Salfred func (stream, "%d", base << value); 2613184610Salfred } 2614184610Salfred break; 2615184610Salfred case 'R': 2616184610Salfred if (given & (1 << 6)) 2617184610Salfred goto Q; 2618184610Salfred /* FALLTHROUGH */ 2619184610Salfred case 'D': 2620184610Salfred func (stream, "d%ld", value); 2621184610Salfred break; 2622184610Salfred case 'Q': 2623184610Salfred Q: 2624184610Salfred if (value & 1) 2625184610Salfred func (stream, "<illegal reg q%ld.5>", value >> 1); 2626184610Salfred else 2627184610Salfred func (stream, "q%ld", value >> 1); 2628184610Salfred break; 2629184610Salfred 2630184610Salfred case '`': 2631184610Salfred c++; 2632184610Salfred if (value == 0) 2633184610Salfred func (stream, "%c", *c); 2634184610Salfred break; 2635184610Salfred case '\'': 2636184610Salfred c++; 2637184610Salfred if (value == ((1ul << width) - 1)) 2638184610Salfred func (stream, "%c", *c); 2639184610Salfred break; 2640184610Salfred case '?': 2641184610Salfred func (stream, "%c", c[(1 << width) - (int)value]); 2642184610Salfred c += 1 << width; 2643184610Salfred break; 2644184610Salfred default: 2645184610Salfred abort (); 2646184610Salfred } 2647184610Salfred break; 2648184610Salfred 2649184610Salfred default: 2650184610Salfred abort (); 2651184610Salfred } 2652184610Salfred } 2653184610Salfred } 2654184610Salfred else 2655184610Salfred func (stream, "%c", *c); 2656184610Salfred } 2657184610Salfred return TRUE; 2658184610Salfred } 2659184610Salfred } 2660184610Salfred return FALSE; 2661184610Salfred} 2662184610Salfred 2663184610Salfred/* Print one ARM instruction from PC on INFO->STREAM. */ 2664184610Salfred 2665184610Salfredstatic void 2666184610Salfredprint_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) 2667184610Salfred{ 2668184610Salfred const struct opcode32 *insn; 2669184610Salfred void *stream = info->stream; 2670184610Salfred fprintf_ftype func = info->fprintf_func; 2671184610Salfred 2672184610Salfred if (print_insn_coprocessor (pc, info, given, FALSE)) 2673184610Salfred return; 2674184610Salfred 2675184610Salfred if (print_insn_neon (info, given, FALSE)) 2676184610Salfred return; 2677184610Salfred 2678184610Salfred for (insn = arm_opcodes; insn->assembler; insn++) 2679184610Salfred { 2680184610Salfred if (insn->value == FIRST_IWMMXT_INSN 2681184610Salfred && info->mach != bfd_mach_arm_XScale 2682184610Salfred && info->mach != bfd_mach_arm_iWMMXt) 2683184610Salfred insn = insn + IWMMXT_INSN_COUNT; 2684184610Salfred 2685184610Salfred if ((given & insn->mask) == insn->value 2686184610Salfred /* Special case: an instruction with all bits set in the condition field 2687184610Salfred (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask, 2688184610Salfred or by the catchall at the end of the table. */ 2689184610Salfred && ((given & 0xF0000000) != 0xF0000000 2690184610Salfred || (insn->mask & 0xF0000000) == 0xF0000000 2691184610Salfred || (insn->mask == 0 && insn->value == 0))) 2692184610Salfred { 2693184610Salfred const char *c; 2694184610Salfred 2695184610Salfred for (c = insn->assembler; *c; c++) 2696184610Salfred { 2697184610Salfred if (*c == '%') 2698184610Salfred { 2699184610Salfred switch (*++c) 2700184610Salfred { 2701184610Salfred case '%': 2702184610Salfred func (stream, "%%"); 2703184610Salfred break; 2704184610Salfred 2705184610Salfred case 'a': 2706184610Salfred print_arm_address (pc, info, given); 2707184610Salfred break; 2708184610Salfred 2709184610Salfred case 'P': 2710184610Salfred /* Set P address bit and use normal address 2711184610Salfred printing routine. */ 2712184610Salfred print_arm_address (pc, info, given | (1 << 24)); 2713184610Salfred break; 2714184610Salfred 2715184610Salfred case 's': 2716184610Salfred if ((given & 0x004f0000) == 0x004f0000) 2717184610Salfred { 2718184610Salfred /* PC relative with immediate offset. */ 2719184610Salfred int offset = ((given & 0xf00) >> 4) | (given & 0xf); 2720184610Salfred 2721184610Salfred if ((given & 0x00800000) == 0) 2722184610Salfred offset = -offset; 2723184610Salfred 2724184610Salfred func (stream, "[pc, #%d]\t; ", offset); 2725184610Salfred info->print_address_func (offset + pc + 8, info); 2726184610Salfred } 2727184610Salfred else 2728184610Salfred { 2729184610Salfred func (stream, "[%s", 2730184610Salfred arm_regnames[(given >> 16) & 0xf]); 2731184610Salfred if ((given & 0x01000000) != 0) 2732184610Salfred { 2733184610Salfred /* Pre-indexed. */ 2734184610Salfred if ((given & 0x00400000) == 0x00400000) 2735184610Salfred { 2736184610Salfred /* Immediate. */ 2737184610Salfred int offset = ((given & 0xf00) >> 4) | (given & 0xf); 2738184610Salfred if (offset) 2739184610Salfred func (stream, ", #%s%d", 2740184610Salfred (((given & 0x00800000) == 0) 2741184610Salfred ? "-" : ""), offset); 2742184610Salfred } 2743184610Salfred else 2744184610Salfred { 2745184610Salfred /* Register. */ 2746184610Salfred func (stream, ", %s%s", 2747184610Salfred (((given & 0x00800000) == 0) 2748184610Salfred ? "-" : ""), 2749184610Salfred arm_regnames[given & 0xf]); 2750184610Salfred } 2751184610Salfred 2752184610Salfred func (stream, "]%s", 2753184610Salfred ((given & 0x00200000) != 0) ? "!" : ""); 2754184610Salfred } 2755184610Salfred else 2756184610Salfred { 2757184610Salfred /* Post-indexed. */ 2758184610Salfred if ((given & 0x00400000) == 0x00400000) 2759184610Salfred { 2760184610Salfred /* Immediate. */ 2761184610Salfred int offset = ((given & 0xf00) >> 4) | (given & 0xf); 2762184610Salfred if (offset) 2763184610Salfred func (stream, "], #%s%d", 2764184610Salfred (((given & 0x00800000) == 0) 2765184610Salfred ? "-" : ""), offset); 2766184610Salfred else 2767184610Salfred func (stream, "]"); 2768184610Salfred } 2769184610Salfred else 2770184610Salfred { 2771184610Salfred /* Register. */ 2772184610Salfred func (stream, "], %s%s", 2773184610Salfred (((given & 0x00800000) == 0) 2774184610Salfred ? "-" : ""), 2775184610Salfred arm_regnames[given & 0xf]); 2776184610Salfred } 2777184610Salfred } 2778184610Salfred } 2779184610Salfred break; 2780184610Salfred 2781184610Salfred case 'b': 2782184610Salfred { 2783184610Salfred int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); 2784184610Salfred info->print_address_func (disp*4 + pc + 8, info); 2785184610Salfred } 2786184610Salfred break; 2787184610Salfred 2788184610Salfred case 'c': 2789184610Salfred if (((given >> 28) & 0xf) != 0xe) 2790184610Salfred func (stream, "%s", 2791184610Salfred arm_conditional [(given >> 28) & 0xf]); 2792184610Salfred break; 2793184610Salfred 2794184610Salfred case 'm': 2795184610Salfred { 2796184610Salfred int started = 0; 2797184610Salfred int reg; 2798184610Salfred 2799184610Salfred func (stream, "{"); 2800184610Salfred for (reg = 0; reg < 16; reg++) 2801184610Salfred if ((given & (1 << reg)) != 0) 2802184610Salfred { 2803184610Salfred if (started) 2804184610Salfred func (stream, ", "); 2805184610Salfred started = 1; 2806184610Salfred func (stream, "%s", arm_regnames[reg]); 2807184610Salfred } 2808184610Salfred func (stream, "}"); 2809184610Salfred } 2810184610Salfred break; 2811184610Salfred 2812184610Salfred case 'q': 2813184610Salfred arm_decode_shift (given, func, stream, 0); 2814184610Salfred break; 2815184610Salfred 2816184610Salfred case 'o': 2817184610Salfred if ((given & 0x02000000) != 0) 2818184610Salfred { 2819184610Salfred int rotate = (given & 0xf00) >> 7; 2820184610Salfred int immed = (given & 0xff); 2821184610Salfred immed = (((immed << (32 - rotate)) 2822184610Salfred | (immed >> rotate)) & 0xffffffff); 2823184610Salfred func (stream, "#%d\t; 0x%x", immed, immed); 2824184610Salfred } 2825184610Salfred else 2826184610Salfred arm_decode_shift (given, func, stream, 1); 2827184610Salfred break; 2828184610Salfred 2829184610Salfred case 'p': 2830184610Salfred if ((given & 0x0000f000) == 0x0000f000) 2831184610Salfred func (stream, "p"); 2832184610Salfred break; 2833184610Salfred 2834184610Salfred case 't': 2835184610Salfred if ((given & 0x01200000) == 0x00200000) 2836184610Salfred func (stream, "t"); 2837184610Salfred break; 2838184610Salfred 2839184610Salfred case 'A': 2840184610Salfred func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); 2841184610Salfred 2842184610Salfred if ((given & (1 << 24)) != 0) 2843184610Salfred { 2844184610Salfred int offset = given & 0xff; 2845184610Salfred 2846184610Salfred if (offset) 2847184610Salfred func (stream, ", #%s%d]%s", 2848184610Salfred ((given & 0x00800000) == 0 ? "-" : ""), 2849184610Salfred offset * 4, 2850184610Salfred ((given & 0x00200000) != 0 ? "!" : "")); 2851184610Salfred else 2852184610Salfred func (stream, "]"); 2853184610Salfred } 2854184610Salfred else 2855184610Salfred { 2856184610Salfred int offset = given & 0xff; 2857184610Salfred 2858184610Salfred func (stream, "]"); 2859184610Salfred 2860184610Salfred if (given & (1 << 21)) 2861184610Salfred { 2862184610Salfred if (offset) 2863184610Salfred func (stream, ", #%s%d", 2864184610Salfred ((given & 0x00800000) == 0 ? "-" : ""), 2865184610Salfred offset * 4); 2866184610Salfred } 2867184610Salfred else 2868184610Salfred func (stream, ", {%d}", offset); 2869184610Salfred } 2870184610Salfred break; 2871184610Salfred 2872184610Salfred case 'B': 2873184610Salfred /* Print ARM V5 BLX(1) address: pc+25 bits. */ 2874184610Salfred { 2875184610Salfred bfd_vma address; 2876184610Salfred bfd_vma offset = 0; 2877184610Salfred 2878184610Salfred if (given & 0x00800000) 2879184610Salfred /* Is signed, hi bits should be ones. */ 2880184610Salfred offset = (-1) ^ 0x00ffffff; 2881184610Salfred 2882184610Salfred /* Offset is (SignExtend(offset field)<<2). */ 2883184610Salfred offset += given & 0x00ffffff; 2884184610Salfred offset <<= 2; 2885184610Salfred address = offset + pc + 8; 2886184610Salfred 2887184610Salfred if (given & 0x01000000) 2888184610Salfred /* H bit allows addressing to 2-byte boundaries. */ 2889184610Salfred address += 2; 2890184610Salfred 2891184610Salfred info->print_address_func (address, info); 2892184610Salfred } 2893184610Salfred break; 2894184610Salfred 2895184610Salfred case 'C': 2896184610Salfred func (stream, "_"); 2897184610Salfred if (given & 0x80000) 2898184610Salfred func (stream, "f"); 2899184610Salfred if (given & 0x40000) 2900184610Salfred func (stream, "s"); 2901184610Salfred if (given & 0x20000) 2902184610Salfred func (stream, "x"); 2903184610Salfred if (given & 0x10000) 2904184610Salfred func (stream, "c"); 2905184610Salfred break; 2906184610Salfred 2907184610Salfred case 'U': 2908184610Salfred switch (given & 0xf) 2909184610Salfred { 2910184610Salfred case 0xf: func(stream, "sy"); break; 2911184610Salfred case 0x7: func(stream, "un"); break; 2912184610Salfred case 0xe: func(stream, "st"); break; 2913184610Salfred case 0x6: func(stream, "unst"); break; 2914184610Salfred default: 2915184610Salfred func(stream, "#%d", (int)given & 0xf); 2916184610Salfred break; 2917184610Salfred } 2918184610Salfred break; 2919184610Salfred 2920184610Salfred case '0': case '1': case '2': case '3': case '4': 2921184610Salfred case '5': case '6': case '7': case '8': case '9': 2922184610Salfred { 2923184610Salfred int width; 2924184610Salfred unsigned long value; 2925184610Salfred 2926184610Salfred c = arm_decode_bitfield (c, given, &value, &width); 2927184610Salfred 2928184610Salfred switch (*c) 2929184610Salfred { 2930184610Salfred case 'r': 2931184610Salfred func (stream, "%s", arm_regnames[value]); 2932184610Salfred break; 2933184610Salfred case 'd': 2934184610Salfred func (stream, "%ld", value); 2935184610Salfred break; 2936184610Salfred case 'b': 2937184610Salfred func (stream, "%ld", value * 8); 2938184610Salfred break; 2939184610Salfred case 'W': 2940184610Salfred func (stream, "%ld", value + 1); 2941184610Salfred break; 2942184610Salfred case 'x': 2943184610Salfred func (stream, "0x%08lx", value); 2944184610Salfred 2945184610Salfred /* Some SWI instructions have special 2946184610Salfred meanings. */ 2947184610Salfred if ((given & 0x0fffffff) == 0x0FF00000) 2948184610Salfred func (stream, "\t; IMB"); 2949184610Salfred else if ((given & 0x0fffffff) == 0x0FF00001) 2950184610Salfred func (stream, "\t; IMBRange"); 2951184610Salfred break; 2952184610Salfred case 'X': 2953184610Salfred func (stream, "%01lx", value & 0xf); 2954184610Salfred break; 2955184610Salfred case '`': 2956184610Salfred c++; 2957184610Salfred if (value == 0) 2958184610Salfred func (stream, "%c", *c); 2959184610Salfred break; 2960184610Salfred case '\'': 2961184610Salfred c++; 2962184610Salfred if (value == ((1ul << width) - 1)) 2963184610Salfred func (stream, "%c", *c); 2964184610Salfred break; 2965184610Salfred case '?': 2966184610Salfred func (stream, "%c", c[(1 << width) - (int)value]); 2967184610Salfred c += 1 << width; 2968184610Salfred break; 2969184610Salfred default: 2970184610Salfred abort (); 2971184610Salfred } 2972184610Salfred break; 2973201758Smbr 2974184610Salfred case 'e': 2975184610Salfred { 2976184610Salfred int imm; 2977184610Salfred 2978184610Salfred imm = (given & 0xf) | ((given & 0xfff00) >> 4); 2979184610Salfred func (stream, "%d", imm); 2980184610Salfred } 2981201758Smbr break; 2982184610Salfred 2983184610Salfred case 'E': 2984184610Salfred /* LSB and WIDTH fields of BFI or BFC. The machine- 2985184610Salfred language instruction encodes LSB and MSB. */ 2986184610Salfred { 2987184610Salfred long msb = (given & 0x001f0000) >> 16; 2988184610Salfred long lsb = (given & 0x00000f80) >> 7; 2989184610Salfred 2990184610Salfred long width = msb - lsb + 1; 2991184610Salfred if (width > 0) 2992184610Salfred func (stream, "#%lu, #%lu", lsb, width); 2993184610Salfred else 2994184610Salfred func (stream, "(invalid: %lu:%lu)", lsb, msb); 2995184610Salfred } 2996184610Salfred break; 2997184610Salfred 2998184610Salfred case 'V': 2999184610Salfred /* 16-bit unsigned immediate from a MOVT or MOVW 3000184610Salfred instruction, encoded in bits 0:11 and 15:19. */ 3001184610Salfred { 3002184610Salfred long hi = (given & 0x000f0000) >> 4; 3003184610Salfred long lo = (given & 0x00000fff); 3004184610Salfred long imm16 = hi | lo; 3005184610Salfred func (stream, "#%lu\t; 0x%lx", imm16, imm16); 3006184610Salfred } 3007184610Salfred break; 3008184610Salfred 3009184610Salfred default: 3010184610Salfred abort (); 3011184610Salfred } 3012184610Salfred } 3013184610Salfred } 3014184610Salfred else 3015184610Salfred func (stream, "%c", *c); 3016207077Sthompsa } 3017184610Salfred return; 3018184610Salfred } 3019184610Salfred } 3020184610Salfred abort (); 3021184610Salfred} 3022184610Salfred 3023184610Salfred/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */ 3024184610Salfred 3025184610Salfredstatic void 3026184610Salfredprint_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) 3027184610Salfred{ 3028184610Salfred const struct opcode16 *insn; 3029184610Salfred void *stream = info->stream; 3030184610Salfred fprintf_ftype func = info->fprintf_func; 3031184610Salfred 3032184610Salfred for (insn = thumb_opcodes; insn->assembler; insn++) 3033184610Salfred if ((given & insn->mask) == insn->value) 3034184610Salfred { 3035184610Salfred const char *c = insn->assembler; 3036184610Salfred for (; *c; c++) 3037184610Salfred { 3038184610Salfred int domaskpc = 0; 3039184610Salfred int domasklr = 0; 3040184610Salfred 3041184610Salfred if (*c != '%') 3042184610Salfred { 3043184610Salfred func (stream, "%c", *c); 3044184610Salfred continue; 3045184610Salfred } 3046184610Salfred 3047184610Salfred switch (*++c) 3048184610Salfred { 3049184610Salfred case '%': 3050184610Salfred func (stream, "%%"); 3051184610Salfred break; 3052184610Salfred 3053184610Salfred case 'c': 3054184610Salfred if (ifthen_state) 3055184610Salfred func (stream, "%s", arm_conditional[IFTHEN_COND]); 3056184610Salfred break; 3057184610Salfred 3058184610Salfred case 'C': 3059184610Salfred if (ifthen_state) 3060184610Salfred func (stream, "%s", arm_conditional[IFTHEN_COND]); 3061184610Salfred else 3062184610Salfred func (stream, "s"); 3063184610Salfred break; 3064184610Salfred 3065184610Salfred case 'I': 3066184610Salfred { 3067184610Salfred unsigned int tmp; 3068184610Salfred 3069184610Salfred ifthen_next_state = given & 0xff; 3070184610Salfred for (tmp = given << 1; tmp & 0xf; tmp <<= 1) 3071184610Salfred func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); 3072184610Salfred func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); 3073184610Salfred } 3074184610Salfred break; 3075184610Salfred 3076184610Salfred case 'x': 3077184610Salfred if (ifthen_next_state) 3078184610Salfred func (stream, "\t; unpredictable branch in IT block\n"); 3079184610Salfred break; 3080184610Salfred 3081184610Salfred case 'X': 3082184610Salfred if (ifthen_state) 3083184610Salfred func (stream, "\t; unpredictable <IT:%s>", 3084184610Salfred arm_conditional[IFTHEN_COND]); 3085184610Salfred break; 3086184610Salfred 3087184610Salfred case 'S': 3088184610Salfred { 3089184610Salfred long reg; 3090184610Salfred 3091184610Salfred reg = (given >> 3) & 0x7; 3092184610Salfred if (given & (1 << 6)) 3093184610Salfred reg += 8; 3094184610Salfred 3095184610Salfred func (stream, "%s", arm_regnames[reg]); 3096184610Salfred } 3097184610Salfred break; 3098184610Salfred 3099184610Salfred case 'D': 3100184610Salfred { 3101 long reg; 3102 3103 reg = given & 0x7; 3104 if (given & (1 << 7)) 3105 reg += 8; 3106 3107 func (stream, "%s", arm_regnames[reg]); 3108 } 3109 break; 3110 3111 case 'N': 3112 if (given & (1 << 8)) 3113 domasklr = 1; 3114 /* Fall through. */ 3115 case 'O': 3116 if (*c == 'O' && (given & (1 << 8))) 3117 domaskpc = 1; 3118 /* Fall through. */ 3119 case 'M': 3120 { 3121 int started = 0; 3122 int reg; 3123 3124 func (stream, "{"); 3125 3126 /* It would be nice if we could spot 3127 ranges, and generate the rS-rE format: */ 3128 for (reg = 0; (reg < 8); reg++) 3129 if ((given & (1 << reg)) != 0) 3130 { 3131 if (started) 3132 func (stream, ", "); 3133 started = 1; 3134 func (stream, "%s", arm_regnames[reg]); 3135 } 3136 3137 if (domasklr) 3138 { 3139 if (started) 3140 func (stream, ", "); 3141 started = 1; 3142 func (stream, arm_regnames[14] /* "lr" */); 3143 } 3144 3145 if (domaskpc) 3146 { 3147 if (started) 3148 func (stream, ", "); 3149 func (stream, arm_regnames[15] /* "pc" */); 3150 } 3151 3152 func (stream, "}"); 3153 } 3154 break; 3155 3156 case 'b': 3157 /* Print ARM V6T2 CZB address: pc+4+6 bits. */ 3158 { 3159 bfd_vma address = (pc + 4 3160 + ((given & 0x00f8) >> 2) 3161 + ((given & 0x0200) >> 3)); 3162 info->print_address_func (address, info); 3163 } 3164 break; 3165 3166 case 's': 3167 /* Right shift immediate -- bits 6..10; 1-31 print 3168 as themselves, 0 prints as 32. */ 3169 { 3170 long imm = (given & 0x07c0) >> 6; 3171 if (imm == 0) 3172 imm = 32; 3173 func (stream, "#%ld", imm); 3174 } 3175 break; 3176 3177 case '0': case '1': case '2': case '3': case '4': 3178 case '5': case '6': case '7': case '8': case '9': 3179 { 3180 int bitstart = *c++ - '0'; 3181 int bitend = 0; 3182 3183 while (*c >= '0' && *c <= '9') 3184 bitstart = (bitstart * 10) + *c++ - '0'; 3185 3186 switch (*c) 3187 { 3188 case '-': 3189 { 3190 long reg; 3191 3192 c++; 3193 while (*c >= '0' && *c <= '9') 3194 bitend = (bitend * 10) + *c++ - '0'; 3195 if (!bitend) 3196 abort (); 3197 reg = given >> bitstart; 3198 reg &= (2 << (bitend - bitstart)) - 1; 3199 switch (*c) 3200 { 3201 case 'r': 3202 func (stream, "%s", arm_regnames[reg]); 3203 break; 3204 3205 case 'd': 3206 func (stream, "%ld", reg); 3207 break; 3208 3209 case 'H': 3210 func (stream, "%ld", reg << 1); 3211 break; 3212 3213 case 'W': 3214 func (stream, "%ld", reg << 2); 3215 break; 3216 3217 case 'a': 3218 /* PC-relative address -- the bottom two 3219 bits of the address are dropped 3220 before the calculation. */ 3221 info->print_address_func 3222 (((pc + 4) & ~3) + (reg << 2), info); 3223 break; 3224 3225 case 'x': 3226 func (stream, "0x%04lx", reg); 3227 break; 3228 3229 case 'B': 3230 reg = ((reg ^ (1 << bitend)) - (1 << bitend)); 3231 info->print_address_func (reg * 2 + pc + 4, info); 3232 break; 3233 3234 case 'c': 3235 func (stream, "%s", arm_conditional [reg]); 3236 break; 3237 3238 default: 3239 abort (); 3240 } 3241 } 3242 break; 3243 3244 case '\'': 3245 c++; 3246 if ((given & (1 << bitstart)) != 0) 3247 func (stream, "%c", *c); 3248 break; 3249 3250 case '?': 3251 ++c; 3252 if ((given & (1 << bitstart)) != 0) 3253 func (stream, "%c", *c++); 3254 else 3255 func (stream, "%c", *++c); 3256 break; 3257 3258 default: 3259 abort (); 3260 } 3261 } 3262 break; 3263 3264 default: 3265 abort (); 3266 } 3267 } 3268 return; 3269 } 3270 3271 /* No match. */ 3272 abort (); 3273} 3274 3275/* Return the name of an V7M special register. */ 3276static const char * 3277psr_name (int regno) 3278{ 3279 switch (regno) 3280 { 3281 case 0: return "APSR"; 3282 case 1: return "IAPSR"; 3283 case 2: return "EAPSR"; 3284 case 3: return "PSR"; 3285 case 5: return "IPSR"; 3286 case 6: return "EPSR"; 3287 case 7: return "IEPSR"; 3288 case 8: return "MSP"; 3289 case 9: return "PSP"; 3290 case 16: return "PRIMASK"; 3291 case 17: return "BASEPRI"; 3292 case 18: return "BASEPRI_MASK"; 3293 case 19: return "FAULTMASK"; 3294 case 20: return "CONTROL"; 3295 default: return "<unknown>"; 3296 } 3297} 3298 3299/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */ 3300 3301static void 3302print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) 3303{ 3304 const struct opcode32 *insn; 3305 void *stream = info->stream; 3306 fprintf_ftype func = info->fprintf_func; 3307 3308 if (print_insn_coprocessor (pc, info, given, TRUE)) 3309 return; 3310 3311 if (print_insn_neon (info, given, TRUE)) 3312 return; 3313 3314 for (insn = thumb32_opcodes; insn->assembler; insn++) 3315 if ((given & insn->mask) == insn->value) 3316 { 3317 const char *c = insn->assembler; 3318 for (; *c; c++) 3319 { 3320 if (*c != '%') 3321 { 3322 func (stream, "%c", *c); 3323 continue; 3324 } 3325 3326 switch (*++c) 3327 { 3328 case '%': 3329 func (stream, "%%"); 3330 break; 3331 3332 case 'c': 3333 if (ifthen_state) 3334 func (stream, "%s", arm_conditional[IFTHEN_COND]); 3335 break; 3336 3337 case 'x': 3338 if (ifthen_next_state) 3339 func (stream, "\t; unpredictable branch in IT block\n"); 3340 break; 3341 3342 case 'X': 3343 if (ifthen_state) 3344 func (stream, "\t; unpredictable <IT:%s>", 3345 arm_conditional[IFTHEN_COND]); 3346 break; 3347 3348 case 'I': 3349 { 3350 unsigned int imm12 = 0; 3351 imm12 |= (given & 0x000000ffu); 3352 imm12 |= (given & 0x00007000u) >> 4; 3353 imm12 |= (given & 0x04000000u) >> 15; 3354 func (stream, "#%u\t; 0x%x", imm12, imm12); 3355 } 3356 break; 3357 3358 case 'M': 3359 { 3360 unsigned int bits = 0, imm, imm8, mod; 3361 bits |= (given & 0x000000ffu); 3362 bits |= (given & 0x00007000u) >> 4; 3363 bits |= (given & 0x04000000u) >> 15; 3364 imm8 = (bits & 0x0ff); 3365 mod = (bits & 0xf00) >> 8; 3366 switch (mod) 3367 { 3368 case 0: imm = imm8; break; 3369 case 1: imm = ((imm8<<16) | imm8); break; 3370 case 2: imm = ((imm8<<24) | (imm8 << 8)); break; 3371 case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break; 3372 default: 3373 mod = (bits & 0xf80) >> 7; 3374 imm8 = (bits & 0x07f) | 0x80; 3375 imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); 3376 } 3377 func (stream, "#%u\t; 0x%x", imm, imm); 3378 } 3379 break; 3380 3381 case 'J': 3382 { 3383 unsigned int imm = 0; 3384 imm |= (given & 0x000000ffu); 3385 imm |= (given & 0x00007000u) >> 4; 3386 imm |= (given & 0x04000000u) >> 15; 3387 imm |= (given & 0x000f0000u) >> 4; 3388 func (stream, "#%u\t; 0x%x", imm, imm); 3389 } 3390 break; 3391 3392 case 'K': 3393 { 3394 unsigned int imm = 0; 3395 imm |= (given & 0x000f0000u) >> 16; 3396 imm |= (given & 0x00000ff0u) >> 0; 3397 imm |= (given & 0x0000000fu) << 12; 3398 func (stream, "#%u\t; 0x%x", imm, imm); 3399 } 3400 break; 3401 3402 case 'S': 3403 { 3404 unsigned int reg = (given & 0x0000000fu); 3405 unsigned int stp = (given & 0x00000030u) >> 4; 3406 unsigned int imm = 0; 3407 imm |= (given & 0x000000c0u) >> 6; 3408 imm |= (given & 0x00007000u) >> 10; 3409 3410 func (stream, "%s", arm_regnames[reg]); 3411 switch (stp) 3412 { 3413 case 0: 3414 if (imm > 0) 3415 func (stream, ", lsl #%u", imm); 3416 break; 3417 3418 case 1: 3419 if (imm == 0) 3420 imm = 32; 3421 func (stream, ", lsr #%u", imm); 3422 break; 3423 3424 case 2: 3425 if (imm == 0) 3426 imm = 32; 3427 func (stream, ", asr #%u", imm); 3428 break; 3429 3430 case 3: 3431 if (imm == 0) 3432 func (stream, ", rrx"); 3433 else 3434 func (stream, ", ror #%u", imm); 3435 } 3436 } 3437 break; 3438 3439 case 'a': 3440 { 3441 unsigned int Rn = (given & 0x000f0000) >> 16; 3442 unsigned int U = (given & 0x00800000) >> 23; 3443 unsigned int op = (given & 0x00000f00) >> 8; 3444 unsigned int i12 = (given & 0x00000fff); 3445 unsigned int i8 = (given & 0x000000ff); 3446 bfd_boolean writeback = FALSE, postind = FALSE; 3447 int offset = 0; 3448 3449 func (stream, "[%s", arm_regnames[Rn]); 3450 if (U) /* 12-bit positive immediate offset */ 3451 offset = i12; 3452 else if (Rn == 15) /* 12-bit negative immediate offset */ 3453 offset = -(int)i12; 3454 else if (op == 0x0) /* shifted register offset */ 3455 { 3456 unsigned int Rm = (i8 & 0x0f); 3457 unsigned int sh = (i8 & 0x30) >> 4; 3458 func (stream, ", %s", arm_regnames[Rm]); 3459 if (sh) 3460 func (stream, ", lsl #%u", sh); 3461 func (stream, "]"); 3462 break; 3463 } 3464 else switch (op) 3465 { 3466 case 0xE: /* 8-bit positive immediate offset */ 3467 offset = i8; 3468 break; 3469 3470 case 0xC: /* 8-bit negative immediate offset */ 3471 offset = -i8; 3472 break; 3473 3474 case 0xF: /* 8-bit + preindex with wb */ 3475 offset = i8; 3476 writeback = TRUE; 3477 break; 3478 3479 case 0xD: /* 8-bit - preindex with wb */ 3480 offset = -i8; 3481 writeback = TRUE; 3482 break; 3483 3484 case 0xB: /* 8-bit + postindex */ 3485 offset = i8; 3486 postind = TRUE; 3487 break; 3488 3489 case 0x9: /* 8-bit - postindex */ 3490 offset = -i8; 3491 postind = TRUE; 3492 break; 3493 3494 default: 3495 func (stream, ", <undefined>]"); 3496 goto skip; 3497 } 3498 3499 if (postind) 3500 func (stream, "], #%d", offset); 3501 else 3502 { 3503 if (offset) 3504 func (stream, ", #%d", offset); 3505 func (stream, writeback ? "]!" : "]"); 3506 } 3507 3508 if (Rn == 15) 3509 { 3510 func (stream, "\t; "); 3511 info->print_address_func (((pc + 4) & ~3) + offset, info); 3512 } 3513 } 3514 skip: 3515 break; 3516 3517 case 'A': 3518 { 3519 unsigned int P = (given & 0x01000000) >> 24; 3520 unsigned int U = (given & 0x00800000) >> 23; 3521 unsigned int W = (given & 0x00400000) >> 21; 3522 unsigned int Rn = (given & 0x000f0000) >> 16; 3523 unsigned int off = (given & 0x000000ff); 3524 3525 func (stream, "[%s", arm_regnames[Rn]); 3526 if (P) 3527 { 3528 if (off || !U) 3529 func (stream, ", #%c%u", U ? '+' : '-', off * 4); 3530 func (stream, "]"); 3531 if (W) 3532 func (stream, "!"); 3533 } 3534 else 3535 { 3536 func (stream, "], "); 3537 if (W) 3538 func (stream, "#%c%u", U ? '+' : '-', off * 4); 3539 else 3540 func (stream, "{%u}", off); 3541 } 3542 } 3543 break; 3544 3545 case 'w': 3546 { 3547 unsigned int Sbit = (given & 0x01000000) >> 24; 3548 unsigned int type = (given & 0x00600000) >> 21; 3549 switch (type) 3550 { 3551 case 0: func (stream, Sbit ? "sb" : "b"); break; 3552 case 1: func (stream, Sbit ? "sh" : "h"); break; 3553 case 2: 3554 if (Sbit) 3555 func (stream, "??"); 3556 break; 3557 case 3: 3558 func (stream, "??"); 3559 break; 3560 } 3561 } 3562 break; 3563 3564 case 'm': 3565 { 3566 int started = 0; 3567 int reg; 3568 3569 func (stream, "{"); 3570 for (reg = 0; reg < 16; reg++) 3571 if ((given & (1 << reg)) != 0) 3572 { 3573 if (started) 3574 func (stream, ", "); 3575 started = 1; 3576 func (stream, "%s", arm_regnames[reg]); 3577 } 3578 func (stream, "}"); 3579 } 3580 break; 3581 3582 case 'E': 3583 { 3584 unsigned int msb = (given & 0x0000001f); 3585 unsigned int lsb = 0; 3586 lsb |= (given & 0x000000c0u) >> 6; 3587 lsb |= (given & 0x00007000u) >> 10; 3588 func (stream, "#%u, #%u", lsb, msb - lsb + 1); 3589 } 3590 break; 3591 3592 case 'F': 3593 { 3594 unsigned int width = (given & 0x0000001f) + 1; 3595 unsigned int lsb = 0; 3596 lsb |= (given & 0x000000c0u) >> 6; 3597 lsb |= (given & 0x00007000u) >> 10; 3598 func (stream, "#%u, #%u", lsb, width); 3599 } 3600 break; 3601 3602 case 'b': 3603 { 3604 unsigned int S = (given & 0x04000000u) >> 26; 3605 unsigned int J1 = (given & 0x00002000u) >> 13; 3606 unsigned int J2 = (given & 0x00000800u) >> 11; 3607 int offset = 0; 3608 3609 offset |= !S << 20; 3610 offset |= J2 << 19; 3611 offset |= J1 << 18; 3612 offset |= (given & 0x003f0000) >> 4; 3613 offset |= (given & 0x000007ff) << 1; 3614 offset -= (1 << 20); 3615 3616 info->print_address_func (pc + 4 + offset, info); 3617 } 3618 break; 3619 3620 case 'B': 3621 { 3622 unsigned int S = (given & 0x04000000u) >> 26; 3623 unsigned int I1 = (given & 0x00002000u) >> 13; 3624 unsigned int I2 = (given & 0x00000800u) >> 11; 3625 int offset = 0; 3626 3627 offset |= !S << 24; 3628 offset |= !(I1 ^ S) << 23; 3629 offset |= !(I2 ^ S) << 22; 3630 offset |= (given & 0x03ff0000u) >> 4; 3631 offset |= (given & 0x000007ffu) << 1; 3632 offset -= (1 << 24); 3633 offset += pc + 4; 3634 3635 /* BLX target addresses are always word aligned. */ 3636 if ((given & 0x00001000u) == 0) 3637 offset &= ~2u; 3638 3639 info->print_address_func (offset, info); 3640 } 3641 break; 3642 3643 case 's': 3644 { 3645 unsigned int shift = 0; 3646 shift |= (given & 0x000000c0u) >> 6; 3647 shift |= (given & 0x00007000u) >> 10; 3648 if (given & 0x00200000u) 3649 func (stream, ", asr #%u", shift); 3650 else if (shift) 3651 func (stream, ", lsl #%u", shift); 3652 /* else print nothing - lsl #0 */ 3653 } 3654 break; 3655 3656 case 'R': 3657 { 3658 unsigned int rot = (given & 0x00000030) >> 4; 3659 if (rot) 3660 func (stream, ", ror #%u", rot * 8); 3661 } 3662 break; 3663 3664 case 'U': 3665 switch (given & 0xf) 3666 { 3667 case 0xf: func(stream, "sy"); break; 3668 case 0x7: func(stream, "un"); break; 3669 case 0xe: func(stream, "st"); break; 3670 case 0x6: func(stream, "unst"); break; 3671 default: 3672 func(stream, "#%d", (int)given & 0xf); 3673 break; 3674 } 3675 break; 3676 3677 case 'C': 3678 if ((given & 0xff) == 0) 3679 { 3680 func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); 3681 if (given & 0x800) 3682 func (stream, "f"); 3683 if (given & 0x400) 3684 func (stream, "s"); 3685 if (given & 0x200) 3686 func (stream, "x"); 3687 if (given & 0x100) 3688 func (stream, "c"); 3689 } 3690 else 3691 { 3692 func (stream, psr_name (given & 0xff)); 3693 } 3694 break; 3695 3696 case 'D': 3697 if ((given & 0xff) == 0) 3698 func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C'); 3699 else 3700 func (stream, psr_name (given & 0xff)); 3701 break; 3702 3703 case '0': case '1': case '2': case '3': case '4': 3704 case '5': case '6': case '7': case '8': case '9': 3705 { 3706 int width; 3707 unsigned long val; 3708 3709 c = arm_decode_bitfield (c, given, &val, &width); 3710 3711 switch (*c) 3712 { 3713 case 'd': func (stream, "%lu", val); break; 3714 case 'W': func (stream, "%lu", val * 4); break; 3715 case 'r': func (stream, "%s", arm_regnames[val]); break; 3716 3717 case 'c': 3718 func (stream, "%s", arm_conditional[val]); 3719 break; 3720 3721 case '\'': 3722 c++; 3723 if (val == ((1ul << width) - 1)) 3724 func (stream, "%c", *c); 3725 break; 3726 3727 case '`': 3728 c++; 3729 if (val == 0) 3730 func (stream, "%c", *c); 3731 break; 3732 3733 case '?': 3734 func (stream, "%c", c[(1 << width) - (int)val]); 3735 c += 1 << width; 3736 break; 3737 3738 default: 3739 abort (); 3740 } 3741 } 3742 break; 3743 3744 default: 3745 abort (); 3746 } 3747 } 3748 return; 3749 } 3750 3751 /* No match. */ 3752 abort (); 3753} 3754 3755/* Print data bytes on INFO->STREAM. */ 3756 3757static void 3758print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info, 3759 long given) 3760{ 3761 switch (info->bytes_per_chunk) 3762 { 3763 case 1: 3764 info->fprintf_func (info->stream, ".byte\t0x%02lx", given); 3765 break; 3766 case 2: 3767 info->fprintf_func (info->stream, ".short\t0x%04lx", given); 3768 break; 3769 case 4: 3770 info->fprintf_func (info->stream, ".word\t0x%08lx", given); 3771 break; 3772 default: 3773 abort (); 3774 } 3775} 3776 3777/* Disallow mapping symbols ($a, $b, $d, $t etc) from 3778 being displayed in symbol relative addresses. */ 3779 3780bfd_boolean 3781arm_symbol_is_valid (asymbol * sym, 3782 struct disassemble_info * info ATTRIBUTE_UNUSED) 3783{ 3784 const char * name; 3785 3786 if (sym == NULL) 3787 return FALSE; 3788 3789 name = bfd_asymbol_name (sym); 3790 3791 return (name && *name != '$'); 3792} 3793 3794/* Parse an individual disassembler option. */ 3795 3796void 3797parse_arm_disassembler_option (char *option) 3798{ 3799 if (option == NULL) 3800 return; 3801 3802 if (CONST_STRNEQ (option, "reg-names-")) 3803 { 3804 int i; 3805 3806 option += 10; 3807 3808 for (i = NUM_ARM_REGNAMES; i--;) 3809 if (strneq (option, regnames[i].name, strlen (regnames[i].name))) 3810 { 3811 regname_selected = i; 3812 break; 3813 } 3814 3815 if (i < 0) 3816 /* XXX - should break 'option' at following delimiter. */ 3817 fprintf (stderr, _("Unrecognised register name set: %s\n"), option); 3818 } 3819 else if (CONST_STRNEQ (option, "force-thumb")) 3820 force_thumb = 1; 3821 else if (CONST_STRNEQ (option, "no-force-thumb")) 3822 force_thumb = 0; 3823 else 3824 /* XXX - should break 'option' at following delimiter. */ 3825 fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); 3826 3827 return; 3828} 3829 3830/* Parse the string of disassembler options, spliting it at whitespaces 3831 or commas. (Whitespace separators supported for backwards compatibility). */ 3832 3833static void 3834parse_disassembler_options (char *options) 3835{ 3836 if (options == NULL) 3837 return; 3838 3839 while (*options) 3840 { 3841 parse_arm_disassembler_option (options); 3842 3843 /* Skip forward to next seperator. */ 3844 while ((*options) && (! ISSPACE (*options)) && (*options != ',')) 3845 ++ options; 3846 /* Skip forward past seperators. */ 3847 while (ISSPACE (*options) || (*options == ',')) 3848 ++ options; 3849 } 3850} 3851 3852/* Search back through the insn stream to determine if this instruction is 3853 conditionally executed. */ 3854static void 3855find_ifthen_state (bfd_vma pc, struct disassemble_info *info, 3856 bfd_boolean little) 3857{ 3858 unsigned char b[2]; 3859 unsigned int insn; 3860 int status; 3861 /* COUNT is twice the number of instructions seen. It will be odd if we 3862 just crossed an instruction boundary. */ 3863 int count; 3864 int it_count; 3865 unsigned int seen_it; 3866 bfd_vma addr; 3867 3868 ifthen_address = pc; 3869 ifthen_state = 0; 3870 3871 addr = pc; 3872 count = 1; 3873 it_count = 0; 3874 seen_it = 0; 3875 /* Scan backwards looking for IT instructions, keeping track of where 3876 instruction boundaries are. We don't know if something is actually an 3877 IT instruction until we find a definite instruction boundary. */ 3878 for (;;) 3879 { 3880 if (addr == 0 || info->symbol_at_address_func(addr, info)) 3881 { 3882 /* A symbol must be on an instruction boundary, and will not 3883 be within an IT block. */ 3884 if (seen_it && (count & 1)) 3885 break; 3886 3887 return; 3888 } 3889 addr -= 2; 3890 status = info->read_memory_func (addr, (bfd_byte *)b, 2, info); 3891 if (status) 3892 return; 3893 3894 if (little) 3895 insn = (b[0]) | (b[1] << 8); 3896 else 3897 insn = (b[1]) | (b[0] << 8); 3898 if (seen_it) 3899 { 3900 if ((insn & 0xf800) < 0xe800) 3901 { 3902 /* Addr + 2 is an instruction boundary. See if this matches 3903 the expected boundary based on the position of the last 3904 IT candidate. */ 3905 if (count & 1) 3906 break; 3907 seen_it = 0; 3908 } 3909 } 3910 if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) 3911 { 3912 /* This could be an IT instruction. */ 3913 seen_it = insn; 3914 it_count = count >> 1; 3915 } 3916 if ((insn & 0xf800) >= 0xe800) 3917 count++; 3918 else 3919 count = (count + 2) | 1; 3920 /* IT blocks contain at most 4 instructions. */ 3921 if (count >= 8 && !seen_it) 3922 return; 3923 } 3924 /* We found an IT instruction. */ 3925 ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); 3926 if ((ifthen_state & 0xf) == 0) 3927 ifthen_state = 0; 3928} 3929 3930/* Try to infer the code type (Arm or Thumb) from a symbol. 3931 Returns nonzero if *MAP_TYPE was set. */ 3932 3933static int 3934get_sym_code_type (struct disassemble_info *info, int n, 3935 enum map_type *map_type) 3936{ 3937 elf_symbol_type *es; 3938 unsigned int type; 3939 const char *name; 3940 3941 es = *(elf_symbol_type **)(info->symtab + n); 3942 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 3943 3944 /* If the symbol has function type then use that. */ 3945 if (type == STT_FUNC || type == STT_ARM_TFUNC) 3946 { 3947 *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM; 3948 return TRUE; 3949 } 3950 3951 /* Check for mapping symbols. */ 3952 name = bfd_asymbol_name(info->symtab[n]); 3953 if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd') 3954 && (name[2] == 0 || name[2] == '.')) 3955 { 3956 *map_type = ((name[1] == 'a') ? MAP_ARM 3957 : (name[1] == 't') ? MAP_THUMB 3958 : MAP_DATA); 3959 return TRUE; 3960 } 3961 3962 return FALSE; 3963} 3964 3965/* NOTE: There are no checks in these routines that 3966 the relevant number of data bytes exist. */ 3967 3968static int 3969print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) 3970{ 3971 unsigned char b[4]; 3972 long given; 3973 int status; 3974 int is_thumb = FALSE; 3975 int is_data = FALSE; 3976 unsigned int size = 4; 3977 void (*printer) (bfd_vma, struct disassemble_info *, long); 3978 bfd_boolean found = FALSE; 3979 3980 if (info->disassembler_options) 3981 { 3982 parse_disassembler_options (info->disassembler_options); 3983 3984 /* To avoid repeated parsing of these options, we remove them here. */ 3985 info->disassembler_options = NULL; 3986 } 3987 3988 /* First check the full symtab for a mapping symbol, even if there 3989 are no usable non-mapping symbols for this address. */ 3990 if (info->symtab != NULL 3991 && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) 3992 { 3993 bfd_vma addr; 3994 int n; 3995 int last_sym = -1; 3996 enum map_type type = MAP_ARM; 3997 3998 if (pc <= last_mapping_addr) 3999 last_mapping_sym = -1; 4000 is_thumb = (last_type == MAP_THUMB); 4001 found = FALSE; 4002 /* Start scanning at the start of the function, or wherever 4003 we finished last time. */ 4004 n = info->symtab_pos + 1; 4005 if (n < last_mapping_sym) 4006 n = last_mapping_sym; 4007 4008 /* Scan up to the location being disassembled. */ 4009 for (; n < info->symtab_size; n++) 4010 { 4011 addr = bfd_asymbol_value (info->symtab[n]); 4012 if (addr > pc) 4013 break; 4014 if ((info->section == NULL 4015 || info->section == info->symtab[n]->section) 4016 && get_sym_code_type (info, n, &type)) 4017 { 4018 last_sym = n; 4019 found = TRUE; 4020 } 4021 } 4022 4023 if (!found) 4024 { 4025 n = info->symtab_pos; 4026 if (n < last_mapping_sym - 1) 4027 n = last_mapping_sym - 1; 4028 4029 /* No mapping symbol found at this address. Look backwards 4030 for a preceeding one. */ 4031 for (; n >= 0; n--) 4032 { 4033 if (get_sym_code_type (info, n, &type)) 4034 { 4035 last_sym = n; 4036 found = TRUE; 4037 break; 4038 } 4039 } 4040 } 4041 4042 last_mapping_sym = last_sym; 4043 last_type = type; 4044 is_thumb = (last_type == MAP_THUMB); 4045 is_data = (last_type == MAP_DATA); 4046 4047 /* Look a little bit ahead to see if we should print out 4048 two or four bytes of data. If there's a symbol, 4049 mapping or otherwise, after two bytes then don't 4050 print more. */ 4051 if (is_data) 4052 { 4053 size = 4 - (pc & 3); 4054 for (n = last_sym + 1; n < info->symtab_size; n++) 4055 { 4056 addr = bfd_asymbol_value (info->symtab[n]); 4057 if (addr > pc) 4058 { 4059 if (addr - pc < size) 4060 size = addr - pc; 4061 break; 4062 } 4063 } 4064 /* If the next symbol is after three bytes, we need to 4065 print only part of the data, so that we can use either 4066 .byte or .short. */ 4067 if (size == 3) 4068 size = (pc & 1) ? 1 : 2; 4069 } 4070 } 4071 4072 if (info->symbols != NULL) 4073 { 4074 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) 4075 { 4076 coff_symbol_type * cs; 4077 4078 cs = coffsymbol (*info->symbols); 4079 is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT 4080 || cs->native->u.syment.n_sclass == C_THUMBSTAT 4081 || cs->native->u.syment.n_sclass == C_THUMBLABEL 4082 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC 4083 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC); 4084 } 4085 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour 4086 && !found) 4087 { 4088 /* If no mapping symbol has been found then fall back to the type 4089 of the function symbol. */ 4090 elf_symbol_type * es; 4091 unsigned int type; 4092 4093 es = *(elf_symbol_type **)(info->symbols); 4094 type = ELF_ST_TYPE (es->internal_elf_sym.st_info); 4095 4096 is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); 4097 } 4098 } 4099 4100 if (force_thumb) 4101 is_thumb = TRUE; 4102 4103 info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; 4104 info->bytes_per_line = 4; 4105 4106 if (is_data) 4107 { 4108 int i; 4109 4110 /* size was already set above. */ 4111 info->bytes_per_chunk = size; 4112 printer = print_insn_data; 4113 4114 status = info->read_memory_func (pc, (bfd_byte *)b, size, info); 4115 given = 0; 4116 if (little) 4117 for (i = size - 1; i >= 0; i--) 4118 given = b[i] | (given << 8); 4119 else 4120 for (i = 0; i < (int) size; i++) 4121 given = b[i] | (given << 8); 4122 } 4123 else if (!is_thumb) 4124 { 4125 /* In ARM mode endianness is a straightforward issue: the instruction 4126 is four bytes long and is either ordered 0123 or 3210. */ 4127 printer = print_insn_arm; 4128 info->bytes_per_chunk = 4; 4129 size = 4; 4130 4131 status = info->read_memory_func (pc, (bfd_byte *)b, 4, info); 4132 if (little) 4133 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); 4134 else 4135 given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); 4136 } 4137 else 4138 { 4139 /* In Thumb mode we have the additional wrinkle of two 4140 instruction lengths. Fortunately, the bits that determine 4141 the length of the current instruction are always to be found 4142 in the first two bytes. */ 4143 printer = print_insn_thumb16; 4144 info->bytes_per_chunk = 2; 4145 size = 2; 4146 4147 status = info->read_memory_func (pc, (bfd_byte *)b, 2, info); 4148 if (little) 4149 given = (b[0]) | (b[1] << 8); 4150 else 4151 given = (b[1]) | (b[0] << 8); 4152 4153 if (!status) 4154 { 4155 /* These bit patterns signal a four-byte Thumb 4156 instruction. */ 4157 if ((given & 0xF800) == 0xF800 4158 || (given & 0xF800) == 0xF000 4159 || (given & 0xF800) == 0xE800) 4160 { 4161 status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info); 4162 if (little) 4163 given = (b[0]) | (b[1] << 8) | (given << 16); 4164 else 4165 given = (b[1]) | (b[0] << 8) | (given << 16); 4166 4167 printer = print_insn_thumb32; 4168 size = 4; 4169 } 4170 } 4171 4172 if (ifthen_address != pc) 4173 find_ifthen_state(pc, info, little); 4174 4175 if (ifthen_state) 4176 { 4177 if ((ifthen_state & 0xf) == 0x8) 4178 ifthen_next_state = 0; 4179 else 4180 ifthen_next_state = (ifthen_state & 0xe0) 4181 | ((ifthen_state & 0xf) << 1); 4182 } 4183 } 4184 4185 if (status) 4186 { 4187 info->memory_error_func (status, pc, info); 4188 return -1; 4189 } 4190 if (info->flags & INSN_HAS_RELOC) 4191 /* If the instruction has a reloc associated with it, then 4192 the offset field in the instruction will actually be the 4193 addend for the reloc. (We are using REL type relocs). 4194 In such cases, we can ignore the pc when computing 4195 addresses, since the addend is not currently pc-relative. */ 4196 pc = 0; 4197 4198 printer (pc, info, given); 4199 4200 if (is_thumb) 4201 { 4202 ifthen_state = ifthen_next_state; 4203 ifthen_address += size; 4204 } 4205 return size; 4206} 4207 4208int 4209print_insn_big_arm (bfd_vma pc, struct disassemble_info *info) 4210{ 4211 return print_insn (pc, info, FALSE); 4212} 4213 4214int 4215print_insn_little_arm (bfd_vma pc, struct disassemble_info *info) 4216{ 4217 return print_insn (pc, info, TRUE); 4218} 4219 4220void 4221print_arm_disassembler_options (FILE *stream) 4222{ 4223 int i; 4224 4225 fprintf (stream, _("\n\ 4226The following ARM specific disassembler options are supported for use with\n\ 4227the -M switch:\n")); 4228 4229 for (i = NUM_ARM_REGNAMES; i--;) 4230 fprintf (stream, " reg-names-%s %*c%s\n", 4231 regnames[i].name, 4232 (int)(14 - strlen (regnames[i].name)), ' ', 4233 regnames[i].description); 4234 4235 fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); 4236 fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n"); 4237} 4238