alpha-opc.c revision 38889
133965Sjdp/* alpha-opc.c -- Alpha AXP opcode list 233965Sjdp Copyright 1996 Free Software Foundation, Inc. 333965Sjdp Contributed by Richard Henderson <rth@tamu.edu>, 433965Sjdp patterned after the PPC opcode handling written by Ian Lance Taylor. 533965Sjdp 633965Sjdp This file is part of GDB, GAS, and the GNU binutils. 733965Sjdp 833965Sjdp GDB, GAS, and the GNU binutils are free software; you can redistribute 933965Sjdp them and/or modify them under the terms of the GNU General Public 1033965Sjdp License as published by the Free Software Foundation; either version 1133965Sjdp 2, or (at your option) any later version. 1233965Sjdp 1333965Sjdp GDB, GAS, and the GNU binutils are distributed in the hope that they 1433965Sjdp will be useful, but WITHOUT ANY WARRANTY; without even the implied 1533965Sjdp warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 1633965Sjdp the GNU General Public License for more details. 1733965Sjdp 1833965Sjdp You should have received a copy of the GNU General Public License 1933965Sjdp along with this file; see the file COPYING. If not, write to the 2033965Sjdp Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2133965Sjdp 02111-1307, USA. */ 2233965Sjdp 2333965Sjdp#include <stdio.h> 2433965Sjdp#include "ansidecl.h" 2533965Sjdp#include "opcode/alpha.h" 2633965Sjdp#include "bfd.h" 2733965Sjdp 2833965Sjdp/* This file holds the Alpha AXP opcode table. The opcode table includes 2933965Sjdp almost all of the extended instruction mnemonics. This permits the 3033965Sjdp disassembler to use them, and simplifies the assembler logic, at the 3133965Sjdp cost of increasing the table size. The table is strictly constant 3233965Sjdp data, so the compiler should be able to put it in the .text section. 3333965Sjdp 3433965Sjdp This file also holds the operand table. All knowledge about inserting 3533965Sjdp operands into instructions and vice-versa is kept in this file. 3633965Sjdp 3733965Sjdp The information for the base instruction set was compiled from the 3833965Sjdp _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, 3933965Sjdp version 2. 4033965Sjdp 4133965Sjdp The information for the post-ev5 architecture extensions BWX, CIX and 4233965Sjdp MAX came from version 3 of this same document, which is also available 4333965Sjdp on-line at http://ftp.digital.com/pub/Digital/info/semiconductor 4433965Sjdp /literature/alphahb2.pdf 4533965Sjdp 4633965Sjdp The information for the EV4 PALcode instructions was compiled from 4733965Sjdp _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware 4833965Sjdp Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary 4933965Sjdp revision dated June 1994. 5033965Sjdp 5133965Sjdp The information for the EV5 PALcode instructions was compiled from 5233965Sjdp _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital 5333965Sjdp Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ 5433965Sjdp 5533965Sjdp/* Local insertion and extraction functions */ 5633965Sjdp 5733965Sjdpstatic unsigned insert_rba PARAMS((unsigned, int, const char **)); 5833965Sjdpstatic unsigned insert_rca PARAMS((unsigned, int, const char **)); 5933965Sjdpstatic unsigned insert_za PARAMS((unsigned, int, const char **)); 6033965Sjdpstatic unsigned insert_zb PARAMS((unsigned, int, const char **)); 6133965Sjdpstatic unsigned insert_zc PARAMS((unsigned, int, const char **)); 6233965Sjdpstatic unsigned insert_bdisp PARAMS((unsigned, int, const char **)); 6333965Sjdpstatic unsigned insert_jhint PARAMS((unsigned, int, const char **)); 6433965Sjdp 6533965Sjdpstatic int extract_rba PARAMS((unsigned, int *)); 6633965Sjdpstatic int extract_rca PARAMS((unsigned, int *)); 6733965Sjdpstatic int extract_za PARAMS((unsigned, int *)); 6833965Sjdpstatic int extract_zb PARAMS((unsigned, int *)); 6933965Sjdpstatic int extract_zc PARAMS((unsigned, int *)); 7033965Sjdpstatic int extract_bdisp PARAMS((unsigned, int *)); 7133965Sjdpstatic int extract_jhint PARAMS((unsigned, int *)); 7233965Sjdp 7333965Sjdp 7433965Sjdp/* The operands table */ 7533965Sjdp 7633965Sjdpconst struct alpha_operand alpha_operands[] = 7733965Sjdp{ 7833965Sjdp /* The fields are bits, shift, insert, extract, flags */ 7933965Sjdp /* The zero index is used to indicate end-of-list */ 8033965Sjdp#define UNUSED 0 8133965Sjdp { 0, 0, 0, 0, 0 }, 8233965Sjdp 8333965Sjdp /* The plain integer register fields */ 8433965Sjdp#define RA (UNUSED + 1) 8533965Sjdp { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, 8633965Sjdp#define RB (RA + 1) 8733965Sjdp { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, 8833965Sjdp#define RC (RB + 1) 8933965Sjdp { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, 9033965Sjdp 9133965Sjdp /* The plain fp register fields */ 9233965Sjdp#define FA (RC + 1) 9333965Sjdp { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, 9433965Sjdp#define FB (FA + 1) 9533965Sjdp { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, 9633965Sjdp#define FC (FB + 1) 9733965Sjdp { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, 9833965Sjdp 9933965Sjdp /* The integer registers when they are ZERO */ 10033965Sjdp#define ZA (FC + 1) 10133965Sjdp { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, 10233965Sjdp#define ZB (ZA + 1) 10333965Sjdp { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, 10433965Sjdp#define ZC (ZB + 1) 10533965Sjdp { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, 10633965Sjdp 10733965Sjdp /* The RB field when it needs parentheses */ 10833965Sjdp#define PRB (ZC + 1) 10933965Sjdp { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, 11033965Sjdp 11133965Sjdp /* The RB field when it needs parentheses _and_ a preceding comma */ 11233965Sjdp#define CPRB (PRB + 1) 11333965Sjdp { 5, 16, 0, 11433965Sjdp AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, 11533965Sjdp 11633965Sjdp /* The RB field when it must be the same as the RA field */ 11733965Sjdp#define RBA (CPRB + 1) 11833965Sjdp { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, 11933965Sjdp 12033965Sjdp /* The RC field when it must be the same as the RB field */ 12133965Sjdp#define RCA (RBA + 1) 12233965Sjdp { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, 12333965Sjdp 12433965Sjdp /* The RC field when it can *default* to RA */ 12533965Sjdp#define DRC1 (RCA + 1) 12633965Sjdp { 5, 0, 0, 12733965Sjdp AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 12833965Sjdp 12933965Sjdp /* The RC field when it can *default* to RB */ 13033965Sjdp#define DRC2 (DRC1 + 1) 13133965Sjdp { 5, 0, 0, 13233965Sjdp AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 13333965Sjdp 13433965Sjdp /* The FC field when it can *default* to RA */ 13533965Sjdp#define DFC1 (DRC2 + 1) 13633965Sjdp { 5, 0, 0, 13733965Sjdp AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 13833965Sjdp 13933965Sjdp /* The FC field when it can *default* to RB */ 14033965Sjdp#define DFC2 (DFC1 + 1) 14133965Sjdp { 5, 0, 0, 14233965Sjdp AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 14333965Sjdp 14433965Sjdp /* The unsigned 8-bit literal of Operate format insns */ 14533965Sjdp#define LIT (DFC2 + 1) 14633965Sjdp { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, 14733965Sjdp 14833965Sjdp /* The signed 16-bit displacement of Memory format insns. From here 14933965Sjdp we can't tell what relocation should be used, so don't use a default. */ 15033965Sjdp#define MDISP (LIT + 1) 15133965Sjdp { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, 15233965Sjdp 15333965Sjdp /* The signed "23-bit" aligned displacement of Branch format insns */ 15433965Sjdp#define BDISP (MDISP + 1) 15533965Sjdp { 21, 0, BFD_RELOC_23_PCREL_S2, 15633965Sjdp AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, 15733965Sjdp 15833965Sjdp /* The 26-bit PALcode function */ 15933965Sjdp#define PALFN (BDISP + 1) 16033965Sjdp { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, 16133965Sjdp 16233965Sjdp /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ 16333965Sjdp#define JMPHINT (PALFN + 1) 16433965Sjdp { 14, 0, BFD_RELOC_ALPHA_HINT, 16533965Sjdp AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 16633965Sjdp insert_jhint, extract_jhint }, 16733965Sjdp 16833965Sjdp /* The optional hint to RET/JSR_COROUTINE */ 16933965Sjdp#define RETHINT (JMPHINT + 1) 17033965Sjdp { 14, 0, -RETHINT, 17133965Sjdp AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, 17233965Sjdp 17333965Sjdp /* The 12-bit displacement for the ev4 hw_{ld,st} (pal1b/pal1f) insns */ 17433965Sjdp#define EV4HWDISP (RETHINT + 1) 17533965Sjdp { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 17633965Sjdp 17733965Sjdp /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ 17833965Sjdp#define EV4HWINDEX (EV4HWDISP + 1) 17933965Sjdp { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 18033965Sjdp 18133965Sjdp /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns 18233965Sjdp that occur in DEC PALcode. */ 18333965Sjdp#define EV4EXTHWINDEX (EV4HWINDEX + 1) 18433965Sjdp { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 18533965Sjdp 18633965Sjdp /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ 18733965Sjdp#define EV5HWDISP (EV4EXTHWINDEX + 1) 18833965Sjdp { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 18933965Sjdp 19033965Sjdp /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ 19133965Sjdp#define EV5HWINDEX (EV5HWDISP + 1) 19233965Sjdp { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 19333965Sjdp}; 19433965Sjdp 19533965Sjdpconst int alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); 19633965Sjdp 19733965Sjdp/* The RB field when it is the same as the RA field in the same insn. 19833965Sjdp This operand is marked fake. The insertion function just copies 19933965Sjdp the RA field into the RB field, and the extraction function just 20033965Sjdp checks that the fields are the same. */ 20133965Sjdp 20233965Sjdp/*ARGSUSED*/ 20333965Sjdpstatic unsigned 20433965Sjdpinsert_rba(insn, value, errmsg) 20533965Sjdp unsigned insn; 20633965Sjdp int value; 20733965Sjdp const char **errmsg; 20833965Sjdp{ 20933965Sjdp return insn | (((insn >> 21) & 0x1f) << 16); 21033965Sjdp} 21133965Sjdp 21233965Sjdpstatic int 21333965Sjdpextract_rba(insn, invalid) 21433965Sjdp unsigned insn; 21533965Sjdp int *invalid; 21633965Sjdp{ 21733965Sjdp if (invalid != (int *) NULL 21833965Sjdp && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 21933965Sjdp *invalid = 1; 22033965Sjdp return 0; 22133965Sjdp} 22233965Sjdp 22333965Sjdp 22433965Sjdp/* The same for the RC field */ 22533965Sjdp 22633965Sjdp/*ARGSUSED*/ 22733965Sjdpstatic unsigned 22833965Sjdpinsert_rca(insn, value, errmsg) 22933965Sjdp unsigned insn; 23033965Sjdp int value; 23133965Sjdp const char **errmsg; 23233965Sjdp{ 23333965Sjdp return insn | ((insn >> 21) & 0x1f); 23433965Sjdp} 23533965Sjdp 23633965Sjdpstatic int 23733965Sjdpextract_rca(insn, invalid) 23833965Sjdp unsigned insn; 23933965Sjdp int *invalid; 24033965Sjdp{ 24133965Sjdp if (invalid != (int *) NULL 24233965Sjdp && ((insn >> 21) & 0x1f) != (insn & 0x1f)) 24333965Sjdp *invalid = 1; 24433965Sjdp return 0; 24533965Sjdp} 24633965Sjdp 24733965Sjdp 24833965Sjdp/* Fake arguments in which the registers must be set to ZERO */ 24933965Sjdp 25033965Sjdp/*ARGSUSED*/ 25133965Sjdpstatic unsigned 25233965Sjdpinsert_za(insn, value, errmsg) 25333965Sjdp unsigned insn; 25433965Sjdp int value; 25533965Sjdp const char **errmsg; 25633965Sjdp{ 25733965Sjdp return insn | (31 << 21); 25833965Sjdp} 25933965Sjdp 26033965Sjdpstatic int 26133965Sjdpextract_za(insn, invalid) 26233965Sjdp unsigned insn; 26333965Sjdp int *invalid; 26433965Sjdp{ 26533965Sjdp if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) 26633965Sjdp *invalid = 1; 26733965Sjdp return 0; 26833965Sjdp} 26933965Sjdp 27033965Sjdp/*ARGSUSED*/ 27133965Sjdpstatic unsigned 27233965Sjdpinsert_zb(insn, value, errmsg) 27333965Sjdp unsigned insn; 27433965Sjdp int value; 27533965Sjdp const char **errmsg; 27633965Sjdp{ 27733965Sjdp return insn | (31 << 16); 27833965Sjdp} 27933965Sjdp 28033965Sjdpstatic int 28133965Sjdpextract_zb(insn, invalid) 28233965Sjdp unsigned insn; 28333965Sjdp int *invalid; 28433965Sjdp{ 28533965Sjdp if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) 28633965Sjdp *invalid = 1; 28733965Sjdp return 0; 28833965Sjdp} 28933965Sjdp 29033965Sjdp/*ARGSUSED*/ 29133965Sjdpstatic unsigned 29233965Sjdpinsert_zc(insn, value, errmsg) 29333965Sjdp unsigned insn; 29433965Sjdp int value; 29533965Sjdp const char **errmsg; 29633965Sjdp{ 29733965Sjdp return insn | 31; 29833965Sjdp} 29933965Sjdp 30033965Sjdpstatic int 30133965Sjdpextract_zc(insn, invalid) 30233965Sjdp unsigned insn; 30333965Sjdp int *invalid; 30433965Sjdp{ 30533965Sjdp if (invalid != (int *) NULL && (insn & 0x1f) != 31) 30633965Sjdp *invalid = 1; 30733965Sjdp return 0; 30833965Sjdp} 30933965Sjdp 31033965Sjdp 31133965Sjdp/* The displacement field of a Branch format insn. */ 31233965Sjdp 31333965Sjdpstatic unsigned 31433965Sjdpinsert_bdisp(insn, value, errmsg) 31533965Sjdp unsigned insn; 31633965Sjdp int value; 31733965Sjdp const char **errmsg; 31833965Sjdp{ 31933965Sjdp if (errmsg != (const char **)NULL && (value & 3)) 32033965Sjdp *errmsg = "branch operand unaligned"; 32133965Sjdp return insn | ((value / 4) & 0x1FFFFF); 32233965Sjdp} 32333965Sjdp 32433965Sjdp/*ARGSUSED*/ 32533965Sjdpstatic int 32633965Sjdpextract_bdisp(insn, invalid) 32733965Sjdp unsigned insn; 32833965Sjdp int *invalid; 32933965Sjdp{ 33033965Sjdp return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); 33133965Sjdp} 33233965Sjdp 33333965Sjdp 33433965Sjdp/* The hint field of a JMP/JSR insn. */ 33533965Sjdp 33633965Sjdpstatic unsigned 33733965Sjdpinsert_jhint(insn, value, errmsg) 33833965Sjdp unsigned insn; 33933965Sjdp int value; 34033965Sjdp const char **errmsg; 34133965Sjdp{ 34233965Sjdp if (errmsg != (const char **)NULL && (value & 3)) 34333965Sjdp *errmsg = "jump hint unaligned"; 34433965Sjdp return insn | ((value / 4) & 0xFFFF); 34533965Sjdp} 34633965Sjdp 34733965Sjdp/*ARGSUSED*/ 34833965Sjdpstatic int 34933965Sjdpextract_jhint(insn, invalid) 35033965Sjdp unsigned insn; 35133965Sjdp int *invalid; 35233965Sjdp{ 35333965Sjdp return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); 35433965Sjdp} 35533965Sjdp 35633965Sjdp 35733965Sjdp/* Macros used to form opcodes */ 35833965Sjdp 35933965Sjdp/* The main opcode */ 36033965Sjdp#define OP(x) (((x) & 0x3F) << 26) 36133965Sjdp#define OP_MASK 0xFC000000 36233965Sjdp 36333965Sjdp/* Branch format instructions */ 36433965Sjdp#define BRA_(oo) OP(oo) 36533965Sjdp#define BRA_MASK OP_MASK 36633965Sjdp#define BRA(oo) BRA_(oo), BRA_MASK 36733965Sjdp 36833965Sjdp/* Floating point format instructions */ 36933965Sjdp#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) 37033965Sjdp#define FP_MASK (OP_MASK | 0xFFE0) 37133965Sjdp#define FP(oo,fff) FP_(oo,fff), FP_MASK 37233965Sjdp 37333965Sjdp/* Memory format instructions */ 37433965Sjdp#define MEM_(oo) OP(oo) 37533965Sjdp#define MEM_MASK OP_MASK 37633965Sjdp#define MEM(oo) MEM_(oo), MEM_MASK 37733965Sjdp 37833965Sjdp/* Memory/Func Code format instructions */ 37933965Sjdp#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) 38033965Sjdp#define MFC_MASK (OP_MASK | 0xFFFF) 38133965Sjdp#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK 38233965Sjdp 38333965Sjdp/* Memory/Branch format instructions */ 38433965Sjdp#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) 38533965Sjdp#define MBR_MASK (OP_MASK | 0xC000) 38633965Sjdp#define MBR(oo,h) MBR_(oo,h), MBR_MASK 38733965Sjdp 38833965Sjdp/* Operate format instructions. The OPRL variant specifies a 38933965Sjdp literal second argument. */ 39033965Sjdp#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) 39133965Sjdp#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) 39233965Sjdp#define OPR_MASK (OP_MASK | 0x1FE0) 39333965Sjdp#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK 39433965Sjdp#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK 39533965Sjdp 39633965Sjdp/* Generic PALcode format instructions */ 39733965Sjdp#define PCD_(oo) OP(oo) 39833965Sjdp#define PCD_MASK OP_MASK 39933965Sjdp#define PCD(oo) PCD_(oo), PCD_MASK 40033965Sjdp 40133965Sjdp/* Specific PALcode instructions */ 40233965Sjdp#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) 40333965Sjdp#define SPCD_MASK 0xFFFFFFFF 40433965Sjdp#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK 40533965Sjdp 40633965Sjdp/* Hardware memory (hw_{ld,st}) instructions */ 40733965Sjdp#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 40833965Sjdp#define EV4HWMEM_MASK (OP_MASK | 0xF000) 40933965Sjdp#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK 41033965Sjdp 41133965Sjdp#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) 41233965Sjdp#define EV5HWMEM_MASK (OP_MASK | 0xF800) 41333965Sjdp#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK 41433965Sjdp 41533965Sjdp/* Abbreviations for instruction subsets. */ 41633965Sjdp#define BASE AXP_OPCODE_BASE 41733965Sjdp#define EV4 AXP_OPCODE_EV4 41833965Sjdp#define EV5 AXP_OPCODE_EV5 41933965Sjdp#define BWX AXP_OPCODE_BWX 42033965Sjdp#define CIX AXP_OPCODE_CIX 42133965Sjdp#define MAX AXP_OPCODE_MAX 42233965Sjdp 42333965Sjdp/* Common combinations of arguments */ 42433965Sjdp#define ARG_NONE { 0 } 42533965Sjdp#define ARG_BRA { RA, BDISP } 42633965Sjdp#define ARG_FBRA { FA, BDISP } 42733965Sjdp#define ARG_FP { FA, FB, DFC1 } 42833965Sjdp#define ARG_FPZ1 { ZA, FB, DFC1 } 42933965Sjdp#define ARG_MEM { RA, MDISP, PRB } 43033965Sjdp#define ARG_FMEM { FA, MDISP, PRB } 43133965Sjdp#define ARG_OPR { RA, RB, DRC1 } 43233965Sjdp#define ARG_OPRL { RA, LIT, DRC1 } 43333965Sjdp#define ARG_OPRZ1 { ZA, RB, DRC1 } 43433965Sjdp#define ARG_OPRLZ1 { ZA, LIT, RC } 43533965Sjdp#define ARG_PCD { PALFN } 43633965Sjdp#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } 43733965Sjdp#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } 43833965Sjdp#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } 43933965Sjdp 44033965Sjdp 44133965Sjdp/* The opcode table. 44233965Sjdp 44333965Sjdp The format of the opcode table is: 44433965Sjdp 44533965Sjdp NAME OPCODE MASK { OPERANDS } 44633965Sjdp 44733965Sjdp NAME is the name of the instruction. 44833965Sjdp 44933965Sjdp OPCODE is the instruction opcode. 45033965Sjdp 45133965Sjdp MASK is the opcode mask; this is used to tell the disassembler 45233965Sjdp which bits in the actual opcode must match OPCODE. 45333965Sjdp 45433965Sjdp OPERANDS is the list of operands. 45533965Sjdp 45633965Sjdp The preceding macros merge the text of the OPCODE and MASK fields. 45733965Sjdp 45833965Sjdp The disassembler reads the table in order and prints the first 45933965Sjdp instruction which matches, so this table is sorted to put more 46033965Sjdp specific instructions before more general instructions. 46133965Sjdp 46233965Sjdp Otherwise, it is sorted by major opcode and minor function code. 46333965Sjdp 46433965Sjdp There are three classes of not-really-instructions in this table: 46533965Sjdp 46633965Sjdp ALIAS is another name for another instruction. Some of 46733965Sjdp these come from the Architecture Handbook, some 46833965Sjdp come from the original gas opcode tables. In all 46933965Sjdp cases, the functionality of the opcode is unchanged. 47033965Sjdp 47133965Sjdp PSEUDO a stylized code form endorsed by Chapter A.4 of the 47233965Sjdp Architecture Handbook. 47333965Sjdp 47433965Sjdp EXTRA a stylized code form found in the original gas tables. 47533965Sjdp 47633965Sjdp And two annotations: 47733965Sjdp 47833965Sjdp EV56 BUT opcodes that are officially introduced as of the ev56, 47933965Sjdp but with defined results on previous implementations. 48033965Sjdp 48133965Sjdp EV56 UNA opcodes that were introduced as of the ev56 with 48233965Sjdp presumably undefined results on previous implementations 48333965Sjdp that were not assigned to a particular extension. 48433965Sjdp*/ 48533965Sjdp 48633965Sjdpconst struct alpha_opcode alpha_opcodes[] = { 48733965Sjdp { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, 48833965Sjdp { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, 48933965Sjdp { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, 49033965Sjdp { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, 49133965Sjdp { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, 49233965Sjdp { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, 49333965Sjdp { "call_pal", PCD(0x00), BASE, ARG_PCD }, 49433965Sjdp { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ 49533965Sjdp 49633965Sjdp { "lda", MEM(0x08), BASE, ARG_MEM }, 49733965Sjdp { "ldah", MEM(0x09), BASE, ARG_MEM }, 49833965Sjdp { "ldbu", MEM(0x0A), BWX, ARG_MEM }, 49933965Sjdp { "unop", MEM(0x0B), BASE, { ZA } }, /* pseudo */ 50033965Sjdp { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, 50133965Sjdp { "ldwu", MEM(0x0C), BWX, ARG_MEM }, 50233965Sjdp { "stw", MEM(0x0D), BWX, ARG_MEM }, 50333965Sjdp { "stb", MEM(0x0E), BWX, ARG_MEM }, 50433965Sjdp { "stq_u", MEM(0x0F), BASE, ARG_MEM }, 50533965Sjdp 50633965Sjdp { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ 50733965Sjdp { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ 50833965Sjdp { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, 50933965Sjdp { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, 51033965Sjdp { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, 51133965Sjdp { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, 51233965Sjdp { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ 51333965Sjdp { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ 51433965Sjdp { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, 51533965Sjdp { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, 51633965Sjdp { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, 51733965Sjdp { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, 51833965Sjdp { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, 51933965Sjdp { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, 52033965Sjdp { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, 52133965Sjdp { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, 52233965Sjdp { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, 52333965Sjdp { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, 52433965Sjdp { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, 52533965Sjdp { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, 52633965Sjdp { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, 52733965Sjdp { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, 52833965Sjdp { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, 52933965Sjdp { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, 53033965Sjdp { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ 53133965Sjdp { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ 53233965Sjdp { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, 53333965Sjdp { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, 53433965Sjdp { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, 53533965Sjdp { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, 53633965Sjdp { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, 53733965Sjdp { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, 53833965Sjdp { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, 53933965Sjdp { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, 54033965Sjdp { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, 54133965Sjdp { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, 54233965Sjdp { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, 54333965Sjdp { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, 54433965Sjdp { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, 54533965Sjdp { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, 54633965Sjdp { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ 54733965Sjdp { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ 54833965Sjdp { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, 54933965Sjdp { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, 55033965Sjdp { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, 55133965Sjdp { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, 55233965Sjdp { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, 55333965Sjdp { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, 55433965Sjdp { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ 55533965Sjdp { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ 55633965Sjdp { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, 55733965Sjdp { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, 55833965Sjdp { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, 55933965Sjdp { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, 56033965Sjdp 56133965Sjdp { "and", OPR(0x11,0x00), BASE, ARG_OPR }, 56233965Sjdp { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, 56333965Sjdp { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ 56433965Sjdp { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ 56533965Sjdp { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, 56633965Sjdp { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, 56733965Sjdp { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, 56833965Sjdp { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, 56933965Sjdp { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, 57033965Sjdp { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, 57133965Sjdp { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ 57233965Sjdp { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ 57333965Sjdp { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ 57433965Sjdp { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ 57533965Sjdp { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ 57633965Sjdp { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ 57733965Sjdp { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ 57833965Sjdp { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, 57933965Sjdp { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, 58033965Sjdp { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, 58133965Sjdp { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, 58233965Sjdp { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, 58333965Sjdp { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, 58433965Sjdp { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ 58533965Sjdp { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ 58633965Sjdp { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, 58733965Sjdp { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, 58833965Sjdp { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, 58933965Sjdp { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, 59033965Sjdp { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, 59133965Sjdp { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, 59233965Sjdp { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, 59333965Sjdp { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, 59433965Sjdp { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, 59533965Sjdp { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, 59633965Sjdp { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ 59733965Sjdp { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ 59833965Sjdp { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ 59933965Sjdp { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ 60033965Sjdp { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, 60133965Sjdp { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, 60233965Sjdp { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, 60333965Sjdp { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, 60433965Sjdp { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), 60533965Sjdp 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ 60633965Sjdp 60733965Sjdp { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, 60833965Sjdp { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, 60933965Sjdp { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, 61033965Sjdp { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, 61133965Sjdp { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, 61233965Sjdp { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, 61333965Sjdp { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, 61433965Sjdp { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, 61533965Sjdp { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, 61633965Sjdp { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, 61733965Sjdp { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, 61833965Sjdp { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, 61933965Sjdp { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, 62033965Sjdp { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, 62133965Sjdp { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, 62233965Sjdp { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, 62333965Sjdp { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, 62433965Sjdp { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, 62533965Sjdp { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, 62633965Sjdp { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, 62733965Sjdp { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, 62833965Sjdp { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, 62933965Sjdp { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, 63033965Sjdp { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, 63133965Sjdp { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, 63233965Sjdp { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, 63333965Sjdp { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, 63433965Sjdp { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, 63533965Sjdp { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, 63633965Sjdp { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, 63733965Sjdp { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, 63833965Sjdp { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, 63933965Sjdp { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, 64033965Sjdp { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, 64133965Sjdp { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, 64233965Sjdp { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, 64333965Sjdp { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, 64433965Sjdp { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, 64533965Sjdp { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, 64633965Sjdp { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, 64733965Sjdp { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, 64833965Sjdp { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, 64933965Sjdp { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, 65033965Sjdp { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, 65133965Sjdp { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, 65233965Sjdp { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, 65333965Sjdp { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, 65433965Sjdp { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, 65533965Sjdp { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, 65633965Sjdp { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, 65733965Sjdp { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, 65833965Sjdp { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, 65933965Sjdp 66033965Sjdp { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, 66133965Sjdp { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, 66233965Sjdp { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, 66333965Sjdp { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, 66433965Sjdp { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, 66533965Sjdp { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, 66633965Sjdp { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, 66733965Sjdp { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, 66833965Sjdp { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, 66933965Sjdp { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, 67033965Sjdp 67133965Sjdp { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, 67233965Sjdp { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, 67333965Sjdp { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, 67433965Sjdp { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, 67533965Sjdp { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, 67633965Sjdp { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, 67733965Sjdp { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, 67833965Sjdp 67933965Sjdp { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, 68033965Sjdp { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, 68133965Sjdp { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, 68233965Sjdp { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, 68333965Sjdp { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, 68433965Sjdp { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, 68533965Sjdp { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, 68633965Sjdp { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, 68733965Sjdp { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, 68833965Sjdp { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, 68933965Sjdp { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, 69033965Sjdp { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, 69133965Sjdp { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, 69233965Sjdp { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, 69333965Sjdp { "addf", FP(0x15,0x080), BASE, ARG_FP }, 69433965Sjdp { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 69533965Sjdp { "subf", FP(0x15,0x081), BASE, ARG_FP }, 69633965Sjdp { "mulf", FP(0x15,0x082), BASE, ARG_FP }, 69733965Sjdp { "divf", FP(0x15,0x083), BASE, ARG_FP }, 69833965Sjdp { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, 69933965Sjdp { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, 70033965Sjdp { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 70133965Sjdp { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, 70233965Sjdp { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, 70333965Sjdp { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, 70433965Sjdp { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, 70533965Sjdp { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, 70633965Sjdp { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, 70733965Sjdp { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, 70833965Sjdp { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, 70933965Sjdp { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, 71033965Sjdp { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, 71133965Sjdp { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, 71233965Sjdp { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, 71333965Sjdp { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, 71433965Sjdp { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, 71533965Sjdp { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, 71633965Sjdp { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, 71733965Sjdp { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, 71833965Sjdp { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, 71933965Sjdp { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, 72033965Sjdp { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, 72133965Sjdp { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, 72233965Sjdp { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, 72333965Sjdp { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, 72433965Sjdp { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, 72533965Sjdp { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, 72633965Sjdp { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, 72733965Sjdp { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, 72833965Sjdp { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, 72933965Sjdp { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, 73033965Sjdp { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, 73133965Sjdp { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, 73233965Sjdp { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, 73333965Sjdp { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, 73433965Sjdp { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, 73533965Sjdp { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, 73633965Sjdp { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, 73733965Sjdp { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, 73833965Sjdp { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, 73933965Sjdp { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, 74033965Sjdp { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, 74133965Sjdp { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, 74233965Sjdp { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, 74333965Sjdp { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, 74433965Sjdp { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, 74533965Sjdp { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, 74633965Sjdp { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, 74733965Sjdp { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, 74833965Sjdp { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, 74933965Sjdp { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ 75033965Sjdp { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, 75133965Sjdp { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, 75233965Sjdp { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, 75333965Sjdp { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, 75433965Sjdp { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, 75533965Sjdp { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ 75633965Sjdp { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, 75733965Sjdp { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, 75833965Sjdp { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, 75933965Sjdp { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, 76033965Sjdp { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, 76133965Sjdp { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, 76233965Sjdp { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, 76333965Sjdp { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, 76433965Sjdp { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, 76533965Sjdp { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, 76633965Sjdp { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, 76733965Sjdp { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, 76833965Sjdp { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, 76933965Sjdp { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, 77033965Sjdp { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, 77133965Sjdp { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, 77233965Sjdp { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, 77333965Sjdp { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, 77433965Sjdp { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, 77533965Sjdp { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, 77633965Sjdp { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, 77733965Sjdp { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, 77833965Sjdp { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, 77933965Sjdp { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, 78033965Sjdp { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, 78133965Sjdp { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, 78233965Sjdp { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, 78333965Sjdp { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, 78433965Sjdp { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, 78533965Sjdp { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, 78633965Sjdp { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, 78733965Sjdp { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, 78833965Sjdp { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, 78933965Sjdp 79033965Sjdp { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, 79133965Sjdp { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, 79233965Sjdp { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, 79333965Sjdp { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, 79433965Sjdp { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, 79533965Sjdp { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, 79633965Sjdp { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, 79733965Sjdp { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, 79833965Sjdp { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, 79933965Sjdp { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, 80033965Sjdp { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, 80133965Sjdp { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, 80233965Sjdp { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, 80333965Sjdp { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, 80433965Sjdp { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, 80533965Sjdp { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, 80633965Sjdp { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, 80733965Sjdp { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, 80833965Sjdp { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, 80933965Sjdp { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, 81033965Sjdp { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, 81133965Sjdp { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, 81233965Sjdp { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, 81333965Sjdp { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, 81433965Sjdp { "adds", FP(0x16,0x080), BASE, ARG_FP }, 81533965Sjdp { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 81633965Sjdp { "subs", FP(0x16,0x081), BASE, ARG_FP }, 81733965Sjdp { "muls", FP(0x16,0x082), BASE, ARG_FP }, 81833965Sjdp { "divs", FP(0x16,0x083), BASE, ARG_FP }, 81933965Sjdp { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, 82033965Sjdp { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 82133965Sjdp { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, 82233965Sjdp { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, 82333965Sjdp { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, 82433965Sjdp { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, 82533965Sjdp { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, 82633965Sjdp { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, 82733965Sjdp { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, 82833965Sjdp { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, 82933965Sjdp { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, 83033965Sjdp { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, 83133965Sjdp { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, 83233965Sjdp { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, 83333965Sjdp { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, 83433965Sjdp { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, 83533965Sjdp { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, 83633965Sjdp { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, 83733965Sjdp { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, 83833965Sjdp { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, 83933965Sjdp { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, 84033965Sjdp { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, 84133965Sjdp { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, 84233965Sjdp { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, 84333965Sjdp { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, 84433965Sjdp { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, 84533965Sjdp { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, 84633965Sjdp { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, 84733965Sjdp { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, 84833965Sjdp { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, 84933965Sjdp { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, 85033965Sjdp { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, 85133965Sjdp { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, 85233965Sjdp { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, 85333965Sjdp { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, 85433965Sjdp { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, 85533965Sjdp { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, 85633965Sjdp { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, 85733965Sjdp { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, 85833965Sjdp { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, 85933965Sjdp { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, 86033965Sjdp { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, 86133965Sjdp { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, 86233965Sjdp { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, 86338889Sjdp { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, 86433965Sjdp { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, 86533965Sjdp { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, 86633965Sjdp { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, 86733965Sjdp { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, 86833965Sjdp { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, 86933965Sjdp { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, 87033965Sjdp { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, 87133965Sjdp { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, 87233965Sjdp { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, 87333965Sjdp { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, 87433965Sjdp { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, 87533965Sjdp { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, 87633965Sjdp { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, 87733965Sjdp { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, 87833965Sjdp { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, 87933965Sjdp { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, 88033965Sjdp { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, 88133965Sjdp { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, 88233965Sjdp { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, 88338889Sjdp { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, 88433965Sjdp { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, 88533965Sjdp { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, 88633965Sjdp { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, 88733965Sjdp { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, 88833965Sjdp { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, 88933965Sjdp { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, 89033965Sjdp { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, 89133965Sjdp { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, 89233965Sjdp { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, 89333965Sjdp { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, 89433965Sjdp { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, 89533965Sjdp { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, 89633965Sjdp { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, 89733965Sjdp { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, 89833965Sjdp { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, 89933965Sjdp { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, 90033965Sjdp { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, 90133965Sjdp { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, 90233965Sjdp { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, 90333965Sjdp { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, 90438889Sjdp { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, 90533965Sjdp { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, 90633965Sjdp { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ 90733965Sjdp { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, 90833965Sjdp { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, 90933965Sjdp { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, 91033965Sjdp { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, 91133965Sjdp { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ 91233965Sjdp { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, 91333965Sjdp { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, 91433965Sjdp { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, 91533965Sjdp { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, 91633965Sjdp { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, 91733965Sjdp { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, 91833965Sjdp { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, 91933965Sjdp { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, 92033965Sjdp { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, 92133965Sjdp { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, 92233965Sjdp { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, 92333965Sjdp { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, 92433965Sjdp { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, 92533965Sjdp { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, 92633965Sjdp { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, 92733965Sjdp { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, 92833965Sjdp { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, 92933965Sjdp { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, 93038889Sjdp { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, 93133965Sjdp { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, 93233965Sjdp { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, 93333965Sjdp { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, 93433965Sjdp { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, 93533965Sjdp { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, 93633965Sjdp { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, 93733965Sjdp { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, 93833965Sjdp { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, 93933965Sjdp { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, 94033965Sjdp { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, 94133965Sjdp { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, 94233965Sjdp { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, 94333965Sjdp { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, 94433965Sjdp { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, 94533965Sjdp { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, 94633965Sjdp { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, 94733965Sjdp { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, 94833965Sjdp { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, 94933965Sjdp { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, 95033965Sjdp { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, 95133965Sjdp { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, 95233965Sjdp { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, 95338889Sjdp { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, 95433965Sjdp { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, 95533965Sjdp { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, 95633965Sjdp { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, 95733965Sjdp { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ 95833965Sjdp { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, 95933965Sjdp { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, 96033965Sjdp { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, 96133965Sjdp { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, 96233965Sjdp { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ 96333965Sjdp { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, 96433965Sjdp { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, 96533965Sjdp { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, 96633965Sjdp { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, 96733965Sjdp { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, 96833965Sjdp { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, 96933965Sjdp { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, 97033965Sjdp { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, 97133965Sjdp { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, 97233965Sjdp { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, 97333965Sjdp { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, 97433965Sjdp { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, 97533965Sjdp { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, 97633965Sjdp { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, 97733965Sjdp { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, 97833965Sjdp { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, 97938889Sjdp { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, 98033965Sjdp { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, 98133965Sjdp { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, 98233965Sjdp 98333965Sjdp { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, 98433965Sjdp { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ 98533965Sjdp { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ 98633965Sjdp { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ 98733965Sjdp { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ 98833965Sjdp { "cpys", FP(0x17,0x020), BASE, ARG_FP }, 98933965Sjdp { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ 99033965Sjdp { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, 99133965Sjdp { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, 99233965Sjdp { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, 99333965Sjdp { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, 99433965Sjdp { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, 99533965Sjdp { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, 99633965Sjdp { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, 99733965Sjdp { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, 99833965Sjdp { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, 99933965Sjdp { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, 100033965Sjdp { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, 100133965Sjdp { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, 100233965Sjdp { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, 100333965Sjdp 100433965Sjdp { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, 100533965Sjdp { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ 100633965Sjdp { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, 100733965Sjdp { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, 100833965Sjdp { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, 100933965Sjdp { "fetch", MFC(0x18,0x8000), BASE, { PRB } }, 101033965Sjdp { "fetch_m", MFC(0x18,0xA000), BASE, { PRB } }, 101133965Sjdp { "rpcc", MFC(0x18,0xC000), BASE, { RA } }, 101233965Sjdp { "rc", MFC(0x18,0xE000), BASE, { RA } }, 101333965Sjdp { "ecb", MFC(0x18,0xE800), BASE, { PRB } }, /* ev56 una */ 101433965Sjdp { "rs", MFC(0x18,0xF000), BASE, { RA } }, 101533965Sjdp { "wh64", MFC(0x18,0xF800), BASE, { PRB } }, /* ev56 una */ 101633965Sjdp 101733965Sjdp { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 101833965Sjdp { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 101933965Sjdp { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, 102033965Sjdp { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, 102133965Sjdp { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, 102233965Sjdp { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, 102333965Sjdp { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, 102433965Sjdp { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, 102533965Sjdp { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, 102633965Sjdp { "pal19", PCD(0x19), BASE, ARG_PCD }, 102733965Sjdp 102833965Sjdp { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, 102933965Sjdp { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, 103033965Sjdp { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, 103133965Sjdp { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ 103233965Sjdp { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, 103333965Sjdp 103433965Sjdp { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 103533965Sjdp { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 103633965Sjdp { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 103733965Sjdp { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 103833965Sjdp { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 103933965Sjdp { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 104033965Sjdp { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 104133965Sjdp { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 104233965Sjdp { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 104333965Sjdp { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 104433965Sjdp { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 104533965Sjdp { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 104633965Sjdp { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 104733965Sjdp { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 104833965Sjdp { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 104933965Sjdp { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 105033965Sjdp { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 105133965Sjdp { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 105233965Sjdp { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 105333965Sjdp { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 105433965Sjdp { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 105533965Sjdp { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 105633965Sjdp { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 105733965Sjdp { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 105833965Sjdp { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 105933965Sjdp { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 106033965Sjdp { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 106133965Sjdp { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 106233965Sjdp { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 106333965Sjdp { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 106433965Sjdp { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 106533965Sjdp { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 106633965Sjdp { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 106733965Sjdp { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 106833965Sjdp { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 106933965Sjdp { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 107033965Sjdp { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 107133965Sjdp { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 107233965Sjdp { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 107333965Sjdp { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 107433965Sjdp { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 107533965Sjdp { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 107633965Sjdp { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 107733965Sjdp { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 107833965Sjdp { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 107933965Sjdp { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 108033965Sjdp { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 108133965Sjdp { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 108233965Sjdp { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 108333965Sjdp { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 108433965Sjdp { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 108533965Sjdp { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 108633965Sjdp { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 108733965Sjdp { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 108833965Sjdp { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 108933965Sjdp { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 109033965Sjdp { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 109133965Sjdp { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 109233965Sjdp { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 109333965Sjdp { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 109433965Sjdp { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 109533965Sjdp { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 109633965Sjdp { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 109733965Sjdp { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 109833965Sjdp { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 109933965Sjdp { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 110033965Sjdp { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 110133965Sjdp { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 110233965Sjdp { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 110333965Sjdp { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 110433965Sjdp { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 110533965Sjdp { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 110633965Sjdp { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 110733965Sjdp { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 110833965Sjdp { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 110933965Sjdp { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 111033965Sjdp { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 111133965Sjdp { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 111233965Sjdp { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 111333965Sjdp { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 111433965Sjdp { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 111533965Sjdp { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 111633965Sjdp { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 111733965Sjdp { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 111833965Sjdp { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 111933965Sjdp { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 112033965Sjdp { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 112133965Sjdp { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 112233965Sjdp { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 112333965Sjdp { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 112433965Sjdp { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 112533965Sjdp { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 112633965Sjdp { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 112733965Sjdp { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 112833965Sjdp { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 112933965Sjdp { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 113033965Sjdp { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 113133965Sjdp { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 113233965Sjdp { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 113333965Sjdp { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 113433965Sjdp { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 113533965Sjdp { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 113633965Sjdp { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 113733965Sjdp { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 113833965Sjdp { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 113933965Sjdp { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 114033965Sjdp { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 114133965Sjdp { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 114233965Sjdp { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 114333965Sjdp { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 114433965Sjdp { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 114533965Sjdp { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 114633965Sjdp { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 114733965Sjdp { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 114833965Sjdp { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 114933965Sjdp { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 115033965Sjdp { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 115133965Sjdp { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 115233965Sjdp { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 115333965Sjdp { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 115433965Sjdp { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 115533965Sjdp { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 115633965Sjdp { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 115733965Sjdp { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 115833965Sjdp { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 115933965Sjdp { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 116033965Sjdp { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 116133965Sjdp { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 116233965Sjdp { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 116333965Sjdp { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 116433965Sjdp { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 116533965Sjdp { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 116633965Sjdp { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 116733965Sjdp { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 116833965Sjdp { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 116933965Sjdp { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 117033965Sjdp { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 117133965Sjdp { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 117233965Sjdp { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 117333965Sjdp { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 117433965Sjdp { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 117533965Sjdp { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 117633965Sjdp { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 117733965Sjdp { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 117833965Sjdp { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 117933965Sjdp { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 118033965Sjdp { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 118133965Sjdp { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 118233965Sjdp { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 118333965Sjdp { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 118433965Sjdp { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 118533965Sjdp { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 118633965Sjdp { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 118733965Sjdp { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 118833965Sjdp { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 118933965Sjdp { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 119033965Sjdp { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 119133965Sjdp { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 119233965Sjdp { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 119333965Sjdp { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 119433965Sjdp { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 119533965Sjdp { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 119633965Sjdp { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 119733965Sjdp { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 119833965Sjdp { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 119933965Sjdp { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 120033965Sjdp { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 120133965Sjdp { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 120233965Sjdp { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 120333965Sjdp { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 120433965Sjdp { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 120533965Sjdp { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 120633965Sjdp { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 120733965Sjdp { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 120833965Sjdp { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 120933965Sjdp { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 121033965Sjdp { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 121133965Sjdp { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 121233965Sjdp { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 121333965Sjdp { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 121433965Sjdp { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 121533965Sjdp { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 121633965Sjdp { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 121733965Sjdp { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 121833965Sjdp { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 121933965Sjdp { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 122033965Sjdp { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 122133965Sjdp { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 122233965Sjdp { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 122333965Sjdp { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 122433965Sjdp { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 122533965Sjdp { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 122633965Sjdp { "pal1b", PCD(0x1B), BASE, ARG_PCD }, 122733965Sjdp 122833965Sjdp { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, 122933965Sjdp { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, 123033965Sjdp { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, 123133965Sjdp { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, 123233965Sjdp { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, 123333965Sjdp { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, 123433965Sjdp { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, 123533965Sjdp { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, 123633965Sjdp { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, 123733965Sjdp { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, 123833965Sjdp { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, 123933965Sjdp { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, 124033965Sjdp { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, 124133965Sjdp { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, 124233965Sjdp { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, 124333965Sjdp { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, 124433965Sjdp { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, 124533965Sjdp { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, 124633965Sjdp { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, 124733965Sjdp { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, 124833965Sjdp { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, 124933965Sjdp { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, 125033965Sjdp { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, 125133965Sjdp { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, 125233965Sjdp { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, 125333965Sjdp { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, 125433965Sjdp { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, 125533965Sjdp { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, 125633965Sjdp 125733965Sjdp { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 125833965Sjdp { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 125933965Sjdp { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, 126033965Sjdp { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, 126133965Sjdp { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, 126233965Sjdp { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, 126333965Sjdp { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, 126433965Sjdp { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, 126533965Sjdp { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, 126633965Sjdp { "pal1d", PCD(0x1D), BASE, ARG_PCD }, 126733965Sjdp 126833965Sjdp { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, 126938889Sjdp { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, 127033965Sjdp { "pal1e", PCD(0x1E), BASE, ARG_PCD }, 127133965Sjdp 127233965Sjdp { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 127333965Sjdp { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 127433965Sjdp { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 127533965Sjdp { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 127633965Sjdp { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 127733965Sjdp { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 127833965Sjdp { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 127933965Sjdp { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 128033965Sjdp { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 128133965Sjdp { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 128233965Sjdp { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 128333965Sjdp { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 128433965Sjdp { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 128533965Sjdp { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 128633965Sjdp { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 128733965Sjdp { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 128833965Sjdp { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 128933965Sjdp { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 129033965Sjdp { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 129133965Sjdp { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 129233965Sjdp { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 129333965Sjdp { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 129433965Sjdp { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 129533965Sjdp { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 129633965Sjdp { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 129733965Sjdp { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 129833965Sjdp { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 129933965Sjdp { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 130033965Sjdp { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 130133965Sjdp { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 130233965Sjdp { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 130333965Sjdp { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 130433965Sjdp { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 130533965Sjdp { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 130633965Sjdp { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 130733965Sjdp { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 130833965Sjdp { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 130933965Sjdp { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 131033965Sjdp { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 131133965Sjdp { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 131233965Sjdp { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 131333965Sjdp { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 131433965Sjdp { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 131533965Sjdp { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 131633965Sjdp { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 131733965Sjdp { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 131833965Sjdp { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 131933965Sjdp { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 132033965Sjdp { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 132133965Sjdp { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 132233965Sjdp { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 132333965Sjdp { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 132433965Sjdp { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 132533965Sjdp { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, 132633965Sjdp { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 132733965Sjdp { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 132833965Sjdp { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 132933965Sjdp { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 133033965Sjdp { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 133133965Sjdp { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 133233965Sjdp { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 133333965Sjdp { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 133433965Sjdp { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 133533965Sjdp { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 133633965Sjdp { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 133733965Sjdp { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 133833965Sjdp { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 133933965Sjdp { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 134033965Sjdp { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 134133965Sjdp { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 134233965Sjdp { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 134333965Sjdp { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 134433965Sjdp { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 134533965Sjdp { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 134633965Sjdp { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 134733965Sjdp { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 134833965Sjdp { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 134933965Sjdp { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 135033965Sjdp { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 135133965Sjdp { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 135233965Sjdp { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 135333965Sjdp { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 135433965Sjdp { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 135533965Sjdp { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 135633965Sjdp { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 135733965Sjdp { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 135833965Sjdp { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 135933965Sjdp { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 136033965Sjdp { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 136133965Sjdp { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 136233965Sjdp { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 136333965Sjdp { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 136433965Sjdp { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 136533965Sjdp { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 136633965Sjdp { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 136733965Sjdp { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 136833965Sjdp { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 136933965Sjdp { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 137033965Sjdp { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 137133965Sjdp { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 137233965Sjdp { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 137333965Sjdp { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 137433965Sjdp { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 137533965Sjdp { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 137633965Sjdp { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 137733965Sjdp { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 137833965Sjdp { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 137933965Sjdp { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 138033965Sjdp { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 138133965Sjdp { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 138233965Sjdp { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 138333965Sjdp { "pal1f", PCD(0x1F), BASE, ARG_PCD }, 138433965Sjdp 138533965Sjdp { "ldf", MEM(0x20), BASE, ARG_FMEM }, 138633965Sjdp { "ldg", MEM(0x21), BASE, ARG_FMEM }, 138733965Sjdp { "lds", MEM(0x22), BASE, ARG_FMEM }, 138833965Sjdp { "ldt", MEM(0x23), BASE, ARG_FMEM }, 138933965Sjdp { "stf", MEM(0x24), BASE, ARG_FMEM }, 139033965Sjdp { "stg", MEM(0x25), BASE, ARG_FMEM }, 139133965Sjdp { "sts", MEM(0x26), BASE, ARG_FMEM }, 139233965Sjdp { "stt", MEM(0x27), BASE, ARG_FMEM }, 139333965Sjdp 139433965Sjdp { "ldl", MEM(0x28), BASE, ARG_MEM }, 139533965Sjdp { "ldq", MEM(0x29), BASE, ARG_MEM }, 139633965Sjdp { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, 139733965Sjdp { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, 139833965Sjdp { "stl", MEM(0x2C), BASE, ARG_MEM }, 139933965Sjdp { "stq", MEM(0x2D), BASE, ARG_MEM }, 140033965Sjdp { "stl_c", MEM(0x2E), BASE, ARG_MEM }, 140133965Sjdp { "stq_c", MEM(0x2F), BASE, ARG_MEM }, 140233965Sjdp 140333965Sjdp { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ 140433965Sjdp { "br", BRA(0x30), BASE, ARG_BRA }, 140533965Sjdp { "fbeq", BRA(0x31), BASE, ARG_FBRA }, 140633965Sjdp { "fblt", BRA(0x32), BASE, ARG_FBRA }, 140733965Sjdp { "fble", BRA(0x33), BASE, ARG_FBRA }, 140833965Sjdp { "bsr", BRA(0x34), BASE, ARG_BRA }, 140933965Sjdp { "fbne", BRA(0x35), BASE, ARG_FBRA }, 141033965Sjdp { "fbge", BRA(0x36), BASE, ARG_FBRA }, 141133965Sjdp { "fbgt", BRA(0x37), BASE, ARG_FBRA }, 141233965Sjdp { "blbc", BRA(0x38), BASE, ARG_BRA }, 141333965Sjdp { "beq", BRA(0x39), BASE, ARG_BRA }, 141433965Sjdp { "blt", BRA(0x3A), BASE, ARG_BRA }, 141533965Sjdp { "ble", BRA(0x3B), BASE, ARG_BRA }, 141633965Sjdp { "blbs", BRA(0x3C), BASE, ARG_BRA }, 141733965Sjdp { "bne", BRA(0x3D), BASE, ARG_BRA }, 141833965Sjdp { "bge", BRA(0x3E), BASE, ARG_BRA }, 141933965Sjdp { "bgt", BRA(0x3F), BASE, ARG_BRA }, 142033965Sjdp}; 142133965Sjdp 142233965Sjdpconst int alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); 1423