alpha-opc.c revision 130561
133965Sjdp/* alpha-opc.c -- Alpha AXP opcode list 2130561Sobrien Copyright 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. 360484Sobrien Contributed by Richard Henderson <rth@cygnus.com>, 433965Sjdp patterned after the PPC opcode handling written by Ian Lance Taylor. 533965Sjdp 633965Sjdp This file is part of GDB, GAS, and the GNU binutils. 733965Sjdp 833965Sjdp GDB, GAS, and the GNU binutils are free software; you can redistribute 933965Sjdp them and/or modify them under the terms of the GNU General Public 1033965Sjdp License as published by the Free Software Foundation; either version 1133965Sjdp 2, or (at your option) any later version. 1233965Sjdp 1333965Sjdp GDB, GAS, and the GNU binutils are distributed in the hope that they 1433965Sjdp will be useful, but WITHOUT ANY WARRANTY; without even the implied 1533965Sjdp warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 1633965Sjdp the GNU General Public License for more details. 1733965Sjdp 1833965Sjdp You should have received a copy of the GNU General Public License 1933965Sjdp along with this file; see the file COPYING. If not, write to the 2033965Sjdp Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2133965Sjdp 02111-1307, USA. */ 2233965Sjdp 2333965Sjdp#include <stdio.h> 2460484Sobrien#include "sysdep.h" 2533965Sjdp#include "opcode/alpha.h" 2633965Sjdp#include "bfd.h" 2760484Sobrien#include "opintl.h" 2833965Sjdp 2933965Sjdp/* This file holds the Alpha AXP opcode table. The opcode table includes 3033965Sjdp almost all of the extended instruction mnemonics. This permits the 3133965Sjdp disassembler to use them, and simplifies the assembler logic, at the 3233965Sjdp cost of increasing the table size. The table is strictly constant 3389857Sobrien data, so the compiler should be able to put it in the text segment. 3433965Sjdp 3533965Sjdp This file also holds the operand table. All knowledge about inserting 3689857Sobrien and extracting operands from instructions is kept in this file. 3733965Sjdp 3833965Sjdp The information for the base instruction set was compiled from the 3933965Sjdp _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, 4033965Sjdp version 2. 4133965Sjdp 4233965Sjdp The information for the post-ev5 architecture extensions BWX, CIX and 4333965Sjdp MAX came from version 3 of this same document, which is also available 4433965Sjdp on-line at http://ftp.digital.com/pub/Digital/info/semiconductor 4533965Sjdp /literature/alphahb2.pdf 4633965Sjdp 4733965Sjdp The information for the EV4 PALcode instructions was compiled from 4833965Sjdp _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware 4933965Sjdp Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary 5033965Sjdp revision dated June 1994. 5133965Sjdp 5233965Sjdp The information for the EV5 PALcode instructions was compiled from 5333965Sjdp _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital 5433965Sjdp Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ 5533965Sjdp 5633965Sjdp/* Local insertion and extraction functions */ 5733965Sjdp 5833965Sjdpstatic unsigned insert_rba PARAMS((unsigned, int, const char **)); 5933965Sjdpstatic unsigned insert_rca PARAMS((unsigned, int, const char **)); 6033965Sjdpstatic unsigned insert_za PARAMS((unsigned, int, const char **)); 6133965Sjdpstatic unsigned insert_zb PARAMS((unsigned, int, const char **)); 6233965Sjdpstatic unsigned insert_zc PARAMS((unsigned, int, const char **)); 6333965Sjdpstatic unsigned insert_bdisp PARAMS((unsigned, int, const char **)); 6433965Sjdpstatic unsigned insert_jhint PARAMS((unsigned, int, const char **)); 6560484Sobrienstatic unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **)); 6633965Sjdp 6733965Sjdpstatic int extract_rba PARAMS((unsigned, int *)); 6833965Sjdpstatic int extract_rca PARAMS((unsigned, int *)); 6933965Sjdpstatic int extract_za PARAMS((unsigned, int *)); 7033965Sjdpstatic int extract_zb PARAMS((unsigned, int *)); 7133965Sjdpstatic int extract_zc PARAMS((unsigned, int *)); 7233965Sjdpstatic int extract_bdisp PARAMS((unsigned, int *)); 7333965Sjdpstatic int extract_jhint PARAMS((unsigned, int *)); 7460484Sobrienstatic int extract_ev6hwjhint PARAMS((unsigned, int *)); 7533965Sjdp 7633965Sjdp 7733965Sjdp/* The operands table */ 7833965Sjdp 7933965Sjdpconst struct alpha_operand alpha_operands[] = 8033965Sjdp{ 8133965Sjdp /* The fields are bits, shift, insert, extract, flags */ 8233965Sjdp /* The zero index is used to indicate end-of-list */ 8333965Sjdp#define UNUSED 0 8460484Sobrien { 0, 0, 0, 0, 0, 0 }, 8533965Sjdp 8633965Sjdp /* The plain integer register fields */ 8733965Sjdp#define RA (UNUSED + 1) 8833965Sjdp { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, 8933965Sjdp#define RB (RA + 1) 9033965Sjdp { 5, 16, 0, AXP_OPERAND_IR, 0, 0 }, 9133965Sjdp#define RC (RB + 1) 9233965Sjdp { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, 9333965Sjdp 9433965Sjdp /* The plain fp register fields */ 9533965Sjdp#define FA (RC + 1) 9633965Sjdp { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, 9733965Sjdp#define FB (FA + 1) 9833965Sjdp { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 }, 9933965Sjdp#define FC (FB + 1) 10033965Sjdp { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, 10133965Sjdp 10233965Sjdp /* The integer registers when they are ZERO */ 10333965Sjdp#define ZA (FC + 1) 10433965Sjdp { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, 10533965Sjdp#define ZB (ZA + 1) 10633965Sjdp { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb }, 10733965Sjdp#define ZC (ZB + 1) 10833965Sjdp { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, 10933965Sjdp 11033965Sjdp /* The RB field when it needs parentheses */ 11133965Sjdp#define PRB (ZC + 1) 11233965Sjdp { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, 11333965Sjdp 11433965Sjdp /* The RB field when it needs parentheses _and_ a preceding comma */ 11533965Sjdp#define CPRB (PRB + 1) 11633965Sjdp { 5, 16, 0, 11733965Sjdp AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, 11833965Sjdp 11933965Sjdp /* The RB field when it must be the same as the RA field */ 12033965Sjdp#define RBA (CPRB + 1) 12133965Sjdp { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, 12233965Sjdp 12333965Sjdp /* The RC field when it must be the same as the RB field */ 12433965Sjdp#define RCA (RBA + 1) 12533965Sjdp { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, 12633965Sjdp 12733965Sjdp /* The RC field when it can *default* to RA */ 12833965Sjdp#define DRC1 (RCA + 1) 12933965Sjdp { 5, 0, 0, 13033965Sjdp AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 13133965Sjdp 13233965Sjdp /* The RC field when it can *default* to RB */ 13333965Sjdp#define DRC2 (DRC1 + 1) 13433965Sjdp { 5, 0, 0, 13533965Sjdp AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 13633965Sjdp 13733965Sjdp /* The FC field when it can *default* to RA */ 13833965Sjdp#define DFC1 (DRC2 + 1) 13933965Sjdp { 5, 0, 0, 14033965Sjdp AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, 14133965Sjdp 14233965Sjdp /* The FC field when it can *default* to RB */ 14333965Sjdp#define DFC2 (DFC1 + 1) 14433965Sjdp { 5, 0, 0, 14533965Sjdp AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, 14633965Sjdp 14733965Sjdp /* The unsigned 8-bit literal of Operate format insns */ 14833965Sjdp#define LIT (DFC2 + 1) 14933965Sjdp { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, 15033965Sjdp 15133965Sjdp /* The signed 16-bit displacement of Memory format insns. From here 15233965Sjdp we can't tell what relocation should be used, so don't use a default. */ 15333965Sjdp#define MDISP (LIT + 1) 15433965Sjdp { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, 15533965Sjdp 15633965Sjdp /* The signed "23-bit" aligned displacement of Branch format insns */ 15733965Sjdp#define BDISP (MDISP + 1) 15833965Sjdp { 21, 0, BFD_RELOC_23_PCREL_S2, 15933965Sjdp AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, 16033965Sjdp 16133965Sjdp /* The 26-bit PALcode function */ 16233965Sjdp#define PALFN (BDISP + 1) 16333965Sjdp { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, 16433965Sjdp 16533965Sjdp /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ 16633965Sjdp#define JMPHINT (PALFN + 1) 16733965Sjdp { 14, 0, BFD_RELOC_ALPHA_HINT, 16833965Sjdp AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 16933965Sjdp insert_jhint, extract_jhint }, 17033965Sjdp 17133965Sjdp /* The optional hint to RET/JSR_COROUTINE */ 17233965Sjdp#define RETHINT (JMPHINT + 1) 17333965Sjdp { 14, 0, -RETHINT, 17433965Sjdp AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, 17533965Sjdp 17660484Sobrien /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */ 17733965Sjdp#define EV4HWDISP (RETHINT + 1) 17860484Sobrien#define EV6HWDISP (EV4HWDISP) 17933965Sjdp { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 18033965Sjdp 18133965Sjdp /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ 18233965Sjdp#define EV4HWINDEX (EV4HWDISP + 1) 18333965Sjdp { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 18433965Sjdp 18533965Sjdp /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns 18633965Sjdp that occur in DEC PALcode. */ 18733965Sjdp#define EV4EXTHWINDEX (EV4HWINDEX + 1) 18833965Sjdp { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 18933965Sjdp 19033965Sjdp /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ 19133965Sjdp#define EV5HWDISP (EV4EXTHWINDEX + 1) 19233965Sjdp { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, 19333965Sjdp 19433965Sjdp /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ 19533965Sjdp#define EV5HWINDEX (EV5HWDISP + 1) 19633965Sjdp { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 19760484Sobrien 19860484Sobrien /* The 16-bit combined index/scoreboard mask for the ev6 19960484Sobrien hw_m[ft]pr (pal19/pal1d) insns */ 20060484Sobrien#define EV6HWINDEX (EV5HWINDEX + 1) 20160484Sobrien { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, 20260484Sobrien 20360484Sobrien /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */ 20460484Sobrien#define EV6HWJMPHINT (EV6HWINDEX+ 1) 20560484Sobrien { 8, 0, -EV6HWJMPHINT, 20660484Sobrien AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, 20760484Sobrien insert_ev6hwjhint, extract_ev6hwjhint } 20833965Sjdp}; 20933965Sjdp 21060484Sobrienconst unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); 21133965Sjdp 21233965Sjdp/* The RB field when it is the same as the RA field in the same insn. 21333965Sjdp This operand is marked fake. The insertion function just copies 21433965Sjdp the RA field into the RB field, and the extraction function just 21533965Sjdp checks that the fields are the same. */ 21633965Sjdp 21733965Sjdpstatic unsigned 21833965Sjdpinsert_rba(insn, value, errmsg) 21933965Sjdp unsigned insn; 22060484Sobrien int value ATTRIBUTE_UNUSED; 22160484Sobrien const char **errmsg ATTRIBUTE_UNUSED; 22233965Sjdp{ 22333965Sjdp return insn | (((insn >> 21) & 0x1f) << 16); 22433965Sjdp} 22533965Sjdp 22633965Sjdpstatic int 22733965Sjdpextract_rba(insn, invalid) 22833965Sjdp unsigned insn; 22933965Sjdp int *invalid; 23033965Sjdp{ 23133965Sjdp if (invalid != (int *) NULL 23233965Sjdp && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 23333965Sjdp *invalid = 1; 23433965Sjdp return 0; 23533965Sjdp} 23633965Sjdp 23733965Sjdp 23833965Sjdp/* The same for the RC field */ 23933965Sjdp 24033965Sjdpstatic unsigned 24133965Sjdpinsert_rca(insn, value, errmsg) 24233965Sjdp unsigned insn; 24360484Sobrien int value ATTRIBUTE_UNUSED; 24460484Sobrien const char **errmsg ATTRIBUTE_UNUSED; 24533965Sjdp{ 24633965Sjdp return insn | ((insn >> 21) & 0x1f); 24733965Sjdp} 24833965Sjdp 24933965Sjdpstatic int 25033965Sjdpextract_rca(insn, invalid) 25133965Sjdp unsigned insn; 25233965Sjdp int *invalid; 25333965Sjdp{ 25433965Sjdp if (invalid != (int *) NULL 25533965Sjdp && ((insn >> 21) & 0x1f) != (insn & 0x1f)) 25633965Sjdp *invalid = 1; 25733965Sjdp return 0; 25833965Sjdp} 25933965Sjdp 26033965Sjdp 26133965Sjdp/* Fake arguments in which the registers must be set to ZERO */ 26233965Sjdp 26333965Sjdpstatic unsigned 26433965Sjdpinsert_za(insn, value, errmsg) 26533965Sjdp unsigned insn; 26660484Sobrien int value ATTRIBUTE_UNUSED; 26760484Sobrien const char **errmsg ATTRIBUTE_UNUSED; 26833965Sjdp{ 26933965Sjdp return insn | (31 << 21); 27033965Sjdp} 27133965Sjdp 27233965Sjdpstatic int 27333965Sjdpextract_za(insn, invalid) 27433965Sjdp unsigned insn; 27533965Sjdp int *invalid; 27633965Sjdp{ 27733965Sjdp if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) 27833965Sjdp *invalid = 1; 27933965Sjdp return 0; 28033965Sjdp} 28133965Sjdp 28233965Sjdpstatic unsigned 28333965Sjdpinsert_zb(insn, value, errmsg) 28433965Sjdp unsigned insn; 28560484Sobrien int value ATTRIBUTE_UNUSED; 28660484Sobrien const char **errmsg ATTRIBUTE_UNUSED; 28733965Sjdp{ 28833965Sjdp return insn | (31 << 16); 28933965Sjdp} 29033965Sjdp 29133965Sjdpstatic int 29233965Sjdpextract_zb(insn, invalid) 29333965Sjdp unsigned insn; 29433965Sjdp int *invalid; 29533965Sjdp{ 29633965Sjdp if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) 29733965Sjdp *invalid = 1; 29833965Sjdp return 0; 29933965Sjdp} 30033965Sjdp 30133965Sjdpstatic unsigned 30233965Sjdpinsert_zc(insn, value, errmsg) 30333965Sjdp unsigned insn; 30460484Sobrien int value ATTRIBUTE_UNUSED; 30560484Sobrien const char **errmsg ATTRIBUTE_UNUSED; 30633965Sjdp{ 30733965Sjdp return insn | 31; 30833965Sjdp} 30933965Sjdp 31033965Sjdpstatic int 31133965Sjdpextract_zc(insn, invalid) 31233965Sjdp unsigned insn; 31333965Sjdp int *invalid; 31433965Sjdp{ 31533965Sjdp if (invalid != (int *) NULL && (insn & 0x1f) != 31) 31633965Sjdp *invalid = 1; 31733965Sjdp return 0; 31833965Sjdp} 31933965Sjdp 32033965Sjdp 32133965Sjdp/* The displacement field of a Branch format insn. */ 32233965Sjdp 32333965Sjdpstatic unsigned 32433965Sjdpinsert_bdisp(insn, value, errmsg) 32533965Sjdp unsigned insn; 32633965Sjdp int value; 32733965Sjdp const char **errmsg; 32833965Sjdp{ 32933965Sjdp if (errmsg != (const char **)NULL && (value & 3)) 33060484Sobrien *errmsg = _("branch operand unaligned"); 33133965Sjdp return insn | ((value / 4) & 0x1FFFFF); 33233965Sjdp} 33333965Sjdp 33433965Sjdpstatic int 33533965Sjdpextract_bdisp(insn, invalid) 33633965Sjdp unsigned insn; 33760484Sobrien int *invalid ATTRIBUTE_UNUSED; 33833965Sjdp{ 33933965Sjdp return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); 34033965Sjdp} 34133965Sjdp 34233965Sjdp 34333965Sjdp/* The hint field of a JMP/JSR insn. */ 34433965Sjdp 34533965Sjdpstatic unsigned 34633965Sjdpinsert_jhint(insn, value, errmsg) 34733965Sjdp unsigned insn; 34833965Sjdp int value; 34933965Sjdp const char **errmsg; 35033965Sjdp{ 35133965Sjdp if (errmsg != (const char **)NULL && (value & 3)) 35260484Sobrien *errmsg = _("jump hint unaligned"); 35360484Sobrien return insn | ((value / 4) & 0x3FFF); 35433965Sjdp} 35533965Sjdp 35633965Sjdpstatic int 35733965Sjdpextract_jhint(insn, invalid) 35833965Sjdp unsigned insn; 35960484Sobrien int *invalid ATTRIBUTE_UNUSED; 36033965Sjdp{ 36133965Sjdp return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); 36233965Sjdp} 36333965Sjdp 36460484Sobrien/* The hint field of an EV6 HW_JMP/JSR insn. */ 36560484Sobrien 36660484Sobrienstatic unsigned 36760484Sobrieninsert_ev6hwjhint(insn, value, errmsg) 36860484Sobrien unsigned insn; 36960484Sobrien int value; 37060484Sobrien const char **errmsg; 37160484Sobrien{ 37260484Sobrien if (errmsg != (const char **)NULL && (value & 3)) 37360484Sobrien *errmsg = _("jump hint unaligned"); 37460484Sobrien return insn | ((value / 4) & 0x1FFF); 37560484Sobrien} 37660484Sobrien 37760484Sobrienstatic int 37860484Sobrienextract_ev6hwjhint(insn, invalid) 37960484Sobrien unsigned insn; 38060484Sobrien int *invalid ATTRIBUTE_UNUSED; 38160484Sobrien{ 38260484Sobrien return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); 38360484Sobrien} 38460484Sobrien 38533965Sjdp 38633965Sjdp/* Macros used to form opcodes */ 38733965Sjdp 38833965Sjdp/* The main opcode */ 38933965Sjdp#define OP(x) (((x) & 0x3F) << 26) 39033965Sjdp#define OP_MASK 0xFC000000 39133965Sjdp 39233965Sjdp/* Branch format instructions */ 39333965Sjdp#define BRA_(oo) OP(oo) 39433965Sjdp#define BRA_MASK OP_MASK 39533965Sjdp#define BRA(oo) BRA_(oo), BRA_MASK 39633965Sjdp 39733965Sjdp/* Floating point format instructions */ 39833965Sjdp#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) 39933965Sjdp#define FP_MASK (OP_MASK | 0xFFE0) 40033965Sjdp#define FP(oo,fff) FP_(oo,fff), FP_MASK 40133965Sjdp 40233965Sjdp/* Memory format instructions */ 40333965Sjdp#define MEM_(oo) OP(oo) 40433965Sjdp#define MEM_MASK OP_MASK 40533965Sjdp#define MEM(oo) MEM_(oo), MEM_MASK 40633965Sjdp 40733965Sjdp/* Memory/Func Code format instructions */ 40833965Sjdp#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) 40933965Sjdp#define MFC_MASK (OP_MASK | 0xFFFF) 41033965Sjdp#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK 41133965Sjdp 41233965Sjdp/* Memory/Branch format instructions */ 41333965Sjdp#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) 41433965Sjdp#define MBR_MASK (OP_MASK | 0xC000) 41533965Sjdp#define MBR(oo,h) MBR_(oo,h), MBR_MASK 41633965Sjdp 41733965Sjdp/* Operate format instructions. The OPRL variant specifies a 41833965Sjdp literal second argument. */ 41933965Sjdp#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) 42033965Sjdp#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) 42133965Sjdp#define OPR_MASK (OP_MASK | 0x1FE0) 42233965Sjdp#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK 42333965Sjdp#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK 42433965Sjdp 42533965Sjdp/* Generic PALcode format instructions */ 42633965Sjdp#define PCD_(oo) OP(oo) 42733965Sjdp#define PCD_MASK OP_MASK 42833965Sjdp#define PCD(oo) PCD_(oo), PCD_MASK 42933965Sjdp 43033965Sjdp/* Specific PALcode instructions */ 43133965Sjdp#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) 43233965Sjdp#define SPCD_MASK 0xFFFFFFFF 43333965Sjdp#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK 43433965Sjdp 43533965Sjdp/* Hardware memory (hw_{ld,st}) instructions */ 43633965Sjdp#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 43733965Sjdp#define EV4HWMEM_MASK (OP_MASK | 0xF000) 43833965Sjdp#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK 43933965Sjdp 44033965Sjdp#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10)) 44133965Sjdp#define EV5HWMEM_MASK (OP_MASK | 0xF800) 44233965Sjdp#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK 44333965Sjdp 44460484Sobrien#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) 44560484Sobrien#define EV6HWMEM_MASK (OP_MASK | 0xF000) 44660484Sobrien#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK 44760484Sobrien 44860484Sobrien#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13)) 44960484Sobrien#define EV6HWMBR_MASK (OP_MASK | 0xE000) 45060484Sobrien#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK 45160484Sobrien 45233965Sjdp/* Abbreviations for instruction subsets. */ 45333965Sjdp#define BASE AXP_OPCODE_BASE 45433965Sjdp#define EV4 AXP_OPCODE_EV4 45533965Sjdp#define EV5 AXP_OPCODE_EV5 45660484Sobrien#define EV6 AXP_OPCODE_EV6 45733965Sjdp#define BWX AXP_OPCODE_BWX 45833965Sjdp#define CIX AXP_OPCODE_CIX 45933965Sjdp#define MAX AXP_OPCODE_MAX 46033965Sjdp 46133965Sjdp/* Common combinations of arguments */ 46233965Sjdp#define ARG_NONE { 0 } 46333965Sjdp#define ARG_BRA { RA, BDISP } 46433965Sjdp#define ARG_FBRA { FA, BDISP } 46533965Sjdp#define ARG_FP { FA, FB, DFC1 } 46633965Sjdp#define ARG_FPZ1 { ZA, FB, DFC1 } 46733965Sjdp#define ARG_MEM { RA, MDISP, PRB } 46833965Sjdp#define ARG_FMEM { FA, MDISP, PRB } 46933965Sjdp#define ARG_OPR { RA, RB, DRC1 } 47033965Sjdp#define ARG_OPRL { RA, LIT, DRC1 } 47133965Sjdp#define ARG_OPRZ1 { ZA, RB, DRC1 } 47233965Sjdp#define ARG_OPRLZ1 { ZA, LIT, RC } 47333965Sjdp#define ARG_PCD { PALFN } 47433965Sjdp#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB } 47533965Sjdp#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX } 47633965Sjdp#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB } 47760484Sobrien#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } 47833965Sjdp 47933965Sjdp/* The opcode table. 48033965Sjdp 48133965Sjdp The format of the opcode table is: 48233965Sjdp 48333965Sjdp NAME OPCODE MASK { OPERANDS } 48433965Sjdp 48533965Sjdp NAME is the name of the instruction. 48633965Sjdp 48733965Sjdp OPCODE is the instruction opcode. 48833965Sjdp 48933965Sjdp MASK is the opcode mask; this is used to tell the disassembler 49033965Sjdp which bits in the actual opcode must match OPCODE. 49133965Sjdp 49233965Sjdp OPERANDS is the list of operands. 49333965Sjdp 49433965Sjdp The preceding macros merge the text of the OPCODE and MASK fields. 49533965Sjdp 49633965Sjdp The disassembler reads the table in order and prints the first 49733965Sjdp instruction which matches, so this table is sorted to put more 49833965Sjdp specific instructions before more general instructions. 49933965Sjdp 50033965Sjdp Otherwise, it is sorted by major opcode and minor function code. 50133965Sjdp 50233965Sjdp There are three classes of not-really-instructions in this table: 50333965Sjdp 50433965Sjdp ALIAS is another name for another instruction. Some of 50533965Sjdp these come from the Architecture Handbook, some 50633965Sjdp come from the original gas opcode tables. In all 50733965Sjdp cases, the functionality of the opcode is unchanged. 50833965Sjdp 50933965Sjdp PSEUDO a stylized code form endorsed by Chapter A.4 of the 51033965Sjdp Architecture Handbook. 51133965Sjdp 51233965Sjdp EXTRA a stylized code form found in the original gas tables. 51333965Sjdp 51433965Sjdp And two annotations: 51533965Sjdp 51633965Sjdp EV56 BUT opcodes that are officially introduced as of the ev56, 51733965Sjdp but with defined results on previous implementations. 51833965Sjdp 51933965Sjdp EV56 UNA opcodes that were introduced as of the ev56 with 52033965Sjdp presumably undefined results on previous implementations 52133965Sjdp that were not assigned to a particular extension. 52233965Sjdp*/ 52333965Sjdp 52433965Sjdpconst struct alpha_opcode alpha_opcodes[] = { 52533965Sjdp { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, 52633965Sjdp { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, 52733965Sjdp { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, 528130561Sobrien { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, 52933965Sjdp { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, 53033965Sjdp { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, 53133965Sjdp { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, 532130561Sobrien { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, 533130561Sobrien { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, 534130561Sobrien { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, 53533965Sjdp { "call_pal", PCD(0x00), BASE, ARG_PCD }, 53633965Sjdp { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ 53733965Sjdp 53891041Sobrien { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ 53933965Sjdp { "lda", MEM(0x08), BASE, ARG_MEM }, 54091041Sobrien { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ 54133965Sjdp { "ldah", MEM(0x09), BASE, ARG_MEM }, 54233965Sjdp { "ldbu", MEM(0x0A), BWX, ARG_MEM }, 54389857Sobrien { "unop", MEM_(0x0B) | (30 << 16), 54489857Sobrien MEM_MASK, BASE, { ZA } }, /* pseudo */ 54533965Sjdp { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, 54633965Sjdp { "ldwu", MEM(0x0C), BWX, ARG_MEM }, 54733965Sjdp { "stw", MEM(0x0D), BWX, ARG_MEM }, 54833965Sjdp { "stb", MEM(0x0E), BWX, ARG_MEM }, 54933965Sjdp { "stq_u", MEM(0x0F), BASE, ARG_MEM }, 55033965Sjdp 55133965Sjdp { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ 55233965Sjdp { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ 55333965Sjdp { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, 55433965Sjdp { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, 55533965Sjdp { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, 55633965Sjdp { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, 55733965Sjdp { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ 55833965Sjdp { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ 55933965Sjdp { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, 56033965Sjdp { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, 56133965Sjdp { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, 56233965Sjdp { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, 56333965Sjdp { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, 56433965Sjdp { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, 56533965Sjdp { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, 56633965Sjdp { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, 56733965Sjdp { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, 56833965Sjdp { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, 56933965Sjdp { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, 57033965Sjdp { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, 57133965Sjdp { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, 57233965Sjdp { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, 57333965Sjdp { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, 57433965Sjdp { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, 57533965Sjdp { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ 57633965Sjdp { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ 57733965Sjdp { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, 57833965Sjdp { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, 57933965Sjdp { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, 58033965Sjdp { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, 58133965Sjdp { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, 58233965Sjdp { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, 58333965Sjdp { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, 58433965Sjdp { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, 58533965Sjdp { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, 58633965Sjdp { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, 58733965Sjdp { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, 58833965Sjdp { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, 58933965Sjdp { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, 59033965Sjdp { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, 59133965Sjdp { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ 59233965Sjdp { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ 59333965Sjdp { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, 59433965Sjdp { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, 59533965Sjdp { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, 59633965Sjdp { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, 59733965Sjdp { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, 59833965Sjdp { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, 59933965Sjdp { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ 60033965Sjdp { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ 60133965Sjdp { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, 60233965Sjdp { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, 60333965Sjdp { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, 60433965Sjdp { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, 60533965Sjdp 60633965Sjdp { "and", OPR(0x11,0x00), BASE, ARG_OPR }, 60733965Sjdp { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, 60860484Sobrien { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ 60933965Sjdp { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ 61033965Sjdp { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, 61133965Sjdp { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, 61233965Sjdp { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, 61333965Sjdp { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, 61433965Sjdp { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, 61533965Sjdp { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, 61633965Sjdp { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ 61733965Sjdp { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ 61833965Sjdp { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ 61933965Sjdp { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ 62033965Sjdp { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ 62160484Sobrien { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ 62233965Sjdp { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ 62333965Sjdp { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, 62433965Sjdp { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, 62533965Sjdp { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, 62633965Sjdp { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, 62733965Sjdp { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, 62833965Sjdp { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, 62933965Sjdp { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ 63033965Sjdp { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ 63133965Sjdp { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, 63233965Sjdp { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, 63333965Sjdp { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, 63433965Sjdp { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, 63533965Sjdp { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, 63633965Sjdp { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, 63733965Sjdp { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, 63833965Sjdp { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, 63933965Sjdp { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, 64033965Sjdp { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, 64133965Sjdp { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ 64233965Sjdp { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ 64333965Sjdp { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ 64433965Sjdp { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ 64533965Sjdp { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, 64633965Sjdp { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, 64733965Sjdp { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, 64833965Sjdp { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, 64933965Sjdp { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), 65033965Sjdp 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ 65133965Sjdp 65233965Sjdp { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, 65333965Sjdp { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, 65433965Sjdp { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, 65533965Sjdp { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, 65633965Sjdp { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, 65733965Sjdp { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, 65833965Sjdp { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, 65933965Sjdp { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, 66033965Sjdp { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, 66133965Sjdp { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, 66233965Sjdp { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, 66333965Sjdp { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, 66433965Sjdp { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, 66533965Sjdp { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, 66633965Sjdp { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, 66733965Sjdp { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, 66833965Sjdp { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, 66933965Sjdp { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, 67033965Sjdp { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, 67133965Sjdp { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, 67233965Sjdp { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, 67333965Sjdp { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, 67433965Sjdp { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, 67533965Sjdp { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, 67633965Sjdp { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, 67733965Sjdp { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, 67833965Sjdp { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, 67933965Sjdp { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, 68033965Sjdp { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, 68133965Sjdp { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, 68233965Sjdp { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, 68333965Sjdp { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, 68433965Sjdp { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, 68533965Sjdp { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, 68633965Sjdp { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, 68733965Sjdp { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, 68833965Sjdp { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, 68933965Sjdp { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, 69033965Sjdp { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, 69133965Sjdp { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, 69233965Sjdp { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, 69333965Sjdp { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, 69433965Sjdp { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, 69533965Sjdp { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, 69633965Sjdp { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, 69733965Sjdp { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, 69833965Sjdp { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, 69933965Sjdp { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, 70033965Sjdp { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, 70133965Sjdp { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, 70233965Sjdp { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, 70333965Sjdp { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, 70433965Sjdp 70533965Sjdp { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, 70633965Sjdp { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, 70733965Sjdp { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, 70833965Sjdp { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, 70933965Sjdp { "umulh", OPR(0x13,0x30), BASE, ARG_OPR }, 71033965Sjdp { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL }, 71133965Sjdp { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR }, 71233965Sjdp { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL }, 71333965Sjdp { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR }, 71433965Sjdp { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL }, 71533965Sjdp 71633965Sjdp { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, 71760484Sobrien { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, 71860484Sobrien { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, 71933965Sjdp { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, 72033965Sjdp { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, 72160484Sobrien { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, 72260484Sobrien { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, 72360484Sobrien { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, 72460484Sobrien { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 }, 72533965Sjdp { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 }, 72660484Sobrien { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 }, 72733965Sjdp { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 }, 72833965Sjdp { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 }, 72960484Sobrien { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 }, 73060484Sobrien { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 }, 73160484Sobrien { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 }, 73260484Sobrien { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 }, 73360484Sobrien { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 }, 73460484Sobrien { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 }, 73560484Sobrien { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 }, 73660484Sobrien { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 }, 73760484Sobrien { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 }, 73860484Sobrien { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 }, 73960484Sobrien { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 }, 74060484Sobrien { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 }, 74160484Sobrien { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 }, 74260484Sobrien { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 }, 74360484Sobrien { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 }, 74460484Sobrien { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 }, 74560484Sobrien { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 }, 74660484Sobrien { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 }, 74760484Sobrien { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 }, 74860484Sobrien { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 }, 74960484Sobrien { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 }, 75060484Sobrien { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 }, 75160484Sobrien { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 }, 75260484Sobrien { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 }, 75360484Sobrien { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 }, 75460484Sobrien { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 }, 75560484Sobrien { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 }, 75660484Sobrien { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 }, 75760484Sobrien { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 }, 75860484Sobrien { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 }, 75960484Sobrien { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 }, 76060484Sobrien { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 }, 76160484Sobrien { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 }, 76260484Sobrien { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 }, 76360484Sobrien { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 }, 76460484Sobrien { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 }, 76560484Sobrien { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 }, 76660484Sobrien { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 }, 76733965Sjdp 76833965Sjdp { "addf/c", FP(0x15,0x000), BASE, ARG_FP }, 76933965Sjdp { "subf/c", FP(0x15,0x001), BASE, ARG_FP }, 77033965Sjdp { "mulf/c", FP(0x15,0x002), BASE, ARG_FP }, 77133965Sjdp { "divf/c", FP(0x15,0x003), BASE, ARG_FP }, 77233965Sjdp { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 }, 77333965Sjdp { "addg/c", FP(0x15,0x020), BASE, ARG_FP }, 77433965Sjdp { "subg/c", FP(0x15,0x021), BASE, ARG_FP }, 77533965Sjdp { "mulg/c", FP(0x15,0x022), BASE, ARG_FP }, 77633965Sjdp { "divg/c", FP(0x15,0x023), BASE, ARG_FP }, 77733965Sjdp { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 }, 77833965Sjdp { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 }, 77933965Sjdp { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 }, 78033965Sjdp { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 }, 78133965Sjdp { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 }, 78233965Sjdp { "addf", FP(0x15,0x080), BASE, ARG_FP }, 78333965Sjdp { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 78433965Sjdp { "subf", FP(0x15,0x081), BASE, ARG_FP }, 78533965Sjdp { "mulf", FP(0x15,0x082), BASE, ARG_FP }, 78633965Sjdp { "divf", FP(0x15,0x083), BASE, ARG_FP }, 78733965Sjdp { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 }, 78833965Sjdp { "addg", FP(0x15,0x0A0), BASE, ARG_FP }, 78933965Sjdp { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 79033965Sjdp { "subg", FP(0x15,0x0A1), BASE, ARG_FP }, 79133965Sjdp { "mulg", FP(0x15,0x0A2), BASE, ARG_FP }, 79233965Sjdp { "divg", FP(0x15,0x0A3), BASE, ARG_FP }, 79333965Sjdp { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP }, 79433965Sjdp { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP }, 79533965Sjdp { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP }, 79633965Sjdp { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 }, 79733965Sjdp { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 }, 79833965Sjdp { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 }, 79933965Sjdp { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 }, 80033965Sjdp { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 }, 80133965Sjdp { "addf/uc", FP(0x15,0x100), BASE, ARG_FP }, 80233965Sjdp { "subf/uc", FP(0x15,0x101), BASE, ARG_FP }, 80333965Sjdp { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP }, 80433965Sjdp { "divf/uc", FP(0x15,0x103), BASE, ARG_FP }, 80533965Sjdp { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 }, 80633965Sjdp { "addg/uc", FP(0x15,0x120), BASE, ARG_FP }, 80733965Sjdp { "subg/uc", FP(0x15,0x121), BASE, ARG_FP }, 80833965Sjdp { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP }, 80933965Sjdp { "divg/uc", FP(0x15,0x123), BASE, ARG_FP }, 81033965Sjdp { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 }, 81133965Sjdp { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 }, 81233965Sjdp { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 }, 81333965Sjdp { "addf/u", FP(0x15,0x180), BASE, ARG_FP }, 81433965Sjdp { "subf/u", FP(0x15,0x181), BASE, ARG_FP }, 81533965Sjdp { "mulf/u", FP(0x15,0x182), BASE, ARG_FP }, 81633965Sjdp { "divf/u", FP(0x15,0x183), BASE, ARG_FP }, 81733965Sjdp { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 }, 81833965Sjdp { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP }, 81933965Sjdp { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP }, 82033965Sjdp { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP }, 82133965Sjdp { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP }, 82233965Sjdp { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 }, 82333965Sjdp { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 }, 82433965Sjdp { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 }, 82533965Sjdp { "addf/sc", FP(0x15,0x400), BASE, ARG_FP }, 82633965Sjdp { "subf/sc", FP(0x15,0x401), BASE, ARG_FP }, 82733965Sjdp { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP }, 82833965Sjdp { "divf/sc", FP(0x15,0x403), BASE, ARG_FP }, 82933965Sjdp { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 }, 83033965Sjdp { "addg/sc", FP(0x15,0x420), BASE, ARG_FP }, 83133965Sjdp { "subg/sc", FP(0x15,0x421), BASE, ARG_FP }, 83233965Sjdp { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP }, 83333965Sjdp { "divg/sc", FP(0x15,0x423), BASE, ARG_FP }, 83433965Sjdp { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 }, 83533965Sjdp { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 }, 83633965Sjdp { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 }, 83733965Sjdp { "addf/s", FP(0x15,0x480), BASE, ARG_FP }, 83833965Sjdp { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */ 83933965Sjdp { "subf/s", FP(0x15,0x481), BASE, ARG_FP }, 84033965Sjdp { "mulf/s", FP(0x15,0x482), BASE, ARG_FP }, 84133965Sjdp { "divf/s", FP(0x15,0x483), BASE, ARG_FP }, 84233965Sjdp { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 }, 84333965Sjdp { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP }, 84433965Sjdp { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */ 84533965Sjdp { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP }, 84633965Sjdp { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP }, 84733965Sjdp { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP }, 84833965Sjdp { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP }, 84933965Sjdp { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP }, 85033965Sjdp { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP }, 85133965Sjdp { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 }, 85233965Sjdp { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 }, 85333965Sjdp { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 }, 85433965Sjdp { "addf/suc", FP(0x15,0x500), BASE, ARG_FP }, 85533965Sjdp { "subf/suc", FP(0x15,0x501), BASE, ARG_FP }, 85633965Sjdp { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP }, 85733965Sjdp { "divf/suc", FP(0x15,0x503), BASE, ARG_FP }, 85833965Sjdp { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 }, 85933965Sjdp { "addg/suc", FP(0x15,0x520), BASE, ARG_FP }, 86033965Sjdp { "subg/suc", FP(0x15,0x521), BASE, ARG_FP }, 86133965Sjdp { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP }, 86233965Sjdp { "divg/suc", FP(0x15,0x523), BASE, ARG_FP }, 86333965Sjdp { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 }, 86433965Sjdp { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 }, 86533965Sjdp { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 }, 86633965Sjdp { "addf/su", FP(0x15,0x580), BASE, ARG_FP }, 86733965Sjdp { "subf/su", FP(0x15,0x581), BASE, ARG_FP }, 86833965Sjdp { "mulf/su", FP(0x15,0x582), BASE, ARG_FP }, 86933965Sjdp { "divf/su", FP(0x15,0x583), BASE, ARG_FP }, 87033965Sjdp { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 }, 87133965Sjdp { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP }, 87233965Sjdp { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP }, 87333965Sjdp { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP }, 87433965Sjdp { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP }, 87533965Sjdp { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 }, 87633965Sjdp { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 }, 87733965Sjdp { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 }, 87833965Sjdp 87933965Sjdp { "adds/c", FP(0x16,0x000), BASE, ARG_FP }, 88033965Sjdp { "subs/c", FP(0x16,0x001), BASE, ARG_FP }, 88133965Sjdp { "muls/c", FP(0x16,0x002), BASE, ARG_FP }, 88233965Sjdp { "divs/c", FP(0x16,0x003), BASE, ARG_FP }, 88333965Sjdp { "addt/c", FP(0x16,0x020), BASE, ARG_FP }, 88433965Sjdp { "subt/c", FP(0x16,0x021), BASE, ARG_FP }, 88533965Sjdp { "mult/c", FP(0x16,0x022), BASE, ARG_FP }, 88633965Sjdp { "divt/c", FP(0x16,0x023), BASE, ARG_FP }, 88733965Sjdp { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 }, 88833965Sjdp { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 }, 88933965Sjdp { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 }, 89033965Sjdp { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 }, 89133965Sjdp { "adds/m", FP(0x16,0x040), BASE, ARG_FP }, 89233965Sjdp { "subs/m", FP(0x16,0x041), BASE, ARG_FP }, 89333965Sjdp { "muls/m", FP(0x16,0x042), BASE, ARG_FP }, 89433965Sjdp { "divs/m", FP(0x16,0x043), BASE, ARG_FP }, 89533965Sjdp { "addt/m", FP(0x16,0x060), BASE, ARG_FP }, 89633965Sjdp { "subt/m", FP(0x16,0x061), BASE, ARG_FP }, 89733965Sjdp { "mult/m", FP(0x16,0x062), BASE, ARG_FP }, 89833965Sjdp { "divt/m", FP(0x16,0x063), BASE, ARG_FP }, 89933965Sjdp { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 }, 90033965Sjdp { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 }, 90133965Sjdp { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 }, 90233965Sjdp { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 }, 90333965Sjdp { "adds", FP(0x16,0x080), BASE, ARG_FP }, 90433965Sjdp { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */ 90533965Sjdp { "subs", FP(0x16,0x081), BASE, ARG_FP }, 90633965Sjdp { "muls", FP(0x16,0x082), BASE, ARG_FP }, 90733965Sjdp { "divs", FP(0x16,0x083), BASE, ARG_FP }, 90833965Sjdp { "addt", FP(0x16,0x0A0), BASE, ARG_FP }, 90933965Sjdp { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */ 91033965Sjdp { "subt", FP(0x16,0x0A1), BASE, ARG_FP }, 91133965Sjdp { "mult", FP(0x16,0x0A2), BASE, ARG_FP }, 91233965Sjdp { "divt", FP(0x16,0x0A3), BASE, ARG_FP }, 91333965Sjdp { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP }, 91433965Sjdp { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP }, 91533965Sjdp { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP }, 91633965Sjdp { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP }, 91733965Sjdp { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 }, 91833965Sjdp { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 }, 91933965Sjdp { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 }, 92033965Sjdp { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 }, 92133965Sjdp { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP }, 92233965Sjdp { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP }, 92333965Sjdp { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP }, 92433965Sjdp { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP }, 92533965Sjdp { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP }, 92633965Sjdp { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP }, 92733965Sjdp { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP }, 92833965Sjdp { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP }, 92933965Sjdp { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 }, 93033965Sjdp { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 }, 93133965Sjdp { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 }, 93233965Sjdp { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 }, 93333965Sjdp { "adds/uc", FP(0x16,0x100), BASE, ARG_FP }, 93433965Sjdp { "subs/uc", FP(0x16,0x101), BASE, ARG_FP }, 93533965Sjdp { "muls/uc", FP(0x16,0x102), BASE, ARG_FP }, 93633965Sjdp { "divs/uc", FP(0x16,0x103), BASE, ARG_FP }, 93733965Sjdp { "addt/uc", FP(0x16,0x120), BASE, ARG_FP }, 93833965Sjdp { "subt/uc", FP(0x16,0x121), BASE, ARG_FP }, 93933965Sjdp { "mult/uc", FP(0x16,0x122), BASE, ARG_FP }, 94033965Sjdp { "divt/uc", FP(0x16,0x123), BASE, ARG_FP }, 94133965Sjdp { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 }, 94233965Sjdp { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 }, 94333965Sjdp { "adds/um", FP(0x16,0x140), BASE, ARG_FP }, 94433965Sjdp { "subs/um", FP(0x16,0x141), BASE, ARG_FP }, 94533965Sjdp { "muls/um", FP(0x16,0x142), BASE, ARG_FP }, 94633965Sjdp { "divs/um", FP(0x16,0x143), BASE, ARG_FP }, 94733965Sjdp { "addt/um", FP(0x16,0x160), BASE, ARG_FP }, 94833965Sjdp { "subt/um", FP(0x16,0x161), BASE, ARG_FP }, 94933965Sjdp { "mult/um", FP(0x16,0x162), BASE, ARG_FP }, 95033965Sjdp { "divt/um", FP(0x16,0x163), BASE, ARG_FP }, 95133965Sjdp { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 }, 95238889Sjdp { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 }, 95333965Sjdp { "adds/u", FP(0x16,0x180), BASE, ARG_FP }, 95433965Sjdp { "subs/u", FP(0x16,0x181), BASE, ARG_FP }, 95533965Sjdp { "muls/u", FP(0x16,0x182), BASE, ARG_FP }, 95633965Sjdp { "divs/u", FP(0x16,0x183), BASE, ARG_FP }, 95733965Sjdp { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP }, 95833965Sjdp { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP }, 95933965Sjdp { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP }, 96033965Sjdp { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP }, 96133965Sjdp { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 }, 96233965Sjdp { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 }, 96333965Sjdp { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP }, 96433965Sjdp { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP }, 96533965Sjdp { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP }, 96633965Sjdp { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP }, 96733965Sjdp { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP }, 96833965Sjdp { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP }, 96933965Sjdp { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP }, 97033965Sjdp { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP }, 97133965Sjdp { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 }, 97238889Sjdp { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 }, 97333965Sjdp { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 }, 97433965Sjdp { "adds/suc", FP(0x16,0x500), BASE, ARG_FP }, 97533965Sjdp { "subs/suc", FP(0x16,0x501), BASE, ARG_FP }, 97633965Sjdp { "muls/suc", FP(0x16,0x502), BASE, ARG_FP }, 97733965Sjdp { "divs/suc", FP(0x16,0x503), BASE, ARG_FP }, 97833965Sjdp { "addt/suc", FP(0x16,0x520), BASE, ARG_FP }, 97933965Sjdp { "subt/suc", FP(0x16,0x521), BASE, ARG_FP }, 98033965Sjdp { "mult/suc", FP(0x16,0x522), BASE, ARG_FP }, 98133965Sjdp { "divt/suc", FP(0x16,0x523), BASE, ARG_FP }, 98233965Sjdp { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 }, 98333965Sjdp { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 }, 98433965Sjdp { "adds/sum", FP(0x16,0x540), BASE, ARG_FP }, 98533965Sjdp { "subs/sum", FP(0x16,0x541), BASE, ARG_FP }, 98633965Sjdp { "muls/sum", FP(0x16,0x542), BASE, ARG_FP }, 98733965Sjdp { "divs/sum", FP(0x16,0x543), BASE, ARG_FP }, 98833965Sjdp { "addt/sum", FP(0x16,0x560), BASE, ARG_FP }, 98933965Sjdp { "subt/sum", FP(0x16,0x561), BASE, ARG_FP }, 99033965Sjdp { "mult/sum", FP(0x16,0x562), BASE, ARG_FP }, 99133965Sjdp { "divt/sum", FP(0x16,0x563), BASE, ARG_FP }, 99233965Sjdp { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 }, 99338889Sjdp { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 }, 99433965Sjdp { "adds/su", FP(0x16,0x580), BASE, ARG_FP }, 99533965Sjdp { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */ 99633965Sjdp { "subs/su", FP(0x16,0x581), BASE, ARG_FP }, 99733965Sjdp { "muls/su", FP(0x16,0x582), BASE, ARG_FP }, 99833965Sjdp { "divs/su", FP(0x16,0x583), BASE, ARG_FP }, 99933965Sjdp { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP }, 100033965Sjdp { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */ 100133965Sjdp { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP }, 100233965Sjdp { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP }, 100333965Sjdp { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP }, 100433965Sjdp { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP }, 100533965Sjdp { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP }, 100633965Sjdp { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP }, 100733965Sjdp { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP }, 100833965Sjdp { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 }, 100933965Sjdp { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 }, 101033965Sjdp { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP }, 101133965Sjdp { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP }, 101233965Sjdp { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP }, 101333965Sjdp { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP }, 101433965Sjdp { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP }, 101533965Sjdp { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP }, 101633965Sjdp { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP }, 101733965Sjdp { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP }, 101833965Sjdp { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 }, 101938889Sjdp { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 }, 102033965Sjdp { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 }, 102133965Sjdp { "adds/suic", FP(0x16,0x700), BASE, ARG_FP }, 102233965Sjdp { "subs/suic", FP(0x16,0x701), BASE, ARG_FP }, 102333965Sjdp { "muls/suic", FP(0x16,0x702), BASE, ARG_FP }, 102433965Sjdp { "divs/suic", FP(0x16,0x703), BASE, ARG_FP }, 102533965Sjdp { "addt/suic", FP(0x16,0x720), BASE, ARG_FP }, 102633965Sjdp { "subt/suic", FP(0x16,0x721), BASE, ARG_FP }, 102733965Sjdp { "mult/suic", FP(0x16,0x722), BASE, ARG_FP }, 102833965Sjdp { "divt/suic", FP(0x16,0x723), BASE, ARG_FP }, 102933965Sjdp { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 }, 103033965Sjdp { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 }, 103133965Sjdp { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 }, 103233965Sjdp { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 }, 103333965Sjdp { "adds/suim", FP(0x16,0x740), BASE, ARG_FP }, 103433965Sjdp { "subs/suim", FP(0x16,0x741), BASE, ARG_FP }, 103533965Sjdp { "muls/suim", FP(0x16,0x742), BASE, ARG_FP }, 103633965Sjdp { "divs/suim", FP(0x16,0x743), BASE, ARG_FP }, 103733965Sjdp { "addt/suim", FP(0x16,0x760), BASE, ARG_FP }, 103833965Sjdp { "subt/suim", FP(0x16,0x761), BASE, ARG_FP }, 103933965Sjdp { "mult/suim", FP(0x16,0x762), BASE, ARG_FP }, 104033965Sjdp { "divt/suim", FP(0x16,0x763), BASE, ARG_FP }, 104133965Sjdp { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 }, 104238889Sjdp { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 }, 104333965Sjdp { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 }, 104433965Sjdp { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 }, 104533965Sjdp { "adds/sui", FP(0x16,0x780), BASE, ARG_FP }, 104633965Sjdp { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */ 104733965Sjdp { "subs/sui", FP(0x16,0x781), BASE, ARG_FP }, 104833965Sjdp { "muls/sui", FP(0x16,0x782), BASE, ARG_FP }, 104933965Sjdp { "divs/sui", FP(0x16,0x783), BASE, ARG_FP }, 105033965Sjdp { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP }, 105133965Sjdp { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */ 105233965Sjdp { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP }, 105333965Sjdp { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP }, 105433965Sjdp { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP }, 105533965Sjdp { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 }, 105633965Sjdp { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 }, 105733965Sjdp { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 }, 105833965Sjdp { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 }, 105933965Sjdp { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP }, 106033965Sjdp { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP }, 106133965Sjdp { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP }, 106233965Sjdp { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP }, 106333965Sjdp { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP }, 106433965Sjdp { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP }, 106533965Sjdp { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP }, 106633965Sjdp { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP }, 106733965Sjdp { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 }, 106838889Sjdp { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 }, 106933965Sjdp { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 }, 107033965Sjdp { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 }, 107133965Sjdp 107233965Sjdp { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 }, 107333965Sjdp { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */ 107433965Sjdp { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */ 107533965Sjdp { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */ 107633965Sjdp { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */ 107733965Sjdp { "cpys", FP(0x17,0x020), BASE, ARG_FP }, 107833965Sjdp { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */ 107933965Sjdp { "cpysn", FP(0x17,0x021), BASE, ARG_FP }, 108033965Sjdp { "cpyse", FP(0x17,0x022), BASE, ARG_FP }, 108133965Sjdp { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } }, 108233965Sjdp { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } }, 108333965Sjdp { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP }, 108433965Sjdp { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP }, 108533965Sjdp { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP }, 108633965Sjdp { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP }, 108733965Sjdp { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP }, 108833965Sjdp { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP }, 108933965Sjdp { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 }, 109033965Sjdp { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 }, 109133965Sjdp { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 }, 109233965Sjdp 109333965Sjdp { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE }, 109433965Sjdp { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */ 109533965Sjdp { "excb", MFC(0x18,0x0400), BASE, ARG_NONE }, 109633965Sjdp { "mb", MFC(0x18,0x4000), BASE, ARG_NONE }, 109733965Sjdp { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, 109860484Sobrien { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, 109960484Sobrien { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, 1100130561Sobrien { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } }, 1101130561Sobrien { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */ 110233965Sjdp { "rc", MFC(0x18,0xE000), BASE, { RA } }, 110360484Sobrien { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ 110433965Sjdp { "rs", MFC(0x18,0xF000), BASE, { RA } }, 110560484Sobrien { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ 110689857Sobrien { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ 110733965Sjdp 110833965Sjdp { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 110933965Sjdp { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 111060484Sobrien { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } }, 111133965Sjdp { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR }, 111233965Sjdp { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR }, 111333965Sjdp { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR }, 111433965Sjdp { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR }, 111533965Sjdp { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR }, 111633965Sjdp { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR }, 111733965Sjdp { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR }, 111833965Sjdp { "pal19", PCD(0x19), BASE, ARG_PCD }, 111933965Sjdp 112091041Sobrien { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */ 112191041Sobrien BASE, { ZA, CPRB } }, 112233965Sjdp { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } }, 112333965Sjdp { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } }, 112491041Sobrien { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */ 112591041Sobrien 0xFFFFFFFF, BASE, { 0 } }, 112633965Sjdp { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } }, 112733965Sjdp { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */ 112833965Sjdp { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, 112933965Sjdp 113033965Sjdp { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 113133965Sjdp { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 113260484Sobrien { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM }, 113333965Sjdp { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 113433965Sjdp { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 113560484Sobrien { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM }, 113633965Sjdp { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 113733965Sjdp { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 113833965Sjdp { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 113933965Sjdp { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 114033965Sjdp { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 114133965Sjdp { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 114233965Sjdp { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 114333965Sjdp { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 114433965Sjdp { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 114533965Sjdp { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 114633965Sjdp { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 114760484Sobrien { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM }, 114833965Sjdp { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 114933965Sjdp { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 115033965Sjdp { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 115133965Sjdp { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 115233965Sjdp { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 115333965Sjdp { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 115433965Sjdp { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 115533965Sjdp { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 115633965Sjdp { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 115733965Sjdp { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 115833965Sjdp { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 115933965Sjdp { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 116033965Sjdp { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 116133965Sjdp { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 116233965Sjdp { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 116333965Sjdp { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 116433965Sjdp { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 116533965Sjdp { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 116633965Sjdp { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 116733965Sjdp { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 116860484Sobrien { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM }, 116933965Sjdp { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 117033965Sjdp { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 117160484Sobrien { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM }, 117260484Sobrien { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM }, 117333965Sjdp { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 117433965Sjdp { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 117533965Sjdp { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 117633965Sjdp { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 117733965Sjdp { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 117833965Sjdp { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 117933965Sjdp { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 118033965Sjdp { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 118133965Sjdp { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 118260484Sobrien { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM }, 118333965Sjdp { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 118433965Sjdp { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 118533965Sjdp { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 118633965Sjdp { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 118733965Sjdp { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 118833965Sjdp { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 118933965Sjdp { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 119033965Sjdp { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 119133965Sjdp { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 119233965Sjdp { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 119333965Sjdp { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 119433965Sjdp { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 119560484Sobrien { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM }, 119633965Sjdp { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 119733965Sjdp { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 119860484Sobrien { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM }, 119933965Sjdp { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 120033965Sjdp { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 120133965Sjdp { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 120233965Sjdp { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 120333965Sjdp { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 120433965Sjdp { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 120533965Sjdp { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 120633965Sjdp { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 120733965Sjdp { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 120833965Sjdp { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 120933965Sjdp { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 121060484Sobrien { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM }, 121133965Sjdp { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 121233965Sjdp { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 121333965Sjdp { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 121433965Sjdp { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 121533965Sjdp { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 121633965Sjdp { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 121733965Sjdp { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 121833965Sjdp { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 121933965Sjdp { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 122033965Sjdp { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 122133965Sjdp { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 122233965Sjdp { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 122333965Sjdp { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 122433965Sjdp { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 122533965Sjdp { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 122633965Sjdp { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 122733965Sjdp { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 122833965Sjdp { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 122933965Sjdp { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 123033965Sjdp { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 123160484Sobrien { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM }, 123233965Sjdp { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 123333965Sjdp { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 123460484Sobrien { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM }, 123560484Sobrien { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM }, 123633965Sjdp { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 123733965Sjdp { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 123833965Sjdp { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 123933965Sjdp { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 124033965Sjdp { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 124133965Sjdp { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 124233965Sjdp { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 124333965Sjdp { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 124433965Sjdp { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 124560484Sobrien { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM }, 124633965Sjdp { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 124733965Sjdp { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 124833965Sjdp { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 124933965Sjdp { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 125033965Sjdp { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 125133965Sjdp { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 125233965Sjdp { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 125333965Sjdp { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 125433965Sjdp { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 125533965Sjdp { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 125633965Sjdp { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM }, 125733965Sjdp { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM }, 125833965Sjdp { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM }, 125933965Sjdp { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM }, 126033965Sjdp { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM }, 126133965Sjdp { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM }, 126233965Sjdp { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM }, 126333965Sjdp { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM }, 126433965Sjdp { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM }, 126533965Sjdp { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM }, 126633965Sjdp { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM }, 126733965Sjdp { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM }, 126833965Sjdp { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM }, 126933965Sjdp { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM }, 127033965Sjdp { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM }, 127133965Sjdp { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM }, 127233965Sjdp { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM }, 127333965Sjdp { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM }, 127433965Sjdp { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM }, 127533965Sjdp { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM }, 127633965Sjdp { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM }, 127733965Sjdp { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM }, 127833965Sjdp { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM }, 127933965Sjdp { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM }, 128033965Sjdp { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM }, 128133965Sjdp { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM }, 128233965Sjdp { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM }, 128333965Sjdp { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM }, 128433965Sjdp { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM }, 128533965Sjdp { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM }, 128633965Sjdp { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM }, 128733965Sjdp { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM }, 128833965Sjdp { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM }, 128933965Sjdp { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM }, 129033965Sjdp { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM }, 129133965Sjdp { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM }, 129233965Sjdp { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM }, 129333965Sjdp { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM }, 129433965Sjdp { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM }, 129533965Sjdp { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM }, 129633965Sjdp { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM }, 129733965Sjdp { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM }, 129833965Sjdp { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM }, 129933965Sjdp { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM }, 130033965Sjdp { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM }, 130133965Sjdp { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM }, 130233965Sjdp { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM }, 130333965Sjdp { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM }, 130433965Sjdp { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM }, 130533965Sjdp { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM }, 130633965Sjdp { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM }, 130733965Sjdp { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM }, 130833965Sjdp { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM }, 130933965Sjdp { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM }, 131033965Sjdp { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM }, 131133965Sjdp { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM }, 131233965Sjdp { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM }, 131333965Sjdp { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM }, 131433965Sjdp { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM }, 131533965Sjdp { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM }, 131633965Sjdp { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM }, 131733965Sjdp { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM }, 131833965Sjdp { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM }, 131933965Sjdp { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM }, 132033965Sjdp { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM }, 132133965Sjdp { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM }, 132233965Sjdp { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM }, 132333965Sjdp { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM }, 132433965Sjdp { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM }, 132533965Sjdp { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM }, 132633965Sjdp { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM }, 132733965Sjdp { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM }, 132833965Sjdp { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM }, 132933965Sjdp { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM }, 133033965Sjdp { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM }, 133133965Sjdp { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM }, 133233965Sjdp { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM }, 133333965Sjdp { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM }, 133433965Sjdp { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM }, 133533965Sjdp { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM }, 133633965Sjdp { "pal1b", PCD(0x1B), BASE, ARG_PCD }, 133733965Sjdp 133833965Sjdp { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 }, 133933965Sjdp { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 }, 134033965Sjdp { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 }, 134133965Sjdp { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR }, 134233965Sjdp { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 }, 134333965Sjdp { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 }, 134433965Sjdp { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 }, 134533965Sjdp { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 }, 134633965Sjdp { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 }, 134733965Sjdp { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 }, 134833965Sjdp { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR }, 134933965Sjdp { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL }, 135033965Sjdp { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR }, 135133965Sjdp { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL }, 135233965Sjdp { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR }, 135333965Sjdp { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL }, 135433965Sjdp { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR }, 135533965Sjdp { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL }, 135633965Sjdp { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR }, 135733965Sjdp { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL }, 135833965Sjdp { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR }, 135933965Sjdp { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL }, 136033965Sjdp { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR }, 136133965Sjdp { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL }, 136233965Sjdp { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR }, 136333965Sjdp { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL }, 136433965Sjdp { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } }, 136533965Sjdp { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } }, 136633965Sjdp 136733965Sjdp { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, 136833965Sjdp { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, 136960484Sobrien { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } }, 137033965Sjdp { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR }, 137133965Sjdp { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR }, 137233965Sjdp { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR }, 137333965Sjdp { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR }, 137433965Sjdp { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR }, 137533965Sjdp { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR }, 137633965Sjdp { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR }, 137733965Sjdp { "pal1d", PCD(0x1D), BASE, ARG_PCD }, 137833965Sjdp 137933965Sjdp { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE }, 138038889Sjdp { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE }, 138160484Sobrien { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } }, 138260484Sobrien { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } }, 138360484Sobrien { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } }, 138460484Sobrien { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, 138560484Sobrien { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */ 138660484Sobrien { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } }, 138760484Sobrien { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } }, 138860484Sobrien { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } }, 138960484Sobrien { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, 139060484Sobrien { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */ 139133965Sjdp { "pal1e", PCD(0x1E), BASE, ARG_PCD }, 139233965Sjdp 139333965Sjdp { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 139433965Sjdp { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 139560484Sobrien { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */ 139633965Sjdp { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 139733965Sjdp { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 139860484Sobrien { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM }, 139933965Sjdp { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 140033965Sjdp { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 140133965Sjdp { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 140233965Sjdp { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 140333965Sjdp { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 140433965Sjdp { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 140533965Sjdp { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 140660484Sobrien { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM }, 140733965Sjdp { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 140833965Sjdp { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 140933965Sjdp { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 141033965Sjdp { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 141133965Sjdp { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 141233965Sjdp { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 141333965Sjdp { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 141433965Sjdp { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 141533965Sjdp { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 141633965Sjdp { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 141733965Sjdp { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 141833965Sjdp { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 141933965Sjdp { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 142033965Sjdp { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 142133965Sjdp { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 142233965Sjdp { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 142360484Sobrien { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM }, 142433965Sjdp { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 142533965Sjdp { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 142633965Sjdp { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 142733965Sjdp { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 142833965Sjdp { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 142933965Sjdp { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 143060484Sobrien { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */ 143133965Sjdp { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 143233965Sjdp { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 143360484Sobrien { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM }, 143433965Sjdp { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 143533965Sjdp { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 143633965Sjdp { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 143733965Sjdp { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 143833965Sjdp { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 143933965Sjdp { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 144033965Sjdp { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 144160484Sobrien { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM }, 144233965Sjdp { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 144333965Sjdp { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 144433965Sjdp { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 144533965Sjdp { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 144633965Sjdp { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 144733965Sjdp { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 144833965Sjdp { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 144933965Sjdp { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 145033965Sjdp { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 145133965Sjdp { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 145233965Sjdp { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 145333965Sjdp { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM }, 145433965Sjdp { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 145533965Sjdp { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 145633965Sjdp { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 145733965Sjdp { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 145833965Sjdp { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 145933965Sjdp { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 146060484Sobrien { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM }, 146133965Sjdp { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 146233965Sjdp { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 146333965Sjdp { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 146433965Sjdp { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 146533965Sjdp { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM }, 146633965Sjdp { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM }, 146733965Sjdp { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM }, 146833965Sjdp { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM }, 146933965Sjdp { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM }, 147033965Sjdp { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM }, 147133965Sjdp { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM }, 147233965Sjdp { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM }, 147333965Sjdp { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM }, 147433965Sjdp { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM }, 147533965Sjdp { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM }, 147633965Sjdp { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM }, 147733965Sjdp { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM }, 147833965Sjdp { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM }, 147933965Sjdp { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM }, 148033965Sjdp { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM }, 148133965Sjdp { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM }, 148233965Sjdp { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM }, 148333965Sjdp { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM }, 148433965Sjdp { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM }, 148533965Sjdp { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM }, 148633965Sjdp { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM }, 148733965Sjdp { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM }, 148833965Sjdp { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM }, 148933965Sjdp { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM }, 149033965Sjdp { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM }, 149133965Sjdp { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM }, 149233965Sjdp { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM }, 149333965Sjdp { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM }, 149433965Sjdp { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM }, 149533965Sjdp { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM }, 149633965Sjdp { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM }, 149733965Sjdp { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM }, 149833965Sjdp { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM }, 149933965Sjdp { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM }, 150033965Sjdp { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM }, 150133965Sjdp { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM }, 150233965Sjdp { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM }, 150333965Sjdp { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM }, 150433965Sjdp { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM }, 150533965Sjdp { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM }, 150633965Sjdp { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM }, 150733965Sjdp { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM }, 150833965Sjdp { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM }, 150933965Sjdp { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM }, 151033965Sjdp { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM }, 151133965Sjdp { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM }, 151233965Sjdp { "pal1f", PCD(0x1F), BASE, ARG_PCD }, 151333965Sjdp 151433965Sjdp { "ldf", MEM(0x20), BASE, ARG_FMEM }, 151533965Sjdp { "ldg", MEM(0x21), BASE, ARG_FMEM }, 151633965Sjdp { "lds", MEM(0x22), BASE, ARG_FMEM }, 151733965Sjdp { "ldt", MEM(0x23), BASE, ARG_FMEM }, 151833965Sjdp { "stf", MEM(0x24), BASE, ARG_FMEM }, 151933965Sjdp { "stg", MEM(0x25), BASE, ARG_FMEM }, 152033965Sjdp { "sts", MEM(0x26), BASE, ARG_FMEM }, 152133965Sjdp { "stt", MEM(0x27), BASE, ARG_FMEM }, 152233965Sjdp 152333965Sjdp { "ldl", MEM(0x28), BASE, ARG_MEM }, 152433965Sjdp { "ldq", MEM(0x29), BASE, ARG_MEM }, 152533965Sjdp { "ldl_l", MEM(0x2A), BASE, ARG_MEM }, 152633965Sjdp { "ldq_l", MEM(0x2B), BASE, ARG_MEM }, 152733965Sjdp { "stl", MEM(0x2C), BASE, ARG_MEM }, 152833965Sjdp { "stq", MEM(0x2D), BASE, ARG_MEM }, 152933965Sjdp { "stl_c", MEM(0x2E), BASE, ARG_MEM }, 153033965Sjdp { "stq_c", MEM(0x2F), BASE, ARG_MEM }, 153133965Sjdp 153233965Sjdp { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */ 153333965Sjdp { "br", BRA(0x30), BASE, ARG_BRA }, 153433965Sjdp { "fbeq", BRA(0x31), BASE, ARG_FBRA }, 153533965Sjdp { "fblt", BRA(0x32), BASE, ARG_FBRA }, 153633965Sjdp { "fble", BRA(0x33), BASE, ARG_FBRA }, 153733965Sjdp { "bsr", BRA(0x34), BASE, ARG_BRA }, 153833965Sjdp { "fbne", BRA(0x35), BASE, ARG_FBRA }, 153933965Sjdp { "fbge", BRA(0x36), BASE, ARG_FBRA }, 154033965Sjdp { "fbgt", BRA(0x37), BASE, ARG_FBRA }, 154133965Sjdp { "blbc", BRA(0x38), BASE, ARG_BRA }, 154233965Sjdp { "beq", BRA(0x39), BASE, ARG_BRA }, 154333965Sjdp { "blt", BRA(0x3A), BASE, ARG_BRA }, 154433965Sjdp { "ble", BRA(0x3B), BASE, ARG_BRA }, 154533965Sjdp { "blbs", BRA(0x3C), BASE, ARG_BRA }, 154633965Sjdp { "bne", BRA(0x3D), BASE, ARG_BRA }, 154733965Sjdp { "bge", BRA(0x3E), BASE, ARG_BRA }, 154833965Sjdp { "bgt", BRA(0x3F), BASE, ARG_BRA }, 154933965Sjdp}; 155033965Sjdp 155160484Sobrienconst unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes); 1552