sparc.h revision 104834
153812Salfred/* Definitions for opcode table for the sparc. 253812Salfred Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002 353812Salfred Free Software Foundation, Inc. 453812Salfred 553812SalfredThis file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 653812Salfredthe GNU Binutils. 753812Salfred 853812SalfredGAS/GDB is free software; you can redistribute it and/or modify 956277Sjasoneit under the terms of the GNU General Public License as published by 1056277Sjasonethe Free Software Foundation; either version 2, or (at your option) 1175369Sdeischenany later version. 1275369Sdeischen 1375369SdeischenGAS/GDB is distributed in the hope that it will be useful, 1475369Sdeischenbut WITHOUT ANY WARRANTY; without even the implied warranty of 1571581SdeischenMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1653812SalfredGNU General Public License for more details. 1771581Sdeischen 1853812SalfredYou should have received a copy of the GNU General Public License 1953812Salfredalong with GAS or GDB; see the file COPYING. If not, write to 2053812Salfredthe Free Software Foundation, 59 Temple Place - Suite 330, 2153812SalfredBoston, MA 02111-1307, USA. */ 2253812Salfred 2353812Salfred#include "ansidecl.h" 2453812Salfred 2553812Salfred/* The SPARC opcode table (and other related data) is defined in 2653812Salfred the opcodes library in sparc-opc.c. If you change anything here, make 2753812Salfred sure you fix up that file, and vice versa. */ 2853812Salfred 2954708Sdeischen /* FIXME-someday: perhaps the ,a's and such should be embedded in the 3054708Sdeischen instruction's name rather than the args. This would make gas faster, pinsn 3154708Sdeischen slower, but would mess up some macros a bit. xoxorich. */ 3254708Sdeischen 3354708Sdeischen/* List of instruction sets variations. 3454708Sdeischen These values are such that each element is either a superset of a 3554708Sdeischen preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P 3654708Sdeischen returns non-zero. 3754708Sdeischen The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 3854708Sdeischen Don't change this without updating sparc-opc.c. */ 3953812Salfred 4053812Salfredenum sparc_opcode_arch_val { 4153812Salfred SPARC_OPCODE_ARCH_V6 = 0, 4253812Salfred SPARC_OPCODE_ARCH_V7, 4353812Salfred SPARC_OPCODE_ARCH_V8, 4453812Salfred SPARC_OPCODE_ARCH_SPARCLET, 4553812Salfred SPARC_OPCODE_ARCH_SPARCLITE, 4653812Salfred /* v9 variants must appear last */ 4753812Salfred SPARC_OPCODE_ARCH_V9, 4853812Salfred SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ 4953812Salfred SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */ 5054708Sdeischen SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ 5153812Salfred}; 5253812Salfred 5353812Salfred/* The highest architecture in the table. */ 5453812Salfred#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) 5553812Salfred 5653812Salfred/* Given an enum sparc_opcode_arch_val, return the bitmask to use in 5753812Salfred insn encoding/decoding. */ 5853812Salfred#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) 5953812Salfred 6053812Salfred/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ 6153812Salfred#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) 6253812Salfred 6353812Salfred/* Table of cpu variants. */ 6453812Salfred 6553812Salfredstruct sparc_opcode_arch { 6676909Sjasone const char *name; 6761681Sjasone /* Mask of sparc_opcode_arch_val's supported. 6861681Sjasone EG: For v7 this would be 6961681Sjasone (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 7061681Sjasone These are short's because sparc_opcode.architecture is. */ 7161681Sjasone short supported; 7261681Sjasone}; 7361681Sjasone 7461681Sjasoneextern const struct sparc_opcode_arch sparc_opcode_archs[]; 7561681Sjasone 7661681Sjasone/* Given architecture name, look up it's sparc_opcode_arch_val value. */ 7761681Sjasoneextern enum sparc_opcode_arch_val sparc_opcode_lookup_arch 7861681Sjasone PARAMS ((const char *)); 7961681Sjasone 8061681Sjasone/* Return the bitmask of supported architectures for ARCH. */ 8153812Salfred#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) 8253812Salfred 8353812Salfred/* Non-zero if ARCH1 conflicts with ARCH2. 8453812Salfred IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 8553812Salfred#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 8653812Salfred(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 8753812Salfred != SPARC_OPCODE_SUPPORTED (ARCH1)) \ 8853812Salfred && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 8953812Salfred != SPARC_OPCODE_SUPPORTED (ARCH2))) 9053812Salfred 9153812Salfred/* Structure of an opcode table entry. */ 9253812Salfred 9356277Sjasonestruct sparc_opcode { 9456277Sjasone const char *name; 9553812Salfred unsigned long match; /* Bits that must be set. */ 9653812Salfred unsigned long lose; /* Bits that must not be set. */ 9753812Salfred const char *args; 9853812Salfred /* This was called "delayed" in versions before the flags. */ 9956277Sjasone char flags; 10053812Salfred short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 10153812Salfred}; 10253812Salfred 10353812Salfred#define F_DELAYED 1 /* Delayed branch */ 10453812Salfred#define F_ALIAS 2 /* Alias for a "real" instruction */ 10553812Salfred#define F_UNBR 4 /* Unconditional branch */ 10653812Salfred#define F_CONDBR 8 /* Conditional branch */ 10754708Sdeischen#define F_JSR 16 /* Subroutine call */ 10853812Salfred#define F_FLOAT 32 /* Floating point instruction (not a branch) */ 10954708Sdeischen#define F_FBR 64 /* Floating point branch */ 11053812Salfred/* FIXME: Add F_ANACHRONISTIC flag for v9. */ 11153812Salfred 11253812Salfred/* 11353812Salfred 11453812SalfredAll sparc opcodes are 32 bits, except for the `set' instruction (really a 11553812Salfredmacro), which is 64 bits. It is handled as a special case. 11653812Salfred 11753812SalfredThe match component is a mask saying which bits must match a particular 11853812Salfredopcode in order for an instruction to be an instance of that opcode. 11971581Sdeischen 12053812SalfredThe args component is a string containing one character for each operand of the 12171581Sdeischeninstruction. 12253812Salfred 12353812SalfredKinds of operands: 12453812Salfred # Number used by optimizer. It is ignored. 12571581Sdeischen 1 rs1 register. 12653812Salfred 2 rs2 register. 12753812Salfred d rd register. 12853812Salfred e frs1 floating point register. 12953812Salfred v frs1 floating point register (double/even). 13053812Salfred V frs1 floating point register (quad/multiple of 4). 13171581Sdeischen f frs2 floating point register. 13271581Sdeischen B frs2 floating point register (double/even). 13353812Salfred R frs2 floating point register (quad/multiple of 4). 13453812Salfred g frsd floating point register. 13553812Salfred H frsd floating point register (double/even). 13653812Salfred J frsd floating point register (quad/multiple of 4). 13753812Salfred b crs1 coprocessor register 13853812Salfred c crs2 coprocessor register 13971581Sdeischen D crsd coprocessor register 14053812Salfred m alternate space register (asr) in rd 14153812Salfred M alternate space register (asr) in rs1 14253812Salfred h 22 high bits. 14353812Salfred X 5 bit unsigned immediate 14453812Salfred Y 6 bit unsigned immediate 14553812Salfred 3 SIAM mode (3 bits). (v9b) 14653812Salfred K MEMBAR mask (7 bits). (v9) 14753812Salfred j 10 bit Immediate. (v9) 14853812Salfred I 11 bit Immediate. (v9) 14953812Salfred i 13 bit Immediate. 15071581Sdeischen n 22 bit immediate. 15153812Salfred k 2+14 bit PC relative immediate. (v9) 15271581Sdeischen G 19 bit PC relative immediate. (v9) 15353812Salfred l 22 bit PC relative immediate. 15453812Salfred L 30 bit PC relative immediate. 15553812Salfred a Annul. The annul bit is set. 15671581Sdeischen A Alternate address space. Stored as 8 bits. 15753812Salfred C Coprocessor state register. 15853812Salfred F floating point state register. 15953812Salfred p Processor state register. 16053812Salfred N Branch predict clear ",pn" (v9) 16171581Sdeischen T Branch predict set ",pt" (v9) 16253812Salfred z %icc. (v9) 16353812Salfred Z %xcc. (v9) 16453812Salfred q Floating point queue. 16553812Salfred r Single register that is both rs1 and rd. 16653812Salfred O Single register that is both rs2 and rd. 16753812Salfred Q Coprocessor queue. 16871581Sdeischen S Special case. 16953812Salfred t Trap base register. 17053812Salfred w Window invalid mask register. 17153812Salfred y Y register. 17253812Salfred u sparclet coprocessor registers in rd position 17353812Salfred U sparclet coprocessor registers in rs1 position 17453812Salfred E %ccr. (v9) 17553812Salfred s %fprs. (v9) 17653812Salfred P %pc. (v9) 17753812Salfred W %tick. (v9) 17853812Salfred o %asi. (v9) 17971581Sdeischen 6 %fcc0. (v9) 18053812Salfred 7 %fcc1. (v9) 18171581Sdeischen 8 %fcc2. (v9) 18271581Sdeischen 9 %fcc3. (v9) 18371581Sdeischen ! Privileged Register in rd (v9) 18471581Sdeischen ? Privileged Register in rs1 (v9) 18553812Salfred * Prefetch function constant. (v9) 18653812Salfred x OPF field (v9 impdep). 18753812Salfred 0 32/64 bit immediate for set or setx (v9) insns 18853812Salfred _ Ancillary state register in rd (v9a) 18953812Salfred / Ancillary state register in rs1 (v9a) 19071581Sdeischen 19153812SalfredThe following chars are unused: (note: ,[] are used as punctuation) 19276909Sjasone[45] 19353812Salfred 19453812Salfred*/ 19553812Salfred 19653812Salfred#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ 19753812Salfred#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ 19853812Salfred#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ 19953812Salfred#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ 20053812Salfred#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ 20171581Sdeischen#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ 20271581Sdeischen#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ 20353812Salfred#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ 20453812Salfred#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ 20571581Sdeischen#define F1(x) (OP(x)) 20653812Salfred#define DISP30(x) ((x)&0x3fffffff) 20753812Salfred#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ 20853812Salfred#define RS2(x) ((x)&0x1f) /* rs2 field */ 20953812Salfred#define SIMM13(x) ((x)&0x1fff) /* simm13 field */ 21053812Salfred#define RD(x) (((x)&0x1f) << 25) /* destination register field */ 21171581Sdeischen#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ 21271581Sdeischen#define ASI_RS2(x) (SIMM13(x)) 21371581Sdeischen#define MEMBAR(x) ((x)&0x7f) 21453812Salfred#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ 21553812Salfred 21653812Salfred#define ANNUL (1<<29) 21756277Sjasone#define BPRED (1<<19) /* v9 */ 21856277Sjasone#define IMMED F3I(1) 21956277Sjasone#define RD_G0 RD(~0) 22056277Sjasone#define RS1_G0 RS1(~0) 22171581Sdeischen#define RS2_G0 RS2(~0) 22256277Sjasone 22371581Sdeischenextern const struct sparc_opcode sparc_opcodes[]; 22471581Sdeischenextern const int sparc_num_opcodes; 22571581Sdeischen 22671581Sdeischenextern int sparc_encode_asi PARAMS ((const char *)); 22771581Sdeischenextern const char *sparc_decode_asi PARAMS ((int)); 22856277Sjasoneextern int sparc_encode_membar PARAMS ((const char *)); 22976909Sjasoneextern const char *sparc_decode_membar PARAMS ((int)); 23056277Sjasoneextern int sparc_encode_prefetch PARAMS ((const char *)); 23156277Sjasoneextern const char *sparc_decode_prefetch PARAMS ((int)); 23256277Sjasoneextern int sparc_encode_sparclet_cpreg PARAMS ((const char *)); 233extern const char *sparc_decode_sparclet_cpreg PARAMS ((int)); 234 235/* 236 * Local Variables: 237 * fill-column: 131 238 * comment-column: 0 239 * End: 240 */ 241 242/* end of sparc.h */ 243