1130561Sobrien/* Xtensa ELF support for BFD. 2218822Sdim Copyright 2003, 2004 Free Software Foundation, Inc. 3130561Sobrien Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 4130561Sobrien 5130561Sobrien This file is part of BFD, the Binary File Descriptor library. 6130561Sobrien 7130561Sobrien This program is free software; you can redistribute it and/or modify 8130561Sobrien it under the terms of the GNU General Public License as published by 9130561Sobrien the Free Software Foundation; either version 2 of the License, or 10130561Sobrien (at your option) any later version. 11130561Sobrien 12130561Sobrien This program is distributed in the hope that it will be useful, 13130561Sobrien but WITHOUT ANY WARRANTY; without even the implied warranty of 14130561Sobrien MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15130561Sobrien GNU General Public License for more details. 16130561Sobrien 17130561Sobrien You should have received a copy of the GNU General Public License 18130561Sobrien along with this program; if not, write to the Free Software 19218822Sdim Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, 20130561Sobrien USA. */ 21130561Sobrien 22130561Sobrien/* This file holds definitions specific to the Xtensa ELF ABI. */ 23130561Sobrien 24130561Sobrien#ifndef _ELF_XTENSA_H 25130561Sobrien#define _ELF_XTENSA_H 26130561Sobrien 27130561Sobrien#include "elf/reloc-macros.h" 28130561Sobrien 29130561Sobrien/* Relocations. */ 30130561SobrienSTART_RELOC_NUMBERS (elf_xtensa_reloc_type) 31130561Sobrien RELOC_NUMBER (R_XTENSA_NONE, 0) 32130561Sobrien RELOC_NUMBER (R_XTENSA_32, 1) 33130561Sobrien RELOC_NUMBER (R_XTENSA_RTLD, 2) 34130561Sobrien RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3) 35130561Sobrien RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4) 36130561Sobrien RELOC_NUMBER (R_XTENSA_RELATIVE, 5) 37130561Sobrien RELOC_NUMBER (R_XTENSA_PLT, 6) 38130561Sobrien RELOC_NUMBER (R_XTENSA_OP0, 8) 39130561Sobrien RELOC_NUMBER (R_XTENSA_OP1, 9) 40130561Sobrien RELOC_NUMBER (R_XTENSA_OP2, 10) 41130561Sobrien RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11) 42130561Sobrien RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12) 43130561Sobrien RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15) 44130561Sobrien RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16) 45218822Sdim RELOC_NUMBER (R_XTENSA_DIFF8, 17) 46218822Sdim RELOC_NUMBER (R_XTENSA_DIFF16, 18) 47218822Sdim RELOC_NUMBER (R_XTENSA_DIFF32, 19) 48218822Sdim RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20) 49218822Sdim RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21) 50218822Sdim RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22) 51218822Sdim RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23) 52218822Sdim RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24) 53218822Sdim RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25) 54218822Sdim RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26) 55218822Sdim RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27) 56218822Sdim RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28) 57218822Sdim RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29) 58218822Sdim RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30) 59218822Sdim RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31) 60218822Sdim RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32) 61218822Sdim RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33) 62218822Sdim RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34) 63218822Sdim RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35) 64218822Sdim RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36) 65218822Sdim RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37) 66218822Sdim RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38) 67218822Sdim RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39) 68218822Sdim RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40) 69218822Sdim RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41) 70218822Sdim RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42) 71218822Sdim RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43) 72218822Sdim RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44) 73218822Sdim RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45) 74218822Sdim RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46) 75218822Sdim RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47) 76218822Sdim RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48) 77218822Sdim RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49) 78130561SobrienEND_RELOC_NUMBERS (R_XTENSA_max) 79130561Sobrien 80130561Sobrien/* Processor-specific flags for the ELF header e_flags field. */ 81130561Sobrien 82130561Sobrien/* Four-bit Xtensa machine type field. */ 83130561Sobrien#define EF_XTENSA_MACH 0x0000000f 84130561Sobrien 85130561Sobrien/* Various CPU types. */ 86130561Sobrien#define E_XTENSA_MACH 0x00000000 87130561Sobrien 88130561Sobrien/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. 89130561Sobrien Highly unlikely, but what the heck. */ 90130561Sobrien 91130561Sobrien#define EF_XTENSA_XT_INSN 0x00000100 92130561Sobrien#define EF_XTENSA_XT_LIT 0x00000200 93130561Sobrien 94130561Sobrien 95130561Sobrien/* Processor-specific dynamic array tags. */ 96130561Sobrien 97130561Sobrien/* Offset of the table that records the GOT location(s). */ 98130561Sobrien#define DT_XTENSA_GOT_LOC_OFF 0x70000000 99130561Sobrien 100130561Sobrien/* Number of entries in the GOT location table. */ 101130561Sobrien#define DT_XTENSA_GOT_LOC_SZ 0x70000001 102130561Sobrien 103130561Sobrien 104130561Sobrien/* Definitions for instruction and literal property tables. The 105130561Sobrien tables for ".gnu.linkonce.*" sections are placed in the following 106130561Sobrien sections: 107130561Sobrien 108130561Sobrien instruction tables: .gnu.linkonce.x.* 109130561Sobrien literal tables: .gnu.linkonce.p.* 110130561Sobrien*/ 111130561Sobrien 112130561Sobrien#define XTENSA_INSN_SEC_NAME ".xt.insn" 113130561Sobrien#define XTENSA_LIT_SEC_NAME ".xt.lit" 114218822Sdim#define XTENSA_PROP_SEC_NAME ".xt.prop" 115130561Sobrien 116130561Sobrientypedef struct property_table_entry_t 117130561Sobrien{ 118130561Sobrien bfd_vma address; 119130561Sobrien bfd_vma size; 120218822Sdim flagword flags; 121130561Sobrien} property_table_entry; 122130561Sobrien 123218822Sdim/* Flags in the property tables to specify whether blocks of memory are 124218822Sdim literals, instructions, data, or unreachable. For instructions, 125218822Sdim blocks that begin loop targets and branch targets are designated. 126218822Sdim Blocks that do not allow density instructions, instruction reordering 127218822Sdim or transformation are also specified. Finally, for branch targets, 128218822Sdim branch target alignment priority is included. Alignment of the next 129218822Sdim block is specified in the current block and the size of the current 130218822Sdim block does not include any fill required to align to the next 131218822Sdim block. */ 132218822Sdim 133218822Sdim#define XTENSA_PROP_LITERAL 0x00000001 134218822Sdim#define XTENSA_PROP_INSN 0x00000002 135218822Sdim#define XTENSA_PROP_DATA 0x00000004 136218822Sdim#define XTENSA_PROP_UNREACHABLE 0x00000008 137218822Sdim/* Instruction-only properties at beginning of code. */ 138218822Sdim#define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 139218822Sdim#define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 140218822Sdim/* Instruction-only properties about code. */ 141218822Sdim#define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 142218822Sdim#define XTENSA_PROP_INSN_NO_REORDER 0x00000080 143218822Sdim/* Historically, NO_TRANSFORM was a property of instructions, 144218822Sdim but it should apply to literals under certain circumstances. */ 145218822Sdim#define XTENSA_PROP_NO_TRANSFORM 0x00000100 146218822Sdim 147218822Sdim/* Branch target alignment information. This transmits information 148218822Sdim to the linker optimization about the priority of aligning a 149218822Sdim particular block for branch target alignment: None, low priority, 150218822Sdim high priority, or required. These only need to be checked in 151218822Sdim instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. 152218822Sdim Common usage is: 153218822Sdim 154218822Sdim switch (GET_XTENSA_PROP_BT_ALIGN(flags)) 155218822Sdim case XTENSA_PROP_BT_ALIGN_NONE: 156218822Sdim case XTENSA_PROP_BT_ALIGN_LOW: 157218822Sdim case XTENSA_PROP_BT_ALIGN_HIGH: 158218822Sdim case XTENSA_PROP_BT_ALIGN_REQUIRE: 159218822Sdim*/ 160218822Sdim#define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 161218822Sdim 162218822Sdim/* No branch target alignment. */ 163218822Sdim#define XTENSA_PROP_BT_ALIGN_NONE 0x0 164218822Sdim/* Low priority branch target alignment. */ 165218822Sdim#define XTENSA_PROP_BT_ALIGN_LOW 0x1 166218822Sdim/* High priority branch target alignment. */ 167218822Sdim#define XTENSA_PROP_BT_ALIGN_HIGH 0x2 168218822Sdim/* Required branch target alignment. */ 169218822Sdim#define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 170218822Sdim 171218822Sdim#define GET_XTENSA_PROP_BT_ALIGN(flag) \ 172218822Sdim (((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) 173218822Sdim#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ 174218822Sdim (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ 175218822Sdim (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) 176218822Sdim 177218822Sdim/* Alignment is specified in the block BEFORE the one that needs 178218822Sdim alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to 179218822Sdim get the required alignment specified as a power of 2. Use 180218822Sdim SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required 181218822Sdim alignment. Be careful of side effects since the SET will evaluate 182218822Sdim flags twice. Also, note that the SIZE of a block in the property 183218822Sdim table does not include the alignment size, so the alignment fill 184218822Sdim must be calculated to determine if two blocks are contiguous. 185218822Sdim TEXT_ALIGN is not currently implemented but is a placeholder for a 186218822Sdim possible future implementation. */ 187218822Sdim 188218822Sdim#define XTENSA_PROP_ALIGN 0x00000800 189218822Sdim 190218822Sdim#define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 191218822Sdim 192218822Sdim#define GET_XTENSA_PROP_ALIGNMENT(flag) \ 193218822Sdim (((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) 194218822Sdim#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ 195218822Sdim (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ 196218822Sdim (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) 197218822Sdim 198218822Sdim#define XTENSA_PROP_INSN_ABSLIT 0x00020000 199218822Sdim 200130561Sobrien#endif /* _ELF_XTENSA_H */ 201