c-i386.texi revision 60484
1251875Speter@c Copyright (C) 1991, 92, 93, 94, 95, 97, 1998 Free Software Foundation, Inc. 2251875Speter@c This is part of the GAS manual. 3251875Speter@c For copying conditions, see the file as.texinfo. 4251875Speter@ifset GENERIC 5251875Speter@page 6251875Speter@node i386-Dependent 7251875Speter@chapter 80386 Dependent Features 8251875Speter@end ifset 9251875Speter@ifclear GENERIC 10251875Speter@node Machine Dependencies 11251875Speter@chapter 80386 Dependent Features 12251875Speter@end ifclear 13251875Speter 14251875Speter@cindex i386 support 15251875Speter@cindex i80306 support 16251875Speter@menu 17251875Speter* i386-Options:: Options 18251875Speter* i386-Syntax:: AT&T Syntax versus Intel Syntax 19251875Speter* i386-Mnemonics:: Instruction Naming 20251875Speter* i386-Regs:: Register Naming 21251875Speter* i386-Prefixes:: Instruction Prefixes 22251875Speter* i386-Memory:: Memory References 23251875Speter* i386-jumps:: Handling of Jump Instructions 24251875Speter* i386-Float:: Floating Point 25251875Speter* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 26251875Speter* i386-16bit:: Writing 16-bit Code 27251875Speter* i386-Bugs:: AT&T Syntax bugs 28251875Speter* i386-Notes:: Notes 29251875Speter@end menu 30251875Speter 31251875Speter@node i386-Options 32251875Speter@section Options 33251875Speter 34251875Speter@cindex options for i386 (none) 35251875Speter@cindex i386 options (none) 36251875SpeterThe 80386 has no machine dependent options. 37251875Speter 38251875Speter@node i386-Syntax 39251875Speter@section AT&T Syntax versus Intel Syntax 40251875Speter 41251875Speter@cindex i386 syntax compatibility 42251875Speter@cindex syntax compatibility, i386 43251875SpeterIn order to maintain compatibility with the output of @code{@value{GCC}}, 44251875Speter@code{@value{AS}} supports AT&T System V/386 assembler syntax. This is quite 45251875Speterdifferent from Intel syntax. We mention these differences because 46251875Speteralmost all 80386 documents use Intel syntax. Notable differences 47251875Speterbetween the two syntaxes are: 48251875Speter 49251875Speter@cindex immediate operands, i386 50251875Speter@cindex i386 immediate operands 51251875Speter@cindex register operands, i386 52251875Speter@cindex i386 register operands 53251875Speter@cindex jump/call operands, i386 54251875Speter@cindex i386 jump/call operands 55251875Speter@cindex operand delimiters, i386 56251875Speter@itemize @bullet 57251875Speter@item 58251875SpeterAT&T immediate operands are preceded by @samp{$}; Intel immediate 59251875Speteroperands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}). 60251875SpeterAT&T register operands are preceded by @samp{%}; Intel register operands 61251875Speterare undelimited. AT&T absolute (as opposed to PC relative) jump/call 62251875Speteroperands are prefixed by @samp{*}; they are undelimited in Intel syntax. 63251875Speter 64251875Speter@cindex i386 source, destination operands 65251875Speter@cindex source, destination operands; i386 66251875Speter@item 67251875SpeterAT&T and Intel syntax use the opposite order for source and destination 68251875Speteroperands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The 69251875Speter@samp{source, dest} convention is maintained for compatibility with 70251875Speterprevious Unix assemblers. Note that instructions with more than one 71251875Spetersource operand, such as the @samp{enter} instruction, do @emph{not} have 72251875Speterreversed order. @ref{i386-Bugs}. 73251875Speter 74251875Speter@cindex mnemonic suffixes, i386 75251875Speter@cindex sizes operands, i386 76251875Speter@cindex i386 size suffixes 77251875Speter@item 78251875SpeterIn AT&T syntax the size of memory operands is determined from the last 79253734Spetercharacter of the instruction mnemonic. Mnemonic suffixes of @samp{b}, 80251875Speter@samp{w}, and @samp{l} specify byte (8-bit), word (16-bit), and long 81251875Speter(32-bit) memory references. Intel syntax accomplishes this by prefixing 82251875Spetermemory operands (@emph{not} the instruction mnemonics) with @samp{byte 83251875Speterptr}, @samp{word ptr}, and @samp{dword ptr}. Thus, Intel @samp{mov al, 84251875Speterbyte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax. 85251875Speter 86251875Speter@cindex return instructions, i386 87251875Speter@cindex i386 jump, call, return 88251875Speter@item 89251875SpeterImmediate form long jumps and calls are 90251875Speter@samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the 91251875SpeterIntel syntax is 92251875Speter@samp{call/jmp far @var{section}:@var{offset}}. Also, the far return 93251875Speterinstruction 94251875Speteris @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is 95251875Speter@samp{ret far @var{stack-adjust}}. 96251875Speter 97251875Speter@cindex sections, i386 98251875Speter@cindex i386 sections 99251875Speter@item 100251875SpeterThe AT&T assembler does not provide support for multiple section 101251875Speterprograms. Unix style systems expect all programs to be single sections. 102251875Speter@end itemize 103251875Speter 104251875Speter@node i386-Mnemonics 105251875Speter@section Instruction Naming 106251875Speter 107251875Speter@cindex i386 instruction naming 108251875Speter@cindex instruction naming, i386 109251875SpeterInstruction mnemonics are suffixed with one character modifiers which 110251875Speterspecify the size of operands. The letters @samp{b}, @samp{w}, and 111251875Speter@samp{l} specify byte, word, and long operands. If no suffix is 112251875Speterspecified by an instruction then @code{@value{AS}} tries to fill in the 113251875Spetermissing suffix based on the destination register operand (the last one 114251875Speterby convention). Thus, @samp{mov %ax, %bx} is equivalent to @samp{movw 115251875Speter%ax, %bx}; also, @samp{mov $1, %bx} is equivalent to @samp{movw $1, 116251875Speter%bx}. Note that this is incompatible with the AT&T Unix assembler which 117251875Speterassumes that a missing mnemonic suffix implies long operand size. (This 118251875Speterincompatibility does not affect compiler output since compilers always 119251875Speterexplicitly specify the mnemonic suffix.) 120251875Speter 121251875SpeterAlmost all instructions have the same names in AT&T and Intel format. 122251875SpeterThere are a few exceptions. The sign extend and zero extend 123251875Speterinstructions need two sizes to specify them. They need a size to 124251875Spetersign/zero extend @emph{from} and a size to zero extend @emph{to}. This 125251875Speteris accomplished by using two instruction mnemonic suffixes in AT&T 126251875Spetersyntax. Base names for sign extend and zero extend are 127251875Speter@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} 128251875Speterand @samp{movzx} in Intel syntax). The instruction mnemonic suffixes 129251875Speterare tacked on to this base name, the @emph{from} suffix before the 130251875Speter@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for 131251875Speter``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, 132251875Speterthus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), 133251875Speterand @samp{wl} (from word to long). 134251875Speter 135251875Speter@cindex conversion instructions, i386 136251875Speter@cindex i386 conversion instructions 137251875SpeterThe Intel-syntax conversion instructions 138251875Speter 139251875Speter@itemize @bullet 140251875Speter@item 141251875Speter@samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax}, 142251875Speter 143251875Speter@item 144251875Speter@samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax}, 145251875Speter 146251875Speter@item 147251875Speter@samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax}, 148251875Speter 149251875Speter@item 150251875Speter@samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax}, 151251875Speter@end itemize 152251875Speter 153251875Speter@noindent 154251875Speterare called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, and @samp{cltd} in 155251875SpeterAT&T naming. @code{@value{AS}} accepts either naming for these instructions. 156251875Speter 157251875Speter@cindex jump instructions, i386 158251875Speter@cindex call instructions, i386 159251875SpeterFar call/jump instructions are @samp{lcall} and @samp{ljmp} in 160251875SpeterAT&T syntax, but are @samp{call far} and @samp{jump far} in Intel 161251875Speterconvention. 162251875Speter 163251875Speter@node i386-Regs 164251875Speter@section Register Naming 165251875Speter 166251875Speter@cindex i386 registers 167251875Speter@cindex registers, i386 168251875SpeterRegister operands are always prefixed with @samp{%}. The 80386 registers 169251875Speterconsist of 170251875Speter 171251875Speter@itemize @bullet 172251875Speter@item 173251875Speterthe 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx}, 174251875Speter@samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the 175251875Speterframe pointer), and @samp{%esp} (the stack pointer). 176251875Speter 177251875Speter@item 178251875Speterthe 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx}, 179251875Speter@samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}. 180251875Speter 181251875Speter@item 182251875Speterthe 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh}, 183251875Speter@samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These 184251875Speterare the high-bytes and low-bytes of @samp{%ax}, @samp{%bx}, 185251875Speter@samp{%cx}, and @samp{%dx}) 186251875Speter 187251875Speter@item 188251875Speterthe 6 section registers @samp{%cs} (code section), @samp{%ds} 189251875Speter(data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs}, 190251875Speterand @samp{%gs}. 191251875Speter 192251875Speter@item 193251875Speterthe 3 processor control registers @samp{%cr0}, @samp{%cr2}, and 194251875Speter@samp{%cr3}. 195251875Speter 196251875Speter@item 197251875Speterthe 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, 198251875Speter@samp{%db3}, @samp{%db6}, and @samp{%db7}. 199251875Speter 200251875Speter@item 201251875Speterthe 2 test registers @samp{%tr6} and @samp{%tr7}. 202251875Speter 203251875Speter@item 204251875Speterthe 8 floating point register stack @samp{%st} or equivalently 205251875Speter@samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)}, 206251875Speter@samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}. 207251875Speter@end itemize 208251875Speter 209251875Speter@node i386-Prefixes 210251875Speter@section Instruction Prefixes 211251875Speter 212251875Speter@cindex i386 instruction prefixes 213251875Speter@cindex instruction prefixes, i386 214251875Speter@cindex prefixes, i386 215251875SpeterInstruction prefixes are used to modify the following instruction. They 216251875Speterare used to repeat string instructions, to provide section overrides, to 217251875Speterperform bus lock operations, and to change operand and address sizes. 218251875Speter(Most instructions that normally operate on 32-bit operands will use 219251875Speter16-bit operands if the instruction has an ``operand size'' prefix.) 220251875SpeterInstruction prefixes are best written on the same line as the instruction 221251875Speterthey act upon. For example, the @samp{scas} (scan string) instruction is 222251875Speterrepeated with: 223251875Speter 224251875Speter@smallexample 225251875Speter repne scas %es:(%edi),%al 226251875Speter@end smallexample 227251875Speter 228251875SpeterYou may also place prefixes on the lines immediately preceding the 229251875Speterinstruction, but this circumvents checks that @code{@value{AS}} does 230251875Speterwith prefixes, and will not work with all prefixes. 231251875Speter 232251875SpeterHere is a list of instruction prefixes: 233251875Speter 234251875Speter@cindex section override prefixes, i386 235251875Speter@itemize @bullet 236251875Speter@item 237251875SpeterSection override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es}, 238251875Speter@samp{fs}, @samp{gs}. These are automatically added by specifying 239251875Speterusing the @var{section}:@var{memory-operand} form for memory references. 240251875Speter 241251875Speter@cindex size prefixes, i386 242251875Speter@item 243251875SpeterOperand/Address size prefixes @samp{data16} and @samp{addr16} 244change 32-bit operands/addresses into 16-bit operands/addresses, 245while @samp{data32} and @samp{addr32} change 16-bit ones (in a 246@code{.code16} section) into 32-bit operands/addresses. These prefixes 247@emph{must} appear on the same line of code as the instruction they 248modify. For example, in a 16-bit @code{.code16} section, you might 249write: 250 251@smallexample 252 addr32 jmpl *(%ebx) 253@end smallexample 254 255@cindex bus lock prefixes, i386 256@cindex inhibiting interrupts, i386 257@item 258The bus lock prefix @samp{lock} inhibits interrupts during execution of 259the instruction it precedes. (This is only valid with certain 260instructions; see a 80386 manual for details). 261 262@cindex coprocessor wait, i386 263@item 264The wait for coprocessor prefix @samp{wait} waits for the coprocessor to 265complete the current instruction. This should never be needed for the 26680386/80387 combination. 267 268@cindex repeat prefixes, i386 269@item 270The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added 271to string instructions to make them repeat @samp{%ecx} times (@samp{%cx} 272times if the current address size is 16-bits). 273@end itemize 274 275@node i386-Memory 276@section Memory References 277 278@cindex i386 memory references 279@cindex memory references, i386 280An Intel syntax indirect memory reference of the form 281 282@smallexample 283@var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}] 284@end smallexample 285 286@noindent 287is translated into the AT&T syntax 288 289@smallexample 290@var{section}:@var{disp}(@var{base}, @var{index}, @var{scale}) 291@end smallexample 292 293@noindent 294where @var{base} and @var{index} are the optional 32-bit base and 295index registers, @var{disp} is the optional displacement, and 296@var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index} 297to calculate the address of the operand. If no @var{scale} is 298specified, @var{scale} is taken to be 1. @var{section} specifies the 299optional section register for the memory operand, and may override the 300default section register (see a 80386 manual for section register 301defaults). Note that section overrides in AT&T syntax @emph{must} 302be preceded by a @samp{%}. If you specify a section override which 303coincides with the default section register, @code{@value{AS}} does @emph{not} 304output any section register override prefixes to assemble the given 305instruction. Thus, section overrides can be specified to emphasize which 306section register is used for a given memory operand. 307 308Here are some examples of Intel and AT&T style memory references: 309 310@table @asis 311@item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]} 312@var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is 313missing, and the default section is used (@samp{%ss} for addressing with 314@samp{%ebp} as the base register). @var{index}, @var{scale} are both missing. 315 316@item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]} 317@var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is 318@samp{foo}. All other fields are missing. The section register here 319defaults to @samp{%ds}. 320 321@item AT&T: @samp{foo(,1)}; Intel @samp{[foo]} 322This uses the value pointed to by @samp{foo} as a memory operand. 323Note that @var{base} and @var{index} are both missing, but there is only 324@emph{one} @samp{,}. This is a syntactic exception. 325 326@item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo} 327This selects the contents of the variable @samp{foo} with section 328register @var{section} being @samp{%gs}. 329@end table 330 331Absolute (as opposed to PC relative) call and jump operands must be 332prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}} 333always chooses PC relative addressing for jump/call labels. 334 335Any instruction that has a memory operand, but no register operand, 336@emph{must} specify its size (byte, word, or long) with an instruction 337mnemonic suffix (@samp{b}, @samp{w}, or @samp{l}, respectively). 338 339@node i386-jumps 340@section Handling of Jump Instructions 341 342@cindex jump optimization, i386 343@cindex i386 jump optimization 344Jump instructions are always optimized to use the smallest possible 345displacements. This is accomplished by using byte (8-bit) displacement 346jumps whenever the target is sufficiently close. If a byte displacement 347is insufficient a long (32-bit) displacement is used. We do not support 348word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 349instruction with the @samp{data16} instruction prefix), since the 80386 350insists upon masking @samp{%eip} to 16 bits after the word displacement 351is added. 352 353Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz}, 354@samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte 355displacements, so that if you use these instructions (@code{@value{GCC}} does 356not use them) you may get an error message (and incorrect code). The AT&T 35780386 assembler tries to get around this problem by expanding @samp{jcxz foo} 358to 359 360@smallexample 361 jcxz cx_zero 362 jmp cx_nonzero 363cx_zero: jmp foo 364cx_nonzero: 365@end smallexample 366 367@node i386-Float 368@section Floating Point 369 370@cindex i386 floating point 371@cindex floating point, i386 372All 80387 floating point types except packed BCD are supported. 373(BCD support may be added without much difficulty). These data 374types are 16-, 32-, and 64- bit integers, and single (32-bit), 375double (64-bit), and extended (80-bit) precision floating point. 376Each supported type has an instruction mnemonic suffix and a constructor 377associated with it. Instruction mnemonic suffixes specify the operand's 378data type. Constructors build these data types into memory. 379 380@cindex @code{float} directive, i386 381@cindex @code{single} directive, i386 382@cindex @code{double} directive, i386 383@cindex @code{tfloat} directive, i386 384@itemize @bullet 385@item 386Floating point constructors are @samp{.float} or @samp{.single}, 387@samp{.double}, and @samp{.tfloat} for 32-, 64-, and 80-bit formats. 388These correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, 389and @samp{t}. @samp{t} stands for 80-bit (ten byte) real. The 80387 390only supports this format via the @samp{fldt} (load 80-bit real to stack 391top) and @samp{fstpt} (store 80-bit real and pop stack) instructions. 392 393@cindex @code{word} directive, i386 394@cindex @code{long} directive, i386 395@cindex @code{int} directive, i386 396@cindex @code{quad} directive, i386 397@item 398Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and 399@samp{.quad} for the 16-, 32-, and 64-bit integer formats. The 400corresponding instruction mnemonic suffixes are @samp{s} (single), 401@samp{l} (long), and @samp{q} (quad). As with the 80-bit real format, 402the 64-bit @samp{q} format is only present in the @samp{fildq} (load 403quad integer to stack top) and @samp{fistpq} (store quad integer and pop 404stack) instructions. 405@end itemize 406 407Register to register operations should not use instruction mnemonic suffixes. 408@samp{fstl %st, %st(1)} will give a warning, and be assembled as if you 409wrote @samp{fst %st, %st(1)}, since all register to register operations 410use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem}, 411which converts @samp{%st} from 80-bit to 64-bit floating point format, 412then stores the result in the 4 byte location @samp{mem}) 413 414@node i386-SIMD 415@section Intel's MMX and AMD's 3DNow! SIMD Operations 416 417@cindex MMX, i386 418@cindex 3DNow!, i386 419@cindex SIMD, i386 420 421@code{@value{AS}} supports Intel's MMX instruction set (SIMD 422instructions for integer data), available on Intel's Pentium MMX 423processors and Pentium II processors, AMD's K6 and K6-2 processors, 424Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! 425instruction set (SIMD instructions for 32-bit floating point data) 426available on AMD's K6-2 processor and possibly others in the future. 427 428Currently, @code{@value{AS}} does not support Intel's floating point 429SIMD, Katmai (KNI). 430 431The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0}, 432@samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four 43316-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 434floating point values. The MMX registers cannot be used at the same time 435as the floating point stack. 436 437See Intel and AMD documentation, keeping in mind that the operand order in 438instructions is reversed from the Intel syntax. 439 440@node i386-16bit 441@section Writing 16-bit Code 442 443@cindex i386 16-bit code 444@cindex 16-bit code, i386 445@cindex real-mode code, i386 446@cindex @code{code16gcc} directive, i386 447@cindex @code{code16} directive, i386 448@cindex @code{code32} directive, i386 449While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code, 450it also supports writing code to run in real mode or in 16-bit protected 451mode code segments. To do this, put a @samp{.code16} or 452@samp{.code16gcc} directive before the assembly language instructions to 453be run in 16-bit mode. You can switch @code{@value{AS}} back to writing 454normal 32-bit code with the @samp{.code32} directive. 455 456@samp{.code16gcc} provides experimental support for generating 16-bit 457code from gcc, and differs from @samp{.code16} in that @samp{call}, 458@samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop}, 459@samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions 460default to 32-bit size. This is so that the stack pointer is 461manipulated in the same way over function calls, allowing access to 462function parameters at the same stack offsets as in 32-bit mode. 463@samp{.code16gcc} also automatically adds address size prefixes where 464necessary to use the 32-bit addressing modes that gcc generates. 465 466The code which @code{@value{AS}} generates in 16-bit mode will not 467necessarily run on a 16-bit pre-80386 processor. To write code that 468runs on such a processor, you must refrain from using @emph{any} 32-bit 469constructs which require @code{@value{AS}} to output address or operand 470size prefixes. 471 472Note that writing 16-bit code instructions by explicitly specifying a 473prefix or an instruction mnemonic suffix within a 32-bit code section 474generates different machine instructions than those generated for a 47516-bit code segment. In a 32-bit code section, the following code 476generates the machine opcode bytes @samp{66 6a 04}, which pushes the 477value @samp{4} onto the stack, decrementing @samp{%esp} by 2. 478 479@smallexample 480 pushw $4 481@end smallexample 482 483The same code in a 16-bit code section would generate the machine 484opcode bytes @samp{6a 04} (ie. without the operand size prefix), which 485is correct since the processor default operand size is assumed to be 16 486bits in a 16-bit code section. 487 488@node i386-Bugs 489@section AT&T Syntax bugs 490 491The UnixWare assembler, and probably other AT&T derived ix86 Unix 492assemblers, generate floating point instructions with reversed source 493and destination registers in certain cases. Unfortunately, gcc and 494possibly many other programs use this reversed syntax, so we're stuck 495with it. 496 497For example 498 499@smallexample 500 fsub %st,%st(3) 501@end smallexample 502@noindent 503results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather 504than the expected @samp{%st(3) - %st}. This happens with all the 505non-commutative arithmetic floating point operations with two register 506operands where the source register is @samp{%st} and the destination 507register is @samp{%st(i)}. 508 509@node i386-Notes 510@section Notes 511 512@cindex i386 @code{mul}, @code{imul} instructions 513@cindex @code{mul} instruction, i386 514@cindex @code{imul} instruction, i386 515There is some trickery concerning the @samp{mul} and @samp{imul} 516instructions that deserves mention. The 16-, 32-, and 64-bit expanding 517multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5 518for @samp{imul}) can be output only in the one operand form. Thus, 519@samp{imul %ebx, %eax} does @emph{not} select the expanding multiply; 520the expanding multiply would clobber the @samp{%edx} register, and this 521would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the 52264-bit product in @samp{%edx:%eax}. 523 524We have added a two operand form of @samp{imul} when the first operand 525is an immediate mode expression and the second operand is a register. 526This is just a shorthand, so that, multiplying @samp{%eax} by 69, for 527example, can be done with @samp{imul $69, %eax} rather than @samp{imul 528$69, %eax, %eax}. 529 530