1218822Sdim@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 278828Sobrien@c Free Software Foundation, Inc. 360484Sobrien@c This is part of the GAS manual. 460484Sobrien@c For copying conditions, see the file as.texinfo. 560484Sobrien 660484Sobrien@ifset GENERIC 760484Sobrien@page 860484Sobrien@node ARM-Dependent 960484Sobrien@chapter ARM Dependent Features 1060484Sobrien@end ifset 1160484Sobrien 1260484Sobrien@ifclear GENERIC 1360484Sobrien@node Machine Dependencies 1460484Sobrien@chapter ARM Dependent Features 1560484Sobrien@end ifclear 1660484Sobrien 1760484Sobrien@cindex ARM support 1860484Sobrien@cindex Thumb support 1960484Sobrien@menu 2060484Sobrien* ARM Options:: Options 2160484Sobrien* ARM Syntax:: Syntax 2260484Sobrien* ARM Floating Point:: Floating Point 2360484Sobrien* ARM Directives:: ARM Machine Directives 2460484Sobrien* ARM Opcodes:: Opcodes 25130561Sobrien* ARM Mapping Symbols:: Mapping Symbols 2660484Sobrien@end menu 2760484Sobrien 2860484Sobrien@node ARM Options 2960484Sobrien@section Options 3060484Sobrien@cindex ARM options (none) 3160484Sobrien@cindex options for ARM (none) 3261843Sobrien 3360484Sobrien@table @code 3461843Sobrien 3589857Sobrien@cindex @code{-mcpu=} command line option, ARM 3689857Sobrien@item -mcpu=@var{processor}[+@var{extension}@dots{}] 3760484SobrienThis option specifies the target processor. The assembler will issue an 3860484Sobrienerror message if an attempt is made to assemble an instruction which 3989857Sobrienwill not execute on the target processor. The following processor names are 4089857Sobrienrecognized: 4189857Sobrien@code{arm1}, 4289857Sobrien@code{arm2}, 4389857Sobrien@code{arm250}, 4489857Sobrien@code{arm3}, 4589857Sobrien@code{arm6}, 4689857Sobrien@code{arm60}, 4789857Sobrien@code{arm600}, 4889857Sobrien@code{arm610}, 4989857Sobrien@code{arm620}, 5089857Sobrien@code{arm7}, 5189857Sobrien@code{arm7m}, 5289857Sobrien@code{arm7d}, 5389857Sobrien@code{arm7dm}, 5489857Sobrien@code{arm7di}, 5589857Sobrien@code{arm7dmi}, 5689857Sobrien@code{arm70}, 5789857Sobrien@code{arm700}, 5889857Sobrien@code{arm700i}, 5989857Sobrien@code{arm710}, 6089857Sobrien@code{arm710t}, 6189857Sobrien@code{arm720}, 6289857Sobrien@code{arm720t}, 6389857Sobrien@code{arm740t}, 6489857Sobrien@code{arm710c}, 6589857Sobrien@code{arm7100}, 6689857Sobrien@code{arm7500}, 6789857Sobrien@code{arm7500fe}, 6889857Sobrien@code{arm7t}, 6989857Sobrien@code{arm7tdmi}, 70218822Sdim@code{arm7tdmi-s}, 7189857Sobrien@code{arm8}, 7289857Sobrien@code{arm810}, 7389857Sobrien@code{strongarm}, 7489857Sobrien@code{strongarm1}, 7589857Sobrien@code{strongarm110}, 7689857Sobrien@code{strongarm1100}, 7789857Sobrien@code{strongarm1110}, 7889857Sobrien@code{arm9}, 7989857Sobrien@code{arm920}, 8089857Sobrien@code{arm920t}, 8189857Sobrien@code{arm922t}, 8289857Sobrien@code{arm940t}, 8389857Sobrien@code{arm9tdmi}, 8489857Sobrien@code{arm9e}, 85130561Sobrien@code{arm926e}, 86218822Sdim@code{arm926ej-s}, 8789857Sobrien@code{arm946e-r0}, 8889857Sobrien@code{arm946e}, 89218822Sdim@code{arm946e-s}, 9089857Sobrien@code{arm966e-r0}, 9189857Sobrien@code{arm966e}, 92218822Sdim@code{arm966e-s}, 93218822Sdim@code{arm968e-s}, 9489857Sobrien@code{arm10t}, 95218822Sdim@code{arm10tdmi}, 9689857Sobrien@code{arm10e}, 9789857Sobrien@code{arm1020}, 9889857Sobrien@code{arm1020t}, 99130561Sobrien@code{arm1020e}, 100218822Sdim@code{arm1022e}, 101218822Sdim@code{arm1026ej-s}, 102218822Sdim@code{arm1136j-s}, 103218822Sdim@code{arm1136jf-s}, 104218822Sdim@code{arm1156t2-s}, 105218822Sdim@code{arm1156t2f-s}, 106218822Sdim@code{arm1176jz-s}, 107218822Sdim@code{arm1176jzf-s}, 108218822Sdim@code{mpcore}, 109218822Sdim@code{mpcorenovfp}, 110218822Sdim@code{cortex-a8}, 111218822Sdim@code{cortex-r4}, 112218822Sdim@code{cortex-m3}, 11389857Sobrien@code{ep9312} (ARM920 with Cirrus Maverick coprocessor), 11489857Sobrien@code{i80200} (Intel XScale processor) 115130561Sobrien@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) 11689857Sobrienand 11789857Sobrien@code{xscale}. 11889857SobrienThe special name @code{all} may be used to allow the 11989857Sobrienassembler to accept instructions valid for any ARM processor. 12061843Sobrien 12189857SobrienIn addition to the basic instruction set, the assembler can be told to 12289857Sobrienaccept various extension mnemonics that extend the processor using the 12389857Sobrienco-processor instruction space. For example, @code{-mcpu=arm920+maverick} 12489857Sobrienis equivalent to specifying @code{-mcpu=ep9312}. The following extensions 12589857Sobrienare currently supported: 12689857Sobrien@code{+maverick} 127130561Sobrien@code{+iwmmxt} 12889857Sobrienand 12989857Sobrien@code{+xscale}. 13089857Sobrien 13189857Sobrien@cindex @code{-march=} command line option, ARM 13289857Sobrien@item -march=@var{architecture}[+@var{extension}@dots{}] 13360484SobrienThis option specifies the target architecture. The assembler will issue 13460484Sobrienan error message if an attempt is made to assemble an instruction which 13589857Sobrienwill not execute on the target architecture. The following architecture 13689857Sobriennames are recognized: 13789857Sobrien@code{armv1}, 13889857Sobrien@code{armv2}, 13989857Sobrien@code{armv2a}, 14089857Sobrien@code{armv2s}, 14189857Sobrien@code{armv3}, 14289857Sobrien@code{armv3m}, 14389857Sobrien@code{armv4}, 14489857Sobrien@code{armv4xm}, 14589857Sobrien@code{armv4t}, 14689857Sobrien@code{armv4txm}, 14789857Sobrien@code{armv5}, 14889857Sobrien@code{armv5t}, 14989857Sobrien@code{armv5txm}, 15089857Sobrien@code{armv5te}, 151130561Sobrien@code{armv5texp}, 152130561Sobrien@code{armv6}, 153130561Sobrien@code{armv6j}, 154218822Sdim@code{armv6k}, 155218822Sdim@code{armv6z}, 156218822Sdim@code{armv6zk}, 157218822Sdim@code{armv7}, 158218822Sdim@code{armv7-a}, 159218822Sdim@code{armv7-r}, 160218822Sdim@code{armv7-m}, 161130561Sobrien@code{iwmmxt} 16289857Sobrienand 16389857Sobrien@code{xscale}. 16489857SobrienIf both @code{-mcpu} and 16589857Sobrien@code{-march} are specified, the assembler will use 16689857Sobrienthe setting for @code{-mcpu}. 16761843Sobrien 16889857SobrienThe architecture option can be extended with the same instruction set 16989857Sobrienextension options as the @code{-mcpu} option. 17061843Sobrien 17189857Sobrien@cindex @code{-mfpu=} command line option, ARM 17289857Sobrien@item -mfpu=@var{floating-point-format} 17361843Sobrien 17489857SobrienThis option specifies the floating point format to assemble for. The 17589857Sobrienassembler will issue an error message if an attempt is made to assemble 17689857Sobrienan instruction which will not execute on the target floating point unit. 17789857SobrienThe following format options are recognized: 17889857Sobrien@code{softfpa}, 17989857Sobrien@code{fpe}, 18089857Sobrien@code{fpe2}, 18189857Sobrien@code{fpe3}, 18289857Sobrien@code{fpa}, 18389857Sobrien@code{fpa10}, 18489857Sobrien@code{fpa11}, 18589857Sobrien@code{arm7500fe}, 18689857Sobrien@code{softvfp}, 18789857Sobrien@code{softvfp+vfp}, 18889857Sobrien@code{vfp}, 18989857Sobrien@code{vfp10}, 19089857Sobrien@code{vfp10-r0}, 19189857Sobrien@code{vfp9}, 19289857Sobrien@code{vfpxd}, 193130561Sobrien@code{arm1020t}, 194130561Sobrien@code{arm1020e}, 195218822Sdim@code{arm1136jf-s} 19689857Sobrienand 197130561Sobrien@code{maverick}. 19861843Sobrien 19989857SobrienIn addition to determining which instructions are assembled, this option 20089857Sobrienalso affects the way in which the @code{.double} assembler directive behaves 20189857Sobrienwhen assembling little-endian code. 20261843Sobrien 20389857SobrienThe default is dependent on the processor selected. For Architecture 5 or 20489857Sobrienlater, the default is to assembler for VFP instructions; for earlier 20589857Sobrienarchitectures the default is to assemble for FPA instructions. 20661843Sobrien 20789857Sobrien@cindex @code{-mthumb} command line option, ARM 20889857Sobrien@item -mthumb 20989857SobrienThis option specifies that the assembler should start assembling Thumb 21089857Sobrieninstructions; that is, it should behave as though the file starts with a 21189857Sobrien@code{.code 16} directive. 21289857Sobrien 21360484Sobrien@cindex @code{-mthumb-interwork} command line option, ARM 21460484Sobrien@item -mthumb-interwork 21560484SobrienThis option specifies that the output generated by the assembler should 21660484Sobrienbe marked as supporting interworking. 21761843Sobrien 21860484Sobrien@cindex @code{-mapcs} command line option, ARM 21977298Sobrien@item -mapcs @code{[26|32]} 22060484SobrienThis option specifies that the output generated by the assembler should 22160484Sobrienbe marked as supporting the indicated version of the Arm Procedure. 22260484SobrienCalling Standard. 22361843Sobrien 22477298Sobrien@cindex @code{-matpcs} command line option, ARM 22577298Sobrien@item -matpcs 22677298SobrienThis option specifies that the output generated by the assembler should 22777298Sobrienbe marked as supporting the Arm/Thumb Procedure Calling Standard. If 22877298Sobrienenabled this option will cause the assembler to create an empty 22977298Sobriendebugging section in the object file called .arm.atpcs. Debuggers can 23077298Sobrienuse this to determine the ABI being used by. 23177298Sobrien 23261843Sobrien@cindex @code{-mapcs-float} command line option, ARM 23360484Sobrien@item -mapcs-float 234130561SobrienThis indicates the floating point variant of the APCS should be 23560484Sobrienused. In this variant floating point arguments are passed in FP 23660484Sobrienregisters rather than integer registers. 23761843Sobrien 23861843Sobrien@cindex @code{-mapcs-reentrant} command line option, ARM 23960484Sobrien@item -mapcs-reentrant 24060484SobrienThis indicates that the reentrant variant of the APCS should be used. 24160484SobrienThis variant supports position independent code. 24261843Sobrien 243130561Sobrien@cindex @code{-mfloat-abi=} command line option, ARM 244130561Sobrien@item -mfloat-abi=@var{abi} 245130561SobrienThis option specifies that the output generated by the assembler should be 246130561Sobrienmarked as using specified floating point ABI. 247130561SobrienThe following values are recognized: 248130561Sobrien@code{soft}, 249130561Sobrien@code{softfp} 250130561Sobrienand 251130561Sobrien@code{hard}. 252130561Sobrien 253218822Sdim@cindex @code{-eabi=} command line option, ARM 254218822Sdim@item -meabi=@var{ver} 255218822SdimThis option specifies which EABI version the produced object files should 256218822Sdimconform to. 257218822SdimThe following values are recognized: 258218822Sdim@code{gnu}, 259218822Sdim@code{4} 260218822Sdimand 261218822Sdim@code{5}. 262218822Sdim 26360484Sobrien@cindex @code{-EB} command line option, ARM 26460484Sobrien@item -EB 26560484SobrienThis option specifies that the output generated by the assembler should 26660484Sobrienbe marked as being encoded for a big-endian processor. 26761843Sobrien 26860484Sobrien@cindex @code{-EL} command line option, ARM 26960484Sobrien@item -EL 27060484SobrienThis option specifies that the output generated by the assembler should 27160484Sobrienbe marked as being encoded for a little-endian processor. 27261843Sobrien 27360484Sobrien@cindex @code{-k} command line option, ARM 27460484Sobrien@cindex PIC code generation for ARM 27560484Sobrien@item -k 27677298SobrienThis option specifies that the output of the assembler should be marked 27777298Sobrienas position-independent code (PIC). 27861843Sobrien 27960484Sobrien@end table 28060484Sobrien 28160484Sobrien 28260484Sobrien@node ARM Syntax 28360484Sobrien@section Syntax 28460484Sobrien@menu 28560484Sobrien* ARM-Chars:: Special Characters 28660484Sobrien* ARM-Regs:: Register Names 287218822Sdim* ARM-Relocations:: Relocations 28860484Sobrien@end menu 28960484Sobrien 29060484Sobrien@node ARM-Chars 29160484Sobrien@subsection Special Characters 29260484Sobrien 29360484Sobrien@cindex line comment character, ARM 29460484Sobrien@cindex ARM line comment character 29560484SobrienThe presence of a @samp{@@} on a line indicates the start of a comment 29660484Sobrienthat extends to the end of the current line. If a @samp{#} appears as 29760484Sobrienthe first character of a line, the whole line is treated as a comment. 29860484Sobrien 29960484Sobrien@cindex line separator, ARM 30060484Sobrien@cindex statement separator, ARM 30160484Sobrien@cindex ARM line separator 30277298SobrienThe @samp{;} character can be used instead of a newline to separate 30377298Sobrienstatements. 30460484Sobrien 30560484Sobrien@cindex immediate character, ARM 30660484Sobrien@cindex ARM immediate character 30760484SobrienEither @samp{#} or @samp{$} can be used to indicate immediate operands. 30860484Sobrien 30960484Sobrien@cindex identifiers, ARM 31060484Sobrien@cindex ARM identifiers 31160484Sobrien*TODO* Explain about /data modifier on symbols. 31260484Sobrien 31360484Sobrien@node ARM-Regs 31460484Sobrien@subsection Register Names 31560484Sobrien 31660484Sobrien@cindex ARM register names 31760484Sobrien@cindex register names, ARM 31860484Sobrien*TODO* Explain about ARM register naming, and the predefined names. 31960484Sobrien 32060484Sobrien@node ARM Floating Point 32160484Sobrien@section Floating Point 32260484Sobrien 32360484Sobrien@cindex floating point, ARM (@sc{ieee}) 32460484Sobrien@cindex ARM floating point (@sc{ieee}) 32560484SobrienThe ARM family uses @sc{ieee} floating-point numbers. 32660484Sobrien 327218822Sdim@node ARM-Relocations 328218822Sdim@subsection ARM relocation generation 32960484Sobrien 330218822Sdim@cindex data relocations, ARM 331218822Sdim@cindex ARM data relocations 332218822SdimSpecific data relocations can be generated by putting the relocation name 333218822Sdimin parentheses after the symbol name. For example: 33460484Sobrien 335218822Sdim@smallexample 336218822Sdim .word foo(TARGET1) 337218822Sdim@end smallexample 338218822Sdim 339218822SdimThis will generate an @samp{R_ARM_TARGET1} relocation against the symbol 340218822Sdim@var{foo}. 341218822SdimThe following relocations are supported: 342218822Sdim@code{GOT}, 343218822Sdim@code{GOTOFF}, 344218822Sdim@code{TARGET1}, 345218822Sdim@code{TARGET2}, 346218822Sdim@code{SBREL}, 347218822Sdim@code{TLSGD}, 348218822Sdim@code{TLSLDM}, 349218822Sdim@code{TLSLDO}, 350218822Sdim@code{GOTTPOFF} 351218822Sdimand 352218822Sdim@code{TPOFF}. 353218822Sdim 354218822SdimFor compatibility with older toolchains the assembler also accepts 355218822Sdim@code{(PLT)} after branch targets. This will generate the deprecated 356218822Sdim@samp{R_ARM_PLT32} relocation. 357218822Sdim 358218822Sdim@cindex MOVW and MOVT relocations, ARM 359218822SdimRelocations for @samp{MOVW} and @samp{MOVT} instructions can be generated 360218822Sdimby prefixing the value with @samp{#:lower16:} and @samp{#:upper16} 361218822Sdimrespectively. For example to load the 32-bit address of foo into r0: 362218822Sdim 363218822Sdim@smallexample 364218822Sdim MOVW r0, #:lower16:foo 365218822Sdim MOVT r0, #:upper16:foo 366218822Sdim@end smallexample 367218822Sdim 36860484Sobrien@node ARM Directives 36960484Sobrien@section ARM Machine Directives 37060484Sobrien 37160484Sobrien@cindex machine directives, ARM 37260484Sobrien@cindex ARM machine directives 37360484Sobrien@table @code 37460484Sobrien 37561843Sobrien@cindex @code{align} directive, ARM 37661843Sobrien@item .align @var{expression} [, @var{expression}] 37761843SobrienThis is the generic @var{.align} directive. For the ARM however if the 37861843Sobrienfirst argument is zero (ie no alignment is needed) the assembler will 37961843Sobrienbehave as if the argument had been 2 (ie pad to the next four byte 380130561Sobrienboundary). This is for compatibility with ARM's own assembler. 38161843Sobrien 38260484Sobrien@cindex @code{req} directive, ARM 38360484Sobrien@item @var{name} .req @var{register name} 38460484SobrienThis creates an alias for @var{register name} called @var{name}. For 38560484Sobrienexample: 38660484Sobrien 38760484Sobrien@smallexample 38860484Sobrien foo .req r0 38960484Sobrien@end smallexample 39060484Sobrien 391130561Sobrien@cindex @code{unreq} directive, ARM 392130561Sobrien@item .unreq @var{alias-name} 393130561SobrienThis undefines a register alias which was previously defined using the 394218822Sdim@code{req}, @code{dn} or @code{qn} directives. For example: 395130561Sobrien 396130561Sobrien@smallexample 397130561Sobrien foo .req r0 398130561Sobrien .unreq foo 399130561Sobrien@end smallexample 400130561Sobrien 401130561SobrienAn error occurs if the name is undefined. Note - this pseudo op can 402130561Sobrienbe used to delete builtin in register name aliases (eg 'r0'). This 403130561Sobrienshould only be done if it is really necessary. 404130561Sobrien 405218822Sdim@cindex @code{dn} and @code{qn} directives, ARM 406218822Sdim@item @var{name} .dn @var{register name} [@var{.type}] [@var{[index]}] 407218822Sdim@item @var{name} .qn @var{register name} [@var{.type}] [@var{[index]}] 408218822Sdim 409218822SdimThe @code{dn} and @code{qn} directives are used to create typed 410218822Sdimand/or indexed register aliases for use in Advanced SIMD Extension 411218822Sdim(Neon) instructions. The former should be used to create aliases 412218822Sdimof double-precision registers, and the latter to create aliases of 413218822Sdimquad-precision registers. 414218822Sdim 415218822SdimIf these directives are used to create typed aliases, those aliases can 416218822Sdimbe used in Neon instructions instead of writing types after the mnemonic 417218822Sdimor after each operand. For example: 418218822Sdim 419218822Sdim@smallexample 420218822Sdim x .dn d2.f32 421218822Sdim y .dn d3.f32 422218822Sdim z .dn d4.f32[1] 423218822Sdim vmul x,y,z 424218822Sdim@end smallexample 425218822Sdim 426218822SdimThis is equivalent to writing the following: 427218822Sdim 428218822Sdim@smallexample 429218822Sdim vmul.f32 d2,d3,d4[1] 430218822Sdim@end smallexample 431218822Sdim 432218822SdimAliases created using @code{dn} or @code{qn} can be destroyed using 433218822Sdim@code{unreq}. 434218822Sdim 43560484Sobrien@cindex @code{code} directive, ARM 43677298Sobrien@item .code @code{[16|32]} 43760484SobrienThis directive selects the instruction set being generated. The value 16 43860484Sobrienselects Thumb, with the value 32 selecting ARM. 43960484Sobrien 44060484Sobrien@cindex @code{thumb} directive, ARM 44160484Sobrien@item .thumb 44260484SobrienThis performs the same action as @var{.code 16}. 44360484Sobrien 44460484Sobrien@cindex @code{arm} directive, ARM 44560484Sobrien@item .arm 44660484SobrienThis performs the same action as @var{.code 32}. 44760484Sobrien 44860484Sobrien@cindex @code{force_thumb} directive, ARM 44960484Sobrien@item .force_thumb 45060484SobrienThis directive forces the selection of Thumb instructions, even if the 45160484Sobrientarget processor does not support those instructions 45260484Sobrien 45360484Sobrien@cindex @code{thumb_func} directive, ARM 45460484Sobrien@item .thumb_func 45560484SobrienThis directive specifies that the following symbol is the name of a 45660484SobrienThumb encoded function. This information is necessary in order to allow 45760484Sobrienthe assembler and linker to generate correct code for interworking 45860484Sobrienbetween Arm and Thumb instructions and should be used even if 45977298Sobrieninterworking is not going to be performed. The presence of this 46077298Sobriendirective also implies @code{.thumb} 46160484Sobrien 462218822SdimThis directive is not neccessary when generating EABI objects. On these 463218822Sdimtargets the encoding is implicit when generating Thumb code. 464218822Sdim 46560484Sobrien@cindex @code{thumb_set} directive, ARM 46660484Sobrien@item .thumb_set 46760484SobrienThis performs the equivalent of a @code{.set} directive in that it 46860484Sobriencreates a symbol which is an alias for another symbol (possibly not yet 46960484Sobriendefined). This directive also has the added property in that it marks 47060484Sobrienthe aliased symbol as being a thumb function entry point, in the same 47160484Sobrienway that the @code{.thumb_func} directive does. 47260484Sobrien 47360484Sobrien@cindex @code{.ltorg} directive, ARM 47460484Sobrien@item .ltorg 47560484SobrienThis directive causes the current contents of the literal pool to be 47660484Sobriendumped into the current section (which is assumed to be the .text 47760484Sobriensection) at the current location (aligned to a word boundary). 478130561Sobrien@code{GAS} maintains a separate literal pool for each section and each 479130561Sobriensub-section. The @code{.ltorg} directive will only affect the literal 480130561Sobrienpool of the current section and sub-section. At the end of assembly 481130561Sobrienall remaining, un-empty literal pools will automatically be dumped. 48260484Sobrien 483130561SobrienNote - older versions of @code{GAS} would dump the current literal 484130561Sobrienpool any time a section change occurred. This is no longer done, since 485130561Sobrienit prevents accurate control of the placement of literal pools. 486130561Sobrien 48760484Sobrien@cindex @code{.pool} directive, ARM 48860484Sobrien@item .pool 48960484SobrienThis is a synonym for .ltorg. 49060484Sobrien 491218822Sdim@cindex @code{.fnstart} directive, ARM 492218822Sdim@item .unwind_fnstart 493218822SdimMarks the start of a function with an unwind table entry. 494218822Sdim 495218822Sdim@cindex @code{.fnend} directive, ARM 496218822Sdim@item .unwind_fnend 497218822SdimMarks the end of a function with an unwind table entry. The unwind index 498218822Sdimtable entry is created when this directive is processed. 499218822Sdim 500218822SdimIf no personality routine has been specified then standard personality 501218822Sdimroutine 0 or 1 will be used, depending on the number of unwind opcodes 502218822Sdimrequired. 503218822Sdim 504218822Sdim@cindex @code{.cantunwind} directive, ARM 505218822Sdim@item .cantunwind 506218822SdimPrevents unwinding through the current function. No personality routine 507218822Sdimor exception table data is required or permitted. 508218822Sdim 509218822Sdim@cindex @code{.personality} directive, ARM 510218822Sdim@item .personality @var{name} 511218822SdimSets the personality routine for the current function to @var{name}. 512218822Sdim 513218822Sdim@cindex @code{.personalityindex} directive, ARM 514218822Sdim@item .personalityindex @var{index} 515218822SdimSets the personality routine for the current function to the EABI standard 516218822Sdimroutine number @var{index} 517218822Sdim 518218822Sdim@cindex @code{.handlerdata} directive, ARM 519218822Sdim@item .handlerdata 520218822SdimMarks the end of the current function, and the start of the exception table 521218822Sdimentry for that function. Anything between this directive and the 522218822Sdim@code{.fnend} directive will be added to the exception table entry. 523218822Sdim 524218822SdimMust be preceded by a @code{.personality} or @code{.personalityindex} 525218822Sdimdirective. 526218822Sdim 527218822Sdim@cindex @code{.save} directive, ARM 528218822Sdim@item .save @var{reglist} 529218822SdimGenerate unwinder annotations to restore the registers in @var{reglist}. 530218822SdimThe format of @var{reglist} is the same as the corresponding store-multiple 531218822Sdiminstruction. 532218822Sdim 533218822Sdim@smallexample 534218822Sdim@exdent @emph{core registers} 535218822Sdim .save @{r4, r5, r6, lr@} 536218822Sdim stmfd sp!, @{r4, r5, r6, lr@} 537218822Sdim@exdent @emph{FPA registers} 538218822Sdim .save f4, 2 539218822Sdim sfmfd f4, 2, [sp]! 540218822Sdim@exdent @emph{VFP registers} 541218822Sdim .save @{d8, d9, d10@} 542218822Sdim fstmdx sp!, @{d8, d9, d10@} 543218822Sdim@exdent @emph{iWMMXt registers} 544218822Sdim .save @{wr10, wr11@} 545218822Sdim wstrd wr11, [sp, #-8]! 546218822Sdim wstrd wr10, [sp, #-8]! 547218822Sdimor 548218822Sdim .save wr11 549218822Sdim wstrd wr11, [sp, #-8]! 550218822Sdim .save wr10 551218822Sdim wstrd wr10, [sp, #-8]! 552218822Sdim@end smallexample 553218822Sdim 554218822Sdim@cindex @code{.vsave} directive, ARM 555218822Sdim@item .vsave @var{vfp-reglist} 556218822SdimGenerate unwinder annotations to restore the VFP registers in @var{vfp-reglist} 557218822Sdimusing FLDMD. Also works for VFPv3 registers 558218822Sdimthat are to be restored using VLDM. 559218822SdimThe format of @var{vfp-reglist} is the same as the corresponding store-multiple 560218822Sdiminstruction. 561218822Sdim 562218822Sdim@smallexample 563218822Sdim@exdent @emph{VFP registers} 564218822Sdim .vsave @{d8, d9, d10@} 565218822Sdim fstmdd sp!, @{d8, d9, d10@} 566218822Sdim@exdent @emph{VFPv3 registers} 567218822Sdim .vsave @{d15, d16, d17@} 568218822Sdim vstm sp!, @{d15, d16, d17@} 569218822Sdim@end smallexample 570218822Sdim 571218822SdimSince FLDMX and FSTMX are now deprecated, this directive should be 572218822Sdimused in favour of @code{.save} for saving VFP registers for ARMv6 and above. 573218822Sdim 574218822Sdim@cindex @code{.pad} directive, ARM 575218822Sdim@item .pad #@var{count} 576218822SdimGenerate unwinder annotations for a stack adjustment of @var{count} bytes. 577218822SdimA positive value indicates the function prologue allocated stack space by 578218822Sdimdecrementing the stack pointer. 579218822Sdim 580218822Sdim@cindex @code{.movsp} directive, ARM 581218822Sdim@item .movsp @var{reg} [, #@var{offset}] 582218822SdimTell the unwinder that @var{reg} contains an offset from the current 583218822Sdimstack pointer. If @var{offset} is not specified then it is assumed to be 584218822Sdimzero. 585218822Sdim 586218822Sdim@cindex @code{.setfp} directive, ARM 587218822Sdim@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}] 588218822SdimMake all unwinder annotations relaive to a frame pointer. Without this 589218822Sdimthe unwinder will use offsets from the stack pointer. 590218822Sdim 591218822SdimThe syntax of this directive is the same as the @code{sub} or @code{mov} 592218822Sdiminstruction used to set the frame pointer. @var{spreg} must be either 593218822Sdim@code{sp} or mentioned in a previous @code{.movsp} directive. 594218822Sdim 595218822Sdim@smallexample 596218822Sdim.movsp ip 597218822Sdimmov ip, sp 598218822Sdim@dots{} 599218822Sdim.setfp fp, ip, #4 600218822Sdimsub fp, ip, #4 601218822Sdim@end smallexample 602218822Sdim 603218822Sdim@cindex @code{.unwind_raw} directive, ARM 604218822Sdim@item .raw @var{offset}, @var{byte1}, @dots{} 605218822SdimInsert one of more arbitary unwind opcode bytes, which are known to adjust 606218822Sdimthe stack pointer by @var{offset} bytes. 607218822Sdim 608218822SdimFor example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to 609218822Sdim@code{.save @{r0@}} 610218822Sdim 611218822Sdim@cindex @code{.cpu} directive, ARM 612218822Sdim@item .cpu @var{name} 613218822SdimSelect the target processor. Valid values for @var{name} are the same as 614218822Sdimfor the @option{-mcpu} commandline option. 615218822Sdim 616218822Sdim@cindex @code{.arch} directive, ARM 617218822Sdim@item .arch @var{name} 618218822SdimSelect the target architecture. Valid values for @var{name} are the same as 619218822Sdimfor the @option{-march} commandline option. 620218822Sdim 621218822Sdim@cindex @code{.object_arch} directive, ARM 622218822Sdim@item .object_arch @var{name} 623218822SdimOverride the architecture recorded in the EABI object attribute section. 624218822SdimValid values for @var{name} are the same as for the @code{.arch} directive. 625218822SdimTypically this is useful when code uses runtime detection of CPU features. 626218822Sdim 627218822Sdim@cindex @code{.fpu} directive, ARM 628218822Sdim@item .fpu @var{name} 629218822SdimSelect the floating point unit to assemble for. Valid values for @var{name} 630218822Sdimare the same as for the @option{-mfpu} commandline option. 631218822Sdim 632218822Sdim@cindex @code{.eabi_attribute} directive, ARM 633218822Sdim@item .eabi_attribute @var{tag}, @var{value} 634218822SdimSet the EABI object attribute number @var{tag} to @var{value}. The value 635218822Sdimis either a @code{number}, @code{"string"}, or @code{number, "string"} 636218822Sdimdepending on the tag. 637218822Sdim 63860484Sobrien@end table 63960484Sobrien 64060484Sobrien@node ARM Opcodes 64160484Sobrien@section Opcodes 64260484Sobrien 64360484Sobrien@cindex ARM opcodes 64460484Sobrien@cindex opcodes for ARM 64560484Sobrien@code{@value{AS}} implements all the standard ARM opcodes. It also 64660484Sobrienimplements several pseudo opcodes, including several synthetic load 64760484Sobrieninstructions. 64860484Sobrien 64960484Sobrien@table @code 65060484Sobrien 65160484Sobrien@cindex @code{NOP} pseudo op, ARM 65260484Sobrien@item NOP 65360484Sobrien@smallexample 65460484Sobrien nop 65560484Sobrien@end smallexample 65660484Sobrien 65760484SobrienThis pseudo op will always evaluate to a legal ARM instruction that does 65860484Sobriennothing. Currently it will evaluate to MOV r0, r0. 65960484Sobrien 66060484Sobrien@cindex @code{LDR reg,=<label>} pseudo op, ARM 66160484Sobrien@item LDR 66260484Sobrien@smallexample 66360484Sobrien ldr <register> , = <expression> 66460484Sobrien@end smallexample 66560484Sobrien 66660484SobrienIf expression evaluates to a numeric constant then a MOV or MVN 66760484Sobrieninstruction will be used in place of the LDR instruction, if the 66860484Sobrienconstant can be generated by either of these instructions. Otherwise 66960484Sobrienthe constant will be placed into the nearest literal pool (if it not 67060484Sobrienalready there) and a PC relative LDR instruction will be generated. 67160484Sobrien 67260484Sobrien@cindex @code{ADR reg,<label>} pseudo op, ARM 67360484Sobrien@item ADR 67460484Sobrien@smallexample 67560484Sobrien adr <register> <label> 67660484Sobrien@end smallexample 67760484Sobrien 67860484SobrienThis instruction will load the address of @var{label} into the indicated 67960484Sobrienregister. The instruction will evaluate to a PC relative ADD or SUB 68060484Sobrieninstruction depending upon where the label is located. If the label is 68160484Sobrienout of range, or if it is not defined in the same file (and section) as 68260484Sobrienthe ADR instruction, then an error will be generated. This instruction 68360484Sobrienwill not make use of the literal pool. 68460484Sobrien 68560484Sobrien@cindex @code{ADRL reg,<label>} pseudo op, ARM 68660484Sobrien@item ADRL 68760484Sobrien@smallexample 68860484Sobrien adrl <register> <label> 68960484Sobrien@end smallexample 69060484Sobrien 69160484SobrienThis instruction will load the address of @var{label} into the indicated 69277298Sobrienregister. The instruction will evaluate to one or two PC relative ADD 69360484Sobrienor SUB instructions depending upon where the label is located. If a 69460484Sobriensecond instruction is not needed a NOP instruction will be generated in 69560484Sobrienits place, so that this instruction is always 8 bytes long. 69660484Sobrien 69760484SobrienIf the label is out of range, or if it is not defined in the same file 69860484Sobrien(and section) as the ADRL instruction, then an error will be generated. 69960484SobrienThis instruction will not make use of the literal pool. 70060484Sobrien 70160484Sobrien@end table 70260484Sobrien 70360484SobrienFor information on the ARM or Thumb instruction sets, see @cite{ARM 70460484SobrienSoftware Development Toolkit Reference Manual}, Advanced RISC Machines 70560484SobrienLtd. 70660484Sobrien 707130561Sobrien@node ARM Mapping Symbols 708130561Sobrien@section Mapping Symbols 709130561Sobrien 710130561SobrienThe ARM ELF specification requires that special symbols be inserted 711130561Sobrieninto object files to mark certain features: 712130561Sobrien 713130561Sobrien@table @code 714130561Sobrien 715130561Sobrien@cindex @code{$a} 716130561Sobrien@item $a 717130561SobrienAt the start of a region of code containing ARM instructions. 718130561Sobrien 719130561Sobrien@cindex @code{$t} 720130561Sobrien@item $t 721130561SobrienAt the start of a region of code containing THUMB instructions. 722130561Sobrien 723130561Sobrien@cindex @code{$d} 724130561Sobrien@item $d 725130561SobrienAt the start of a region of data. 726130561Sobrien 727130561Sobrien@end table 728130561Sobrien 729130561SobrienThe assembler will automatically insert these symbols for you - there 730130561Sobrienis no need to code them yourself. Support for tagging symbols ($b, 731130561Sobrien$f, $p and $m) which is also mentioned in the current ARM ELF 732130561Sobrienspecification is not implemented. This is because they have been 733130561Sobriendropped from the new EABI and so tools cannot rely upon their 734130561Sobrienpresence. 735130561Sobrien 736