cap.c revision 173059
1166435Sjhb/*- 2166435Sjhb * Copyright (c) 2007 John Baldwin <jhb@FreeBSD.org> 3166435Sjhb * All rights reserved. 4166435Sjhb * 5166435Sjhb * Redistribution and use in source and binary forms, with or without 6166435Sjhb * modification, are permitted provided that the following conditions 7166435Sjhb * are met: 8166435Sjhb * 1. Redistributions of source code must retain the above copyright 9166435Sjhb * notice, this list of conditions and the following disclaimer. 10166435Sjhb * 2. Redistributions in binary form must reproduce the above copyright 11166435Sjhb * notice, this list of conditions and the following disclaimer in the 12166435Sjhb * documentation and/or other materials provided with the distribution. 13166435Sjhb * 3. Neither the name of the author nor the names of any co-contributors 14166435Sjhb * may be used to endorse or promote products derived from this software 15166435Sjhb * without specific prior written permission. 16166435Sjhb * 17166435Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18166435Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19166435Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20166435Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21166435Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22166435Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23166435Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24166435Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25166435Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26166435Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27166435Sjhb * SUCH DAMAGE. 28166435Sjhb */ 29166435Sjhb 30166435Sjhb#ifndef lint 31166435Sjhbstatic const char rcsid[] = 32166435Sjhb "$FreeBSD: head/usr.sbin/pciconf/cap.c 173059 2007-10-27 13:16:25Z jhb $"; 33166435Sjhb#endif /* not lint */ 34166435Sjhb 35166435Sjhb#include <sys/types.h> 36166435Sjhb 37166435Sjhb#include <err.h> 38166435Sjhb#include <stdio.h> 39166435Sjhb#include <sys/agpio.h> 40166435Sjhb#include <sys/pciio.h> 41166435Sjhb 42166435Sjhb#include <pci/agpreg.h> 43166435Sjhb#include <dev/pci/pcireg.h> 44166435Sjhb 45166435Sjhb#include "pciconf.h" 46166435Sjhb 47166435Sjhbstatic void 48166435Sjhbcap_power(int fd, struct pci_conf *p, uint8_t ptr) 49166435Sjhb{ 50166435Sjhb uint16_t cap, status; 51166435Sjhb 52166435Sjhb cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 53166435Sjhb status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 54166435Sjhb printf("powerspec %d supports D0%s%s D3 current D%d", 55166435Sjhb cap & PCIM_PCAP_SPEC, 56166435Sjhb cap & PCIM_PCAP_D1SUPP ? " D1" : "", 57166435Sjhb cap & PCIM_PCAP_D2SUPP ? " D2" : "", 58166435Sjhb status & PCIM_PSTAT_DMASK); 59166435Sjhb} 60166435Sjhb 61166435Sjhbstatic void 62166435Sjhbcap_agp(int fd, struct pci_conf *p, uint8_t ptr) 63166435Sjhb{ 64166435Sjhb uint32_t status, command; 65166435Sjhb 66166435Sjhb status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 67166435Sjhb command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 68166435Sjhb printf("AGP "); 69166435Sjhb if (AGP_MODE_GET_MODE_3(status)) { 70166435Sjhb printf("v3 "); 71166435Sjhb if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 72166435Sjhb printf("8x "); 73166435Sjhb if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 74166435Sjhb printf("4x "); 75166435Sjhb } else { 76166435Sjhb if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 77166435Sjhb printf("4x "); 78166435Sjhb if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 79166435Sjhb printf("2x "); 80166435Sjhb if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 81166435Sjhb printf("1x "); 82166435Sjhb } 83166435Sjhb if (AGP_MODE_GET_SBA(status)) 84166435Sjhb printf("SBA "); 85166435Sjhb if (AGP_MODE_GET_AGP(command)) { 86166435Sjhb printf("enabled at "); 87166435Sjhb if (AGP_MODE_GET_MODE_3(command)) { 88166435Sjhb printf("v3 "); 89166435Sjhb switch (AGP_MODE_GET_RATE(command)) { 90166435Sjhb case AGP_MODE_V3_RATE_8x: 91166435Sjhb printf("8x "); 92166435Sjhb break; 93166435Sjhb case AGP_MODE_V3_RATE_4x: 94166435Sjhb printf("4x "); 95166435Sjhb break; 96166435Sjhb } 97166435Sjhb } else 98166435Sjhb switch (AGP_MODE_GET_RATE(command)) { 99166435Sjhb case AGP_MODE_V2_RATE_4x: 100166435Sjhb printf("4x "); 101166435Sjhb break; 102166435Sjhb case AGP_MODE_V2_RATE_2x: 103166435Sjhb printf("2x "); 104166435Sjhb break; 105166435Sjhb case AGP_MODE_V2_RATE_1x: 106166435Sjhb printf("1x "); 107166435Sjhb break; 108166435Sjhb } 109166435Sjhb if (AGP_MODE_GET_SBA(command)) 110166435Sjhb printf("SBA "); 111166435Sjhb } else 112166435Sjhb printf("disabled"); 113166435Sjhb} 114166435Sjhb 115166435Sjhbstatic void 116166435Sjhbcap_vpd(int fd, struct pci_conf *p, uint8_t ptr) 117166435Sjhb{ 118166435Sjhb 119166435Sjhb printf("VPD"); 120166435Sjhb} 121166435Sjhb 122166435Sjhbstatic void 123166435Sjhbcap_msi(int fd, struct pci_conf *p, uint8_t ptr) 124166435Sjhb{ 125166435Sjhb uint16_t ctrl; 126166435Sjhb int msgnum; 127166435Sjhb 128166435Sjhb ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 129166435Sjhb msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 130166435Sjhb printf("MSI supports %d message%s%s%s ", msgnum, 131166435Sjhb (msgnum == 1) ? "" : "s", 132166435Sjhb (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 133166435Sjhb (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 134166435Sjhb if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 135166435Sjhb msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 136166435Sjhb printf("enabled with %d message%s", msgnum, 137166435Sjhb (msgnum == 1) ? "" : "s"); 138166435Sjhb } 139166435Sjhb} 140166435Sjhb 141166435Sjhbstatic void 142166435Sjhbcap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 143166435Sjhb{ 144166435Sjhb uint32_t status; 145166435Sjhb int comma, max_splits, max_burst_read; 146166435Sjhb 147166435Sjhb status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 148166435Sjhb printf("PCI-X "); 149166435Sjhb if (status & PCIXM_STATUS_64BIT) 150166435Sjhb printf("64-bit "); 151166435Sjhb if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 152166435Sjhb printf("bridge "); 153166435Sjhb printf("supports"); 154166435Sjhb comma = 0; 155166435Sjhb if (status & PCIXM_STATUS_133CAP) { 156166435Sjhb printf("%s 133MHz", comma ? "," : ""); 157166435Sjhb comma = 1; 158166435Sjhb } 159166435Sjhb if (status & PCIXM_STATUS_266CAP) { 160166435Sjhb printf("%s 266MHz", comma ? "," : ""); 161166435Sjhb comma = 1; 162166435Sjhb } 163166435Sjhb if (status & PCIXM_STATUS_533CAP) { 164166435Sjhb printf("%s 533MHz", comma ? "," : ""); 165166435Sjhb comma = 1; 166166435Sjhb } 167166435Sjhb if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 168166435Sjhb return; 169166435Sjhb switch (status & PCIXM_STATUS_MAX_READ) { 170166435Sjhb case PCIXM_STATUS_MAX_READ_512: 171166435Sjhb max_burst_read = 512; 172166435Sjhb break; 173166435Sjhb case PCIXM_STATUS_MAX_READ_1024: 174166435Sjhb max_burst_read = 1024; 175166435Sjhb break; 176166435Sjhb case PCIXM_STATUS_MAX_READ_2048: 177166435Sjhb max_burst_read = 2048; 178166435Sjhb break; 179166435Sjhb case PCIXM_STATUS_MAX_READ_4096: 180166435Sjhb max_burst_read = 4096; 181166435Sjhb break; 182166435Sjhb } 183166435Sjhb switch (status & PCIXM_STATUS_MAX_SPLITS) { 184166435Sjhb case PCIXM_STATUS_MAX_SPLITS_1: 185166435Sjhb max_splits = 1; 186166435Sjhb break; 187166435Sjhb case PCIXM_STATUS_MAX_SPLITS_2: 188166435Sjhb max_splits = 2; 189166435Sjhb break; 190166435Sjhb case PCIXM_STATUS_MAX_SPLITS_3: 191166435Sjhb max_splits = 3; 192166435Sjhb break; 193166435Sjhb case PCIXM_STATUS_MAX_SPLITS_4: 194166435Sjhb max_splits = 4; 195166435Sjhb break; 196166435Sjhb case PCIXM_STATUS_MAX_SPLITS_8: 197166435Sjhb max_splits = 8; 198166435Sjhb break; 199166435Sjhb case PCIXM_STATUS_MAX_SPLITS_12: 200166435Sjhb max_splits = 12; 201166435Sjhb break; 202166435Sjhb case PCIXM_STATUS_MAX_SPLITS_16: 203166435Sjhb max_splits = 16; 204166435Sjhb break; 205166435Sjhb case PCIXM_STATUS_MAX_SPLITS_32: 206166435Sjhb max_splits = 32; 207166435Sjhb break; 208166435Sjhb } 209166435Sjhb printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 210166435Sjhb max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 211166435Sjhb} 212166435Sjhb 213166435Sjhbstatic void 214166435Sjhbcap_ht(int fd, struct pci_conf *p, uint8_t ptr) 215166435Sjhb{ 216166435Sjhb uint32_t reg; 217166435Sjhb uint16_t command; 218166435Sjhb 219166435Sjhb command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 220166435Sjhb printf("HT "); 221166435Sjhb if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 222166435Sjhb printf("slave"); 223166435Sjhb else if ((command & 0xe000) == PCIM_HTCAP_HOST) 224166435Sjhb printf("host"); 225166435Sjhb else 226166435Sjhb switch (command & PCIM_HTCMD_CAP_MASK) { 227166435Sjhb case PCIM_HTCAP_SWITCH: 228166435Sjhb printf("switch"); 229166435Sjhb break; 230166435Sjhb case PCIM_HTCAP_INTERRUPT: 231166435Sjhb printf("interrupt"); 232166435Sjhb break; 233166435Sjhb case PCIM_HTCAP_REVISION_ID: 234166435Sjhb printf("revision ID"); 235166435Sjhb break; 236166435Sjhb case PCIM_HTCAP_UNITID_CLUMPING: 237166435Sjhb printf("unit ID clumping"); 238166435Sjhb break; 239166435Sjhb case PCIM_HTCAP_EXT_CONFIG_SPACE: 240166435Sjhb printf("extended config space"); 241166435Sjhb break; 242166435Sjhb case PCIM_HTCAP_ADDRESS_MAPPING: 243166435Sjhb printf("address mapping"); 244166435Sjhb break; 245166435Sjhb case PCIM_HTCAP_MSI_MAPPING: 246169037Sjhb printf("MSI %saddress window %s at 0x", 247169037Sjhb command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 248166435Sjhb command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 249166435Sjhb "disabled"); 250169037Sjhb if (command & PCIM_HTCMD_MSI_FIXED) 251169037Sjhb printf("fee00000"); 252169037Sjhb else { 253169037Sjhb reg = read_config(fd, &p->pc_sel, 254169037Sjhb ptr + PCIR_HTMSI_ADDRESS_HI, 4); 255169037Sjhb if (reg != 0) 256169037Sjhb printf("%08x", reg); 257169037Sjhb reg = read_config(fd, &p->pc_sel, 258169037Sjhb ptr + PCIR_HTMSI_ADDRESS_LO, 4); 259166435Sjhb printf("%08x", reg); 260169037Sjhb } 261166435Sjhb break; 262166435Sjhb case PCIM_HTCAP_DIRECT_ROUTE: 263166435Sjhb printf("direct route"); 264166435Sjhb break; 265166435Sjhb case PCIM_HTCAP_VCSET: 266166435Sjhb printf("VC set"); 267166435Sjhb break; 268166435Sjhb case PCIM_HTCAP_RETRY_MODE: 269166435Sjhb printf("retry mode"); 270166435Sjhb break; 271173059Sjhb case PCIM_HTCAP_X86_ENCODING: 272173059Sjhb printf("X86 encoding"); 273173059Sjhb break; 274166435Sjhb default: 275166435Sjhb printf("unknown %02x", command); 276166435Sjhb break; 277166435Sjhb } 278166435Sjhb} 279166435Sjhb 280166435Sjhbstatic void 281166435Sjhbcap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 282166435Sjhb{ 283166435Sjhb uint8_t length; 284166435Sjhb 285166435Sjhb length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 286166435Sjhb printf("vendor (length %d)", length); 287166435Sjhb if (p->pc_vendor == 0x8086) { 288166435Sjhb /* Intel */ 289166435Sjhb uint8_t version; 290166435Sjhb 291166435Sjhb version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 292166435Sjhb 1); 293166435Sjhb printf(" Intel cap %d version %d", version >> 4, version & 0xf); 294166435Sjhb if (version >> 4 == 1 && length == 12) { 295166435Sjhb /* Feature Detection */ 296166435Sjhb uint32_t fvec; 297166435Sjhb int comma; 298166435Sjhb 299166435Sjhb comma = 0; 300166435Sjhb fvec = read_config(fd, &p->pc_sel, ptr + 301166435Sjhb PCIR_VENDOR_DATA + 5, 4); 302166435Sjhb printf("\n\t\t features:"); 303166435Sjhb if (fvec & (1 << 0)) { 304166435Sjhb printf(" AMT"); 305166435Sjhb comma = 1; 306166435Sjhb } 307166435Sjhb fvec = read_config(fd, &p->pc_sel, ptr + 308166435Sjhb PCIR_VENDOR_DATA + 1, 4); 309166435Sjhb if (fvec & (1 << 21)) { 310166435Sjhb printf("%s Quick Resume", comma ? "," : ""); 311166435Sjhb comma = 1; 312166435Sjhb } 313166435Sjhb if (fvec & (1 << 18)) { 314166435Sjhb printf("%s SATA RAID-5", comma ? "," : ""); 315166435Sjhb comma = 1; 316166435Sjhb } 317166435Sjhb if (fvec & (1 << 9)) { 318166435Sjhb printf("%s Mobile", comma ? "," : ""); 319166435Sjhb comma = 1; 320166435Sjhb } 321166435Sjhb if (fvec & (1 << 7)) { 322166435Sjhb printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 323166435Sjhb comma = 1; 324166435Sjhb } else { 325166435Sjhb printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 326166435Sjhb comma = 1; 327166435Sjhb } 328166435Sjhb if (fvec & (1 << 5)) { 329166435Sjhb printf("%s SATA RAID-0/1/10", comma ? "," : ""); 330166435Sjhb comma = 1; 331166435Sjhb } 332166435Sjhb if (fvec & (1 << 3)) { 333166435Sjhb printf("%s SATA AHCI", comma ? "," : ""); 334166435Sjhb comma = 1; 335166435Sjhb } 336166435Sjhb } 337166435Sjhb } 338166435Sjhb} 339166435Sjhb 340166435Sjhbstatic void 341166435Sjhbcap_debug(int fd, struct pci_conf *p, uint8_t ptr) 342166435Sjhb{ 343166435Sjhb uint16_t debug_port; 344166435Sjhb 345166435Sjhb debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 346166435Sjhb printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 347166435Sjhb PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 348166435Sjhb} 349166435Sjhb 350166435Sjhbstatic void 351166435Sjhbcap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 352166435Sjhb{ 353166435Sjhb uint32_t id; 354166435Sjhb 355166435Sjhb id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 356166435Sjhb printf("PCI Bridge card=0x%08x", id); 357166435Sjhb} 358166435Sjhb 359166435Sjhbstatic void 360166435Sjhbcap_express(int fd, struct pci_conf *p, uint8_t ptr) 361166435Sjhb{ 362166435Sjhb uint16_t flags; 363166435Sjhb 364166435Sjhb flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2); 365166435Sjhb printf("PCI-Express %d ", flags & PCIM_EXP_FLAGS_VERSION); 366166435Sjhb switch (flags & PCIM_EXP_FLAGS_TYPE) { 367166435Sjhb case PCIM_EXP_TYPE_ENDPOINT: 368166435Sjhb printf("endpoint"); 369166435Sjhb break; 370166435Sjhb case PCIM_EXP_TYPE_LEGACY_ENDPOINT: 371166435Sjhb printf("legacy endpoint"); 372166435Sjhb break; 373166435Sjhb case PCIM_EXP_TYPE_ROOT_PORT: 374166435Sjhb printf("root port"); 375166435Sjhb break; 376166435Sjhb case PCIM_EXP_TYPE_UPSTREAM_PORT: 377166435Sjhb printf("upstream port"); 378166435Sjhb break; 379166435Sjhb case PCIM_EXP_TYPE_DOWNSTREAM_PORT: 380166435Sjhb printf("downstream port"); 381166435Sjhb break; 382166435Sjhb case PCIM_EXP_TYPE_PCI_BRIDGE: 383166435Sjhb printf("PCI bridge"); 384166435Sjhb break; 385166435Sjhb default: 386166435Sjhb printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 8); 387166435Sjhb break; 388166435Sjhb } 389166435Sjhb if (flags & PCIM_EXP_FLAGS_IRQ) 390166435Sjhb printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 17); 391166435Sjhb} 392166435Sjhb 393166435Sjhbstatic void 394166435Sjhbcap_msix(int fd, struct pci_conf *p, uint8_t ptr) 395166435Sjhb{ 396166435Sjhb uint32_t val; 397166435Sjhb uint16_t ctrl; 398166435Sjhb int msgnum, table_bar, pba_bar; 399166435Sjhb 400166435Sjhb ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 401166435Sjhb msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 402166435Sjhb val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 403166435Sjhb table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 404166435Sjhb val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 405166435Sjhb pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 406166435Sjhb printf("MSI-X supports %d message%s ", msgnum, 407166435Sjhb (msgnum == 1) ? "" : "s"); 408166435Sjhb if (table_bar == pba_bar) 409166435Sjhb printf("in map 0x%x", table_bar); 410166435Sjhb else 411166435Sjhb printf("in maps 0x%x and 0x%x", table_bar, pba_bar); 412166435Sjhb if (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) 413166435Sjhb printf(" enabled"); 414166435Sjhb} 415166435Sjhb 416166435Sjhbvoid 417166435Sjhblist_caps(int fd, struct pci_conf *p) 418166435Sjhb{ 419166435Sjhb uint16_t cmd; 420166435Sjhb uint8_t ptr, cap; 421166435Sjhb 422166435Sjhb /* Are capabilities present for this device? */ 423166435Sjhb cmd = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 424166435Sjhb if (!(cmd & PCIM_STATUS_CAPPRESENT)) 425166435Sjhb return; 426166435Sjhb 427166435Sjhb switch (p->pc_hdr & PCIM_HDRTYPE) { 428166435Sjhb case 0: 429166435Sjhb case 1: 430166435Sjhb ptr = PCIR_CAP_PTR; 431166435Sjhb break; 432166435Sjhb case 2: 433166435Sjhb ptr = PCIR_CAP_PTR_2; 434166435Sjhb break; 435166435Sjhb default: 436166435Sjhb errx(1, "list_caps: bad header type"); 437166435Sjhb } 438166435Sjhb 439166435Sjhb /* Walk the capability list. */ 440166435Sjhb ptr = read_config(fd, &p->pc_sel, ptr, 1); 441166435Sjhb while (ptr != 0 && ptr != 0xff) { 442166435Sjhb cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 443166435Sjhb printf(" cap %02x[%02x] = ", cap, ptr); 444166435Sjhb switch (cap) { 445166435Sjhb case PCIY_PMG: 446166435Sjhb cap_power(fd, p, ptr); 447166435Sjhb break; 448166435Sjhb case PCIY_AGP: 449166435Sjhb cap_agp(fd, p, ptr); 450166435Sjhb break; 451166435Sjhb case PCIY_VPD: 452166435Sjhb cap_vpd(fd, p, ptr); 453166435Sjhb break; 454166435Sjhb case PCIY_MSI: 455166435Sjhb cap_msi(fd, p, ptr); 456166435Sjhb break; 457166435Sjhb case PCIY_PCIX: 458166435Sjhb cap_pcix(fd, p, ptr); 459166435Sjhb break; 460166435Sjhb case PCIY_HT: 461166435Sjhb cap_ht(fd, p, ptr); 462166435Sjhb break; 463166435Sjhb case PCIY_VENDOR: 464166435Sjhb cap_vendor(fd, p, ptr); 465166435Sjhb break; 466166435Sjhb case PCIY_DEBUG: 467166435Sjhb cap_debug(fd, p, ptr); 468166435Sjhb break; 469166435Sjhb case PCIY_SUBVENDOR: 470166435Sjhb cap_subvendor(fd, p, ptr); 471166435Sjhb break; 472166435Sjhb case PCIY_EXPRESS: 473166435Sjhb cap_express(fd, p, ptr); 474166435Sjhb break; 475166435Sjhb case PCIY_MSIX: 476166435Sjhb cap_msix(fd, p, ptr); 477166435Sjhb break; 478166435Sjhb default: 479166435Sjhb printf("unknown"); 480166435Sjhb break; 481166435Sjhb } 482166435Sjhb printf("\n"); 483166435Sjhb ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 484166435Sjhb } 485166435Sjhb} 486