local_apic.c revision 185341
1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/i386/i386/local_apic.c 185341 2008-11-26 19:25:13Z jkim $"); 36 37#include "opt_hwpmc_hooks.h" 38#include "opt_kdtrace.h" 39 40#include "opt_ddb.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/mutex.h> 48#include <sys/pcpu.h> 49#include <sys/smp.h> 50 51#include <vm/vm.h> 52#include <vm/pmap.h> 53 54#include <machine/apicreg.h> 55#include <machine/cpu.h> 56#include <machine/cputypes.h> 57#include <machine/frame.h> 58#include <machine/intr_machdep.h> 59#include <machine/apicvar.h> 60#include <machine/md_var.h> 61#include <machine/smp.h> 62#include <machine/specialreg.h> 63 64#ifdef DDB 65#include <sys/interrupt.h> 66#include <ddb/ddb.h> 67#endif 68 69#ifdef KDTRACE_HOOKS 70#include <sys/dtrace_bsd.h> 71cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU]; 72#endif 73 74/* Sanity checks on IDT vectors. */ 75CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 76CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 77CTASSERT(APIC_LOCAL_INTS == 240); 78CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 79 80/* Magic IRQ values for the timer and syscalls. */ 81#define IRQ_TIMER (NUM_IO_INTS + 1) 82#define IRQ_SYSCALL (NUM_IO_INTS + 2) 83 84/* 85 * Support for local APICs. Local APICs manage interrupts on each 86 * individual processor as opposed to I/O APICs which receive interrupts 87 * from I/O devices and then forward them on to the local APICs. 88 * 89 * Local APICs can also send interrupts to each other thus providing the 90 * mechanism for IPIs. 91 */ 92 93struct lvt { 94 u_int lvt_edgetrigger:1; 95 u_int lvt_activehi:1; 96 u_int lvt_masked:1; 97 u_int lvt_active:1; 98 u_int lvt_mode:16; 99 u_int lvt_vector:8; 100}; 101 102struct lapic { 103 struct lvt la_lvts[LVT_MAX + 1]; 104 u_int la_id:8; 105 u_int la_cluster:4; 106 u_int la_cluster_id:2; 107 u_int la_present:1; 108 u_long *la_timer_count; 109 u_long la_hard_ticks; 110 u_long la_stat_ticks; 111 u_long la_prof_ticks; 112} static lapics[MAX_APIC_ID + 1]; 113 114/* XXX: should thermal be an NMI? */ 115 116/* Global defaults for local APIC LVT entries. */ 117static struct lvt lvts[LVT_MAX + 1] = { 118 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 119 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 120 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 121 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 122 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 124}; 125 126static inthand_t *ioint_handlers[] = { 127 NULL, /* 0 - 31 */ 128 IDTVEC(apic_isr1), /* 32 - 63 */ 129 IDTVEC(apic_isr2), /* 64 - 95 */ 130 IDTVEC(apic_isr3), /* 96 - 127 */ 131 IDTVEC(apic_isr4), /* 128 - 159 */ 132 IDTVEC(apic_isr5), /* 160 - 191 */ 133 IDTVEC(apic_isr6), /* 192 - 223 */ 134 IDTVEC(apic_isr7), /* 224 - 255 */ 135}; 136 137/* Include IDT_SYSCALL to make indexing easier. */ 138static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 139 140static u_int32_t lapic_timer_divisors[] = { 141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 143}; 144 145extern inthand_t IDTVEC(rsvd); 146 147volatile lapic_t *lapic; 148vm_paddr_t lapic_paddr; 149static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 150 151static void lapic_enable(void); 152static void lapic_resume(struct pic *pic); 153static void lapic_timer_enable_intr(void); 154static void lapic_timer_oneshot(u_int count); 155static void lapic_timer_periodic(u_int count); 156static void lapic_timer_set_divisor(u_int divisor); 157static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 158 159struct pic lapic_pic = { .pic_resume = lapic_resume }; 160 161static uint32_t 162lvt_mode(struct lapic *la, u_int pin, uint32_t value) 163{ 164 struct lvt *lvt; 165 166 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 167 if (la->la_lvts[pin].lvt_active) 168 lvt = &la->la_lvts[pin]; 169 else 170 lvt = &lvts[pin]; 171 172 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 173 APIC_LVT_VECTOR); 174 if (lvt->lvt_edgetrigger == 0) 175 value |= APIC_LVT_TM; 176 if (lvt->lvt_activehi == 0) 177 value |= APIC_LVT_IIPP_INTALO; 178 if (lvt->lvt_masked) 179 value |= APIC_LVT_M; 180 value |= lvt->lvt_mode; 181 switch (lvt->lvt_mode) { 182 case APIC_LVT_DM_NMI: 183 case APIC_LVT_DM_SMI: 184 case APIC_LVT_DM_INIT: 185 case APIC_LVT_DM_EXTINT: 186 if (!lvt->lvt_edgetrigger) { 187 printf("lapic%u: Forcing LINT%u to edge trigger\n", 188 la->la_id, pin); 189 value |= APIC_LVT_TM; 190 } 191 /* Use a vector of 0. */ 192 break; 193 case APIC_LVT_DM_FIXED: 194 value |= lvt->lvt_vector; 195 break; 196 default: 197 panic("bad APIC LVT delivery mode: %#x\n", value); 198 } 199 return (value); 200} 201 202/* 203 * Map the local APIC and setup necessary interrupt vectors. 204 */ 205void 206lapic_init(vm_paddr_t addr) 207{ 208 209 /* Map the local APIC and setup the spurious interrupt handler. */ 210 KASSERT(trunc_page(addr) == addr, 211 ("local APIC not aligned on a page boundary")); 212 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 213 lapic_paddr = addr; 214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 215 GSEL(GCODE_SEL, SEL_KPL)); 216 217 /* Perform basic initialization of the BSP's local APIC. */ 218 lapic_enable(); 219 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 220 221 /* Set BSP's per-CPU local APIC ID. */ 222 PCPU_SET(apic_id, lapic_id()); 223 224 /* Local APIC timer interrupt. */ 225 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 226 GSEL(GCODE_SEL, SEL_KPL)); 227 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 228 229 /* XXX: error/thermal interrupts */ 230} 231 232/* 233 * Create a local APIC instance. 234 */ 235void 236lapic_create(u_int apic_id, int boot_cpu) 237{ 238 int i; 239 240 if (apic_id > MAX_APIC_ID) { 241 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 242 if (boot_cpu) 243 panic("Can't ignore BSP"); 244 return; 245 } 246 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 247 apic_id)); 248 249 /* 250 * Assume no local LVT overrides and a cluster of 0 and 251 * intra-cluster ID of 0. 252 */ 253 lapics[apic_id].la_present = 1; 254 lapics[apic_id].la_id = apic_id; 255 for (i = 0; i < LVT_MAX; i++) { 256 lapics[apic_id].la_lvts[i] = lvts[i]; 257 lapics[apic_id].la_lvts[i].lvt_active = 0; 258 } 259 260#ifdef SMP 261 cpu_add(apic_id, boot_cpu); 262#endif 263} 264 265/* 266 * Dump contents of local APIC registers 267 */ 268void 269lapic_dump(const char* str) 270{ 271 272 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 273 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 274 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 275 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 276 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 277 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 278 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 279 lapic->lvt_pcint); 280} 281 282void 283lapic_setup(int boot) 284{ 285 struct lapic *la; 286 u_int32_t maxlvt; 287 register_t eflags; 288 char buf[MAXCOMLEN + 1]; 289 290 la = &lapics[lapic_id()]; 291 KASSERT(la->la_present, ("missing APIC structure")); 292 eflags = intr_disable(); 293 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 294 295 /* Initialize the TPR to allow all interrupts. */ 296 lapic_set_tpr(0); 297 298 /* Setup spurious vector and enable the local APIC. */ 299 lapic_enable(); 300 301 /* Program LINT[01] LVT entries. */ 302 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 303 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 304#ifdef HWPMC_HOOKS 305 /* Program the PMC LVT entry if present. */ 306 if (maxlvt >= LVT_PMC) 307 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 308#endif 309 310 /* Program timer LVT and setup handler. */ 311 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 312 if (boot) { 313 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 314 intrcnt_add(buf, &la->la_timer_count); 315 } 316 317 /* We don't setup the timer during boot on the BSP until later. */ 318 if (!(boot && PCPU_GET(cpuid) == 0)) { 319 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 320 lapic_id())); 321 lapic_timer_set_divisor(lapic_timer_divisor); 322 lapic_timer_periodic(lapic_timer_period); 323 lapic_timer_enable_intr(); 324 } 325 326 /* XXX: Error and thermal LVTs */ 327 328 if (cpu_vendor_id == CPU_VENDOR_AMD) { 329 /* 330 * Detect the presence of C1E capability mostly on latest 331 * dual-cores (or future) k8 family. This feature renders 332 * the local APIC timer dead, so we disable it by reading 333 * the Interrupt Pending Message register and clearing both 334 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 335 * 336 * Reference: 337 * "BIOS and Kernel Developer's Guide for AMD NPT 338 * Family 0Fh Processors" 339 * #32559 revision 3.00 340 */ 341 if ((cpu_id & 0x00000f00) == 0x00000f00 && 342 (cpu_id & 0x0fff0000) >= 0x00040000) { 343 uint64_t msr; 344 345 msr = rdmsr(0xc0010055); 346 if (msr & 0x18000000) 347 wrmsr(0xc0010055, msr & ~0x18000000ULL); 348 } 349 } 350 351 intr_restore(eflags); 352} 353 354/* 355 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 356 * that it can drive hardclock, statclock, and profclock. This function 357 * returns true if it is able to use the local APIC timer to drive the 358 * clocks and false if it is not able. 359 */ 360int 361lapic_setup_clock(void) 362{ 363 u_long value; 364 365 /* Can't drive the timer without a local APIC. */ 366 if (lapic == NULL) 367 return (0); 368 369 /* Start off with a divisor of 2 (power on reset default). */ 370 lapic_timer_divisor = 2; 371 372 /* Try to calibrate the local APIC timer. */ 373 do { 374 lapic_timer_set_divisor(lapic_timer_divisor); 375 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 376 DELAY(2000000); 377 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 378 if (value != APIC_TIMER_MAX_COUNT) 379 break; 380 lapic_timer_divisor <<= 1; 381 } while (lapic_timer_divisor <= 128); 382 if (lapic_timer_divisor > 128) 383 panic("lapic: Divisor too big"); 384 value /= 2; 385 if (bootverbose) 386 printf("lapic: Divisor %lu, Frequency %lu hz\n", 387 lapic_timer_divisor, value); 388 389 /* 390 * We want to run stathz in the neighborhood of 128hz. We would 391 * like profhz to run as often as possible, so we let it run on 392 * each clock tick. We try to honor the requested 'hz' value as 393 * much as possible. 394 * 395 * If 'hz' is above 1500, then we just let the lapic timer 396 * (and profhz) run at hz. If 'hz' is below 1500 but above 397 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz' 398 * is below 750 then we let the lapic timer run at 4 * 'hz'. 399 */ 400 if (hz >= 1500) 401 lapic_timer_hz = hz; 402 else if (hz >= 750) 403 lapic_timer_hz = hz * 2; 404 else 405 lapic_timer_hz = hz * 4; 406 if (lapic_timer_hz < 128) 407 stathz = lapic_timer_hz; 408 else 409 stathz = lapic_timer_hz / (lapic_timer_hz / 128); 410 profhz = lapic_timer_hz; 411 lapic_timer_period = value / lapic_timer_hz; 412 413 /* 414 * Start up the timer on the BSP. The APs will kick off their 415 * timer during lapic_setup(). 416 */ 417 lapic_timer_periodic(lapic_timer_period); 418 lapic_timer_enable_intr(); 419 return (1); 420} 421 422void 423lapic_disable(void) 424{ 425 uint32_t value; 426 427 /* Software disable the local APIC. */ 428 value = lapic->svr; 429 value &= ~APIC_SVR_SWEN; 430 lapic->svr = value; 431} 432 433static void 434lapic_enable(void) 435{ 436 u_int32_t value; 437 438 /* Program the spurious vector to enable the local APIC. */ 439 value = lapic->svr; 440 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 441 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 442 lapic->svr = value; 443} 444 445/* Reset the local APIC on the BSP during resume. */ 446static void 447lapic_resume(struct pic *pic) 448{ 449 450 lapic_setup(0); 451} 452 453int 454lapic_id(void) 455{ 456 457 KASSERT(lapic != NULL, ("local APIC is not mapped")); 458 return (lapic->id >> APIC_ID_SHIFT); 459} 460 461int 462lapic_intr_pending(u_int vector) 463{ 464 volatile u_int32_t *irr; 465 466 /* 467 * The IRR registers are an array of 128-bit registers each of 468 * which only describes 32 interrupts in the low 32 bits.. Thus, 469 * we divide the vector by 32 to get the 128-bit index. We then 470 * multiply that index by 4 to get the equivalent index from 471 * treating the IRR as an array of 32-bit registers. Finally, we 472 * modulus the vector by 32 to determine the individual bit to 473 * test. 474 */ 475 irr = &lapic->irr0; 476 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 477} 478 479void 480lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 481{ 482 struct lapic *la; 483 484 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 485 __func__, apic_id)); 486 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 487 __func__, cluster)); 488 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 489 ("%s: intra cluster id %u too big", __func__, cluster_id)); 490 la = &lapics[apic_id]; 491 la->la_cluster = cluster; 492 la->la_cluster_id = cluster_id; 493} 494 495int 496lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 497{ 498 499 if (pin > LVT_MAX) 500 return (EINVAL); 501 if (apic_id == APIC_ID_ALL) { 502 lvts[pin].lvt_masked = masked; 503 if (bootverbose) 504 printf("lapic:"); 505 } else { 506 KASSERT(lapics[apic_id].la_present, 507 ("%s: missing APIC %u", __func__, apic_id)); 508 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 509 lapics[apic_id].la_lvts[pin].lvt_active = 1; 510 if (bootverbose) 511 printf("lapic%u:", apic_id); 512 } 513 if (bootverbose) 514 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 515 return (0); 516} 517 518int 519lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 520{ 521 struct lvt *lvt; 522 523 if (pin > LVT_MAX) 524 return (EINVAL); 525 if (apic_id == APIC_ID_ALL) { 526 lvt = &lvts[pin]; 527 if (bootverbose) 528 printf("lapic:"); 529 } else { 530 KASSERT(lapics[apic_id].la_present, 531 ("%s: missing APIC %u", __func__, apic_id)); 532 lvt = &lapics[apic_id].la_lvts[pin]; 533 lvt->lvt_active = 1; 534 if (bootverbose) 535 printf("lapic%u:", apic_id); 536 } 537 lvt->lvt_mode = mode; 538 switch (mode) { 539 case APIC_LVT_DM_NMI: 540 case APIC_LVT_DM_SMI: 541 case APIC_LVT_DM_INIT: 542 case APIC_LVT_DM_EXTINT: 543 lvt->lvt_edgetrigger = 1; 544 lvt->lvt_activehi = 1; 545 if (mode == APIC_LVT_DM_EXTINT) 546 lvt->lvt_masked = 1; 547 else 548 lvt->lvt_masked = 0; 549 break; 550 default: 551 panic("Unsupported delivery mode: 0x%x\n", mode); 552 } 553 if (bootverbose) { 554 printf(" Routing "); 555 switch (mode) { 556 case APIC_LVT_DM_NMI: 557 printf("NMI"); 558 break; 559 case APIC_LVT_DM_SMI: 560 printf("SMI"); 561 break; 562 case APIC_LVT_DM_INIT: 563 printf("INIT"); 564 break; 565 case APIC_LVT_DM_EXTINT: 566 printf("ExtINT"); 567 break; 568 } 569 printf(" -> LINT%u\n", pin); 570 } 571 return (0); 572} 573 574int 575lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 576{ 577 578 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 579 return (EINVAL); 580 if (apic_id == APIC_ID_ALL) { 581 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 582 if (bootverbose) 583 printf("lapic:"); 584 } else { 585 KASSERT(lapics[apic_id].la_present, 586 ("%s: missing APIC %u", __func__, apic_id)); 587 lapics[apic_id].la_lvts[pin].lvt_active = 1; 588 lapics[apic_id].la_lvts[pin].lvt_activehi = 589 (pol == INTR_POLARITY_HIGH); 590 if (bootverbose) 591 printf("lapic%u:", apic_id); 592 } 593 if (bootverbose) 594 printf(" LINT%u polarity: %s\n", pin, 595 pol == INTR_POLARITY_HIGH ? "high" : "low"); 596 return (0); 597} 598 599int 600lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 601{ 602 603 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 604 return (EINVAL); 605 if (apic_id == APIC_ID_ALL) { 606 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 607 if (bootverbose) 608 printf("lapic:"); 609 } else { 610 KASSERT(lapics[apic_id].la_present, 611 ("%s: missing APIC %u", __func__, apic_id)); 612 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 613 (trigger == INTR_TRIGGER_EDGE); 614 lapics[apic_id].la_lvts[pin].lvt_active = 1; 615 if (bootverbose) 616 printf("lapic%u:", apic_id); 617 } 618 if (bootverbose) 619 printf(" LINT%u trigger: %s\n", pin, 620 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 621 return (0); 622} 623 624/* 625 * Adjust the TPR of the current CPU so that it blocks all interrupts below 626 * the passed in vector. 627 */ 628void 629lapic_set_tpr(u_int vector) 630{ 631#ifdef CHEAP_TPR 632 lapic->tpr = vector; 633#else 634 u_int32_t tpr; 635 636 tpr = lapic->tpr & ~APIC_TPR_PRIO; 637 tpr |= vector; 638 lapic->tpr = tpr; 639#endif 640} 641 642void 643lapic_eoi(void) 644{ 645 646 lapic->eoi = 0; 647} 648 649void 650lapic_handle_intr(int vector, struct trapframe *frame) 651{ 652 struct intsrc *isrc; 653 654 if (vector == -1) 655 panic("Couldn't get vector from ISR!"); 656 isrc = intr_lookup_source(apic_idt_to_irq(vector)); 657 intr_execute_handlers(isrc, frame); 658} 659 660void 661lapic_handle_timer(struct trapframe *frame) 662{ 663 struct lapic *la; 664 665 /* Send EOI first thing. */ 666 lapic_eoi(); 667 668#if defined(SMP) && !defined(SCHED_ULE) 669 /* 670 * Don't do any accounting for the disabled HTT cores, since it 671 * will provide misleading numbers for the userland. 672 * 673 * No locking is necessary here, since even if we loose the race 674 * when hlt_cpus_mask changes it is not a big deal, really. 675 * 676 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 677 * and unlike other schedulers it actually schedules threads to 678 * those CPUs. 679 */ 680 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 681 return; 682#endif 683 684 /* Look up our local APIC structure for the tick counters. */ 685 la = &lapics[PCPU_GET(apic_id)]; 686 (*la->la_timer_count)++; 687 critical_enter(); 688 689#ifdef KDTRACE_HOOKS 690 /* 691 * If the DTrace hooks are configured and a callback function 692 * has been registered, then call it to process the high speed 693 * timers. 694 */ 695 int cpu = PCPU_GET(cpuid); 696 if (lapic_cyclic_clock_func[cpu] != NULL) 697 (*lapic_cyclic_clock_func[cpu])(frame); 698#endif 699 700 /* Fire hardclock at hz. */ 701 la->la_hard_ticks += hz; 702 if (la->la_hard_ticks >= lapic_timer_hz) { 703 la->la_hard_ticks -= lapic_timer_hz; 704 if (PCPU_GET(cpuid) == 0) 705 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 706 else 707 hardclock_cpu(TRAPF_USERMODE(frame)); 708 } 709 710 /* Fire statclock at stathz. */ 711 la->la_stat_ticks += stathz; 712 if (la->la_stat_ticks >= lapic_timer_hz) { 713 la->la_stat_ticks -= lapic_timer_hz; 714 statclock(TRAPF_USERMODE(frame)); 715 } 716 717 /* Fire profclock at profhz, but only when needed. */ 718 la->la_prof_ticks += profhz; 719 if (la->la_prof_ticks >= lapic_timer_hz) { 720 la->la_prof_ticks -= lapic_timer_hz; 721 if (profprocs != 0) 722 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 723 } 724 critical_exit(); 725} 726 727static void 728lapic_timer_set_divisor(u_int divisor) 729{ 730 731 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 732 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 733 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 734 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 735} 736 737static void 738lapic_timer_oneshot(u_int count) 739{ 740 u_int32_t value; 741 742 value = lapic->lvt_timer; 743 value &= ~APIC_LVTT_TM; 744 value |= APIC_LVTT_TM_ONE_SHOT; 745 lapic->lvt_timer = value; 746 lapic->icr_timer = count; 747} 748 749static void 750lapic_timer_periodic(u_int count) 751{ 752 u_int32_t value; 753 754 value = lapic->lvt_timer; 755 value &= ~APIC_LVTT_TM; 756 value |= APIC_LVTT_TM_PERIODIC; 757 lapic->lvt_timer = value; 758 lapic->icr_timer = count; 759} 760 761static void 762lapic_timer_enable_intr(void) 763{ 764 u_int32_t value; 765 766 value = lapic->lvt_timer; 767 value &= ~APIC_LVT_M; 768 lapic->lvt_timer = value; 769} 770 771/* Request a free IDT vector to be used by the specified IRQ. */ 772u_int 773apic_alloc_vector(u_int irq) 774{ 775 u_int vector; 776 777 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 778 779 /* 780 * Search for a free vector. Currently we just use a very simple 781 * algorithm to find the first free vector. 782 */ 783 mtx_lock_spin(&icu_lock); 784 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 785 if (ioint_irqs[vector] != 0) 786 continue; 787 ioint_irqs[vector] = irq; 788 mtx_unlock_spin(&icu_lock); 789 return (vector + APIC_IO_INTS); 790 } 791 mtx_unlock_spin(&icu_lock); 792 panic("Couldn't find an APIC vector for IRQ %u", irq); 793} 794 795/* 796 * Request 'count' free contiguous IDT vectors to be used by 'count' 797 * IRQs. 'count' must be a power of two and the vectors will be 798 * aligned on a boundary of 'align'. If the request cannot be 799 * satisfied, 0 is returned. 800 */ 801u_int 802apic_alloc_vectors(u_int *irqs, u_int count, u_int align) 803{ 804 u_int first, run, vector; 805 806 KASSERT(powerof2(count), ("bad count")); 807 KASSERT(powerof2(align), ("bad align")); 808 KASSERT(align >= count, ("align < count")); 809#ifdef INVARIANTS 810 for (run = 0; run < count; run++) 811 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 812 irqs[run], run)); 813#endif 814 815 /* 816 * Search for 'count' free vectors. As with apic_alloc_vector(), 817 * this just uses a simple first fit algorithm. 818 */ 819 run = 0; 820 first = 0; 821 mtx_lock_spin(&icu_lock); 822 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 823 824 /* Vector is in use, end run. */ 825 if (ioint_irqs[vector] != 0) { 826 run = 0; 827 first = 0; 828 continue; 829 } 830 831 /* Start a new run if run == 0 and vector is aligned. */ 832 if (run == 0) { 833 if ((vector & (align - 1)) != 0) 834 continue; 835 first = vector; 836 } 837 run++; 838 839 /* Keep looping if the run isn't long enough yet. */ 840 if (run < count) 841 continue; 842 843 /* Found a run, assign IRQs and return the first vector. */ 844 for (vector = 0; vector < count; vector++) 845 ioint_irqs[first + vector] = irqs[vector]; 846 mtx_unlock_spin(&icu_lock); 847 return (first + APIC_IO_INTS); 848 } 849 mtx_unlock_spin(&icu_lock); 850 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 851 return (0); 852} 853 854void 855apic_enable_vector(u_int vector) 856{ 857 858 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 859 KASSERT(ioint_handlers[vector / 32] != NULL, 860 ("No ISR handler for vector %u", vector)); 861 setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 862 GSEL(GCODE_SEL, SEL_KPL)); 863} 864 865void 866apic_disable_vector(u_int vector) 867{ 868 869 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 870 KASSERT(ioint_handlers[vector / 32] != NULL, 871 ("No ISR handler for vector %u", vector)); 872 setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL, 873 GSEL(GCODE_SEL, SEL_KPL)); 874} 875 876/* Release an APIC vector when it's no longer in use. */ 877void 878apic_free_vector(u_int vector, u_int irq) 879{ 880 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 881 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 882 ("Vector %u does not map to an IRQ line", vector)); 883 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 884 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 885 mtx_lock_spin(&icu_lock); 886 ioint_irqs[vector - APIC_IO_INTS] = 0; 887 mtx_unlock_spin(&icu_lock); 888} 889 890/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 891u_int 892apic_idt_to_irq(u_int vector) 893{ 894 895 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 896 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 897 ("Vector %u does not map to an IRQ line", vector)); 898 return (ioint_irqs[vector - APIC_IO_INTS]); 899} 900 901#ifdef DDB 902/* 903 * Dump data about APIC IDT vector mappings. 904 */ 905DB_SHOW_COMMAND(apic, db_show_apic) 906{ 907 struct intsrc *isrc; 908 int i, verbose; 909 u_int irq; 910 911 if (strcmp(modif, "vv") == 0) 912 verbose = 2; 913 else if (strcmp(modif, "v") == 0) 914 verbose = 1; 915 else 916 verbose = 0; 917 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 918 irq = ioint_irqs[i]; 919 if (irq != 0 && irq != IRQ_SYSCALL) { 920 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 921 if (irq == IRQ_TIMER) 922 db_printf("lapic timer\n"); 923 else if (irq < NUM_IO_INTS) { 924 isrc = intr_lookup_source(irq); 925 if (isrc == NULL || verbose == 0) 926 db_printf("IRQ %u\n", irq); 927 else 928 db_dump_intr_event(isrc->is_event, 929 verbose == 2); 930 } else 931 db_printf("IRQ %u ???\n", irq); 932 } 933 } 934} 935 936static void 937dump_mask(const char *prefix, uint32_t v, int base) 938{ 939 int i, first; 940 941 first = 1; 942 for (i = 0; i < 32; i++) 943 if (v & (1 << i)) { 944 if (first) { 945 db_printf("%s:", prefix); 946 first = 0; 947 } 948 db_printf(" %02x", base + i); 949 } 950 if (!first) 951 db_printf("\n"); 952} 953 954/* Show info from the lapic regs for this CPU. */ 955DB_SHOW_COMMAND(lapic, db_show_lapic) 956{ 957 uint32_t v; 958 959 db_printf("lapic ID = %d\n", lapic_id()); 960 v = lapic->version; 961 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 962 v & 0xf); 963 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 964 v = lapic->svr; 965 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 966 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 967 db_printf("TPR = %02x\n", lapic->tpr); 968 969#define dump_field(prefix, index) \ 970 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 971 index * 32) 972 973 db_printf("In-service Interrupts:\n"); 974 dump_field(isr, 0); 975 dump_field(isr, 1); 976 dump_field(isr, 2); 977 dump_field(isr, 3); 978 dump_field(isr, 4); 979 dump_field(isr, 5); 980 dump_field(isr, 6); 981 dump_field(isr, 7); 982 983 db_printf("TMR Interrupts:\n"); 984 dump_field(tmr, 0); 985 dump_field(tmr, 1); 986 dump_field(tmr, 2); 987 dump_field(tmr, 3); 988 dump_field(tmr, 4); 989 dump_field(tmr, 5); 990 dump_field(tmr, 6); 991 dump_field(tmr, 7); 992 993 db_printf("IRR Interrupts:\n"); 994 dump_field(irr, 0); 995 dump_field(irr, 1); 996 dump_field(irr, 2); 997 dump_field(irr, 3); 998 dump_field(irr, 4); 999 dump_field(irr, 5); 1000 dump_field(irr, 6); 1001 dump_field(irr, 7); 1002 1003#undef dump_field 1004} 1005#endif 1006 1007/* 1008 * APIC probing support code. This includes code to manage enumerators. 1009 */ 1010 1011static SLIST_HEAD(, apic_enumerator) enumerators = 1012 SLIST_HEAD_INITIALIZER(enumerators); 1013static struct apic_enumerator *best_enum; 1014 1015void 1016apic_register_enumerator(struct apic_enumerator *enumerator) 1017{ 1018#ifdef INVARIANTS 1019 struct apic_enumerator *apic_enum; 1020 1021 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1022 if (apic_enum == enumerator) 1023 panic("%s: Duplicate register of %s", __func__, 1024 enumerator->apic_name); 1025 } 1026#endif 1027 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1028} 1029 1030/* 1031 * Probe the APIC enumerators, enumerate CPUs, and initialize the 1032 * local APIC. 1033 */ 1034static void 1035apic_init(void *dummy __unused) 1036{ 1037 struct apic_enumerator *enumerator; 1038 uint64_t apic_base; 1039 int retval, best; 1040 1041 /* We only support built in local APICs. */ 1042 if (!(cpu_feature & CPUID_APIC)) 1043 return; 1044 1045 /* Don't probe if APIC mode is disabled. */ 1046 if (resource_disabled("apic", 0)) 1047 return; 1048 1049 /* First, probe all the enumerators to find the best match. */ 1050 best_enum = NULL; 1051 best = 0; 1052 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1053 retval = enumerator->apic_probe(); 1054 if (retval > 0) 1055 continue; 1056 if (best_enum == NULL || best < retval) { 1057 best_enum = enumerator; 1058 best = retval; 1059 } 1060 } 1061 if (best_enum == NULL) { 1062 if (bootverbose) 1063 printf("APIC: Could not find any APICs.\n"); 1064 return; 1065 } 1066 1067 if (bootverbose) 1068 printf("APIC: Using the %s enumerator.\n", 1069 best_enum->apic_name); 1070 1071 /* 1072 * To work around an errata, we disable the local APIC on some 1073 * CPUs during early startup. We need to turn the local APIC back 1074 * on on such CPUs now. 1075 */ 1076 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL && 1077 (cpu_id & 0xff0) == 0x610) { 1078 apic_base = rdmsr(MSR_APICBASE); 1079 apic_base |= APICBASE_ENABLED; 1080 wrmsr(MSR_APICBASE, apic_base); 1081 } 1082 1083 /* Second, probe the CPU's in the system. */ 1084 retval = best_enum->apic_probe_cpus(); 1085 if (retval != 0) 1086 printf("%s: Failed to probe CPUs: returned %d\n", 1087 best_enum->apic_name, retval); 1088 1089 /* Third, initialize the local APIC. */ 1090 retval = best_enum->apic_setup_local(); 1091 if (retval != 0) 1092 printf("%s: Failed to setup the local APIC: returned %d\n", 1093 best_enum->apic_name, retval); 1094} 1095SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL); 1096 1097/* 1098 * Setup the I/O APICs. 1099 */ 1100static void 1101apic_setup_io(void *dummy __unused) 1102{ 1103 int retval; 1104 1105 if (best_enum == NULL) 1106 return; 1107 retval = best_enum->apic_setup_io(); 1108 if (retval != 0) 1109 printf("%s: Failed to setup I/O APICs: returned %d\n", 1110 best_enum->apic_name, retval); 1111 1112#ifdef XEN 1113 return; 1114#endif 1115 /* 1116 * Finish setting up the local APIC on the BSP once we know how to 1117 * properly program the LINT pins. 1118 */ 1119 lapic_setup(1); 1120 intr_register_pic(&lapic_pic); 1121 if (bootverbose) 1122 lapic_dump("BSP"); 1123 1124 /* Enable the MSI "pic". */ 1125 msi_init(); 1126} 1127SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1128 1129#ifdef SMP 1130/* 1131 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1132 * private to the sys/i386 code. The public interface for the rest of the 1133 * kernel is defined in mp_machdep.c. 1134 */ 1135int 1136lapic_ipi_wait(int delay) 1137{ 1138 int x, incr; 1139 1140 /* 1141 * Wait delay loops for IPI to be sent. This is highly bogus 1142 * since this is sensitive to CPU clock speed. If delay is 1143 * -1, we wait forever. 1144 */ 1145 if (delay == -1) { 1146 incr = 0; 1147 delay = 1; 1148 } else 1149 incr = 1; 1150 for (x = 0; x < delay; x += incr) { 1151 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1152 return (1); 1153 ia32_pause(); 1154 } 1155 return (0); 1156} 1157 1158void 1159lapic_ipi_raw(register_t icrlo, u_int dest) 1160{ 1161 register_t value, eflags; 1162 1163 /* XXX: Need more sanity checking of icrlo? */ 1164 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1165 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1166 ("%s: invalid dest field", __func__)); 1167 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1168 ("%s: reserved bits set in ICR LO register", __func__)); 1169 1170 /* Set destination in ICR HI register if it is being used. */ 1171 eflags = intr_disable(); 1172 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1173 value = lapic->icr_hi; 1174 value &= ~APIC_ID_MASK; 1175 value |= dest << APIC_ID_SHIFT; 1176 lapic->icr_hi = value; 1177 } 1178 1179 /* Program the contents of the IPI and dispatch it. */ 1180 value = lapic->icr_lo; 1181 value &= APIC_ICRLO_RESV_MASK; 1182 value |= icrlo; 1183 lapic->icr_lo = value; 1184 intr_restore(eflags); 1185} 1186 1187#define BEFORE_SPIN 1000000 1188#ifdef DETECT_DEADLOCK 1189#define AFTER_SPIN 1000 1190#endif 1191 1192void 1193lapic_ipi_vectored(u_int vector, int dest) 1194{ 1195 register_t icrlo, destfield; 1196 1197 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1198 ("%s: invalid vector %d", __func__, vector)); 1199 1200 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1201 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1202 destfield = 0; 1203 switch (dest) { 1204 case APIC_IPI_DEST_SELF: 1205 icrlo |= APIC_DEST_SELF; 1206 break; 1207 case APIC_IPI_DEST_ALL: 1208 icrlo |= APIC_DEST_ALLISELF; 1209 break; 1210 case APIC_IPI_DEST_OTHERS: 1211 icrlo |= APIC_DEST_ALLESELF; 1212 break; 1213 default: 1214 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1215 ("%s: invalid destination 0x%x", __func__, dest)); 1216 destfield = dest; 1217 } 1218 1219 /* Wait for an earlier IPI to finish. */ 1220 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1221 if (panicstr != NULL) 1222 return; 1223 else 1224 panic("APIC: Previous IPI is stuck"); 1225 } 1226 1227 lapic_ipi_raw(icrlo, destfield); 1228 1229#ifdef DETECT_DEADLOCK 1230 /* Wait for IPI to be delivered. */ 1231 if (!lapic_ipi_wait(AFTER_SPIN)) { 1232#ifdef needsattention 1233 /* 1234 * XXX FIXME: 1235 * 1236 * The above function waits for the message to actually be 1237 * delivered. It breaks out after an arbitrary timeout 1238 * since the message should eventually be delivered (at 1239 * least in theory) and that if it wasn't we would catch 1240 * the failure with the check above when the next IPI is 1241 * sent. 1242 * 1243 * We could skip this wait entirely, EXCEPT it probably 1244 * protects us from other routines that assume that the 1245 * message was delivered and acted upon when this function 1246 * returns. 1247 */ 1248 printf("APIC: IPI might be stuck\n"); 1249#else /* !needsattention */ 1250 /* Wait until mesage is sent without a timeout. */ 1251 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1252 ia32_pause(); 1253#endif /* needsattention */ 1254 } 1255#endif /* DETECT_DEADLOCK */ 1256} 1257#endif /* SMP */ 1258