nmi.c revision 71236
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91 37 * $FreeBSD: head/sys/i386/isa/nmi.c 71236 2001-01-19 09:07:16Z peter $ 38 */ 39 40#include "opt_auto_eoi.h" 41 42#include "isa.h" 43 44#include <sys/param.h> 45#include <sys/bus.h> 46#ifndef SMP 47#include <machine/lock.h> 48#endif 49#include <sys/proc.h> 50#include <sys/systm.h> 51#include <sys/syslog.h> 52#include <sys/ipl.h> 53#include <sys/kernel.h> 54#include <sys/kthread.h> 55#include <sys/malloc.h> 56#include <sys/module.h> 57#include <sys/mutex.h> 58#include <sys/unistd.h> 59#include <sys/errno.h> 60#include <sys/interrupt.h> 61#include <machine/md_var.h> 62#include <machine/segments.h> 63#include <sys/bus.h> 64 65#if defined(APIC_IO) 66#include <machine/smptests.h> /** FAST_HI */ 67#include <machine/smp.h> 68#include <machine/resource.h> 69#endif /* APIC_IO */ 70#ifdef PC98 71#include <pc98/pc98/pc98.h> 72#include <pc98/pc98/pc98_machdep.h> 73#include <pc98/pc98/epsonio.h> 74#else 75#include <i386/isa/isa.h> 76#endif 77#include <i386/isa/icu.h> 78 79#if NISA > 0 80#include <isa/isavar.h> 81#endif 82#include <i386/isa/intr_machdep.h> 83#include <sys/interrupt.h> 84#ifdef APIC_IO 85#include <machine/clock.h> 86#endif 87 88#include "mca.h" 89#if NMCA > 0 90#include <i386/isa/mca_machdep.h> 91#endif 92 93/* 94 * Per-interrupt data. 95 */ 96u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */ 97driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */ 98struct ithd *ithds[ICU_LEN]; /* real interrupt handler */ 99void *intr_unit[ICU_LEN]; 100 101static inthand_t *fastintr[ICU_LEN] = { 102 &IDTVEC(fastintr0), &IDTVEC(fastintr1), 103 &IDTVEC(fastintr2), &IDTVEC(fastintr3), 104 &IDTVEC(fastintr4), &IDTVEC(fastintr5), 105 &IDTVEC(fastintr6), &IDTVEC(fastintr7), 106 &IDTVEC(fastintr8), &IDTVEC(fastintr9), 107 &IDTVEC(fastintr10), &IDTVEC(fastintr11), 108 &IDTVEC(fastintr12), &IDTVEC(fastintr13), 109 &IDTVEC(fastintr14), &IDTVEC(fastintr15), 110#if defined(APIC_IO) 111 &IDTVEC(fastintr16), &IDTVEC(fastintr17), 112 &IDTVEC(fastintr18), &IDTVEC(fastintr19), 113 &IDTVEC(fastintr20), &IDTVEC(fastintr21), 114 &IDTVEC(fastintr22), &IDTVEC(fastintr23), 115#endif /* APIC_IO */ 116}; 117 118static inthand_t *slowintr[ICU_LEN] = { 119 &IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3), 120 &IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7), 121 &IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11), 122 &IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15), 123#if defined(APIC_IO) 124 &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19), 125 &IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23), 126#endif /* APIC_IO */ 127}; 128 129static driver_intr_t isa_strayintr; 130 131#ifdef PC98 132#define NMI_PARITY 0x04 133#define NMI_EPARITY 0x02 134#else 135#define NMI_PARITY (1 << 7) 136#define NMI_IOCHAN (1 << 6) 137#define ENMI_WATCHDOG (1 << 7) 138#define ENMI_BUSTIMER (1 << 6) 139#define ENMI_IOSTATUS (1 << 5) 140#endif 141 142/* 143 * Bus attachment for the ISA PIC. 144 */ 145static struct isa_pnp_id atpic_ids[] = { 146 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" }, 147 { 0 } 148}; 149 150static int 151atpic_probe(device_t dev) 152{ 153 int result; 154 155 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0) 156 device_quiet(dev); 157 return(result); 158} 159 160/* 161 * In the APIC_IO case we might be granted IRQ 2, as this is typically 162 * consumed by chaining between the two PIC components. If we're using 163 * the APIC, however, this may not be the case, and as such we should 164 * free the resource. (XXX untested) 165 * 166 * The generic ISA attachment code will handle allocating any other resources 167 * that we don't explicitly claim here. 168 */ 169static int 170atpic_attach(device_t dev) 171{ 172#ifdef APIC_IO 173 int rid; 174 struct resource *res; 175 176 /* try to allocate our IRQ and then free it */ 177 rid = 0; 178 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0); 179 if (res != NULL) 180 bus_release_resource(dev, SYS_RES_IRQ, rid, res); 181#endif 182 return(0); 183} 184 185static device_method_t atpic_methods[] = { 186 /* Device interface */ 187 DEVMETHOD(device_probe, atpic_probe), 188 DEVMETHOD(device_attach, atpic_attach), 189 DEVMETHOD(device_detach, bus_generic_detach), 190 DEVMETHOD(device_shutdown, bus_generic_shutdown), 191 DEVMETHOD(device_suspend, bus_generic_suspend), 192 DEVMETHOD(device_resume, bus_generic_resume), 193 { 0, 0 } 194}; 195 196static driver_t atpic_driver = { 197 "atpic", 198 atpic_methods, 199 1, /* no softc */ 200}; 201 202static devclass_t atpic_devclass; 203 204DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0); 205 206/* 207 * Handle a NMI, possibly a machine check. 208 * return true to panic system, false to ignore. 209 */ 210int 211isa_nmi(cd) 212 int cd; 213{ 214 int retval = 0; 215#ifdef PC98 216 int port = inb(0x33); 217 218 log(LOG_CRIT, "NMI PC98 port = %x\n", port); 219 if (epson_machine_id == 0x20) 220 epson_outb(0xc16, epson_inb(0xc16) | 0x1); 221 if (port & NMI_PARITY) { 222 log(LOG_CRIT, "BASE RAM parity error, likely hardware failure."); 223 retval = 1; 224 } else if (port & NMI_EPARITY) { 225 log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure."); 226 retval = 1; 227 } else { 228 log(LOG_CRIT, "\nNMI Resume ??\n"); 229 } 230#else /* IBM-PC */ 231 int isa_port = inb(0x61); 232 int eisa_port = inb(0x461); 233 234 log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port); 235#if NMCA > 0 236 if (MCA_system && mca_bus_nmi()) 237 return(0); 238#endif 239 240 if (isa_port & NMI_PARITY) { 241 log(LOG_CRIT, "RAM parity error, likely hardware failure."); 242 retval = 1; 243 } 244 245 if (isa_port & NMI_IOCHAN) { 246 log(LOG_CRIT, "I/O channel check, likely hardware failure."); 247 retval = 1; 248 } 249 250 /* 251 * On a real EISA machine, this will never happen. However it can 252 * happen on ISA machines which implement XT style floating point 253 * error handling (very rare). Save them from a meaningless panic. 254 */ 255 if (eisa_port == 0xff) 256 return(retval); 257 258 if (eisa_port & ENMI_WATCHDOG) { 259 log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure."); 260 retval = 1; 261 } 262 263 if (eisa_port & ENMI_BUSTIMER) { 264 log(LOG_CRIT, "EISA bus timeout, likely hardware failure."); 265 retval = 1; 266 } 267 268 if (eisa_port & ENMI_IOSTATUS) { 269 log(LOG_CRIT, "EISA I/O port status error."); 270 retval = 1; 271 } 272#endif 273 return(retval); 274} 275 276/* 277 * Create a default interrupt table to avoid problems caused by 278 * spurious interrupts during configuration of kernel, then setup 279 * interrupt control unit. 280 */ 281void 282isa_defaultirq() 283{ 284 int i; 285 286 /* icu vectors */ 287 for (i = 0; i < ICU_LEN; i++) 288 icu_unset(i, (driver_intr_t *)NULL); 289 290 /* initialize 8259's */ 291#if NMCA > 0 292 if (MCA_system) 293 outb(IO_ICU1, 0x19); /* reset; program device, four bytes */ 294 else 295#endif 296 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 297 298 outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */ 299 outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */ 300#ifdef PC98 301#ifdef AUTO_EOI_1 302 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */ 303#else 304 outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */ 305#endif 306#else /* IBM-PC */ 307#ifdef AUTO_EOI_1 308 outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ 309#else 310 outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */ 311#endif 312#endif /* PC98 */ 313 outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ 314 outb(IO_ICU1, 0x0a); /* default to IRR on read */ 315#ifndef PC98 316 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 317#endif /* !PC98 */ 318 319#if NMCA > 0 320 if (MCA_system) 321 outb(IO_ICU2, 0x19); /* reset; program device, four bytes */ 322 else 323#endif 324 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 325 326 outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */ 327 outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */ 328#ifdef PC98 329 outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */ 330#else /* IBM-PC */ 331#ifdef AUTO_EOI_2 332 outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */ 333#else 334 outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */ 335#endif 336#endif /* PC98 */ 337 outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */ 338 outb(IO_ICU2, 0x0a); /* default to IRR on read */ 339} 340 341/* 342 * Caught a stray interrupt, notify 343 */ 344static void 345isa_strayintr(vcookiep) 346 void *vcookiep; 347{ 348 int intr = (void **)vcookiep - &intr_unit[0]; 349 350 /* 351 * XXX TODO print a different message for #7 if it is for a 352 * glitch. Glitches can be distinguished from real #7's by 353 * testing that the in-service bit is _not_ set. The test 354 * must be done before sending an EOI so it can't be done if 355 * we are using AUTO_EOI_1. 356 */ 357 if (intrcnt[1 + intr] <= 5) 358 log(LOG_ERR, "stray irq %d\n", intr); 359 if (intrcnt[1 + intr] == 5) 360 log(LOG_CRIT, 361 "too many stray irq %d's; not logging any more\n", intr); 362} 363 364#if NISA > 0 365/* 366 * Return a bitmap of the current interrupt requests. This is 8259-specific 367 * and is only suitable for use at probe time. 368 */ 369intrmask_t 370isa_irq_pending() 371{ 372 u_char irr1; 373 u_char irr2; 374 375 irr1 = inb(IO_ICU1); 376 irr2 = inb(IO_ICU2); 377 return ((irr2 << 8) | irr1); 378} 379#endif 380 381/* 382 * Update intrnames array with the specified name. This is used by 383 * vmstat(8) and the like. 384 */ 385static void 386update_intrname(int intr, char *name) 387{ 388 char buf[32]; 389 char *cp; 390 int name_index, off, strayintr; 391 392 /* 393 * Initialise strings for bitbucket and stray interrupt counters. 394 * These have statically allocated indices 0 and 1 through ICU_LEN. 395 */ 396 if (intrnames[0] == '\0') { 397 off = sprintf(intrnames, "???") + 1; 398 for (strayintr = 0; strayintr < ICU_LEN; strayintr++) 399 off += sprintf(intrnames + off, "stray irq%d", 400 strayintr) + 1; 401 } 402 403 if (name == NULL) 404 name = "???"; 405 if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf)) 406 goto use_bitbucket; 407 408 /* 409 * Search for `buf' in `intrnames'. In the usual case when it is 410 * not found, append it to the end if there is enough space (the \0 411 * terminator for the previous string, if any, becomes a separator). 412 */ 413 for (cp = intrnames, name_index = 0; 414 cp != eintrnames && name_index < NR_INTRNAMES; 415 cp += strlen(cp) + 1, name_index++) { 416 if (*cp == '\0') { 417 if (strlen(buf) >= eintrnames - cp) 418 break; 419 strcpy(cp, buf); 420 goto found; 421 } 422 if (strcmp(cp, buf) == 0) 423 goto found; 424 } 425 426use_bitbucket: 427 printf("update_intrname: counting %s irq%d as %s\n", name, intr, 428 intrnames); 429 name_index = 0; 430found: 431 intr_countp[intr] = &intrcnt[name_index]; 432} 433 434int 435icu_setup(int intr, driver_intr_t *handler, void *arg, int flags) 436{ 437#ifdef FAST_HI 438 int select; /* the select register is 8 bits */ 439 int vector; 440 u_int32_t value; /* the window register is 32 bits */ 441#endif /* FAST_HI */ 442 u_long ef; 443 444#if defined(APIC_IO) 445 if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */ 446#else 447 if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID) 448#endif /* APIC_IO */ 449 if (intr_handler[intr] != isa_strayintr) 450 return (EBUSY); 451 452 ef = read_eflags(); 453 disable_intr(); 454 intr_handler[intr] = handler; 455 intr_unit[intr] = arg; 456#ifdef FAST_HI 457 if (flags & INTR_FAST) { 458 vector = TPR_FAST_INTS + intr; 459 setidt(vector, fastintr[intr], 460 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 461 } 462 else { 463 vector = TPR_SLOW_INTS + intr; 464#ifdef APIC_INTR_REORDER 465#ifdef APIC_INTR_HIGHPRI_CLOCK 466 /* XXX: Hack (kludge?) for more accurate clock. */ 467 if (intr == apic_8254_intr || intr == 8) { 468 vector = TPR_FAST_INTS + intr; 469 } 470#endif 471#endif 472 setidt(vector, slowintr[intr], 473 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 474 } 475#ifdef APIC_INTR_REORDER 476 set_lapic_isrloc(intr, vector); 477#endif 478 /* 479 * Reprogram the vector in the IO APIC. 480 */ 481 if (int_to_apicintpin[intr].ioapic >= 0) { 482 select = int_to_apicintpin[intr].redirindex; 483 value = io_apic_read(int_to_apicintpin[intr].ioapic, 484 select) & ~IOART_INTVEC; 485 io_apic_write(int_to_apicintpin[intr].ioapic, 486 select, value | vector); 487 } 488#else 489 setidt(ICU_OFFSET + intr, 490 flags & INTR_FAST ? fastintr[intr] : slowintr[intr], 491 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 492#endif /* FAST_HI */ 493 INTREN(1 << intr); 494 write_eflags(ef); 495 return (0); 496} 497 498/* 499 * Dissociate an interrupt handler from an IRQ and set the handler to 500 * the stray interrupt handler. The 'handler' parameter is used only 501 * for consistency checking. 502 */ 503int 504icu_unset(intr, handler) 505 int intr; 506 driver_intr_t *handler; 507{ 508 u_long ef; 509 510 if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr]) 511 return (EINVAL); 512 513 INTRDIS(1 << intr); 514 ef = read_eflags(); 515 disable_intr(); 516 intr_countp[intr] = &intrcnt[1 + intr]; 517 intr_handler[intr] = isa_strayintr; 518 intr_unit[intr] = &intr_unit[intr]; 519#ifdef FAST_HI_XXX 520 /* XXX how do I re-create dvp here? */ 521 setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr, 522 slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 523#else /* FAST_HI */ 524#ifdef APIC_INTR_REORDER 525 set_lapic_isrloc(intr, ICU_OFFSET + intr); 526#endif 527 setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL, 528 GSEL(GCODE_SEL, SEL_KPL)); 529#endif /* FAST_HI */ 530 write_eflags(ef); 531 return (0); 532} 533 534struct intrhand * 535inthand_add(const char *name, int irq, driver_intr_t handler, void *arg, 536 int pri, int flags) 537{ 538 struct ithd *ithd = ithds[irq]; /* descriptor for the IRQ */ 539 struct intrhand *head; /* chain of handlers for IRQ */ 540 struct intrhand *idesc; /* descriptor for this handler */ 541 struct proc *p; /* interrupt thread */ 542 int errcode = 0; 543 544 if (name == NULL) /* no name? */ 545 panic ("anonymous interrupt"); 546 if (ithd == NULL || ithd->it_ih == NULL) { 547 /* first handler for this irq. */ 548 if (ithd == NULL) { 549 ithd = malloc(sizeof (struct ithd), M_DEVBUF, 550 M_WAITOK | M_ZERO); 551 if (ithd == NULL) 552 return (NULL); 553 ithd->irq = irq; 554 ithds[irq] = ithd; 555 } 556 /* 557 * If we have a fast interrupt, we need to set the 558 * handler address directly. Do that below. For a 559 * slow interrupt, we don't need to know more details, 560 * so do it here because it's tidier. 561 */ 562 if ((flags & INTR_FAST) == 0) { 563 /* 564 * Only create a kernel thread if we don't already 565 * have one. 566 */ 567 if (ithd->it_proc == NULL) { 568 errcode = kthread_create(ithd_loop, NULL, &p, 569 RFSTOPPED | RFHIGHPID, "irq%d: %s", irq, 570 name); 571 if (errcode) 572 panic("inthand_add: Can't create " 573 "interrupt thread"); 574 p->p_rtprio.type = RTP_PRIO_ITHREAD; 575 p->p_stat = SWAIT; /* we're idle */ 576 577 /* Put in linkages. */ 578 ithd->it_proc = p; 579 p->p_ithd = ithd; 580 } else 581 snprintf(ithd->it_proc->p_comm, MAXCOMLEN, 582 "irq%d: %s", irq, name); 583 p->p_rtprio.prio = pri; 584 585 /* 586 * The interrupt process must be in place, but 587 * not necessarily schedulable, before we 588 * initialize the ICU, since it may cause an 589 * immediate interrupt. 590 */ 591 if (icu_setup(irq, &sched_ithd, arg, flags) != 0) 592 panic("inthand_add: Can't initialize ICU"); 593 } 594 } else if ((flags & INTR_EXCL) != 0 595 || (ithd->it_ih->ih_flags & INTR_EXCL) != 0) { 596 /* 597 * We can't append the new handler if either 598 * list ithd or new handler do not allow 599 * interrupts to be shared. 600 */ 601 if (bootverbose) 602 printf("\tdevice combination %s and %s " 603 "doesn't support shared irq%d\n", 604 ithd->it_ih->ih_name, name, irq); 605 return(NULL); 606 } else if (flags & INTR_FAST) { 607 /* We can only have one fast interrupt by itself. */ 608 if (bootverbose) 609 printf("\tCan't add fast interrupt %s" 610 " to normal interrupt %s on irq%d", 611 name, ithd->it_ih->ih_name, irq); 612 return (NULL); 613 } else { /* update p_comm */ 614 p = ithd->it_proc; 615 if (strlen(p->p_comm) + strlen(name) < MAXCOMLEN) { 616 strcat(p->p_comm, " "); 617 strcat(p->p_comm, name); 618 } else if (strlen(p->p_comm) == MAXCOMLEN) 619 p->p_comm[MAXCOMLEN - 1] = '+'; 620 else 621 strcat(p->p_comm, "+"); 622 } 623 idesc = malloc(sizeof (struct intrhand), M_DEVBUF, M_WAITOK | M_ZERO); 624 if (idesc == NULL) 625 return (NULL); 626 627 idesc->ih_handler = handler; 628 idesc->ih_argument = arg; 629 idesc->ih_flags = flags; 630 idesc->ih_ithd = ithd; 631 632 idesc->ih_name = malloc(strlen(name) + 1, M_DEVBUF, M_WAITOK); 633 if (idesc->ih_name == NULL) { 634 free(idesc, M_DEVBUF); 635 return (NULL); 636 } 637 strcpy(idesc->ih_name, name); 638 639 /* Slow interrupts got set up above. */ 640 if ((flags & INTR_FAST) 641 && (icu_setup(irq, idesc->ih_handler, idesc->ih_argument, 642 idesc->ih_flags) != 0) ) { 643 if (bootverbose) 644 printf("\tinthand_add(irq%d) failed, result=%d\n", 645 irq, errcode); 646 free(idesc->ih_name, M_DEVBUF); 647 free(idesc, M_DEVBUF); 648 return NULL; 649 } 650 head = ithd->it_ih; /* look at chain of handlers */ 651 if (head) { 652 while (head->ih_next != NULL) 653 head = head->ih_next; /* find the end */ 654 head->ih_next = idesc; /* hook it in there */ 655 } else 656 ithd->it_ih = idesc; /* put it up front */ 657 update_intrname(irq, idesc->ih_name); 658 return (idesc); 659} 660 661/* 662 * Deactivate and remove linked list the interrupt handler descriptor 663 * data connected created by an earlier call of inthand_add(), then 664 * adjust the interrupt masks if necessary. 665 * 666 * Return the memory held by the interrupt handler descriptor data 667 * structure to the system. First ensure the handler is not actively 668 * in use. 669 */ 670 671int 672inthand_remove(struct intrhand *idesc) 673{ 674 struct ithd *ithd; /* descriptor for the IRQ */ 675 struct intrhand *ih; /* chain of handlers */ 676 677 if (idesc == NULL) 678 return (-1); 679 ithd = idesc->ih_ithd; 680 ih = ithd->it_ih; 681 682 if (ih == idesc) /* first in the chain */ 683 ithd->it_ih = idesc->ih_next; /* unhook it */ 684 else { 685 while ((ih != NULL) 686 && (ih->ih_next != idesc) ) 687 ih = ih->ih_next; 688 if (ih->ih_next != idesc) 689 return (-1); 690 ih->ih_next = ih->ih_next->ih_next; 691 } 692 693 if (ithd->it_ih == NULL) { /* no handlers left, */ 694 icu_unset(ithd->irq, idesc->ih_handler); 695 ithds[ithd->irq] = NULL; 696 697 if ((idesc->ih_flags & INTR_FAST) == 0) { 698 mtx_enter(&sched_lock, MTX_SPIN); 699 if (ithd->it_proc->p_stat == SWAIT) { 700 ithd->it_proc->p_stat = SRUN; 701 setrunqueue(ithd->it_proc); 702 /* 703 * We don't do an ast here because we really 704 * don't care when it runs next. 705 * 706 * XXX: should we lower the threads priority? 707 */ 708 } 709 mtx_exit(&sched_lock, MTX_SPIN); 710 } 711 } 712 free(idesc->ih_name, M_DEVBUF); 713 free(idesc, M_DEVBUF); 714 return (0); 715} 716