specialreg.h revision 40003 
1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *	This product includes software developed by the University of
16 *	California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 *	from: @(#)specialreg.h	7.1 (Berkeley) 5/9/91
34 *	$Id: specialreg.h,v 1.15 1998/03/04 11:39:16 kato Exp $
35 */
36
37#ifndef _MACHINE_SPECIALREG_H_
38#define	_MACHINE_SPECIALREG_H_
39
40/*
41 * Bits in 386 special registers:
42 */
43#define	CR0_PE	0x00000001	/* Protected mode Enable */
44#define	CR0_MP	0x00000002	/* "Math" Present (NPX or NPX emulator) */
45#define	CR0_EM	0x00000004	/* EMulate non-NPX coproc. (trap ESC only) */
46#define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
47#ifdef notused
48#define	CR0_ET	0x00000010	/* Extension Type (387 (if set) vs 287) */
49#endif
50#define	CR0_PG	0x80000000	/* PaGing enable */
51
52/*
53 * Bits in 486 special registers:
54 */
55#define	CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
56#define	CR0_WP	0x00010000	/* Write Protect (honor page protect in
57							   all modes) */
58#define	CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
59#define	CR0_NW  0x20000000	/* Not Write-through */
60#define	CR0_CD  0x40000000	/* Cache Disable */
61
62/*
63 * Bits in PPro special registers
64 */
65#define	CR4_VME	0x00000001	/* Virtual 8086 mode extensions */
66#define	CR4_PVI	0x00000002	/* Protected-mode virtual interrupts */
67#define	CR4_TSD	0x00000004	/* Time stamp disable */
68#define	CR4_DE	0x00000008	/* Debugging extensions */
69#define	CR4_PSE	0x00000010	/* Page size extensions */
70#define	CR4_PAE	0x00000020	/* Physical address extension */
71#define	CR4_MCE	0x00000040	/* Machine check enable */
72#define	CR4_PGE	0x00000080	/* Page global enable */
73#define	CR4_PCE	0x00000100	/* Performance monitoring counter enable */
74
75/*
76 * CPUID instruction features register
77 */
78#define	CPUID_FPU	0x0001
79#define	CPUID_VME	0x0002
80#define	CPUID_DE	0x0004
81#define	CPUID_PSE	0x0008
82#define	CPUID_TSC	0x0010
83#define	CPUID_MSR	0x0020
84#define	CPUID_PAE	0x0040
85#define	CPUID_MCE	0x0080
86#define	CPUID_CX8	0x0100
87#define	CPUID_APIC	0x0200
88#define	CPUID_B10	0x0400
89#define	CPUID_B11	0x0800
90#define	CPUID_MTRR	0x1000
91#define	CPUID_PGE	0x2000
92#define	CPUID_MCA	0x4000
93#define	CPUID_CMOV	0x8000
94
95/*
96 * Cyrix configuration registers, accessible as IO ports.
97 */
98#define	CCR0			0xc0	/* Configuration control register 0 */
99#define	CCR0_NC0		0x01	/* First 64K of each 1M memory region is
100								   non-cacheable */
101#define	CCR0_NC1		0x02	/* 640K-1M region is non-cacheable */
102#define	CCR0_A20M		0x04	/* Enables A20M# input pin */
103#define	CCR0_KEN		0x08	/* Enables KEN# input pin */
104#define	CCR0_FLUSH		0x10	/* Enables FLUSH# input pin */
105#define	CCR0_BARB		0x20	/* Flushes internal cache when entering hold
106								   state */
107#define	CCR0_CO			0x40	/* Cache org: 1=direct mapped, 0=2x set
108								   assoc */
109#define	CCR0_SUSPEND	0x80	/* Enables SUSP# and SUSPA# pins */
110
111#define	CCR1			0xc1	/* Configuration control register 1 */
112#define	CCR1_RPL		0x01	/* Enables RPLSET and RPLVAL# pins */
113#define	CCR1_SMI		0x02	/* Enables SMM pins */
114#define	CCR1_SMAC		0x04	/* System management memory access */
115#define	CCR1_MMAC		0x08	/* Main memory access */
116#define	CCR1_NO_LOCK	0x10	/* Negate LOCK# */
117#define	CCR1_SM3		0x80	/* SMM address space address region 3 */
118
119#define	CCR2			0xc2
120#define	CCR2_WB			0x02	/* Enables WB cache interface pins */
121#define	CCR2_SADS		0x02	/* Slow ADS */
122#define	CCR2_LOCK_NW	0x04	/* LOCK NW Bit */
123#define	CCR2_SUSP_HLT	0x08	/* Suspend on HALT */
124#define	CCR2_WT1		0x10	/* WT region 1 */
125#define	CCR2_WPR1		0x10	/* Write-protect region 1 */
126#define CCR2_BARB		0x20	/* Flushes write-back cache when entering
127								   hold state. */
128#define	CCR2_BWRT		0x40	/* Enables burst write cycles */
129#define	CCR2_USE_SUSP	0x80	/* Enables suspend pins */
130
131#define	CCR3			0xc3
132#define	CCR3_SMILOCK	0x01	/* SMM register lock */
133#define	CCR3_NMI		0x02	/* Enables NMI during SMM */
134#define	CCR3_LINBRST	0x04	/* Linear address burst cycles */
135#define	CCR3_SMMMODE	0x08	/* SMM Mode */
136#define	CCR3_MAPEN0		0x10	/* Enables Map0 */
137#define	CCR3_MAPEN1		0x20	/* Enables Map1 */
138#define	CCR3_MAPEN2		0x40	/* Enables Map2 */
139#define	CCR3_MAPEN3		0x80	/* Enables Map3 */
140
141#define	CCR4			0xe8
142#define	CCR4_IOMASK		0x07
143#define	CCR4_MEM		0x08	/* Enables momory bypassing */
144#define	CCR4_DTE		0x10	/* Enables directory table entry cache */
145#define	CCR4_FASTFPE	0x20	/* Fast FPU exception */
146#define	CCR4_CPUID		0x80	/* Enables CPUID instruction */
147
148#define	CCR5			0xe9
149#define	CCR5_WT_ALLOC	0x01	/* Write-through allocate */
150#define	CCR5_SLOP		0x02	/* LOOP instruction slowed down */
151#define	CCR5_LBR1		0x10	/* Local bus region 1 */
152#define	CCR5_ARREN		0x20	/* Enables ARR region */
153
154#define	CCR6			0xea
155
156#define	CCR7			0xeb
157
158/* Performance Control Register (5x86 only). */
159#define	PCR0			0x20
160#define	PCR0_RSTK		0x01	/* Enables return stack */
161#define	PCR0_BTB		0x02	/* Enables branch target buffer */
162#define	PCR0_LOOP		0x04	/* Enables loop */
163#define	PCR0_AIS		0x08	/* Enables all instrcutions stalled to
164								   serialize pipe. */
165#define	PCR0_MLR		0x10	/* Enables reordering of misaligned loads */
166#define	PCR0_BTBRT		0x40	/* Enables BTB test register. */
167#define	PCR0_LSSER		0x80	/* Disable reorder */
168
169/* Device Identification Registers */
170#define	DIR0			0xfe
171#define	DIR1			0xff
172
173/*
174 * The following four 3-byte registers control the non-cacheable regions.
175 * These registers must be written as three separate bytes.
176 *
177 * NCRx+0: A31-A24 of starting address
178 * NCRx+1: A23-A16 of starting address
179 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
180 *
181 * The non-cacheable region's starting address must be aligned to the
182 * size indicated by the NCR_SIZE_xx field.
183 */
184#define	NCR1	0xc4
185#define	NCR2	0xc7
186#define	NCR3	0xca
187#define	NCR4	0xcd
188
189#define	NCR_SIZE_0K	0
190#define	NCR_SIZE_4K	1
191#define	NCR_SIZE_8K	2
192#define	NCR_SIZE_16K	3
193#define	NCR_SIZE_32K	4
194#define	NCR_SIZE_64K	5
195#define	NCR_SIZE_128K	6
196#define	NCR_SIZE_256K	7
197#define	NCR_SIZE_512K	8
198#define	NCR_SIZE_1M	9
199#define	NCR_SIZE_2M	10
200#define	NCR_SIZE_4M	11
201#define	NCR_SIZE_8M	12
202#define	NCR_SIZE_16M	13
203#define	NCR_SIZE_32M	14
204#define	NCR_SIZE_4G	15
205
206/*
207 * The address region registers are used to specify the location and
208 * size for the eight address regions.
209 *
210 * ARRx + 0: A31-A24 of start address
211 * ARRx + 1: A23-A16 of start address
212 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
213 */
214#define	ARR0	0xc4
215#define	ARR1	0xc7
216#define	ARR2	0xca
217#define	ARR3	0xcd
218#define	ARR4	0xd0
219#define	ARR5	0xd3
220#define	ARR6	0xd6
221#define	ARR7	0xd9
222
223#define	ARR_SIZE_0K		0
224#define	ARR_SIZE_4K		1
225#define	ARR_SIZE_8K		2
226#define	ARR_SIZE_16K	3
227#define	ARR_SIZE_32K	4
228#define	ARR_SIZE_64K	5
229#define	ARR_SIZE_128K	6
230#define	ARR_SIZE_256K	7
231#define	ARR_SIZE_512K	8
232#define	ARR_SIZE_1M		9
233#define	ARR_SIZE_2M		10
234#define	ARR_SIZE_4M		11
235#define	ARR_SIZE_8M		12
236#define	ARR_SIZE_16M	13
237#define	ARR_SIZE_32M	14
238#define	ARR_SIZE_4G		15
239
240/*
241 * The region control registers specify the attributes associated with
242 * the ARRx addres regions.
243 */
244#define	RCR0	0xdc
245#define	RCR1	0xdd
246#define	RCR2	0xde
247#define	RCR3	0xdf
248#define	RCR4	0xe0
249#define	RCR5	0xe1
250#define	RCR6	0xe2
251#define	RCR7	0xe3
252
253#define RCR_RCD	0x01	/* Disables caching for ARRx (x = 0-6). */
254#define RCR_RCE	0x01	/* Enables caching for ARR7. */
255#define RCR_WWO	0x02	/* Weak write ordering. */
256#define	RCR_WL	0x04	/* Weak locking. */
257#define RCR_WG	0x08	/* Write gathering. */
258#define	RCR_WT	0x10	/* Write-through. */
259#define	RCR_NLB	0x20	/* LBA# pin is not asserted. */
260
261/* AMD Write Allocate Top-Of-Memory and Control Register */
262#define	AMD_WT_ALLOC_TME	0x40000	/* top-of-memory enable */
263#define	AMD_WT_ALLOC_PRE	0x20000	/* programmable range enable */
264#define	AMD_WT_ALLOC_FRE	0x10000	/* fixed (A0000-FFFFF) range enable */
265
266
267#ifndef LOCORE
268static __inline u_char
269read_cyrix_reg(u_char reg)
270{
271	outb(0x22, reg);
272	return inb(0x23);
273}
274
275static __inline void
276write_cyrix_reg(u_char reg, u_char data)
277{
278	outb(0x22, reg);
279	outb(0x23, data);
280}
281#endif
282
283#endif /* !_MACHINE_SPECIALREG_H_ */
284