mptable.h revision 26019
1/* 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $Id: mp_machdep.c,v 1.9 1997/05/07 22:25:27 fsmp Exp $ 26 */ 27 28#include "opt_smp.h" 29 30#define FIX_MP_TABLE_WORKS 31 32#include "opt_serial.h" 33 34#include <sys/param.h> /* for KERNBASE */ 35#include <sys/types.h> 36#include <sys/sysproto.h> 37#include <sys/time.h> 38#include <sys/systm.h> 39 40#include <vm/vm.h> /* for KERNBASE */ 41#include <vm/vm_param.h> /* for KERNBASE */ 42#include <vm/pmap.h> /* for KERNBASE */ 43#include <machine/pmap.h> /* for KERNBASE */ 44 45#include <machine/smp.h> 46#include <machine/apic.h> 47#include <machine/mpapic.h> 48#include <machine/cpufunc.h> 49#include <machine/segments.h> 50#include <machine/smptests.h> /** TEST_DEFAULT_CONFIG */ 51 52#include <i386/i386/cons.h> /* cngetc() */ 53 54#if defined(APIC_IO) 55#include <i386/include/md_var.h> /* setidt() */ 56#include <i386/isa/icu.h> /* Xinvltlb() */ 57#include <i386/isa/isa_device.h> /* Xinvltlb() */ 58#endif /* APIC_IO */ 59 60#define WARMBOOT_TARGET 0 61#define WARMBOOT_OFF (KERNBASE + 0x0467) 62#define WARMBOOT_SEG (KERNBASE + 0x0469) 63 64#define BIOS_BASE (0xf0000) 65#define BIOS_SIZE (0x10000) 66#define BIOS_COUNT (BIOS_SIZE/4) 67 68#define CMOS_REG (0x70) 69#define CMOS_DATA (0x71) 70#define BIOS_RESET (0x0f) 71#define BIOS_WARM (0x0a) 72 73/* 74 * this code MUST be enabled here and in mpboot.s. 75 * it follows the very early stages of AP boot by placing values in CMOS ram. 76 * it NORMALLY will never be needed and thus the primitive method for enabling. 77 * 78#define CHECK_POINTS 79 */ 80 81#if defined(CHECK_POINTS) 82#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 83#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 84 85#define CHECK_INIT(D); \ 86 CHECK_WRITE(0x34, (D)); \ 87 CHECK_WRITE(0x35, (D)); \ 88 CHECK_WRITE(0x36, (D)); \ 89 CHECK_WRITE(0x37, (D)); \ 90 CHECK_WRITE(0x38, (D)); \ 91 CHECK_WRITE(0x39, (D)); 92 93#define CHECK_PRINT(S); \ 94 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 95 (S), \ 96 CHECK_READ(0x34), \ 97 CHECK_READ(0x35), \ 98 CHECK_READ(0x36), \ 99 CHECK_READ(0x37), \ 100 CHECK_READ(0x38), \ 101 CHECK_READ(0x39)); 102 103#else /* CHECK_POINTS */ 104 105#define CHECK_INIT(D) 106#define CHECK_PRINT(S) 107 108#endif /* CHECK_POINTS */ 109 110 111/** FIXME: what system files declare these??? */ 112extern struct region_descriptor r_gdt, r_idt; 113 114/* global data */ 115struct proc *SMPcurproc[NCPU]; 116struct pcb *SMPcurpcb[NCPU]; 117struct timeval SMPruntime[NCPU]; 118 119int mp_ncpus; /* # of CPUs, including BSP */ 120int mp_naps; /* # of Applications processors */ 121int mp_nbusses; /* # of busses */ 122int mp_napics; /* # of IO APICs */ 123int mpenabled; 124int boot_cpu_id; /* designated BSP */ 125vm_offset_t cpu_apic_address; 126vm_offset_t io_apic_address[NAPIC]; 127 128u_int32_t cpu_apic_versions[NCPU]; 129u_int32_t io_apic_versions[NAPIC]; 130 131/* 132 * APIC ID logical/physical mapping structures 133 */ 134int cpu_num_to_apic_id[NCPU]; 135int io_num_to_apic_id[NAPIC]; 136int apic_id_to_logical[NAPICID]; 137 138/* 139 * look for MP compliant motherboard. 140 */ 141 142static u_int boot_address; 143static u_int base_memory; 144 145static int picmode; /* 0: virtual wire mode, 1: PIC mode */ 146static u_int mpfps; 147static int search_for_sig(u_int32_t target, int count); 148static int mp_probe(u_int base_top); 149static void mp_enable(u_int boot_addr); 150 151 152/* 153 * calculate usable address in base memory for AP trampoline code 154 */ 155u_int 156mp_bootaddress(u_int basemem) 157{ 158 base_memory = basemem * 1024; /* convert to bytes */ 159 160 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */ 161 if ((base_memory - boot_address) < bootMP_size) 162 boot_address -= 4096; /* not enough, lower by 4k */ 163 164 return boot_address; 165} 166 167 168/* 169 * startup the SMP processors 170 */ 171void 172mp_start(void) 173{ 174 /* look for MP capable motherboard */ 175 if (mp_probe(base_memory)) 176 mp_enable(boot_address); 177 else { 178 printf( "MP FPS not found, can't continue!\n" ); 179 panic( "\n" ); 180 } 181 182 /* finish pmap initialization - turn off V==P mapping at zero */ 183 pmap_bootstrap2(); 184} 185 186 187/* 188 * print various information about the SMP system hardware and setup 189 */ 190void 191mp_announce(void) 192{ 193 int x; 194 195 printf("FreeBSD/SMP: Multiprocessor motherboard\n"); 196 printf(" cpu0 (BSP): apic id: %d", CPU_TO_ID(0)); 197 printf(", version: 0x%08x\n", cpu_apic_versions[0]); 198 for (x = 1; x <= mp_naps; ++x) { 199 printf(" cpu%d (AP): apic id: %d", x, CPU_TO_ID(x)); 200 printf(", version: 0x%08x\n", cpu_apic_versions[x]); 201 } 202 203#if defined(APIC_IO) 204 for (x = 0; x < mp_napics; ++x) { 205 printf(" io%d (APIC): apic id: %d", x, IO_TO_ID(x)); 206 printf(", version: 0x%08x\n", io_apic_versions[x]); 207 } 208#else 209 printf(" Warning: APIC I/O disabled\n"); 210#endif /* APIC_IO */ 211} 212 213 214/* 215 * AP cpu's call this to sync up protected mode. 216 */ 217void 218init_secondary(void) 219{ 220 int gsel_tss, slot; 221 222 r_gdt.rd_limit = sizeof(gdt[0]) * (NGDT + NCPU) - 1; 223 r_gdt.rd_base = (int) gdt; 224 lgdt(&r_gdt); /* does magic intra-segment return */ 225 lidt(&r_idt); 226 lldt(_default_ldt); 227 228 slot = NGDT + cpunumber(); 229 gsel_tss = GSEL(slot, SEL_KPL); 230 gdt[slot].sd.sd_type = SDT_SYS386TSS; 231 ltr(gsel_tss); 232 233 load_cr0(0x8005003b); /* XXX! */ 234} 235 236 237#if defined(APIC_IO) 238void 239configure_local_apic(void) 240{ 241 u_char byte; 242 u_int32_t temp; 243 244 if (picmode) { 245 outb(0x22, 0x70); /* select IMCR */ 246 byte = inb(0x23); /* current contents */ 247 byte |= 0x01; /* mask external INTR */ 248 outb(0x23, byte); /* disconnect 8259s/NMI */ 249 } 250 /* mask the LVT1 */ 251 temp = apic_base[APIC_LVT1]; 252 temp |= APIC_LVT_M; 253 apic_base[APIC_LVT1] = temp; 254} 255#endif /* APIC_IO */ 256 257 258/******************************************************************* 259 * local functions and data 260 */ 261 262static int 263mp_probe(u_int base_top) 264{ 265 int x; 266 u_long segment; 267 u_int32_t target; 268 269 /* see if EBDA exists */ 270 if (segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) { 271 /* search first 1K of EBDA */ 272 target = (u_int32_t) (segment << 4); 273 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 274 goto found; 275 } else { 276 /*last 1K of base memory, effective 'top of base' is passed in*/ 277 target = (u_int32_t) (base_top - 0x400); 278 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 279 goto found; 280 } 281 282 /* search the BIOS */ 283 target = (u_int32_t) BIOS_BASE; 284 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 285 goto found; 286 287 /* nothing found */ 288 mpfps = mpenabled = 0; 289 return 0; 290 291found: /* please forgive the 'goto'! */ 292 /* flag fact that we are running multiple processors */ 293 mpfps = x; 294 mpenabled = 1; 295 return 1; 296} 297 298 299/* 300 * start the SMP system 301 */ 302static int parse_mp_table(void); 303static void default_mp_table(int type); 304static int start_all_aps(u_int boot_addr); 305 306static void 307mp_enable(u_int boot_addr) 308{ 309 int x; 310#if defined(APIC_IO) 311 int apic; 312 u_int ux; 313#endif /* APIC_IO */ 314 315 /* examine the MP table for needed info */ 316 x = parse_mp_table(); 317 318 /* create pages for (address common) cpu APIC and each IO APIC */ 319 pmap_bootstrap_apics(); 320 321 /* can't process default configs till the CPU APIC is pmapped */ 322 if (x) 323 default_mp_table(x); 324 325#if defined(APIC_IO) 326 /* fill the LOGICAL io_apic_versions table */ 327 for (apic = 0; apic < mp_napics; ++apic) { 328 ux = io_apic_read(apic, IOAPIC_VER); 329 io_apic_versions[apic] = ux; 330 } 331 332 /* program each IO APIC in the system */ 333 for (apic = 0; apic < mp_napics; ++apic) 334 if (io_apic_setup(apic) < 0) { 335 printf( "IO APIC setup failure\n" ); 336 panic( "\n" ); 337 } 338 339 /* install an inter-CPU IPI for TLB invalidation */ 340 setidt(ICU_OFFSET + XINVLTLB_OFFSET, Xinvltlb, 341 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 342#endif /* APIC_IO */ 343 344 /* start each Application Processor */ 345 start_all_aps(boot_addr); 346} 347 348 349/* 350 * look for the MP spec signature 351 */ 352 353/* string defined by the Intel MP Spec as identifying the MP table */ 354#define MP_SIG 0x5f504d5f /* _MP_ */ 355#define NEXT(X) ((X) += 4) 356static int 357search_for_sig(u_int32_t target, int count) 358{ 359 int x; 360 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 361 362 for (x = 0; x < count; NEXT(x)) 363 if (addr[x] == MP_SIG) 364 /* make array index a byte index */ 365 return (target + (x * sizeof(u_int32_t))); 366 367 return -1; 368} 369 370 371#define PROCENTRY_FLAG_EN 0x01 372#define PROCENTRY_FLAG_BP 0x02 373#define IOAPICENTRY_FLAG_EN 0x01 374 375/* MP Floating Pointer Structure */ 376typedef struct MPFPS { 377 char signature[4]; 378 void *pap; 379 u_char length; 380 u_char spec_rev; 381 u_char checksum; 382 u_char mpfb1; 383 u_char mpfb2; 384 u_char mpfb3; 385 u_char mpfb4; 386 u_char mpfb5; 387} *mpfps_t; 388/* MP Configuration Table Header */ 389typedef struct MPCTH { 390 char signature[4]; 391 u_short base_table_length; 392 u_char spec_rev; 393 u_char checksum; 394 u_char oem_id[8]; 395 u_char product_id[12]; 396 void *oem_table_pointer; 397 u_short oem_table_size; 398 u_short entry_count; 399 void *apic_address; 400 u_short extended_table_length; 401 u_char extended_table_checksum; 402 u_char reserved; 403} *mpcth_t; 404 405 406typedef struct PROCENTRY { 407 u_char type; 408 u_char apic_id; 409 u_char apic_version; 410 u_char cpu_flags; 411 u_long cpu_signature; 412 u_long feature_flags; 413 u_long reserved1; 414 u_long reserved2; 415} *proc_entry_ptr; 416 417typedef struct BUSENTRY { 418 u_char type; 419 u_char bus_id; 420 char bus_type[6]; 421} *bus_entry_ptr; 422 423typedef struct IOAPICENTRY { 424 u_char type; 425 u_char apic_id; 426 u_char apic_version; 427 u_char apic_flags; 428 void *apic_address; 429} *io_apic_entry_ptr; 430 431typedef struct INTENTRY { 432 u_char type; 433 u_char int_type; 434 u_short int_flags; 435 u_char src_bus_id; 436 u_char src_bus_irq; 437 u_char dst_apic_id; 438 u_char dst_apic_int; 439} *int_entry_ptr; 440/* descriptions of MP basetable entries */ 441typedef struct BASETABLE_ENTRY { 442 u_char type; 443 u_char length; 444 char name[16]; 445} basetable_entry; 446 447static basetable_entry basetable_entry_types[] = 448{ 449 {0, 20, "Processor"}, 450 {1, 8, "Bus"}, 451 {2, 8, "I/O APIC"}, 452 {3, 8, "I/O INT"}, 453 {4, 8, "Local INT"} 454}; 455 456typedef struct BUSDATA { 457 u_char bus_id; 458 enum busTypes bus_type; 459} bus_datum; 460 461typedef struct INTDATA { 462 u_char int_type; 463 u_short int_flags; 464 u_char src_bus_id; 465 u_char src_bus_irq; 466 u_char dst_apic_id; 467 u_char dst_apic_int; 468} io_int, local_int; 469 470typedef struct BUSTYPENAME { 471 u_char type; 472 char name[7]; 473} bus_type_name; 474 475static bus_type_name bus_type_table[] = 476{ 477 {CBUS, "CBUS"}, 478 {CBUSII, "CBUSII"}, 479 {EISA, "EISA"}, 480 {UNKNOWN_BUSTYPE, "---"}, 481 {UNKNOWN_BUSTYPE, "---"}, 482 {ISA, "ISA"}, 483 {UNKNOWN_BUSTYPE, "---"}, 484 {UNKNOWN_BUSTYPE, "---"}, 485 {UNKNOWN_BUSTYPE, "---"}, 486 {UNKNOWN_BUSTYPE, "---"}, 487 {UNKNOWN_BUSTYPE, "---"}, 488 {UNKNOWN_BUSTYPE, "---"}, 489 {PCI, "PCI"}, 490 {UNKNOWN_BUSTYPE, "---"}, 491 {UNKNOWN_BUSTYPE, "---"}, 492 {UNKNOWN_BUSTYPE, "---"}, 493 {UNKNOWN_BUSTYPE, "---"}, 494 {XPRESS, "XPRESS"}, 495 {UNKNOWN_BUSTYPE, "---"} 496}; 497/* from MP spec v1.4, table 5-1 */ 498static int default_data[7][5] = 499{ 500/* nbus, id0, type0, id1, type1 */ 501 {1, 0, ISA, 255, 255}, 502 {1, 0, EISA, 255, 255}, 503 {1, 0, EISA, 255, 255}, 504 {0, 255, 255, 255, 255},/* MCA not supported */ 505 {2, 0, ISA, 1, PCI}, 506 {2, 0, EISA, 1, PCI}, 507 {0, 255, 255, 255, 255} /* MCA not supported */ 508}; 509 510 511/* the bus data */ 512bus_datum bus_data[NBUS]; 513 514/* the IO INT data, one entry per possible APIC INTerrupt */ 515io_int io_apic_ints[NINTR]; 516 517static int nintrs; 518 519#if defined(FIX_MP_TABLE_WORKS) 520static void fix_mp_table __P((void)); 521#endif /* FIX_MP_TABLE_WORKS */ 522 523static void processor_entry __P((proc_entry_ptr entry, int *cpu)); 524static void io_apic_entry __P((io_apic_entry_ptr entry, int *apic)); 525static void bus_entry __P((bus_entry_ptr entry, int *bus)); 526static void int_entry __P((int_entry_ptr entry, int *intr)); 527static int lookup_bus_type __P((char *name)); 528 529 530/* 531 * parse an Intel MP specification table 532 */ 533static int 534parse_mp_table(void) 535{ 536 int x; 537 mpfps_t fps; 538 mpcth_t cth; 539 int totalSize; 540 void *position; 541 int count; 542 int type; 543 int apic, bus, cpu, intr; 544 545 /* clear physical APIC ID to logical CPU/IO table */ 546 for (x = 0; x < NAPICID; ++x) 547 ID_TO_IO(x) = -1; 548 549 /* clear logical CPU to APIC ID table */ 550 for (x = 0; x < NCPU; ++x) 551 CPU_TO_ID(x) = -1; 552 553 /* clear logical IO to APIC ID table */ 554 for (x = 0; x < NAPIC; ++x) 555 IO_TO_ID(x) = -1; 556 557 /* clear IO APIC address table */ 558 for (x = 0; x < NAPIC; ++x) 559 io_apic_address[x] = ~0; 560 561 /* clear bus data table */ 562 for (x = 0; x < NBUS; ++x) 563 bus_data[x].bus_id = 0xff; 564 565 /* clear IO APIC INT table */ 566 for (x = 0; x < NINTR; ++x) 567 io_apic_ints[x].int_type = 0xff; 568 nintrs = 0; 569 570 /* count the BSP */ 571 mp_ncpus = 1; 572 573 /* setup the cpu/apic mapping arrays */ 574 boot_cpu_id = -1; 575 576 /* local pointer */ 577 fps = (mpfps_t) mpfps; 578 579 /* record whether PIC or virtual-wire mode */ 580 picmode = (fps->mpfb2 & 0x80) ? 1 : 0; 581 582 /* check for use of 'default' configuration */ 583#if defined(TEST_DEFAULT_CONFIG) 584 /* use default addresses */ 585 cpu_apic_address = DEFAULT_APIC_BASE; 586 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 587 588 /* return default configuration type */ 589 return TEST_DEFAULT_CONFIG; 590#else 591 if (fps->mpfb1 != 0) { 592 /* use default addresses */ 593 cpu_apic_address = DEFAULT_APIC_BASE; 594 io_apic_address[0] = DEFAULT_IO_APIC_BASE; 595 596 /* return default configuration type */ 597 return fps->mpfb1; 598 } 599#endif /* TEST_DEFAULT_CONFIG */ 600 601 if ((cth = fps->pap) == 0) { 602 printf( "MP Configuration Table Header MISSING!\n" ); 603 panic( "\n" ); 604 } 605 606 cpu_apic_address = (vm_offset_t) cth->apic_address; 607 608 totalSize = cth->base_table_length - sizeof(struct MPCTH); 609 position = (u_char *) cth + sizeof(struct MPCTH); 610 count = cth->entry_count; 611 612 apic = 0; /* logical apic# start @ 0 */ 613 bus = 0; /* logical bus# start @ 0 */ 614 cpu = 1; /* logical cpu# start @ 0, BUT reserve 0 for */ 615 /* BSP */ 616 intr = 0; /* unknown */ 617 618 /* walk the table, recording info of interest */ 619 while (count--) { 620 switch (type = *(u_char *) position) { 621 case 0: 622 processor_entry(position, &cpu); 623 break; 624 case 1: 625 bus_entry(position, &bus); 626 break; 627 case 2: 628 io_apic_entry(position, &apic); 629 break; 630 case 3: 631 int_entry(position, &intr); 632 break; 633 case 4: 634 /* int_entry(position); */ 635 break; 636 default: 637 printf( "mpfps Base Table HOSED!\n" ); 638 panic( "\n" ); 639 /* NOTREACHED */ 640 } 641 642 totalSize -= basetable_entry_types[type].length; 643 (u_char *) position += basetable_entry_types[type].length; 644 } 645 646 if (boot_cpu_id == -1) { 647 printf( "NO BSP found!\n" ); 648 panic( "\n" ); 649 } 650 651 /* record # of APs found */ 652 mp_naps = (cpu - 1); 653 654 /* record # of busses found */ 655 mp_nbusses = bus; 656 657 /* record # of IO APICs found */ 658 mp_napics = apic; 659 660 /* record # of IO APICs found */ 661 nintrs = intr; 662 663#if defined(FIX_MP_TABLE_WORKS) 664 /* post scan cleanup */ 665 fix_mp_table(); 666#endif /* FIX_MP_TABLE_WORKS */ 667 668 /* report fact that its NOT a default configuration */ 669 return 0; 670} 671 672 673/* 674 * parse an Intel MP specification table 675 */ 676#if defined(FIX_MP_TABLE_WORKS) 677static void 678fix_mp_table(void) 679{ 680 int x; 681 int id; 682 int bus_0; 683 int bus_pci; 684 int num_pci_bus; 685 686 /* 687 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS 688 * did it wrong. The MP spec says that when more than 1 PCI bus 689 * exists the BIOS must begin with bus entries for the PCI bus and use 690 * actual PCI bus numbering. This implies that when only 1 PCI bus 691 * exists the BIOS can choose to ignore this ordering, and indeed many 692 * MP motherboards do ignore it. This causes a problem when the PCI 693 * sub-system makes requests of the MP sub-system based on PCI bus 694 * numbers. So here we look for the situation and renumber the 695 * busses and associated INTs in an effort to "make it right". 696 */ 697 698 /* find bus 0, PCI bus, count the number of PCI busses */ 699 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) { 700 if (bus_data[x].bus_id == 0) { 701 bus_0 = x; 702 } 703 if (bus_data[x].bus_type == PCI) { 704 ++num_pci_bus; 705 bus_pci = x; 706 } 707 } 708 /* 709 * bus_0 == slot of bus with ID of 0 710 * bus_pci == slot of last PCI bus encountered 711 */ 712 713 /* check the 1 PCI bus case for sanity */ 714 if (num_pci_bus == 1) { 715 716 /* if it is number 0 all is well */ 717 if (bus_data[bus_pci].bus_id == 0) 718 return; 719 720 /* mis-numbered, swap with whichever bus uses slot 0 */ 721 722 /* swap the bus entry types */ 723 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type; 724 bus_data[bus_0].bus_type = PCI; 725 726 /* swap each relavant INTerrupt entry */ 727 id = bus_data[bus_pci].bus_id; 728 for (x = 0; x < nintrs; ++x) { 729 if (io_apic_ints[x].src_bus_id == id) { 730 io_apic_ints[x].src_bus_id = 0; 731 } 732 else if (io_apic_ints[x].src_bus_id == 0) { 733 io_apic_ints[x].src_bus_id = id; 734 } 735 } 736 } 737 /* sanity check if more than 1 PCI bus */ 738 else if (num_pci_bus > 1) { 739 for (x = 0; x < mp_nbusses; ++x) { 740 if (bus_data[x].bus_type != PCI) 741 continue; 742 if (bus_data[x].bus_id >= num_pci_bus ) { 743 printf( "bad PCI bus numbering\n" ); 744 panic( "\n" ); 745 } 746 } 747 } 748} 749#endif /* FIX_MP_TABLE_WORKS */ 750 751 752static void 753processor_entry(proc_entry_ptr entry, int *cpu) 754{ 755 int x = *cpu; 756 757 /* check for usability */ 758 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN)) 759 return; 760 761 /* check for BSP flag */ 762 if (entry->cpu_flags & PROCENTRY_FLAG_BP) { 763 /* always give boot CPU the logical value of 0 */ 764 x = 0; 765 boot_cpu_id = entry->apic_id; 766 } else { 767 /* add another AP to list, if less than max number of CPUs */ 768 if (x == NCPU) { 769 printf("Warning: only using %d of the available CPUs!\n", x); 770 return; 771 } 772 ++(*cpu); 773 } 774 775 CPU_TO_ID(x) = entry->apic_id; 776 ID_TO_CPU(entry->apic_id) = x; 777} 778 779 780static void 781bus_entry(bus_entry_ptr entry, int *bus) 782{ 783 int x, y; 784 char name[8]; 785 char c; 786 787 if ((x = (*bus)++) == NBUS) { 788 printf( "too many busses, increase 'NBUS'\n" ); 789 panic( "\n" ); 790 } 791 792 /* encode the name into an index */ 793 for (y = 0; y < 6; ++y) { 794 if ((c = entry->bus_type[y]) == ' ') 795 break; 796 name[y] = c; 797 } 798 name[y] = '\0'; 799 800 if ((y = lookup_bus_type(name)) == UNKNOWN_BUSTYPE) { 801 printf( "unknown bus type: '%s'\n", name ); 802 panic( "\n" ); 803 } 804 805 bus_data[x].bus_id = entry->bus_id; 806 bus_data[x].bus_type = y; 807} 808 809 810static void 811io_apic_entry(io_apic_entry_ptr entry, int *apic) 812{ 813 int x; 814 815 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN)) 816 return; 817 818 if ((x = (*apic)++) == NAPIC) { 819 printf( "too many APICs, increase 'NAPIC'\n" ); 820 panic( "\n" ); 821 } 822 823 IO_TO_ID(x) = entry->apic_id; 824 ID_TO_IO(entry->apic_id) = x; 825 826 io_apic_address[x] = (vm_offset_t) entry->apic_address; 827} 828 829 830static int 831lookup_bus_type(char *name) 832{ 833 int x; 834 835 for (x = 0; x < MAX_BUSTYPE; ++x) 836 if (strcmp(bus_type_table[x].name, name) == 0) 837 return bus_type_table[x].type; 838 839 return UNKNOWN_BUSTYPE; 840} 841 842 843static void 844int_entry(int_entry_ptr entry, int *intr) 845{ 846 int x; 847 848 if ((x = (*intr)++) == NINTR) { 849 printf( "too many INTs, increase 'NINTR'\n" ); 850 panic( "\n" ); 851 } 852 853 io_apic_ints[x].int_type = entry->int_type; 854 io_apic_ints[x].int_flags = entry->int_flags; 855 io_apic_ints[x].src_bus_id = entry->src_bus_id; 856 io_apic_ints[x].src_bus_irq = entry->src_bus_irq; 857 io_apic_ints[x].dst_apic_id = entry->dst_apic_id; 858 io_apic_ints[x].dst_apic_int = entry->dst_apic_int; 859} 860 861 862static int 863apic_int_is_bus_type(int intr, int bus_type) 864{ 865 int bus; 866 867 for (bus = 0; bus < mp_nbusses; ++bus) 868 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id) 869 && ((int) bus_data[bus].bus_type == bus_type)) 870 return 1; 871 872 return 0; 873} 874 875 876/* 877 * determine which APIC pin an ISA INT is attached to. 878 */ 879#define INTTYPE(I) (io_apic_ints[(I)].int_type) 880#define INTPIN(I) (io_apic_ints[(I)].dst_apic_int) 881 882#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 883int 884get_isa_apic_irq(int isaIRQ) 885{ 886 int intr; 887 888#if defined(SMP_TIMER_NC) 889 if (isaIRQ == 0) 890 return -1; 891#endif /* SMP_TIMER_NC */ 892 893 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 894 if ((INTTYPE(intr) == 0) 895 && (SRCBUSIRQ(intr) == isaIRQ)) /* a candidate IRQ */ 896 if (apic_int_is_bus_type(intr, ISA)) /* check bus match */ 897 return INTPIN(intr); /* exact match */ 898 899 return -1; /* NOT found */ 900} 901#undef SRCBUSIRQ 902 903 904/* 905 * 906 */ 907u_int 908get_isa_apic_mask(u_int isaMASK) 909{ 910 int apicpin, isairq; 911 912 isairq = ffs(isaMASK); 913 if (isairq == 0) { 914 return 0; 915 } 916 --isairq; 917 918 apicpin = get_isa_apic_irq( isairq ); 919 if (apicpin == -1) { 920 apicpin = get_eisa_apic_irq( isairq ); 921 if (apicpin == -1) { 922 return 0; 923 } 924 } 925 926 return (1 << apicpin); 927} 928 929 930/* 931 * determine which APIC pin an EISA INT is attached to. 932 */ 933#define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq) 934int 935get_eisa_apic_irq(int eisaIRQ) 936{ 937 int intr; 938 939#if defined(SMP_TIMER_NC) 940 if (eisaIRQ == 0) 941 return -1; 942#endif /* SMP_TIMER_NC */ 943 944 for (intr = 0; intr < nintrs; ++intr) /* search each INT record */ 945 if ((INTTYPE(intr) == 0) 946 && (SRCBUSIRQ(intr) == eisaIRQ)) /* a candidate IRQ */ 947 if (apic_int_is_bus_type(intr, EISA)) /* check bus match */ 948 return INTPIN(intr); /* exact match */ 949 950 return -1; /* NOT found */ 951} 952#undef SRCBUSIRQ 953 954 955/* 956 * determine which APIC pin a PCI INT is attached to. 957 */ 958#define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id) 959#define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f) 960#define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03) 961int 962get_pci_apic_irq(int pciBus, int pciDevice, int pciInt) 963{ 964 int intr; 965 966 --pciInt; /* zero based */ 967 968 for (intr = 0; intr < nintrs; ++intr) /* search each record */ 969 if ((INTTYPE(intr) == 0) 970#if defined(FIX_MP_TABLE_WORKS) 971 && (SRCBUSID(intr) == pciBus) 972#endif /* FIX_MP_TABLE_WORKS */ 973 && (SRCBUSDEVICE(intr) == pciDevice) 974 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */ 975 if (apic_int_is_bus_type(intr, PCI)) /* check bus match */ 976 return INTPIN(intr); /* exact match */ 977 978 return -1; /* NOT found */ 979} 980#undef SRCBUSLINE 981#undef SRCBUSDEVICE 982#undef SRCBUSID 983 984#undef INTPIN 985#undef INTTYPE 986 987 988/* 989 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt 990 */ 991int 992undirect_pci_irq(int rirq) 993{ 994#if defined(READY) 995 printf("Freeing redirected PCI irq %d.\n", rirq); 996 /** FIXME: tickle the MB redirector chip */ 997 return ???; 998#else 999 printf("Freeing (NOT implemented) redirected PCI irq %d.\n", rirq); 1000 return 0; 1001#endif /* READY */ 1002} 1003 1004 1005/* 1006 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt. 1007 * 1008 * XXX FIXME: 1009 * Exactly what this means is unclear at this point. It is a solution 1010 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard 1011 * could route any of the ISA INTs to upper (>15) IRQ values. But most would 1012 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an 1013 * option. 1014 */ 1015int 1016undirect_isa_irq(int rirq) 1017{ 1018#if defined(READY) 1019 printf("Freeing redirected ISA irq %d.\n", rirq); 1020 /** FIXME: tickle the MB redirector chip */ 1021 return ???; 1022#else 1023 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq); 1024 return 0; 1025#endif /* READY */ 1026} 1027 1028 1029/* 1030 * given a bus ID, return: 1031 * the bus type if found 1032 * -1 if NOT found 1033 */ 1034int 1035apic_bus_type(int id) 1036{ 1037 int x; 1038 1039 for (x = 0; x < mp_nbusses; ++x) 1040 if (bus_data[x].bus_id == id) 1041 return bus_data[x].bus_type; 1042 1043 return -1; 1044} 1045 1046 1047/* 1048 * given a LOGICAL APIC# and pin#, return: 1049 * the associated src bus ID if found 1050 * -1 if NOT found 1051 */ 1052int 1053apic_src_bus_id(int apic, int pin) 1054{ 1055 int x; 1056 1057 /* search each of the possible INTerrupt sources */ 1058 for (x = 0; x < nintrs; ++x) 1059 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1060 (pin == io_apic_ints[x].dst_apic_int)) 1061 return (io_apic_ints[x].src_bus_id); 1062 1063 return -1; /* NOT found */ 1064} 1065 1066 1067/* 1068 * given a LOGICAL APIC# and pin#, return: 1069 * the associated src bus IRQ if found 1070 * -1 if NOT found 1071 */ 1072int 1073apic_src_bus_irq(int apic, int pin) 1074{ 1075 int x; 1076 1077 for (x = 0; x < nintrs; x++) 1078 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1079 (pin == io_apic_ints[x].dst_apic_int)) 1080 return (io_apic_ints[x].src_bus_irq); 1081 1082 return -1; /* NOT found */ 1083} 1084 1085 1086/* 1087 * given a LOGICAL APIC# and pin#, return: 1088 * the associated INTerrupt type if found 1089 * -1 if NOT found 1090 */ 1091int 1092apic_int_type(int apic, int pin) 1093{ 1094 int x; 1095 1096 /* search each of the possible INTerrupt sources */ 1097 for (x = 0; x < nintrs; ++x) 1098 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1099 (pin == io_apic_ints[x].dst_apic_int)) 1100 return (io_apic_ints[x].int_type); 1101 1102 return -1; /* NOT found */ 1103} 1104 1105 1106/* 1107 * given a LOGICAL APIC# and pin#, return: 1108 * the associated trigger mode if found 1109 * -1 if NOT found 1110 */ 1111int 1112apic_trigger(int apic, int pin) 1113{ 1114 int x; 1115 1116 /* search each of the possible INTerrupt sources */ 1117 for (x = 0; x < nintrs; ++x) 1118 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1119 (pin == io_apic_ints[x].dst_apic_int)) 1120 return ((io_apic_ints[x].int_flags >> 2) & 0x03); 1121 1122 return -1; /* NOT found */ 1123} 1124 1125 1126/* 1127 * given a LOGICAL APIC# and pin#, return: 1128 * the associated 'active' level if found 1129 * -1 if NOT found 1130 */ 1131int 1132apic_polarity(int apic, int pin) 1133{ 1134 int x; 1135 1136 /* search each of the possible INTerrupt sources */ 1137 for (x = 0; x < nintrs; ++x) 1138 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) && 1139 (pin == io_apic_ints[x].dst_apic_int)) 1140 return (io_apic_ints[x].int_flags & 0x03); 1141 1142 return -1; /* NOT found */ 1143} 1144 1145 1146/* 1147 * set data according to MP defaults 1148 * FIXME: probably not complete yet... 1149 */ 1150static void 1151default_mp_table(int type) 1152{ 1153 int ap_cpu_id; 1154#if defined(APIC_IO) 1155 u_int32_t ux; 1156 int io_apic_id; 1157 int pin; 1158#endif /* APIC_IO */ 1159 1160#if 0 1161 printf(" MP default config type: %d\n", type); 1162 switch (type) { 1163 case 1: 1164 printf(" bus: ISA, APIC: 82489DX\n"); 1165 break; 1166 case 2: 1167 printf(" bus: EISA, APIC: 82489DX\n"); 1168 break; 1169 case 3: 1170 printf(" bus: EISA, APIC: 82489DX\n"); 1171 break; 1172 case 4: 1173 printf(" bus: MCA, APIC: 82489DX\n"); 1174 break; 1175 case 5: 1176 printf(" bus: ISA+PCI, APIC: Integrated\n"); 1177 break; 1178 case 6: 1179 printf(" bus: EISA+PCI, APIC: Integrated\n"); 1180 break; 1181 case 7: 1182 printf(" bus: MCA+PCI, APIC: Integrated\n"); 1183 break; 1184 default: 1185 printf(" future type\n"); 1186 break; 1187 /* NOTREACHED */ 1188 } 1189#endif /* 0 */ 1190 1191 boot_cpu_id = (apic_base[APIC_ID] & APIC_ID_MASK) >> 24; 1192 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0; 1193 1194 /* BSP */ 1195 CPU_TO_ID(0) = boot_cpu_id; 1196 ID_TO_CPU(boot_cpu_id) = 0; 1197 1198 /* one and only AP */ 1199 CPU_TO_ID(1) = ap_cpu_id; 1200 ID_TO_CPU(ap_cpu_id) = 1; 1201 mp_naps = 1; 1202 1203 /* one and only IO APIC */ 1204#if defined(APIC_IO) 1205 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24; 1206 1207 /* 1208 * sanity check, refer to MP spec section 3.6.6, last paragraph 1209 * necessary as some hardware isn't properly setting up the IO APIC 1210 */ 1211#if defined(REALLY_ANAL_IOAPICID_VALUE) 1212 if (io_apic_id != 2) { 1213#else 1214 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) { 1215#endif /* REALLY_ANAL_IOAPICID_VALUE */ 1216 ux = io_apic_read(0, IOAPIC_ID); /* get current contents */ 1217 ux &= ~APIC_ID_MASK; /* clear the ID field */ 1218 ux |= 0x02000000; /* set it to '2' */ 1219 io_apic_write(0, IOAPIC_ID, ux); /* write new value */ 1220 ux = io_apic_read(0, IOAPIC_ID); /* re-read && test */ 1221 if ((ux & APIC_ID_MASK) != 0x02000000) { 1222 printf( "can't control IO APIC ID, reg: 0x%08x\n", ux ); 1223 panic( "\n" ); 1224 } 1225 io_apic_id = 2; 1226 } 1227 IO_TO_ID(0) = io_apic_id; 1228 ID_TO_IO(io_apic_id) = 0; 1229 mp_napics = 1; 1230#else 1231 mp_napics = 0; 1232#endif /* APIC_IO */ 1233 1234 /* fill out bus entries */ 1235 switch (type) { 1236 case 1: 1237 case 2: 1238 case 3: 1239 case 5: 1240 case 6: 1241 mp_nbusses = default_data[type - 1][0]; 1242 bus_data[0].bus_id = default_data[type - 1][1]; 1243 bus_data[0].bus_type = default_data[type - 1][2]; 1244 bus_data[1].bus_id = default_data[type - 1][3]; 1245 bus_data[1].bus_type = default_data[type - 1][4]; 1246 break; 1247 1248 /* case 4: case 7: MCA NOT supported */ 1249 default: /* illegal/reserved */ 1250 printf( "BAD default MP config: %d\n", type ); 1251 panic( "\n" ); 1252 } 1253 1254#if defined(APIC_IO) 1255 /* general cases from MP v1.4, table 5-2 */ 1256 for (pin = 0; pin < 16; ++pin) { 1257 io_apic_ints[pin].int_type = 0; 1258 io_apic_ints[pin].int_flags = 0x05; /* edge-triggered/active-hi */ 1259 io_apic_ints[pin].src_bus_id = 0; 1260 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 is caught below */ 1261 io_apic_ints[pin].dst_apic_id = io_apic_id; 1262 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 correspondence */ 1263 } 1264 1265 /* special cases from MP v1.4, table 5-2 */ 1266 if (type == 2) { 1267 io_apic_ints[2].int_type = 0xff; /* N/C */ 1268 io_apic_ints[13].int_type = 0xff; /* N/C */ 1269#if !defined(APIC_MIXED_MODE) 1270 /** FIXME: ??? */ 1271 printf( "sorry, can't support type 2 default yet\n" ); 1272 panic( "\n" ); 1273#endif /* APIC_MIXED_MODE */ 1274 } 1275 else 1276 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */ 1277 1278 if (type == 7) 1279 io_apic_ints[0].int_type = 0xff; /* N/C */ 1280 else 1281 io_apic_ints[0].int_type = 3; /* vectored 8259 */ 1282 1283 nintrs = 16; 1284#endif /* APIC_IO */ 1285} 1286 1287 1288static void install_ap_tramp(u_int boot_addr); 1289static int start_ap(int logicalCpu, u_int boot_addr); 1290 1291/* 1292 * start each AP in our list 1293 */ 1294static int 1295start_all_aps(u_int boot_addr) 1296{ 1297 int x; 1298 u_char mpbiosreason; 1299 u_long mpbioswarmvec; 1300 1301 /** 1302 * NOTE: this needs further thought: 1303 * where does it get released? 1304 * should it be set to empy? 1305 * 1306 * get the initial mp_lock with a count of 1 for the BSP 1307 */ 1308 mp_lock = (apic_base[APIC_ID] & APIC_ID_MASK) + 1; 1309 1310 /* initialize BSP's local APIC */ 1311 apic_initialize(1); 1312 1313 /* install the AP 1st level boot code */ 1314 install_ap_tramp(boot_addr); 1315 1316 /* save the current value of the warm-start vector */ 1317 mpbioswarmvec = *((u_long *) WARMBOOT_OFF); 1318 outb(CMOS_REG, BIOS_RESET); 1319 mpbiosreason = inb(CMOS_DATA); 1320 1321 /* start each AP */ 1322 for (x = 1; x <= mp_naps; ++x) { 1323 1324 /* setup a vector to our boot code */ 1325 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 1326 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4); 1327 outb(CMOS_REG, BIOS_RESET); 1328 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 1329 1330 /* attempt to start the Application Processor */ 1331 CHECK_INIT(99); /* setup checkpoints */ 1332 if (!start_ap(x, boot_addr)) { 1333 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x)); 1334 CHECK_PRINT("trace"); /* show checkpoints */ 1335 /* 1336 * better panic as the AP may be running loose 1337 * somewhere 1338 */ 1339 printf("panic y/n? [n] "); 1340 if (cngetc() != 'n') { 1341 printf( "bye-bye\n" ); 1342 panic( "\n" ); 1343 } 1344 } 1345 CHECK_PRINT("trace"); /* show checkpoints */ 1346 1347 /* record its version info */ 1348 cpu_apic_versions[x] = cpu_apic_versions[0]; 1349 } 1350 1351 /* fill in our (BSP) APIC version */ 1352 cpu_apic_versions[0] = apic_base[APIC_VER]; 1353 1354 /* restore the warmstart vector */ 1355 *(u_long *) WARMBOOT_OFF = mpbioswarmvec; 1356 outb(CMOS_REG, BIOS_RESET); 1357 outb(CMOS_DATA, mpbiosreason); 1358 1359 /* number of APs actually started */ 1360 return mp_ncpus - 1; 1361} 1362 1363 1364/* 1365 * load the 1st level AP boot code into base memory. 1366 */ 1367 1368/* targets for relocation */ 1369extern void bigJump(void); 1370extern void bootCodeSeg(void); 1371extern void bootDataSeg(void); 1372extern void MPentry(void); 1373extern u_int MP_GDT; 1374extern u_int mp_gdtbase; 1375 1376static void 1377install_ap_tramp(u_int boot_addr) 1378{ 1379 int x; 1380 int size = *(int *) ((u_long) & bootMP_size); 1381 u_char *src = (u_char *) ((u_long) bootMP); 1382 u_char *dst = (u_char *) boot_addr + KERNBASE; 1383 u_int boot_base = (u_int) bootMP; 1384 u_int8_t *dst8; 1385 u_int16_t *dst16; 1386 u_int32_t *dst32; 1387 1388 for (x = 0; x < size; ++x) 1389 *dst++ = *src++; 1390 1391 /* 1392 * modify addresses in code we just moved to basemem. unfortunately we 1393 * need fairly detailed info about mpboot.s for this to work. changes 1394 * to mpboot.s might require changes here. 1395 */ 1396 1397 /* boot code is located in KERNEL space */ 1398 dst = (u_char *) boot_addr + KERNBASE; 1399 1400 /* modify the lgdt arg */ 1401 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1402 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base); 1403 1404 /* modify the ljmp target for MPentry() */ 1405 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1406 *dst32 = ((u_int) MPentry - KERNBASE); 1407 1408 /* modify the target for boot code segment */ 1409 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1410 dst8 = (u_int8_t *) (dst16 + 1); 1411 *dst16 = (u_int) boot_addr & 0xffff; 1412 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1413 1414 /* modify the target for boot data segment */ 1415 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1416 dst8 = (u_int8_t *) (dst16 + 1); 1417 *dst16 = (u_int) boot_addr & 0xffff; 1418 *dst8 = ((u_int) boot_addr >> 16) & 0xff; 1419} 1420 1421 1422/* 1423 * this function starts the AP (application processor) identified 1424 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1425 * to accomplish this. This is necessary because of the nuances 1426 * of the different hardware we might encounter. It ain't pretty, 1427 * but it seems to work. 1428 */ 1429static int 1430start_ap(int logical_cpu, u_int boot_addr) 1431{ 1432 int physical_cpu; 1433 int vector; 1434 int cpus; 1435 u_long icr_lo, icr_hi; 1436 1437 /* get the PHYSICAL APIC ID# */ 1438 physical_cpu = CPU_TO_ID(logical_cpu); 1439 1440 /* calculate the vector */ 1441 vector = (boot_addr >> 12) & 0xff; 1442 1443 /* used as a watchpoint to signal AP startup */ 1444 cpus = mp_ncpus; 1445 1446 /* 1447 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1448 * and running the target CPU. OR this INIT IPI might be latched (P5 1449 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1450 * ignored. 1451 */ 1452 1453 /* setup the address for the target AP */ 1454 icr_hi = apic_base[APIC_ICR_HI] & ~APIC_ID_MASK; 1455 icr_hi |= (physical_cpu << 24); 1456 apic_base[APIC_ICR_HI] = icr_hi; 1457 1458 /* do an INIT IPI: assert RESET */ 1459 icr_lo = apic_base[APIC_ICR_LOW] & 0xfff00000; 1460 apic_base[APIC_ICR_LOW] = icr_lo | 0x0000c500; 1461 1462 /* wait for pending status end */ 1463 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1464 /* spin */ ; 1465 1466 /* do an INIT IPI: deassert RESET */ 1467 apic_base[APIC_ICR_LOW] = icr_lo | 0x00008500; 1468 1469 /* wait for pending status end */ 1470 u_sleep(10000); /* wait ~10mS */ 1471 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1472 /* spin */ ; 1473 1474 /* 1475 * next we do a STARTUP IPI: the previous INIT IPI might still be 1476 * latched, (P5 bug) this 1st STARTUP would then terminate 1477 * immediately, and the previously started INIT IPI would continue. OR 1478 * the previous INIT IPI has already run. and this STARTUP IPI will 1479 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1480 * will run. 1481 */ 1482 1483 /* do a STARTUP IPI */ 1484 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1485 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1486 /* spin */ ; 1487 u_sleep(200); /* wait ~200uS */ 1488 1489 /* 1490 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1491 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1492 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1493 * recognized after hardware RESET or INIT IPI. 1494 */ 1495 1496 apic_base[APIC_ICR_LOW] = icr_lo | 0x00000600 | vector; 1497 while (apic_base[APIC_ICR_LOW] & APIC_DELSTAT_MASK) 1498 /* spin */ ; 1499 u_sleep(200); /* wait ~200uS */ 1500 1501 /* wait for it to start */ 1502 set_apic_timer(5000000);/* == 5 seconds */ 1503 while (read_apic_timer()) 1504 if (mp_ncpus > cpus) 1505 return 1; /* return SUCCESS */ 1506 1507 return 0; /* return FAILURE */ 1508} 1509 1510 1511/* 1512 * Flush the TLB on all other CPU's 1513 * 1514 * XXX: Needs to handshake and wait for completion before proceding. 1515 */ 1516void 1517smp_invltlb(void) 1518{ 1519#if defined(APIC_IO) 1520 if (smp_active && invltlb_ok) 1521 all_but_self_ipi(ICU_OFFSET + XINVLTLB_OFFSET); 1522#endif /* APIC_IO */ 1523} 1524 1525void 1526invlpg(u_int addr) 1527{ 1528 __asm __volatile("invlpg (%0)"::"r"(addr):"memory"); 1529 1530 /* send a message to the other CPUs */ 1531 smp_invltlb(); 1532} 1533 1534void 1535invltlb(void) 1536{ 1537 u_long temp; 1538 1539 /* 1540 * This should be implemented as load_cr3(rcr3()) when load_cr3() is 1541 * inlined. 1542 */ 1543 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3":"=r"(temp) :: "memory"); 1544 1545 /* send a message to the other CPUs */ 1546 smp_invltlb(); 1547} 1548