ata.h revision 93881
174298Ssos/*- 291645Ssos * Copyright (c) 2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 374298Ssos * All rights reserved. 474298Ssos * 574298Ssos * Redistribution and use in source and binary forms, with or without 674298Ssos * modification, are permitted provided that the following conditions 774298Ssos * are met: 874298Ssos * 1. Redistributions of source code must retain the above copyright 974298Ssos * notice, this list of conditions and the following disclaimer, 1074298Ssos * without modification, immediately at the beginning of the file. 1174298Ssos * 2. Redistributions in binary form must reproduce the above copyright 1274298Ssos * notice, this list of conditions and the following disclaimer in the 1374298Ssos * documentation and/or other materials provided with the distribution. 1474298Ssos * 3. The name of the author may not be used to endorse or promote products 1574298Ssos * derived from this software without specific prior written permission. 1674298Ssos * 1774298Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1874298Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1974298Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2074298Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2174298Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2274298Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2374298Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2474298Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2574298Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2674298Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2774298Ssos * 2874298Ssos * $FreeBSD: head/sys/sys/ata.h 93881 2002-04-05 13:10:26Z sos $ 2974298Ssos */ 3074298Ssos 3174298Ssos#ifndef _SYS_ATA_H_ 3274298Ssos#define _SYS_ATA_H_ 3374298Ssos 3474298Ssos#include <sys/ioccom.h> 3574298Ssos 3682560Ssos#define ATAPI_PSIZE_12 0 /* 12 bytes */ 3782560Ssos#define ATAPI_PSIZE_16 1 /* 16 bytes */ 3874298Ssos 3982560Ssos#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */ 4082560Ssos#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */ 4182560Ssos#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */ 4274298Ssos 4382560Ssos#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */ 4482560Ssos#define ATAPI_TYPE_TAPE 1 /* streaming tape */ 4582560Ssos#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */ 4682560Ssos#define ATAPI_TYPE_OPTICAL 7 /* optical disk */ 4774298Ssos 4884584Ssos#define ATA_PROTO_ATA 0 4984584Ssos#define ATA_PROTO_ATAPI 1 5074298Ssos 5193881Ssos#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */ 5293881Ssos#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */ 5393881Ssos#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */ 5493881Ssos 5593881Ssos#define ATA_FLAG_54_58 1 /* words 54-58 valid */ 5693881Ssos#define ATA_FLAG_64_70 2 /* words 64-70 valid */ 5793881Ssos#define ATA_FLAG_88 4 /* word 88 valid */ 5893881Ssos 5993881Ssos/* ATA/ATAPI device parameter information */ 6093881Ssosstruct ata_params { 6193881Ssos 6293881Ssos#if BYTE_ORDER == LITTLE_ENDIAN 6393881Ssos/*000*/ u_int16_t packet_size :2; /* packet command size */ 6493881Ssos 6593881Ssos u_int16_t incomplete :1; 6693881Ssos u_int16_t :2; 6793881Ssos u_int16_t drq_type :2; /* DRQ type */ 6893881Ssos 6993881Ssos u_int16_t removable :1; /* device is removable */ 7093881Ssos u_int16_t type :5; /* device type */ 7193881Ssos 7293881Ssos u_int16_t :2; 7393881Ssos u_int16_t cmd_protocol :1; /* command protocol */ 7493881Ssos#else 7593881Ssos u_int16_t cmd_protocol :1; /* command protocol */ 7693881Ssos u_int16_t :2; 7793881Ssos 7893881Ssos u_int16_t type :5; /* device type */ 7993881Ssos u_int16_t removable :1; /* device is removable */ 8093881Ssos 8193881Ssos u_int16_t drq_type :2; /* DRQ type */ 8293881Ssos u_int16_t :2; 8393881Ssos u_int16_t incomplete :1; 8493881Ssos 8593881Ssos u_int16_t packet_size :2; /* packet command size */ 8693881Ssos#endif 8793881Ssos 8884584Ssos/*001*/ u_int16_t cylinders; /* # of cylinders */ 8984584Ssos u_int16_t reserved2; 9084584Ssos/*003*/ u_int16_t heads; /* # heads */ 9184584Ssos u_int16_t obsolete4; 9284584Ssos u_int16_t obsolete5; 9384584Ssos/*006*/ u_int16_t sectors; /* # sectors/track */ 9484584Ssos/*007*/ u_int16_t vendor7[3]; 9584584Ssos/*010*/ u_int8_t serial[20]; /* serial number */ 9684584Ssos u_int16_t retired20; 9784584Ssos u_int16_t retired21; 9884584Ssos u_int16_t obsolete22; 9984584Ssos/*023*/ u_int8_t revision[8]; /* firmware revision */ 10084584Ssos/*027*/ u_int8_t model[40]; /* model name */ 10193881Ssos 10293881Ssos#if BYTE_ORDER == LITTLE_ENDIAN 10384584Ssos/*047*/ u_int16_t sectors_intr:8; /* sectors per interrupt */ 10484584Ssos u_int16_t :8; 10593881Ssos#else 10693881Ssos u_int16_t :8; 10793881Ssos u_int16_t sectors_intr:8; /* sectors per interrupt */ 10893881Ssos#endif 10974298Ssos 11084584Ssos/*048*/ u_int16_t usedmovsd; /* double word read/write? */ 11193881Ssos 11293881Ssos#if BYTE_ORDER == LITTLE_ENDIAN 11384584Ssos/*049*/ u_int16_t retired49:8; 11484584Ssos u_int16_t support_dma :1; /* DMA supported */ 11584584Ssos u_int16_t support_lba :1; /* LBA supported */ 11684584Ssos u_int16_t disable_iordy :1; /* IORDY may be disabled */ 11784584Ssos u_int16_t support_iordy :1; /* IORDY supported */ 11884584Ssos u_int16_t softreset :1; /* needs softreset when busy */ 11984584Ssos u_int16_t stdby_ovlap :1; /* standby/overlap supported */ 12084584Ssos u_int16_t support_queueing:1; /* supports queuing overlap */ 12184584Ssos u_int16_t support_idma :1; /* interleaved DMA supported */ 12274298Ssos 12384584Ssos/*050*/ u_int16_t device_stdby_min:1; 12484584Ssos u_int16_t :13; 12584584Ssos u_int16_t capability_one:1; 12684584Ssos u_int16_t capability_zero:1; 12774298Ssos 12884584Ssos/*051*/ u_int16_t vendor51:8; 12984584Ssos u_int16_t retired_piomode:8; /* PIO modes 0-2 */ 13084584Ssos/*052*/ u_int16_t vendor52:8; 13184584Ssos u_int16_t retired_dmamode:8; /* DMA modes, not ATA-3 */ 13293881Ssos#else 13393881Ssos u_int16_t support_idma :1; /* interleaved DMA supported */ 13493881Ssos u_int16_t support_queueing:1; /* supports queuing overlap */ 13593881Ssos u_int16_t stdby_ovlap :1; /* standby/overlap supported */ 13693881Ssos u_int16_t softreset :1; /* needs softreset when busy */ 13793881Ssos u_int16_t support_iordy :1; /* IORDY supported */ 13893881Ssos u_int16_t disable_iordy :1; /* IORDY may be disabled */ 13993881Ssos u_int16_t support_lba :1; /* LBA supported */ 14093881Ssos u_int16_t support_dma :1; /* DMA supported */ 14193881Ssos u_int16_t retired49:8; 14293881Ssos 14393881Ssos u_int16_t capability_zero:1; 14493881Ssos u_int16_t capability_one:1; 14593881Ssos u_int16_t :13; 14693881Ssos u_int16_t device_stdby_min:1; 14793881Ssos 14893881Ssos u_int16_t retired_piomode:8; /* PIO modes 0-2 */ 14993881Ssos u_int16_t vendor51:8; 15093881Ssos u_int16_t retired_dmamode:8; /* DMA modes, not ATA-3 */ 15193881Ssos u_int16_t vendor52:8; 15293881Ssos#endif 15393881Ssos 15484584Ssos/*053*/ u_int16_t atavalid; /* fields valid */ 15574298Ssos 15684584Ssos u_int16_t obsolete54[5]; 15793881Ssos 15893881Ssos#if BYTE_ORDER == LITTLE_ENDIAN 15984584Ssos/*059*/ u_int16_t multi_count:8; 16084584Ssos u_int16_t multi_valid:1; 16184584Ssos u_int16_t :7; 16293881Ssos#else 16393881Ssos u_int16_t :7; 16493881Ssos u_int16_t multi_valid:1; 16593881Ssos u_int16_t multi_count:8; 16693881Ssos#endif 16774298Ssos 16893881Ssos/*060*/ u_int16_t lba_size_lo; 16993881Ssos u_int16_t lba_size_hi; 17084584Ssos u_int16_t obsolete62; 17184584Ssos/*063*/ u_int16_t mwdmamodes; /* multiword DMA modes */ 17284584Ssos/*064*/ u_int16_t apiomodes; /* advanced PIO modes */ 17374298Ssos 17484584Ssos/*065*/ u_int16_t mwdmamin; /* min. M/W DMA time/word ns */ 17584584Ssos/*066*/ u_int16_t mwdmarec; /* rec. M/W DMA time ns */ 17684584Ssos/*067*/ u_int16_t pioblind; /* min. PIO cycle w/o flow */ 17784584Ssos/*068*/ u_int16_t pioiordy; /* min. PIO cycle IORDY flow */ 17884584Ssos u_int16_t reserved69; 17984584Ssos u_int16_t reserved70; 18084584Ssos/*071*/ u_int16_t rlsovlap; /* rel time (us) for overlap */ 18184584Ssos/*072*/ u_int16_t rlsservice; /* rel time (us) for service */ 18284584Ssos u_int16_t reserved73; 18384584Ssos u_int16_t reserved74; 18474298Ssos 18593881Ssos#if BYTE_ORDER == LITTLE_ENDIAN 18684584Ssos/*075*/ u_int16_t queuelen:5; 18784584Ssos u_int16_t :11; 18893881Ssos#else 18993881Ssos u_int16_t :11; 19093881Ssos u_int16_t queuelen:5; 19193881Ssos#endif 19284584Ssos 19384584Ssos u_int16_t reserved76; 19484584Ssos u_int16_t reserved77; 19584584Ssos u_int16_t reserved78; 19684584Ssos u_int16_t reserved79; 19784584Ssos/*080*/ u_int16_t version_major; 19884584Ssos/*081*/ u_int16_t version_minor; 19984584Ssos struct { 20093881Ssos#if BYTE_ORDER == LITTLE_ENDIAN 20184584Ssos/*082/085*/ u_int16_t smart:1; 20284584Ssos u_int16_t security:1; 20384584Ssos u_int16_t removable:1; 20484584Ssos u_int16_t power_mngt:1; 20584584Ssos u_int16_t packet:1; 20684584Ssos u_int16_t write_cache:1; 20784584Ssos u_int16_t look_ahead:1; 20884584Ssos u_int16_t release_irq:1; 20984584Ssos u_int16_t service_irq:1; 21084584Ssos u_int16_t reset:1; 21184584Ssos u_int16_t protected:1; 21284584Ssos u_int16_t :1; 21384584Ssos u_int16_t write_buffer:1; 21484584Ssos u_int16_t read_buffer:1; 21584584Ssos u_int16_t nop:1; 21684584Ssos u_int16_t :1; 21784584Ssos 21884584Ssos/*083/086*/ u_int16_t microcode:1; 21984584Ssos u_int16_t queued:1; 22084584Ssos u_int16_t cfa:1; 22184584Ssos u_int16_t apm:1; 22284584Ssos u_int16_t notify:1; 22384584Ssos u_int16_t standby:1; 22484584Ssos u_int16_t spinup:1; 22584584Ssos u_int16_t :1; 22684584Ssos u_int16_t max_security:1; 22784584Ssos u_int16_t auto_acoustic:1; 22884584Ssos u_int16_t address48:1; 22984584Ssos u_int16_t config_overlay:1; 23084584Ssos u_int16_t flush_cache:1; 23184584Ssos u_int16_t flush_cache48:1; 23284584Ssos u_int16_t support_one:1; 23384584Ssos u_int16_t support_zero:1; 23484584Ssos 23584584Ssos/*084/087*/ u_int16_t smart_error_log:1; 23684584Ssos u_int16_t smart_self_test:1; 23784584Ssos u_int16_t media_serial_no:1; 23884584Ssos u_int16_t media_card_pass:1; 23984584Ssos u_int16_t streaming:1; 24084584Ssos u_int16_t logging:1; 24184584Ssos u_int16_t :8; 24284584Ssos u_int16_t extended_one:1; 24384584Ssos u_int16_t extended_zero:1; 24493881Ssos#else 24593881Ssos u_int16_t :1; 24693881Ssos u_int16_t nop:1; 24793881Ssos u_int16_t read_buffer:1; 24893881Ssos u_int16_t write_buffer:1; 24993881Ssos u_int16_t :1; 25093881Ssos u_int16_t protected:1; 25193881Ssos u_int16_t reset:1; 25293881Ssos u_int16_t service_irq:1; 25393881Ssos u_int16_t release_irq:1; 25493881Ssos u_int16_t look_ahead:1; 25593881Ssos u_int16_t write_cache:1; 25693881Ssos u_int16_t packet:1; 25793881Ssos u_int16_t power_mngt:1; 25893881Ssos u_int16_t removable:1; 25993881Ssos u_int16_t security:1; 26093881Ssos u_int16_t smart:1; 26193881Ssos 26293881Ssos u_int16_t support_zero:1; 26393881Ssos u_int16_t support_one:1; 26493881Ssos u_int16_t flush_cache48:1; 26593881Ssos u_int16_t flush_cache:1; 26693881Ssos u_int16_t config_overlay:1; 26793881Ssos u_int16_t address48:1; 26893881Ssos u_int16_t auto_acoustic:1; 26993881Ssos u_int16_t max_security:1; 27093881Ssos u_int16_t :1; 27193881Ssos u_int16_t spinup:1; 27293881Ssos u_int16_t standby:1; 27393881Ssos u_int16_t notify:1; 27493881Ssos u_int16_t apm:1; 27593881Ssos u_int16_t cfa:1; 27693881Ssos u_int16_t queued:1; 27793881Ssos u_int16_t microcode:1; 27893881Ssos 27993881Ssos u_int16_t extended_zero:1; 28093881Ssos u_int16_t extended_one:1; 28193881Ssos u_int16_t :8; 28293881Ssos u_int16_t logging:1; 28393881Ssos u_int16_t streaming:1; 28493881Ssos u_int16_t media_card_pass:1; 28593881Ssos u_int16_t media_serial_no:1; 28693881Ssos u_int16_t smart_self_test:1; 28793881Ssos u_int16_t smart_error_log:1; 28893881Ssos#endif 28984584Ssos } support, enabled; 29084584Ssos 29184584Ssos/*088*/ u_int16_t udmamodes; /* UltraDMA modes */ 29284584Ssos/*089*/ u_int16_t erase_time; 29384584Ssos/*090*/ u_int16_t enhanced_erase_time; 29484584Ssos/*091*/ u_int16_t apm_value; 29584584Ssos/*092*/ u_int16_t master_passwd_revision; 29684584Ssos 29793881Ssos#if BYTE_ORDER == LITTLE_ENDIAN 29884584Ssos/*093*/ u_int16_t hwres_master :8; 29984584Ssos u_int16_t hwres_slave :5; 30084584Ssos u_int16_t hwres_cblid :1; 30184584Ssos u_int16_t hwres_valid:2; 30284584Ssos 30384584Ssos/*094*/ u_int16_t current_acoustic:8; 30484584Ssos u_int16_t vendor_acoustic:8; 30593881Ssos#else 30693881Ssos u_int16_t hwres_valid:2; 30793881Ssos u_int16_t hwres_cblid :1; 30893881Ssos u_int16_t hwres_slave :5; 30993881Ssos u_int16_t hwres_master :8; 31084584Ssos 31193881Ssos u_int16_t vendor_acoustic:8; 31293881Ssos u_int16_t current_acoustic:8; 31393881Ssos#endif 31493881Ssos 31584584Ssos/*095*/ u_int16_t stream_min_req_size; 31684584Ssos/*096*/ u_int16_t stream_transfer_time; 31784584Ssos/*097*/ u_int16_t stream_access_latency; 31884584Ssos/*098*/ u_int32_t stream_granularity; 31993881Ssos/*100*/ u_int16_t lba_size48_1; 32093881Ssos u_int16_t lba_size48_2; 32193881Ssos u_int16_t lba_size48_3; 32293881Ssos u_int16_t lba_size48_4; 32384584Ssos u_int16_t reserved104[23]; 32484584Ssos/*127*/ u_int16_t removable_status; 32584584Ssos/*128*/ u_int16_t security_status; 32684584Ssos u_int16_t reserved129[31]; 32784584Ssos/*160*/ u_int16_t cfa_powermode1; 32884584Ssos u_int16_t reserved161[14]; 32984584Ssos/*176*/ u_int16_t media_serial[30]; 33084584Ssos u_int16_t reserved206[49]; 33184584Ssos/*255*/ u_int16_t integrity; 33274298Ssos}; 33374298Ssos 33482560Ssos#define ATA_MODE_MASK 0x0f 33582560Ssos#define ATA_DMA_MASK 0xf0 33676740Ssos#define ATA_PIO 0x00 33776740Ssos#define ATA_PIO0 0x08 33882560Ssos#define ATA_PIO1 0x09 33982560Ssos#define ATA_PIO2 0x0a 34082560Ssos#define ATA_PIO3 0x0b 34182560Ssos#define ATA_PIO4 0x0c 34282560Ssos#define ATA_DMA 0x10 34382560Ssos#define ATA_WDMA 0x20 34482560Ssos#define ATA_WDMA2 0x22 34582560Ssos#define ATA_UDMA 0x40 34682560Ssos#define ATA_UDMA2 0x42 34782560Ssos#define ATA_UDMA4 0x44 34882560Ssos#define ATA_UDMA5 0x45 34984584Ssos#define ATA_UDMA6 0x46 35074298Ssos 35176740Ssosstruct ata_cmd { 35282560Ssos int channel; 35382560Ssos int device; 35476740Ssos int cmd; 35582560Ssos#define ATAGPARM 1 35682560Ssos#define ATAGMODE 2 35782560Ssos#define ATASMODE 3 35882560Ssos#define ATAREINIT 4 35982560Ssos#define ATAATTACH 5 36082560Ssos#define ATADETACH 6 36182560Ssos#define ATAPICMD 7 36293275Ssos#define ATARAIDREBUILD 8 36393275Ssos#define ATARAIDCREATE 9 36493275Ssos#define ATARAIDDELETE 10 36593433Ssos#define ATARAIDSTATUS 11 36693433Ssos#define ATAENCSTAT 12 36774298Ssos 36876740Ssos union { 36976740Ssos struct { 37076740Ssos int mode[2]; 37176740Ssos } mode; 37283421Sobrien struct { 37376740Ssos int type[2]; 37476740Ssos char name[2][32]; 37576740Ssos struct ata_params params[2]; 37676740Ssos } param; 37793275Ssos struct raid_setup { 37893275Ssos int type; 37993662Ssos#define AR_RAID0 1 38093662Ssos#define AR_RAID1 2 38193662Ssos#define AR_SPAN 4 38293662Ssos 38393275Ssos int total_disks; 38493275Ssos int disks[16]; 38593275Ssos int interleave; 38693275Ssos int unit; 38793275Ssos } raid_setup; 38893662Ssos struct raid_status { 38993662Ssos int type; 39093662Ssos int total_disks; 39193662Ssos int disks[16]; 39293662Ssos int interleave; 39393662Ssos int status; 39493662Ssos#define AR_READY 1 39593662Ssos#define AR_DEGRADED 2 39693662Ssos#define AR_REBUILDING 4 39793662Ssos 39893662Ssos int progress; 39993662Ssos } raid_status; 40082560Ssos struct { 40193433Ssos int fan; 40293433Ssos int temp; 40393433Ssos int v05; 40493433Ssos int v12; 40593433Ssos } enclosure; 40693433Ssos struct { 40782560Ssos char ccb[16]; 40882560Ssos caddr_t data; 40982560Ssos int count; 41082560Ssos int flags; 41182560Ssos#define ATAPI_CMD_CTRL 0x00 41282560Ssos#define ATAPI_CMD_READ 0x01 41382560Ssos#define ATAPI_CMD_WRITE 0x02 41482560Ssos 41582560Ssos int timeout; 41682560Ssos int error; 41782560Ssos char sense_data[18]; 41882560Ssos } atapi; 41976740Ssos } u; 42074298Ssos}; 42174298Ssos 42276740Ssos#define IOCATA _IOWR('a', 1, struct ata_cmd) 42374298Ssos 42474298Ssos#endif /* _SYS_ATA_H_ */ 425