ata.h revision 83421
1/*- 2 * Copyright (c) 2000,2001 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/sys/ata.h 83421 2001-09-13 22:52:42Z obrien $ 29 */ 30 31#ifndef _SYS_ATA_H_ 32#define _SYS_ATA_H_ 33 34#include <sys/ioccom.h> 35 36/* ATA/ATAPI device parameter information */ 37struct ata_params { 38 u_int8_t cmdsize :2; /* packet command size */ 39#define ATAPI_PSIZE_12 0 /* 12 bytes */ 40#define ATAPI_PSIZE_16 1 /* 16 bytes */ 41 42 u_int8_t :3; 43 u_int8_t drqtype :2; /* DRQ type */ 44#define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */ 45#define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */ 46#define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */ 47 48 u_int8_t removable :1; /* device is removable */ 49 u_int8_t device_type :5; /* device type */ 50#define ATAPI_TYPE_DIRECT 0 /* disk/floppy */ 51#define ATAPI_TYPE_TAPE 1 /* streaming tape */ 52#define ATAPI_TYPE_CDROM 5 /* CD-ROM device */ 53#define ATAPI_TYPE_OPTICAL 7 /* optical disk */ 54 55 u_int8_t :1; 56 u_int8_t proto :2; /* command protocol */ 57#define ATAPI_PROTO_ATAPI 2 58 59 u_int16_t cylinders; /* number of cylinders */ 60 u_int16_t reserved2; 61 u_int16_t heads; /* # heads */ 62 u_int16_t unfbytespertrk; /* # unformatted bytes/track */ 63 u_int16_t unfbytes; /* # unformatted bytes/sector */ 64 u_int16_t sectors; /* # sectors/track */ 65 u_int16_t vendorunique0[3]; 66 u_int8_t serial[20]; /* serial number */ 67 u_int16_t buffertype; /* buffer type */ 68#define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */ 69#define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */ 70#define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */ 71 72 u_int16_t buffersize; /* buf size, 512-byte units */ 73 u_int16_t necc; /* ecc bytes appended */ 74 u_int8_t revision[8]; /* firmware revision */ 75 u_int8_t model[40]; /* model name */ 76 u_int8_t nsecperint; /* sectors per interrupt */ 77 u_int8_t vendorunique1; 78 u_int16_t usedmovsd; /* double word read/write? */ 79 80 u_int8_t vendorcap; /* vendor capabilities */ 81 u_int8_t dmaflag :1; /* DMA supported - always 1 */ 82 u_int8_t lbaflag :1; /* LBA supported - always 1 */ 83 u_int8_t iordydis :1; /* IORDY may be disabled */ 84 u_int8_t iordyflag :1; /* IORDY supported */ 85 u_int8_t softreset :1; /* needs softreset when busy */ 86 u_int8_t stdby_ovlap :1; /* standby/overlap supported */ 87 u_int8_t queueing :1; /* supports queuing overlap */ 88 u_int8_t idmaflag :1; /* interleaved DMA supported */ 89 u_int16_t capvalidate; /* validation for above */ 90 91 u_int8_t vendorunique3; 92 u_int8_t opiomode; /* PIO modes 0-2 */ 93 u_int8_t vendorunique4; 94 u_int8_t odmamode; /* old DMA modes, not ATA-3 */ 95 96 u_int16_t atavalid; /* fields valid */ 97#define ATA_FLAG_54_58 1 /* words 54-58 valid */ 98#define ATA_FLAG_64_70 2 /* words 64-70 valid */ 99#define ATA_FLAG_88 4 /* word 88 valid */ 100 101 u_int16_t currcyls; 102 u_int16_t currheads; 103 u_int16_t currsectors; 104 u_int16_t currsize0; 105 u_int16_t currsize1; 106 u_int8_t currmultsect; 107 u_int8_t multsectvalid; 108 u_int32_t lbasize; 109 110 u_int16_t sdmamodes; /* singleword DMA modes */ 111 u_int16_t wdmamodes; /* multiword DMA modes */ 112 u_int16_t apiomodes; /* advanced PIO modes */ 113 114 u_int16_t mwdmamin; /* min. M/W DMA time/word ns */ 115 u_int16_t mwdmarec; /* rec. M/W DMA time ns */ 116 u_int16_t pioblind; /* min. PIO cycle w/o flow */ 117 u_int16_t pioiordy; /* min. PIO cycle IORDY flow */ 118 119 u_int16_t reserved69; 120 u_int16_t reserved70; 121 u_int16_t rlsovlap; /* rel time (us) for overlap */ 122 u_int16_t rlsservice; /* rel time (us) for service */ 123 u_int16_t reserved73; 124 u_int16_t reserved74; 125 u_int16_t queuelen:5; 126 u_int16_t :11; 127 u_int16_t reserved76; 128 u_int16_t reserved77; 129 u_int16_t reserved78; 130 u_int16_t reserved79; 131 u_int16_t versmajor; 132 u_int16_t versminor; 133 u_int16_t featsupp1; /* 82 */ 134 u_int16_t supmicrocode:1; 135 u_int16_t supqueued:1; 136 u_int16_t supcfa:1; 137 u_int16_t supapm:1; 138 u_int16_t suprmsn:1; 139 u_int16_t :11; 140 u_int16_t featsupp3; /* 84 */ 141 u_int16_t featenab1; /* 85 */ 142 u_int16_t enabmicrocode:1; 143 u_int16_t enabqueued:1; 144 u_int16_t enabcfa:1; 145 u_int16_t enabapm:1; 146 u_int16_t enabrmsn:1; 147 u_int16_t :11; 148 u_int16_t featenab3; /* 87 */ 149 u_int16_t udmamodes; /* UltraDMA modes */ 150 u_int16_t erasetime; 151 u_int16_t enherasetime; 152 u_int16_t apmlevel; 153 u_int16_t masterpasswdrev; 154 u_int16_t masterhwres :8; 155 u_int16_t slavehwres :5; 156 u_int16_t cblid :1; 157 u_int16_t reserved93_1415 :2; 158 u_int16_t reserved94[32]; 159 u_int16_t rmvstat; 160 u_int16_t securstat; 161 u_int16_t reserved129[30]; 162 u_int16_t cfapwrmode; 163 u_int16_t reserved160[85]; 164 u_int16_t integrity; 165 u_int16_t reserved246[10]; 166}; 167 168#define ATA_MODE_MASK 0x0f 169#define ATA_DMA_MASK 0xf0 170#define ATA_PIO 0x00 171#define ATA_PIO0 0x08 172#define ATA_PIO1 0x09 173#define ATA_PIO2 0x0a 174#define ATA_PIO3 0x0b 175#define ATA_PIO4 0x0c 176#define ATA_DMA 0x10 177#define ATA_WDMA 0x20 178#define ATA_WDMA2 0x22 179#define ATA_UDMA 0x40 180#define ATA_UDMA2 0x42 181#define ATA_UDMA4 0x44 182#define ATA_UDMA5 0x45 183 184struct ata_cmd { 185 int channel; 186 int device; 187 int cmd; 188#define ATAGPARM 1 189#define ATAGMODE 2 190#define ATASMODE 3 191#define ATAREINIT 4 192#define ATAATTACH 5 193#define ATADETACH 6 194#define ATAPICMD 7 195 196 union { 197 struct { 198 int mode[2]; 199 } mode; 200 struct { 201 int type[2]; 202 char name[2][32]; 203 struct ata_params params[2]; 204 } param; 205 struct { 206 char ccb[16]; 207 caddr_t data; 208 int count; 209 int flags; 210#define ATAPI_CMD_CTRL 0x00 211#define ATAPI_CMD_READ 0x01 212#define ATAPI_CMD_WRITE 0x02 213 214 int timeout; 215 int error; 216 char sense_data[18]; 217 } atapi; 218 } u; 219}; 220 221#define IOCATA _IOWR('a', 1, struct ata_cmd) 222 223#endif /* _SYS_ATA_H_ */ 224