pmap.c revision 99559
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the University of 24 * California, Berkeley and its contributors. 25 * 4. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 42 * $FreeBSD: head/sys/sparc64/sparc64/pmap.c 99559 2002-07-07 23:05:27Z peter $ 43 */ 44 45/* 46 * Manages physical address maps. 47 * 48 * In addition to hardware address maps, this module is called upon to 49 * provide software-use-only maps which may or may not be stored in the 50 * same form as hardware maps. These pseudo-maps are used to store 51 * intermediate results from copy operations to and from address spaces. 52 * 53 * Since the information managed by this module is also stored by the 54 * logical address mapping module, this module may throw away valid virtual 55 * to physical mappings at almost any time. However, invalidations of 56 * mappings must be done as requested. 57 * 58 * In order to cope with hardware architectures which make virtual to 59 * physical map invalidates expensive, this module may delay invalidate 60 * reduced protection operations until such time as they are actually 61 * necessary. This module is given full information as to which processors 62 * are currently using which maps, and to when physical maps must be made 63 * correct. 64 */ 65 66#include "opt_msgbuf.h" 67#include "opt_pmap.h" 68 69#include <sys/param.h> 70#include <sys/kernel.h> 71#include <sys/ktr.h> 72#include <sys/lock.h> 73#include <sys/msgbuf.h> 74#include <sys/mutex.h> 75#include <sys/proc.h> 76#include <sys/smp.h> 77#include <sys/sysctl.h> 78#include <sys/systm.h> 79#include <sys/vmmeter.h> 80 81#include <dev/ofw/openfirm.h> 82 83#include <vm/vm.h> 84#include <vm/vm_param.h> 85#include <vm/vm_kern.h> 86#include <vm/vm_page.h> 87#include <vm/vm_map.h> 88#include <vm/vm_object.h> 89#include <vm/vm_extern.h> 90#include <vm/vm_pageout.h> 91#include <vm/vm_pager.h> 92#include <vm/uma.h> 93 94#include <machine/cache.h> 95#include <machine/frame.h> 96#include <machine/md_var.h> 97#include <machine/metadata.h> 98#include <machine/smp.h> 99#include <machine/tlb.h> 100#include <machine/tte.h> 101#include <machine/tsb.h> 102 103#define PMAP_DEBUG 104 105#ifndef PMAP_SHPGPERPROC 106#define PMAP_SHPGPERPROC 200 107#endif 108 109struct mem_region { 110 vm_offset_t mr_start; 111 vm_offset_t mr_size; 112}; 113 114struct ofw_map { 115 vm_offset_t om_start; 116 vm_offset_t om_size; 117 u_long om_tte; 118}; 119 120/* 121 * Virtual and physical address of message buffer. 122 */ 123struct msgbuf *msgbufp; 124vm_offset_t msgbuf_phys; 125 126/* 127 * Physical addresses of first and last available physical page. 128 */ 129vm_offset_t avail_start; 130vm_offset_t avail_end; 131 132int pmap_pagedaemon_waken; 133 134/* 135 * Map of physical memory reagions. 136 */ 137vm_offset_t phys_avail[128]; 138static struct mem_region mra[128]; 139static struct ofw_map translations[128]; 140static int translations_size; 141 142/* 143 * First and last available kernel virtual addresses. 144 */ 145vm_offset_t virtual_avail; 146vm_offset_t virtual_end; 147vm_offset_t kernel_vm_end; 148 149/* 150 * Kernel pmap. 151 */ 152struct pmap kernel_pmap_store; 153 154static boolean_t pmap_initialized = FALSE; 155 156/* 157 * Allocate physical memory for use in pmap_bootstrap. 158 */ 159static vm_offset_t pmap_bootstrap_alloc(vm_size_t size); 160 161/* 162 * If user pmap is processed with pmap_remove and with pmap_remove and the 163 * resident count drops to 0, there are no more pages to remove, so we 164 * need not continue. 165 */ 166#define PMAP_REMOVE_DONE(pm) \ 167 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0) 168 169/* 170 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove() 171 * and pmap_protect() instead of trying each virtual address. 172 */ 173#define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE) 174 175#ifdef PMAP_STATS 176static long pmap_enter_nupdate; 177static long pmap_enter_nreplace; 178static long pmap_enter_nnew; 179static long pmap_ncache_enter; 180static long pmap_ncache_enter_nc; 181static long pmap_niflush; 182 183SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "Statistics"); 184SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_enter_nupdate, CTLFLAG_RD, 185 &pmap_enter_nupdate, 0, "Number of pmap_enter() updates"); 186SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_enter_nreplace, CTLFLAG_RD, 187 &pmap_enter_nreplace, 0, "Number of pmap_enter() replacements"); 188SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_enter_nnew, CTLFLAG_RD, 189 &pmap_enter_nnew, 0, "Number of pmap_enter() additions"); 190SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_ncache_enter, CTLFLAG_RD, 191 &pmap_ncache_enter, 0, "Number of pmap_cache_enter() calls"); 192SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_ncache_enter_nc, CTLFLAG_RD, 193 &pmap_ncache_enter_nc, 0, "Number of pmap_cache_enter() nc"); 194SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_niflush, CTLFLAG_RD, 195 &pmap_niflush, 0, "Number of pmap I$ flushes"); 196 197#define PMAP_STATS_INC(var) atomic_add_long(&var, 1) 198#else 199#define PMAP_STATS_INC(var) 200#endif 201 202/* 203 * Quick sort callout for comparing memory regions. 204 */ 205static int mr_cmp(const void *a, const void *b); 206static int om_cmp(const void *a, const void *b); 207static int 208mr_cmp(const void *a, const void *b) 209{ 210 const struct mem_region *mra; 211 const struct mem_region *mrb; 212 213 mra = a; 214 mrb = b; 215 if (mra->mr_start < mrb->mr_start) 216 return (-1); 217 else if (mra->mr_start > mrb->mr_start) 218 return (1); 219 else 220 return (0); 221} 222static int 223om_cmp(const void *a, const void *b) 224{ 225 const struct ofw_map *oma; 226 const struct ofw_map *omb; 227 228 oma = a; 229 omb = b; 230 if (oma->om_start < omb->om_start) 231 return (-1); 232 else if (oma->om_start > omb->om_start) 233 return (1); 234 else 235 return (0); 236} 237 238/* 239 * Bootstrap the system enough to run with virtual memory. 240 */ 241void 242pmap_bootstrap(vm_offset_t ekva) 243{ 244 struct pmap *pm; 245 struct tte *tp; 246 vm_offset_t off; 247 vm_offset_t pa; 248 vm_offset_t va; 249 vm_size_t physsz; 250 ihandle_t pmem; 251 ihandle_t vmem; 252 int sz; 253 int i; 254 int j; 255 256 /* 257 * Set the start and end of kva. The kernel is loaded at the first 258 * available 4 meg super page, so round up to the end of the page. 259 */ 260 virtual_avail = roundup2(ekva, PAGE_SIZE_4M); 261 virtual_end = VM_MAX_KERNEL_ADDRESS; 262 263 /* 264 * Find out what physical memory is available from the prom and 265 * initialize the phys_avail array. This must be done before 266 * pmap_bootstrap_alloc is called. 267 */ 268 if ((pmem = OF_finddevice("/memory")) == -1) 269 panic("pmap_bootstrap: finddevice /memory"); 270 if ((sz = OF_getproplen(pmem, "available")) == -1) 271 panic("pmap_bootstrap: getproplen /memory/available"); 272 if (sizeof(phys_avail) < sz) 273 panic("pmap_bootstrap: phys_avail too small"); 274 if (sizeof(mra) < sz) 275 panic("pmap_bootstrap: mra too small"); 276 bzero(mra, sz); 277 if (OF_getprop(pmem, "available", mra, sz) == -1) 278 panic("pmap_bootstrap: getprop /memory/available"); 279 sz /= sizeof(*mra); 280 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 281 qsort(mra, sz, sizeof (*mra), mr_cmp); 282 physsz = 0; 283 for (i = 0, j = 0; i < sz; i++, j += 2) { 284 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start, 285 mra[i].mr_size); 286 phys_avail[j] = mra[i].mr_start; 287 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size; 288 physsz += mra[i].mr_size; 289 } 290 physmem = btoc(physsz); 291 292 /* 293 * Allocate the kernel tsb and lock it in the tlb. 294 */ 295 pa = pmap_bootstrap_alloc(KVA_PAGES * PAGE_SIZE_4M); 296 if (pa & PAGE_MASK_4M) 297 panic("pmap_bootstrap: tsb unaligned\n"); 298 tsb_kernel_phys = pa; 299 tsb_kernel = (struct tte *)virtual_avail; 300 virtual_avail += KVA_PAGES * PAGE_SIZE_4M; 301 pmap_map_tsb(); 302 bzero(tsb_kernel, KVA_PAGES * PAGE_SIZE_4M); 303 304 /* 305 * Enter fake 8k pages for the 4MB kernel pages, so that 306 * pmap_kextract() will work for them. 307 */ 308 for (i = 0; i < kernel_tlb_slots; i++) { 309 pa = kernel_tlbs[i].te_pa; 310 va = kernel_tlbs[i].te_va; 311 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) { 312 tp = tsb_kvtotte(va + off); 313 tp->tte_vpn = TV_VPN(va + off); 314 tp->tte_data = TD_V | TD_8K | TD_PA(pa + off) | 315 TD_REF | TD_SW | TD_CP | TD_CV | TD_P | TD_W; 316 } 317 } 318 319 /* 320 * Allocate a kernel stack with guard page for thread0 and map it into 321 * the kernel tsb. 322 */ 323 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE); 324 kstack0_phys = pa; 325 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 326 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 327 for (i = 0; i < KSTACK_PAGES; i++) { 328 pa = kstack0_phys + i * PAGE_SIZE; 329 va = kstack0 + i * PAGE_SIZE; 330 tp = tsb_kvtotte(va); 331 tp->tte_vpn = TV_VPN(va); 332 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | 333 TD_CP | TD_CV | TD_P | TD_W; 334 } 335 336 /* 337 * Allocate the message buffer. 338 */ 339 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE); 340 341 /* 342 * Add the prom mappings to the kernel tsb. 343 */ 344 if ((vmem = OF_finddevice("/virtual-memory")) == -1) 345 panic("pmap_bootstrap: finddevice /virtual-memory"); 346 if ((sz = OF_getproplen(vmem, "translations")) == -1) 347 panic("pmap_bootstrap: getproplen translations"); 348 if (sizeof(translations) < sz) 349 panic("pmap_bootstrap: translations too small"); 350 bzero(translations, sz); 351 if (OF_getprop(vmem, "translations", translations, sz) == -1) 352 panic("pmap_bootstrap: getprop /virtual-memory/translations"); 353 sz /= sizeof(*translations); 354 translations_size = sz; 355 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 356 qsort(translations, sz, sizeof (*translations), om_cmp); 357 for (i = 0; i < sz; i++) { 358 CTR3(KTR_PMAP, 359 "translation: start=%#lx size=%#lx tte=%#lx", 360 translations[i].om_start, translations[i].om_size, 361 translations[i].om_tte); 362 if (translations[i].om_start < VM_MIN_PROM_ADDRESS || 363 translations[i].om_start > VM_MAX_PROM_ADDRESS) 364 continue; 365 for (off = 0; off < translations[i].om_size; 366 off += PAGE_SIZE) { 367 va = translations[i].om_start + off; 368 tp = tsb_kvtotte(va); 369 tp->tte_vpn = TV_VPN(va); 370 tp->tte_data = translations[i].om_tte + off; 371 } 372 } 373 374 /* 375 * Calculate the first and last available physical addresses. 376 */ 377 avail_start = phys_avail[0]; 378 for (i = 0; phys_avail[i + 2] != 0; i += 2) 379 ; 380 avail_end = phys_avail[i + 1]; 381 Maxmem = sparc64_btop(avail_end); 382 383 /* 384 * Allocate virtual address space for the message buffer. 385 */ 386 msgbufp = (struct msgbuf *)virtual_avail; 387 virtual_avail += round_page(MSGBUF_SIZE); 388 389 /* 390 * Initialize the kernel pmap (which is statically allocated). 391 */ 392 pm = kernel_pmap; 393 for (i = 0; i < MAXCPU; i++) 394 pm->pm_context[i] = TLB_CTX_KERNEL; 395 pm->pm_active = ~0; 396 397 /* XXX flush all non-locked tlb entries */ 398} 399 400void 401pmap_map_tsb(void) 402{ 403 vm_offset_t va; 404 vm_offset_t pa; 405 u_long data; 406 u_long s; 407 int i; 408 409 s = intr_disable(); 410 411 /* 412 * Map the 4mb tsb pages. 413 */ 414 for (i = 0; i < KVA_PAGES; i++) { 415 va = (vm_offset_t)tsb_kernel + i * PAGE_SIZE_4M; 416 pa = tsb_kernel_phys + i * PAGE_SIZE_4M; 417 /* XXX - cheetah */ 418 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV | 419 TD_P | TD_W; 420 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | 421 TLB_TAR_CTX(TLB_CTX_KERNEL)); 422 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data); 423 } 424 425 /* 426 * Load the tsb registers. 427 */ 428 stxa(AA_DMMU_TSB, ASI_DMMU, (vm_offset_t)tsb_kernel); 429 stxa(AA_IMMU_TSB, ASI_IMMU, (vm_offset_t)tsb_kernel); 430 membar(Sync); 431 flush(tsb_kernel); 432 433 /* 434 * Set the secondary context to be the kernel context (needed for 435 * fp block operations in the kernel and the cache code). 436 */ 437 stxa(AA_DMMU_SCXR, ASI_DMMU, TLB_CTX_KERNEL); 438 membar(Sync); 439 440 intr_restore(s); 441} 442 443/* 444 * Allocate a physical page of memory directly from the phys_avail map. 445 * Can only be called from pmap_bootstrap before avail start and end are 446 * calculated. 447 */ 448static vm_offset_t 449pmap_bootstrap_alloc(vm_size_t size) 450{ 451 vm_offset_t pa; 452 int i; 453 454 size = round_page(size); 455 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 456 if (phys_avail[i + 1] - phys_avail[i] < size) 457 continue; 458 pa = phys_avail[i]; 459 phys_avail[i] += size; 460 return (pa); 461 } 462 panic("pmap_bootstrap_alloc"); 463} 464 465void 466pmap_context_rollover(void) 467{ 468 u_long data; 469 u_long tag; 470 int i; 471 472 mtx_assert(&sched_lock, MA_OWNED); 473 CTR0(KTR_PMAP, "pmap_context_rollover"); 474 for (i = 0; i < tlb_slot_count; i++) { 475 /* XXX - cheetah */ 476 data = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG); 477 tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG); 478 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 479 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 480 stxa_sync(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG, 0); 481 data = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG); 482 tag = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG); 483 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 484 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 485 stxa_sync(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG, 0); 486 } 487 PCPU_SET(tlb_ctx, PCPU_GET(tlb_ctx_min)); 488} 489 490static __inline u_int 491pmap_context_alloc(void) 492{ 493 u_int context; 494 495 mtx_assert(&sched_lock, MA_OWNED); 496 context = PCPU_GET(tlb_ctx); 497 if (context + 1 == PCPU_GET(tlb_ctx_max)) 498 pmap_context_rollover(); 499 else 500 PCPU_SET(tlb_ctx, context + 1); 501 return (context); 502} 503 504/* 505 * Initialize the pmap module. 506 */ 507void 508pmap_init(vm_offset_t phys_start, vm_offset_t phys_end) 509{ 510 vm_offset_t addr; 511 vm_size_t size; 512 int result; 513 int i; 514 515 for (i = 0; i < vm_page_array_size; i++) { 516 vm_page_t m; 517 518 m = &vm_page_array[i]; 519 STAILQ_INIT(&m->md.tte_list); 520 m->md.flags = 0; 521 } 522 523 for (i = 0; i < translations_size; i++) { 524 addr = translations[i].om_start; 525 size = translations[i].om_size; 526 if (addr < 0xf0000000) /* XXX */ 527 continue; 528 result = vm_map_find(kernel_map, NULL, 0, &addr, size, TRUE, 529 VM_PROT_ALL, VM_PROT_ALL, 0); 530 if (result != KERN_SUCCESS || addr != translations[i].om_start) 531 panic("pmap_init: vm_map_find"); 532 } 533 534 pmap_initialized = TRUE; 535} 536 537/* 538 * Initialize the address space (zone) for the pv_entries. Set a 539 * high water mark so that the system can recover from excessive 540 * numbers of pv entries. 541 */ 542void 543pmap_init2(void) 544{ 545} 546 547/* 548 * Extract the physical page address associated with the given 549 * map/virtual_address pair. 550 */ 551vm_offset_t 552pmap_extract(pmap_t pm, vm_offset_t va) 553{ 554 struct tte *tp; 555 556 if (pm == kernel_pmap) 557 return (pmap_kextract(va)); 558 tp = tsb_tte_lookup(pm, va); 559 if (tp == NULL) 560 return (0); 561 else 562 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp))); 563} 564 565/* 566 * Extract the physical page address associated with the given kernel virtual 567 * address. 568 */ 569vm_offset_t 570pmap_kextract(vm_offset_t va) 571{ 572 struct tte *tp; 573 574 tp = tsb_kvtotte(va); 575 if ((tp->tte_data & TD_V) == 0) 576 return (0); 577 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp))); 578} 579 580int 581pmap_cache_enter(vm_page_t m, vm_offset_t va) 582{ 583 struct tte *tp; 584 int c, i; 585 586 CTR2(KTR_PMAP, "pmap_cache_enter: m=%p va=%#lx", m, va); 587 PMAP_STATS_INC(pmap_ncache_enter); 588 for (i = 0, c = 0; i < DCACHE_COLORS; i++) { 589 if (i != DCACHE_COLOR(va) && m->md.colors[i] != 0) 590 c++; 591 } 592 m->md.colors[DCACHE_COLOR(va)]++; 593 if (c == 0) { 594 CTR0(KTR_PMAP, "pmap_cache_enter: cacheable"); 595 return (1); 596 } 597 PMAP_STATS_INC(pmap_ncache_enter_nc); 598 if ((m->md.flags & PG_UNCACHEABLE) != 0) { 599 CTR0(KTR_PMAP, "pmap_cache_enter: already uncacheable"); 600 return (0); 601 } 602 CTR0(KTR_PMAP, "pmap_cache_enter: marking uncacheable"); 603 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 604 tp->tte_data &= ~TD_CV; 605 tlb_page_demap(TLB_DTLB | TLB_ITLB, TTE_GET_PMAP(tp), 606 TTE_GET_VA(tp)); 607 } 608 dcache_page_inval(VM_PAGE_TO_PHYS(m)); 609 m->md.flags |= PG_UNCACHEABLE; 610 return (0); 611} 612 613void 614pmap_cache_remove(vm_page_t m, vm_offset_t va) 615{ 616 struct tte *tp; 617 int c, i; 618 619 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va, 620 m->md.colors[DCACHE_COLOR(va)]); 621 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0, 622 ("pmap_cache_remove: no mappings %d <= 0", 623 m->md.colors[DCACHE_COLOR(va)])); 624 m->md.colors[DCACHE_COLOR(va)]--; 625 for (i = 0, c = 0; i < DCACHE_COLORS; i++) { 626 if (m->md.colors[i] != 0) 627 c++; 628 } 629 if (c > 1 || (m->md.flags & PG_UNCACHEABLE) == 0) 630 return; 631 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 632 tp->tte_data |= TD_CV; 633 tlb_page_demap(TLB_DTLB | TLB_ITLB, TTE_GET_PMAP(tp), 634 TTE_GET_VA(tp)); 635 } 636 m->md.flags &= ~PG_UNCACHEABLE; 637} 638 639/* 640 * Map a wired page into kernel virtual address space. 641 */ 642void 643pmap_kenter(vm_offset_t va, vm_offset_t pa) 644{ 645 vm_offset_t ova; 646 struct tte *tp; 647 vm_page_t om; 648 vm_page_t m; 649 u_long data; 650 651 tp = tsb_kvtotte(va); 652 m = PHYS_TO_VM_PAGE(pa); 653 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx", 654 va, pa, tp, tp->tte_data); 655 if ((tp->tte_data & TD_V) != 0) { 656 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 657 ova = TTE_GET_VA(tp); 658 STAILQ_REMOVE(&om->md.tte_list, tp, tte, tte_link); 659 pmap_cache_remove(om, ova); 660 if (va != ova) 661 tlb_page_demap(TLB_DTLB, kernel_pmap, ova); 662 } 663 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP | TD_P | TD_W; 664 if (pmap_cache_enter(m, va) != 0) 665 data |= TD_CV; 666 tp->tte_vpn = TV_VPN(va); 667 tp->tte_data = data; 668 STAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link); 669 tp->tte_pmap = kernel_pmap; 670} 671 672/* 673 * Map a wired page into kernel virtual address space. This additionally 674 * takes a flag argument wich is or'ed to the TTE data. This is used by 675 * bus_space_map(). 676 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility 677 * to flush entries that might still be in the cache, if applicable. 678 */ 679void 680pmap_kenter_flags(vm_offset_t va, vm_offset_t pa, u_long flags) 681{ 682 struct tte *tp; 683 684 tp = tsb_kvtotte(va); 685 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx", 686 va, pa, tp, tp->tte_data); 687 tp->tte_vpn = TV_VPN(va); 688 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags; 689} 690 691/* 692 * Make a temporary mapping for a physical address. This is only intended 693 * to be used for panic dumps. 694 */ 695void * 696pmap_kenter_temporary(vm_offset_t pa, int i) 697{ 698 699 TODO; 700} 701 702/* 703 * Remove a wired page from kernel virtual address space. 704 */ 705void 706pmap_kremove(vm_offset_t va) 707{ 708 struct tte *tp; 709 vm_page_t m; 710 711 tp = tsb_kvtotte(va); 712 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp, 713 tp->tte_data); 714 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 715 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 716 pmap_cache_remove(m, va); 717 TTE_ZERO(tp); 718} 719 720/* 721 * Inverse of pmap_kenter_flags, used by bus_space_unmap(). 722 */ 723void 724pmap_kremove_flags(vm_offset_t va) 725{ 726 struct tte *tp; 727 728 tp = tsb_kvtotte(va); 729 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp, 730 tp->tte_data); 731 TTE_ZERO(tp); 732} 733 734/* 735 * Map a range of physical addresses into kernel virtual address space. 736 * 737 * The value passed in *virt is a suggested virtual address for the mapping. 738 * Architectures which can support a direct-mapped physical to virtual region 739 * can return the appropriate address within that region, leaving '*virt' 740 * unchanged. We cannot and therefore do not; *virt is updated with the 741 * first usable address after the mapped region. 742 */ 743vm_offset_t 744pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 745{ 746 struct tte *tp; 747 vm_offset_t sva; 748 vm_offset_t va; 749 vm_offset_t pa; 750 751 pa = pa_start; 752 sva = *virt; 753 va = sva; 754 for (; pa < pa_end; pa += PAGE_SIZE, va += PAGE_SIZE) { 755 tp = tsb_kvtotte(va); 756 tp->tte_vpn = TV_VPN(va); 757 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | 758 TD_CP | TD_CV | TD_P | TD_W; 759 } 760 tlb_range_demap(kernel_pmap, sva, sva + (pa_end - pa_start) - 1); 761 *virt = va; 762 return (sva); 763} 764 765/* 766 * Map a list of wired pages into kernel virtual address space. This is 767 * intended for temporary mappings which do not need page modification or 768 * references recorded. Existing mappings in the region are overwritten. 769 */ 770void 771pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 772{ 773 vm_offset_t va; 774 int i; 775 776 va = sva; 777 for (i = 0; i < count; i++, va += PAGE_SIZE) 778 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 779 tlb_range_demap(kernel_pmap, sva, sva + (count * PAGE_SIZE) - 1); 780} 781 782/* 783 * As above, but take an additional flags argument and call 784 * pmap_kenter_flags(). 785 */ 786void 787pmap_qenter_flags(vm_offset_t sva, vm_page_t *m, int count, u_long fl) 788{ 789 vm_offset_t va; 790 int i; 791 792 va = sva; 793 for (i = 0; i < count; i++, va += PAGE_SIZE) 794 pmap_kenter_flags(va, VM_PAGE_TO_PHYS(m[i]), fl); 795 tlb_range_demap(kernel_pmap, sva, sva + (count * PAGE_SIZE) - 1); 796} 797 798/* 799 * Remove page mappings from kernel virtual address space. Intended for 800 * temporary mappings entered by pmap_qenter. 801 */ 802void 803pmap_qremove(vm_offset_t sva, int count) 804{ 805 vm_offset_t va; 806 int i; 807 808 va = sva; 809 for (i = 0; i < count; i++, va += PAGE_SIZE) 810 pmap_kremove(va); 811 tlb_range_demap(kernel_pmap, sva, sva + (count * PAGE_SIZE) - 1); 812} 813 814/* 815 * Create the kernel stack and pcb for a new thread. 816 * This routine directly affects the fork perf for a process and 817 * create performance for a thread. 818 */ 819void 820pmap_new_thread(struct thread *td) 821{ 822 vm_page_t ma[KSTACK_PAGES]; 823 vm_object_t ksobj; 824 vm_offset_t ks; 825 vm_page_t m; 826 u_int i; 827 828 /* 829 * Allocate object for the kstack, 830 */ 831 ksobj = vm_object_allocate(OBJT_DEFAULT, KSTACK_PAGES); 832 td->td_kstack_obj = ksobj; 833 834 /* 835 * Get a kernel virtual address for the kstack for this thread. 836 */ 837 ks = kmem_alloc_nofault(kernel_map, 838 (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE); 839 if (ks == 0) 840 panic("pmap_new_thread: kstack allocation failed"); 841 if (KSTACK_GUARD_PAGES != 0) { 842 tlb_page_demap(TLB_DTLB, kernel_pmap, ks); 843 ks += KSTACK_GUARD_PAGES * PAGE_SIZE; 844 } 845 td->td_kstack = ks; 846 847 for (i = 0; i < KSTACK_PAGES; i++) { 848 /* 849 * Get a kernel stack page. 850 */ 851 m = vm_page_grab(ksobj, i, VM_ALLOC_NORMAL | VM_ALLOC_RETRY); 852 ma[i] = m; 853 854 /* 855 * Wire the page. 856 */ 857 m->wire_count++; 858 cnt.v_wire_count++; 859 860 vm_page_wakeup(m); 861 vm_page_flag_clear(m, PG_ZERO); 862 vm_page_flag_set(m, PG_MAPPED | PG_WRITEABLE); 863 m->valid = VM_PAGE_BITS_ALL; 864 } 865 866 /* 867 * Enter the page into the kernel address space. 868 */ 869 pmap_qenter(ks, ma, KSTACK_PAGES); 870} 871 872/* 873 * Dispose the kernel stack for a thread that has exited. 874 * This routine directly impacts the exit perf of a process and thread. 875 */ 876void 877pmap_dispose_thread(struct thread *td) 878{ 879 vm_object_t ksobj; 880 vm_offset_t ks; 881 vm_page_t m; 882 int i; 883 884 ksobj = td->td_kstack_obj; 885 ks = td->td_kstack; 886 for (i = 0; i < KSTACK_PAGES; i++) { 887 m = vm_page_lookup(ksobj, i); 888 if (m == NULL) 889 panic("pmap_dispose_thread: kstack already missing?"); 890 vm_page_busy(m); 891 vm_page_unwire(m, 0); 892 vm_page_free(m); 893 } 894 pmap_qremove(ks, KSTACK_PAGES); 895 kmem_free(kernel_map, ks - (KSTACK_GUARD_PAGES * PAGE_SIZE), 896 (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE); 897 vm_object_deallocate(ksobj); 898} 899 900/* 901 * Allow the kernel stack for a thread to be prejudicially paged out. 902 */ 903void 904pmap_swapout_thread(struct thread *td) 905{ 906 vm_object_t ksobj; 907 vm_offset_t ks; 908 vm_page_t m; 909 int i; 910 911 ksobj = td->td_kstack_obj; 912 ks = (vm_offset_t)td->td_kstack; 913 for (i = 0; i < KSTACK_PAGES; i++) { 914 m = vm_page_lookup(ksobj, i); 915 if (m == NULL) 916 panic("pmap_swapout_thread: kstack already missing?"); 917 vm_page_dirty(m); 918 vm_page_unwire(m, 0); 919 } 920 pmap_qremove(ks, KSTACK_PAGES); 921} 922 923/* 924 * Bring the kernel stack for a specified thread back in. 925 */ 926void 927pmap_swapin_thread(struct thread *td) 928{ 929 vm_page_t ma[KSTACK_PAGES]; 930 vm_object_t ksobj; 931 vm_offset_t ks; 932 vm_page_t m; 933 int rv; 934 int i; 935 936 ksobj = td->td_kstack_obj; 937 ks = td->td_kstack; 938 for (i = 0; i < KSTACK_PAGES; i++) { 939 m = vm_page_grab(ksobj, i, VM_ALLOC_NORMAL | VM_ALLOC_RETRY); 940 if (m->valid != VM_PAGE_BITS_ALL) { 941 rv = vm_pager_get_pages(ksobj, &m, 1, 0); 942 if (rv != VM_PAGER_OK) 943 panic("pmap_swapin_thread: cannot get kstack"); 944 m = vm_page_lookup(ksobj, i); 945 m->valid = VM_PAGE_BITS_ALL; 946 } 947 ma[i] = m; 948 vm_page_wire(m); 949 vm_page_wakeup(m); 950 vm_page_flag_set(m, PG_MAPPED | PG_WRITEABLE); 951 } 952 pmap_qenter(ks, ma, KSTACK_PAGES); 953} 954 955/* 956 * Initialize the pmap associated with process 0. 957 */ 958void 959pmap_pinit0(pmap_t pm) 960{ 961 int i; 962 963 for (i = 0; i < MAXCPU; i++) 964 pm->pm_context[i] = 0; 965 pm->pm_active = 0; 966 pm->pm_tsb = NULL; 967 pm->pm_tsb_obj = NULL; 968 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 969} 970 971/* 972 * Initialize a preallocated and zeroed pmap structure, uch as one in a 973 * vmspace structure. 974 */ 975void 976pmap_pinit(pmap_t pm) 977{ 978 vm_page_t ma[TSB_PAGES]; 979 vm_page_t m; 980 int i; 981 982 /* 983 * Allocate kva space for the tsb. 984 */ 985 if (pm->pm_tsb == NULL) { 986 pm->pm_tsb = (struct tte *)kmem_alloc_pageable(kernel_map, 987 TSB_BSIZE); 988 } 989 990 /* 991 * Allocate an object for it. 992 */ 993 if (pm->pm_tsb_obj == NULL) 994 pm->pm_tsb_obj = vm_object_allocate(OBJT_DEFAULT, TSB_PAGES); 995 996 for (i = 0; i < TSB_PAGES; i++) { 997 m = vm_page_grab(pm->pm_tsb_obj, i, 998 VM_ALLOC_RETRY | VM_ALLOC_ZERO); 999 if ((m->flags & PG_ZERO) == 0) 1000 pmap_zero_page(m); 1001 1002 m->wire_count++; 1003 cnt.v_wire_count++; 1004 1005 vm_page_flag_clear(m, PG_MAPPED | PG_BUSY); 1006 m->valid = VM_PAGE_BITS_ALL; 1007 1008 ma[i] = m; 1009 } 1010 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES); 1011 1012 for (i = 0; i < MAXCPU; i++) 1013 pm->pm_context[i] = -1; 1014 pm->pm_active = 0; 1015 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1016} 1017 1018void 1019pmap_pinit2(pmap_t pmap) 1020{ 1021 /* XXX: Remove this stub when no longer called */ 1022} 1023 1024/* 1025 * Release any resources held by the given physical map. 1026 * Called when a pmap initialized by pmap_pinit is being released. 1027 * Should only be called if the map contains no valid mappings. 1028 */ 1029void 1030pmap_release(pmap_t pm) 1031{ 1032 vm_object_t obj; 1033 vm_page_t m; 1034 1035 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p", 1036 pm->pm_context[PCPU_GET(cpuid)], pm->pm_tsb); 1037 obj = pm->pm_tsb_obj; 1038 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1")); 1039 KASSERT(pmap_resident_count(pm) == 0, 1040 ("pmap_release: resident pages %ld != 0", 1041 pmap_resident_count(pm))); 1042 while (!TAILQ_EMPTY(&obj->memq)) { 1043 m = TAILQ_FIRST(&obj->memq); 1044 if (vm_page_sleep_busy(m, FALSE, "pmaprl")) 1045 continue; 1046 vm_page_busy(m); 1047 KASSERT(m->hold_count == 0, 1048 ("pmap_release: freeing held tsb page")); 1049 m->wire_count--; 1050 cnt.v_wire_count--; 1051 vm_page_free_zero(m); 1052 } 1053 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES); 1054} 1055 1056/* 1057 * Grow the number of kernel page table entries. Unneeded. 1058 */ 1059void 1060pmap_growkernel(vm_offset_t addr) 1061{ 1062} 1063 1064/* 1065 * This routine is very drastic, but can save the system 1066 * in a pinch. 1067 */ 1068void 1069pmap_collect(void) 1070{ 1071} 1072 1073int 1074pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp, 1075 vm_offset_t va) 1076{ 1077 vm_page_t m; 1078 1079 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1080 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 1081 if ((tp->tte_data & TD_WIRED) != 0) 1082 pm->pm_stats.wired_count--; 1083 if ((tp->tte_data & TD_PV) != 0) { 1084 if ((tp->tte_data & TD_W) != 0 && 1085 pmap_track_modified(pm, va)) 1086 vm_page_dirty(m); 1087 if ((tp->tte_data & TD_REF) != 0) 1088 vm_page_flag_set(m, PG_REFERENCED); 1089 if (STAILQ_EMPTY(&m->md.tte_list)) 1090 vm_page_flag_clear(m, PG_MAPPED | PG_WRITEABLE); 1091 pm->pm_stats.resident_count--; 1092 } 1093 pmap_cache_remove(m, va); 1094 TTE_ZERO(tp); 1095 if (PMAP_REMOVE_DONE(pm)) 1096 return (0); 1097 return (1); 1098} 1099 1100/* 1101 * Remove the given range of addresses from the specified map. 1102 */ 1103void 1104pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end) 1105{ 1106 struct tte *tp; 1107 vm_offset_t va; 1108 1109 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx", 1110 pm->pm_context[PCPU_GET(cpuid)], start, end); 1111 if (PMAP_REMOVE_DONE(pm)) 1112 return; 1113 if (end - start > PMAP_TSB_THRESH) { 1114 tsb_foreach(pm, NULL, start, end, pmap_remove_tte); 1115 tlb_context_demap(pm); 1116 } else { 1117 for (va = start; va < end; va += PAGE_SIZE) { 1118 if ((tp = tsb_tte_lookup(pm, va)) != NULL) { 1119 if (!pmap_remove_tte(pm, NULL, tp, va)) 1120 break; 1121 } 1122 } 1123 tlb_range_demap(pm, start, end - 1); 1124 } 1125} 1126 1127void 1128pmap_remove_all(vm_page_t m) 1129{ 1130 struct pmap *pm; 1131 struct tte *tpn; 1132 struct tte *tp; 1133 vm_offset_t va; 1134 1135 KASSERT((m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) == 0, 1136 ("pv_remove_all: illegal for unmanaged page %#lx", 1137 VM_PAGE_TO_PHYS(m))); 1138 for (tp = STAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) { 1139 tpn = STAILQ_NEXT(tp, tte_link); 1140 if ((tp->tte_data & TD_PV) == 0) 1141 continue; 1142 pm = TTE_GET_PMAP(tp); 1143 va = TTE_GET_VA(tp); 1144 if ((tp->tte_data & TD_WIRED) != 0) 1145 pm->pm_stats.wired_count--; 1146 if ((tp->tte_data & TD_REF) != 0) 1147 vm_page_flag_set(m, PG_REFERENCED); 1148 if ((tp->tte_data & TD_W) != 0 && 1149 pmap_track_modified(pm, va)) 1150 vm_page_dirty(m); 1151 tp->tte_data &= ~TD_V; 1152 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, va); 1153 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 1154 pm->pm_stats.resident_count--; 1155 pmap_cache_remove(m, va); 1156 TTE_ZERO(tp); 1157 } 1158 vm_page_flag_clear(m, PG_MAPPED | PG_WRITEABLE); 1159} 1160 1161int 1162pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp, 1163 vm_offset_t va) 1164{ 1165 vm_page_t m; 1166 1167 if ((tp->tte_data & TD_PV) != 0) { 1168 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1169 if ((tp->tte_data & TD_REF) != 0) { 1170 vm_page_flag_set(m, PG_REFERENCED); 1171 tp->tte_data &= ~TD_REF; 1172 } 1173 if ((tp->tte_data & TD_W) != 0 && 1174 pmap_track_modified(pm, va)) { 1175 vm_page_dirty(m); 1176 } 1177 } 1178 tp->tte_data &= ~(TD_W | TD_SW); 1179 return (0); 1180} 1181 1182/* 1183 * Set the physical protection on the specified range of this map as requested. 1184 */ 1185void 1186pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1187{ 1188 vm_offset_t va; 1189 struct tte *tp; 1190 1191 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx", 1192 pm->pm_context[PCPU_GET(cpuid)], sva, eva, prot); 1193 1194 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1195 pmap_remove(pm, sva, eva); 1196 return; 1197 } 1198 1199 if (prot & VM_PROT_WRITE) 1200 return; 1201 1202 if (eva - sva > PMAP_TSB_THRESH) { 1203 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte); 1204 tlb_context_demap(pm); 1205 } else { 1206 for (va = sva; va < eva; va += PAGE_SIZE) { 1207 if ((tp = tsb_tte_lookup(pm, va)) != NULL) 1208 pmap_protect_tte(pm, NULL, tp, va); 1209 } 1210 tlb_range_demap(pm, sva, eva - 1); 1211 } 1212} 1213 1214/* 1215 * Map the given physical page at the specified virtual address in the 1216 * target pmap with the protection requested. If specified the page 1217 * will be wired down. 1218 */ 1219void 1220pmap_enter(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1221 boolean_t wired) 1222{ 1223 struct tte *tp; 1224 vm_offset_t pa; 1225 u_long data; 1226 1227 pa = VM_PAGE_TO_PHYS(m); 1228 CTR6(KTR_PMAP, 1229 "pmap_enter: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d", 1230 pm->pm_context[PCPU_GET(cpuid)], m, va, pa, prot, wired); 1231 1232 /* 1233 * If there is an existing mapping, and the physical address has not 1234 * changed, must be protection or wiring change. 1235 */ 1236 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) { 1237 CTR0(KTR_PMAP, "pmap_enter: update"); 1238 PMAP_STATS_INC(pmap_enter_nupdate); 1239 1240 /* 1241 * Wiring change, just update stats. 1242 */ 1243 if (wired) { 1244 if ((tp->tte_data & TD_WIRED) == 0) { 1245 tp->tte_data |= TD_WIRED; 1246 pm->pm_stats.wired_count++; 1247 } 1248 } else { 1249 if ((tp->tte_data & TD_WIRED) != 0) { 1250 tp->tte_data &= ~TD_WIRED; 1251 pm->pm_stats.wired_count--; 1252 } 1253 } 1254 1255 /* 1256 * Save the old bits and clear the ones we're interested in. 1257 */ 1258 data = tp->tte_data; 1259 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W); 1260 1261 /* 1262 * If we're turning off write permissions, sense modify status. 1263 */ 1264 if ((prot & VM_PROT_WRITE) != 0) { 1265 tp->tte_data |= TD_SW; 1266 if (wired) { 1267 tp->tte_data |= TD_W; 1268 } 1269 } else if ((data & TD_W) != 0 && 1270 pmap_track_modified(pm, va)) { 1271 vm_page_dirty(m); 1272 } 1273 1274 /* 1275 * If we're turning on execute permissions, flush the icache. 1276 */ 1277 if ((prot & VM_PROT_EXECUTE) != 0) { 1278 if ((data & TD_EXEC) == 0) { 1279 PMAP_STATS_INC(pmap_niflush); 1280 icache_page_inval(pa); 1281 } 1282 tp->tte_data |= TD_EXEC; 1283 } 1284 1285 /* 1286 * Delete the old mapping. 1287 */ 1288 tlb_tte_demap(tp, pm); 1289 } else { 1290 /* 1291 * If there is an existing mapping, but its for a different 1292 * phsyical address, delete the old mapping. 1293 */ 1294 if (tp != NULL) { 1295 CTR0(KTR_PMAP, "pmap_enter: replace"); 1296 PMAP_STATS_INC(pmap_enter_nreplace); 1297 pmap_remove_tte(pm, NULL, tp, va); 1298 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, va); 1299 } else { 1300 CTR0(KTR_PMAP, "pmap_enter: new"); 1301 PMAP_STATS_INC(pmap_enter_nnew); 1302 } 1303 1304 /* 1305 * Now set up the data and install the new mapping. 1306 */ 1307 data = TD_V | TD_8K | TD_PA(pa) | TD_CP; 1308 if (pm == kernel_pmap) 1309 data |= TD_P; 1310 if (prot & VM_PROT_WRITE) 1311 data |= TD_SW; 1312 if (prot & VM_PROT_EXECUTE) { 1313 data |= TD_EXEC; 1314 PMAP_STATS_INC(pmap_niflush); 1315 icache_page_inval(pa); 1316 } 1317 1318 /* 1319 * If its wired update stats. We also don't need reference or 1320 * modify tracking for wired mappings, so set the bits now. 1321 */ 1322 if (wired) { 1323 pm->pm_stats.wired_count++; 1324 data |= TD_REF | TD_WIRED; 1325 if ((prot & VM_PROT_WRITE) != 0) 1326 data |= TD_W; 1327 } 1328 1329 tsb_tte_enter(pm, m, va, data); 1330 } 1331} 1332 1333void 1334pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1335 vm_pindex_t pindex, vm_size_t size, int limit) 1336{ 1337 /* XXX */ 1338} 1339 1340void 1341pmap_prefault(pmap_t pm, vm_offset_t va, vm_map_entry_t entry) 1342{ 1343 /* XXX */ 1344} 1345 1346/* 1347 * Change the wiring attribute for a map/virtual-address pair. 1348 * The mapping must already exist in the pmap. 1349 */ 1350void 1351pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 1352{ 1353 struct tte *tp; 1354 1355 if ((tp = tsb_tte_lookup(pm, va)) != NULL) { 1356 if (wired) { 1357 if ((tp->tte_data & TD_WIRED) == 0) 1358 pm->pm_stats.wired_count++; 1359 tp->tte_data |= TD_WIRED; 1360 } else { 1361 if ((tp->tte_data & TD_WIRED) != 0) 1362 pm->pm_stats.wired_count--; 1363 tp->tte_data &= ~TD_WIRED; 1364 } 1365 } 1366} 1367 1368static int 1369pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp, vm_offset_t va) 1370{ 1371 vm_page_t m; 1372 u_long data; 1373 1374 if (tsb_tte_lookup(dst_pmap, va) == NULL) { 1375 data = tp->tte_data & 1376 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W); 1377 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1378 tsb_tte_enter(dst_pmap, m, va, data); 1379 } 1380 return (1); 1381} 1382 1383void 1384pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1385 vm_size_t len, vm_offset_t src_addr) 1386{ 1387 struct tte *tp; 1388 vm_offset_t va; 1389 1390 if (dst_addr != src_addr) 1391 return; 1392 if (len > PMAP_TSB_THRESH) { 1393 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len, 1394 pmap_copy_tte); 1395 tlb_context_demap(dst_pmap); 1396 } else { 1397 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE) { 1398 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL) 1399 pmap_copy_tte(src_pmap, dst_pmap, tp, va); 1400 } 1401 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1); 1402 } 1403} 1404 1405/* 1406 * Zero a page of physical memory by temporarily mapping it into the tlb. 1407 */ 1408void 1409pmap_zero_page(vm_page_t m) 1410{ 1411 vm_offset_t pa; 1412 1413 pa = VM_PAGE_TO_PHYS(m); 1414 CTR1(KTR_PMAP, "pmap_zero_page: pa=%#lx", pa); 1415 dcache_page_inval(pa); 1416 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE); 1417} 1418 1419void 1420pmap_zero_page_area(vm_page_t m, int off, int size) 1421{ 1422 vm_offset_t pa; 1423 1424 pa = VM_PAGE_TO_PHYS(m); 1425 CTR3(KTR_PMAP, "pmap_zero_page_area: pa=%#lx off=%#x size=%#x", 1426 pa, off, size); 1427 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size")); 1428 dcache_page_inval(pa); 1429 aszero(ASI_PHYS_USE_EC, pa + off, size); 1430} 1431 1432/* 1433 * Copy a page of physical memory by temporarily mapping it into the tlb. 1434 */ 1435void 1436pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 1437{ 1438 vm_offset_t dst; 1439 vm_offset_t src; 1440 1441 dst = VM_PAGE_TO_PHYS(mdst); 1442 src = VM_PAGE_TO_PHYS(msrc); 1443 CTR2(KTR_PMAP, "pmap_copy_page: src=%#lx dst=%#lx", src, dst); 1444 dcache_page_inval(dst); 1445 ascopy(ASI_PHYS_USE_EC, src, dst, PAGE_SIZE); 1446} 1447 1448/* 1449 * Make the specified page pageable (or not). Unneeded. 1450 */ 1451void 1452pmap_pageable(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1453 boolean_t pageable) 1454{ 1455} 1456 1457/* 1458 * Returns true if the pmap's pv is one of the first 1459 * 16 pvs linked to from this page. This count may 1460 * be changed upwards or downwards in the future; it 1461 * is only necessary that true be returned for a small 1462 * subset of pmaps for proper page aging. 1463 */ 1464boolean_t 1465pmap_page_exists_quick(pmap_t pm, vm_page_t m) 1466{ 1467 struct tte *tp; 1468 int loops; 1469 1470 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1471 return (FALSE); 1472 loops = 0; 1473 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1474 if ((tp->tte_data & TD_PV) == 0) 1475 continue; 1476 if (TTE_GET_PMAP(tp) == pm) 1477 return (TRUE); 1478 if (++loops >= 16) 1479 break; 1480 } 1481 return (FALSE); 1482} 1483 1484/* 1485 * Remove all pages from specified address space, this aids process exit 1486 * speeds. This is much faster than pmap_remove n the case of running down 1487 * an entire address space. Only works for the current pmap. 1488 */ 1489void 1490pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1491{ 1492} 1493 1494/* 1495 * Lower the permission for all mappings to a given page. 1496 */ 1497void 1498pmap_page_protect(vm_page_t m, vm_prot_t prot) 1499{ 1500 1501 if ((prot & VM_PROT_WRITE) == 0) { 1502 if (prot & (VM_PROT_READ | VM_PROT_EXECUTE)) 1503 pmap_clear_write(m); 1504 else 1505 pmap_remove_all(m); 1506 } 1507} 1508 1509vm_offset_t 1510pmap_phys_address(int ppn) 1511{ 1512 1513 return (sparc64_ptob(ppn)); 1514} 1515 1516/* 1517 * pmap_ts_referenced: 1518 * 1519 * Return a count of reference bits for a page, clearing those bits. 1520 * It is not necessary for every reference bit to be cleared, but it 1521 * is necessary that 0 only be returned when there are truly no 1522 * reference bits set. 1523 * 1524 * XXX: The exact number of bits to check and clear is a matter that 1525 * should be tested and standardized at some point in the future for 1526 * optimal aging of shared pages. 1527 */ 1528 1529int 1530pmap_ts_referenced(vm_page_t m) 1531{ 1532 struct tte *tpf; 1533 struct tte *tpn; 1534 struct tte *tp; 1535 int count; 1536 1537 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1538 return (0); 1539 count = 0; 1540 if ((tp = STAILQ_FIRST(&m->md.tte_list)) != NULL) { 1541 tpf = tp; 1542 do { 1543 tpn = STAILQ_NEXT(tp, tte_link); 1544 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 1545 STAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link); 1546 if ((tp->tte_data & TD_PV) == 0 || 1547 !pmap_track_modified(TTE_GET_PMAP(tp), 1548 TTE_GET_VA(tp))) 1549 continue; 1550 if ((tp->tte_data & TD_REF) != 0) { 1551 tp->tte_data &= ~TD_REF; 1552 if (++count > 4) 1553 break; 1554 } 1555 } while ((tp = tpn) != NULL && tp != tpf); 1556 } 1557 return (count); 1558} 1559 1560boolean_t 1561pmap_is_modified(vm_page_t m) 1562{ 1563 struct tte *tp; 1564 1565 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1566 return FALSE; 1567 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1568 if ((tp->tte_data & TD_PV) == 0 || 1569 !pmap_track_modified(TTE_GET_PMAP(tp), TTE_GET_VA(tp))) 1570 continue; 1571 if ((tp->tte_data & TD_W) != 0) 1572 return (TRUE); 1573 } 1574 return (FALSE); 1575} 1576 1577void 1578pmap_clear_modify(vm_page_t m) 1579{ 1580 struct tte *tp; 1581 1582 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1583 return; 1584 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1585 if ((tp->tte_data & TD_PV) == 0) 1586 continue; 1587 if ((tp->tte_data & TD_W) != 0) { 1588 tp->tte_data &= ~TD_W; 1589 tlb_tte_demap(tp, TTE_GET_PMAP(tp)); 1590 } 1591 } 1592} 1593 1594void 1595pmap_clear_reference(vm_page_t m) 1596{ 1597 struct tte *tp; 1598 1599 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1600 return; 1601 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1602 if ((tp->tte_data & TD_PV) == 0) 1603 continue; 1604 if ((tp->tte_data & TD_REF) != 0) { 1605 tp->tte_data &= ~TD_REF; 1606 tlb_tte_demap(tp, TTE_GET_PMAP(tp)); 1607 } 1608 } 1609} 1610 1611void 1612pmap_clear_write(vm_page_t m) 1613{ 1614 struct tte *tp; 1615 1616 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1617 return; 1618 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1619 if ((tp->tte_data & TD_PV) == 0) 1620 continue; 1621 if ((tp->tte_data & (TD_SW | TD_W)) != 0) { 1622 if ((tp->tte_data & TD_W) != 0 && 1623 pmap_track_modified(TTE_GET_PMAP(tp), 1624 TTE_GET_VA(tp))) 1625 vm_page_dirty(m); 1626 tp->tte_data &= ~(TD_SW | TD_W); 1627 tlb_tte_demap(tp, TTE_GET_PMAP(tp)); 1628 } 1629 } 1630} 1631 1632int 1633pmap_mincore(pmap_t pm, vm_offset_t addr) 1634{ 1635 TODO; 1636 return (0); 1637} 1638 1639/* 1640 * Activate a user pmap. The pmap must be activated before its address space 1641 * can be accessed in any way. 1642 */ 1643void 1644pmap_activate(struct thread *td) 1645{ 1646 struct vmspace *vm; 1647 vm_offset_t tsb; 1648 u_long context; 1649 pmap_t pm; 1650 1651 /* 1652 * Load all the data we need up front to encourage the compiler to 1653 * not issue any loads while we have interrupts disable below. 1654 */ 1655 vm = td->td_proc->p_vmspace; 1656 pm = &vm->vm_pmap; 1657 tsb = (vm_offset_t)pm->pm_tsb; 1658 1659 KASSERT(pm->pm_active == 0, ("pmap_activate: pmap already active?")); 1660 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != 0, 1661 ("pmap_activate: activating nucleus context?")); 1662 1663 mtx_lock_spin(&sched_lock); 1664 wrpr(pstate, 0, PSTATE_MMU); 1665 mov(tsb, TSB_REG); 1666 wrpr(pstate, 0, PSTATE_KERNEL); 1667 context = pmap_context_alloc(); 1668 pm->pm_context[PCPU_GET(cpuid)] = context; 1669 pm->pm_active |= PCPU_GET(cpumask); 1670 PCPU_SET(vmspace, vm); 1671 stxa(AA_DMMU_PCXR, ASI_DMMU, context); 1672 membar(Sync); 1673 mtx_unlock_spin(&sched_lock); 1674} 1675 1676vm_offset_t 1677pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 1678{ 1679 1680 return (va); 1681} 1682