pmap.c revision 97447
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the University of 24 * California, Berkeley and its contributors. 25 * 4. Neither the name of the University nor the names of its contributors 26 * may be used to endorse or promote products derived from this software 27 * without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 39 * SUCH DAMAGE. 40 * 41 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 42 * $FreeBSD: head/sys/sparc64/sparc64/pmap.c 97447 2002-05-29 06:08:45Z jake $ 43 */ 44 45/* 46 * Manages physical address maps. 47 * 48 * In addition to hardware address maps, this module is called upon to 49 * provide software-use-only maps which may or may not be stored in the 50 * same form as hardware maps. These pseudo-maps are used to store 51 * intermediate results from copy operations to and from address spaces. 52 * 53 * Since the information managed by this module is also stored by the 54 * logical address mapping module, this module may throw away valid virtual 55 * to physical mappings at almost any time. However, invalidations of 56 * mappings must be done as requested. 57 * 58 * In order to cope with hardware architectures which make virtual to 59 * physical map invalidates expensive, this module may delay invalidate 60 * reduced protection operations until such time as they are actually 61 * necessary. This module is given full information as to which processors 62 * are currently using which maps, and to when physical maps must be made 63 * correct. 64 */ 65 66#include "opt_msgbuf.h" 67#include "opt_pmap.h" 68 69#include <sys/param.h> 70#include <sys/kernel.h> 71#include <sys/ktr.h> 72#include <sys/lock.h> 73#include <sys/msgbuf.h> 74#include <sys/mutex.h> 75#include <sys/proc.h> 76#include <sys/smp.h> 77#include <sys/sysctl.h> 78#include <sys/systm.h> 79#include <sys/vmmeter.h> 80 81#include <dev/ofw/openfirm.h> 82 83#include <vm/vm.h> 84#include <vm/vm_param.h> 85#include <vm/vm_kern.h> 86#include <vm/vm_page.h> 87#include <vm/vm_map.h> 88#include <vm/vm_object.h> 89#include <vm/vm_extern.h> 90#include <vm/vm_pageout.h> 91#include <vm/vm_pager.h> 92#include <vm/uma.h> 93 94#include <machine/cache.h> 95#include <machine/frame.h> 96#include <machine/md_var.h> 97#include <machine/metadata.h> 98#include <machine/smp.h> 99#include <machine/tlb.h> 100#include <machine/tte.h> 101#include <machine/tsb.h> 102 103#define PMAP_DEBUG 104 105#ifndef PMAP_SHPGPERPROC 106#define PMAP_SHPGPERPROC 200 107#endif 108 109struct mem_region { 110 vm_offset_t mr_start; 111 vm_offset_t mr_size; 112}; 113 114struct ofw_map { 115 vm_offset_t om_start; 116 vm_offset_t om_size; 117 u_long om_tte; 118}; 119 120/* 121 * Virtual and physical address of message buffer. 122 */ 123struct msgbuf *msgbufp; 124vm_offset_t msgbuf_phys; 125 126/* 127 * Physical addresses of first and last available physical page. 128 */ 129vm_offset_t avail_start; 130vm_offset_t avail_end; 131 132int pmap_pagedaemon_waken; 133 134/* 135 * Map of physical memory reagions. 136 */ 137vm_offset_t phys_avail[128]; 138static struct mem_region mra[128]; 139static struct ofw_map translations[128]; 140static int translations_size; 141 142/* 143 * First and last available kernel virtual addresses. 144 */ 145vm_offset_t virtual_avail; 146vm_offset_t virtual_end; 147vm_offset_t kernel_vm_end; 148 149/* 150 * Kernel pmap. 151 */ 152struct pmap kernel_pmap_store; 153 154static boolean_t pmap_initialized = FALSE; 155 156/* 157 * Allocate physical memory for use in pmap_bootstrap. 158 */ 159static vm_offset_t pmap_bootstrap_alloc(vm_size_t size); 160 161/* 162 * If user pmap is processed with pmap_remove and with pmap_remove and the 163 * resident count drops to 0, there are no more pages to remove, so we 164 * need not continue. 165 */ 166#define PMAP_REMOVE_DONE(pm) \ 167 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0) 168 169/* 170 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove() 171 * and pmap_protect() instead of trying each virtual address. 172 */ 173#define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE) 174 175#ifdef PMAP_STATS 176static long pmap_enter_nupdate; 177static long pmap_enter_nreplace; 178static long pmap_enter_nnew; 179static long pmap_ncache_enter; 180static long pmap_ncache_enter_nc; 181static long pmap_niflush; 182 183SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, "Statistics"); 184SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_enter_nupdate, CTLFLAG_RD, 185 &pmap_enter_nupdate, 0, "Number of pmap_enter() updates"); 186SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_enter_nreplace, CTLFLAG_RD, 187 &pmap_enter_nreplace, 0, "Number of pmap_enter() replacements"); 188SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_enter_nnew, CTLFLAG_RD, 189 &pmap_enter_nnew, 0, "Number of pmap_enter() additions"); 190SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_ncache_enter, CTLFLAG_RD, 191 &pmap_ncache_enter, 0, "Number of pmap_cache_enter() calls"); 192SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_ncache_enter_nc, CTLFLAG_RD, 193 &pmap_ncache_enter_nc, 0, "Number of pmap_cache_enter() nc"); 194SYSCTL_LONG(_debug_pmap_stats, OID_AUTO, pmap_niflush, CTLFLAG_RD, 195 &pmap_niflush, 0, "Number of pmap I$ flushes"); 196 197#define PMAP_STATS_INC(var) atomic_add_long(&var, 1) 198#else 199#define PMAP_STATS_INC(var) 200#endif 201 202/* 203 * Quick sort callout for comparing memory regions. 204 */ 205static int mr_cmp(const void *a, const void *b); 206static int om_cmp(const void *a, const void *b); 207static int 208mr_cmp(const void *a, const void *b) 209{ 210 const struct mem_region *mra; 211 const struct mem_region *mrb; 212 213 mra = a; 214 mrb = b; 215 if (mra->mr_start < mrb->mr_start) 216 return (-1); 217 else if (mra->mr_start > mrb->mr_start) 218 return (1); 219 else 220 return (0); 221} 222static int 223om_cmp(const void *a, const void *b) 224{ 225 const struct ofw_map *oma; 226 const struct ofw_map *omb; 227 228 oma = a; 229 omb = b; 230 if (oma->om_start < omb->om_start) 231 return (-1); 232 else if (oma->om_start > omb->om_start) 233 return (1); 234 else 235 return (0); 236} 237 238/* 239 * Bootstrap the system enough to run with virtual memory. 240 */ 241void 242pmap_bootstrap(vm_offset_t ekva) 243{ 244 struct pmap *pm; 245 struct tte *tp; 246 vm_offset_t off; 247 vm_offset_t pa; 248 vm_offset_t va; 249 vm_size_t physsz; 250 ihandle_t pmem; 251 ihandle_t vmem; 252 int sz; 253 int i; 254 int j; 255 256 /* 257 * Set the start and end of kva. The kernel is loaded at the first 258 * available 4 meg super page, so round up to the end of the page. 259 */ 260 virtual_avail = roundup2(ekva, PAGE_SIZE_4M); 261 virtual_end = VM_MAX_KERNEL_ADDRESS; 262 263 /* 264 * Find out what physical memory is available from the prom and 265 * initialize the phys_avail array. This must be done before 266 * pmap_bootstrap_alloc is called. 267 */ 268 if ((pmem = OF_finddevice("/memory")) == -1) 269 panic("pmap_bootstrap: finddevice /memory"); 270 if ((sz = OF_getproplen(pmem, "available")) == -1) 271 panic("pmap_bootstrap: getproplen /memory/available"); 272 if (sizeof(phys_avail) < sz) 273 panic("pmap_bootstrap: phys_avail too small"); 274 if (sizeof(mra) < sz) 275 panic("pmap_bootstrap: mra too small"); 276 bzero(mra, sz); 277 if (OF_getprop(pmem, "available", mra, sz) == -1) 278 panic("pmap_bootstrap: getprop /memory/available"); 279 sz /= sizeof(*mra); 280 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 281 qsort(mra, sz, sizeof (*mra), mr_cmp); 282 physsz = 0; 283 for (i = 0, j = 0; i < sz; i++, j += 2) { 284 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start, 285 mra[i].mr_size); 286 phys_avail[j] = mra[i].mr_start; 287 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size; 288 physsz += mra[i].mr_size; 289 } 290 physmem = btoc(physsz); 291 292 /* 293 * Allocate the kernel tsb and lock it in the tlb. 294 */ 295 pa = pmap_bootstrap_alloc(KVA_PAGES * PAGE_SIZE_4M); 296 if (pa & PAGE_MASK_4M) 297 panic("pmap_bootstrap: tsb unaligned\n"); 298 tsb_kernel_phys = pa; 299 tsb_kernel = (struct tte *)virtual_avail; 300 virtual_avail += KVA_PAGES * PAGE_SIZE_4M; 301 pmap_map_tsb(); 302 bzero(tsb_kernel, KVA_PAGES * PAGE_SIZE_4M); 303 304 /* 305 * Enter fake 8k pages for the 4MB kernel pages, so that 306 * pmap_kextract() will work for them. 307 */ 308 for (i = 0; i < kernel_tlb_slots; i++) { 309 pa = kernel_tlbs[i].te_pa; 310 va = kernel_tlbs[i].te_va; 311 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) { 312 tp = tsb_kvtotte(va + off); 313 tp->tte_vpn = TV_VPN(va + off); 314 tp->tte_data = TD_V | TD_8K | TD_PA(pa + off) | 315 TD_REF | TD_SW | TD_CP | TD_CV | TD_P | TD_W; 316 } 317 } 318 319 /* 320 * Allocate a kernel stack with guard page for thread0 and map it into 321 * the kernel tsb. 322 */ 323 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE); 324 kstack0_phys = pa; 325 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE); 326 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE; 327 for (i = 0; i < KSTACK_PAGES; i++) { 328 pa = kstack0_phys + i * PAGE_SIZE; 329 va = kstack0 + i * PAGE_SIZE; 330 tp = tsb_kvtotte(va); 331 tp->tte_vpn = TV_VPN(va); 332 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | 333 TD_CP | TD_CV | TD_P | TD_W; 334 } 335 336 /* 337 * Allocate the message buffer. 338 */ 339 msgbuf_phys = pmap_bootstrap_alloc(MSGBUF_SIZE); 340 341 /* 342 * Add the prom mappings to the kernel tsb. 343 */ 344 if ((vmem = OF_finddevice("/virtual-memory")) == -1) 345 panic("pmap_bootstrap: finddevice /virtual-memory"); 346 if ((sz = OF_getproplen(vmem, "translations")) == -1) 347 panic("pmap_bootstrap: getproplen translations"); 348 if (sizeof(translations) < sz) 349 panic("pmap_bootstrap: translations too small"); 350 bzero(translations, sz); 351 if (OF_getprop(vmem, "translations", translations, sz) == -1) 352 panic("pmap_bootstrap: getprop /virtual-memory/translations"); 353 sz /= sizeof(*translations); 354 translations_size = sz; 355 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 356 qsort(translations, sz, sizeof (*translations), om_cmp); 357 for (i = 0; i < sz; i++) { 358 CTR3(KTR_PMAP, 359 "translation: start=%#lx size=%#lx tte=%#lx", 360 translations[i].om_start, translations[i].om_size, 361 translations[i].om_tte); 362 if (translations[i].om_start < 0xf0000000) /* XXX!!! */ 363 continue; 364 for (off = 0; off < translations[i].om_size; 365 off += PAGE_SIZE) { 366 va = translations[i].om_start + off; 367 tp = tsb_kvtotte(va); 368 tp->tte_vpn = TV_VPN(va); 369 tp->tte_data = translations[i].om_tte + off; 370 } 371 } 372 373 /* 374 * Calculate the first and last available physical addresses. 375 */ 376 avail_start = phys_avail[0]; 377 for (i = 0; phys_avail[i + 2] != 0; i += 2) 378 ; 379 avail_end = phys_avail[i + 1]; 380 Maxmem = sparc64_btop(avail_end); 381 382 /* 383 * Allocate virtual address space for the message buffer. 384 */ 385 msgbufp = (struct msgbuf *)virtual_avail; 386 virtual_avail += round_page(MSGBUF_SIZE); 387 388 /* 389 * Initialize the kernel pmap (which is statically allocated). 390 */ 391 pm = kernel_pmap; 392 for (i = 0; i < MAXCPU; i++) 393 pm->pm_context[i] = TLB_CTX_KERNEL; 394 pm->pm_active = ~0; 395 396 /* XXX flush all non-locked tlb entries */ 397} 398 399void 400pmap_map_tsb(void) 401{ 402 vm_offset_t va; 403 vm_offset_t pa; 404 u_long data; 405 u_long s; 406 int i; 407 408 s = intr_disable(); 409 410 /* 411 * Map the 4mb tsb pages. 412 */ 413 for (i = 0; i < KVA_PAGES; i++) { 414 va = (vm_offset_t)tsb_kernel + i * PAGE_SIZE_4M; 415 pa = tsb_kernel_phys + i * PAGE_SIZE_4M; 416 /* XXX - cheetah */ 417 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV | 418 TD_P | TD_W; 419 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | 420 TLB_TAR_CTX(TLB_CTX_KERNEL)); 421 stxa(0, ASI_DTLB_DATA_IN_REG, data); 422 membar(Sync); 423 } 424 425 /* 426 * Load the tsb registers. 427 */ 428 stxa(AA_DMMU_TSB, ASI_DMMU, (vm_offset_t)tsb_kernel); 429 stxa(AA_IMMU_TSB, ASI_IMMU, (vm_offset_t)tsb_kernel); 430 membar(Sync); 431 flush(tsb_kernel); 432 433 /* 434 * Set the secondary context to be the kernel context (needed for 435 * fp block operations in the kernel and the cache code). 436 */ 437 stxa(AA_DMMU_SCXR, ASI_DMMU, TLB_CTX_KERNEL); 438 membar(Sync); 439 440 intr_restore(s); 441} 442 443/* 444 * Allocate a physical page of memory directly from the phys_avail map. 445 * Can only be called from pmap_bootstrap before avail start and end are 446 * calculated. 447 */ 448static vm_offset_t 449pmap_bootstrap_alloc(vm_size_t size) 450{ 451 vm_offset_t pa; 452 int i; 453 454 size = round_page(size); 455 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 456 if (phys_avail[i + 1] - phys_avail[i] < size) 457 continue; 458 pa = phys_avail[i]; 459 phys_avail[i] += size; 460 return (pa); 461 } 462 panic("pmap_bootstrap_alloc"); 463} 464 465void 466pmap_context_rollover(void) 467{ 468 u_long data; 469 u_long tag; 470 int i; 471 472 mtx_assert(&sched_lock, MA_OWNED); 473 CTR0(KTR_PMAP, "pmap_context_rollover"); 474 for (i = 0; i < 64; i++) { 475 /* XXX - cheetah */ 476 data = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG); 477 tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG); 478 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 479 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 480 stxa_sync(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG, 0); 481 data = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG); 482 tag = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG); 483 if ((data & TD_V) != 0 && (data & TD_L) == 0 && 484 TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 485 stxa_sync(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG, 0); 486 } 487 PCPU_SET(tlb_ctx, PCPU_GET(tlb_ctx_min)); 488} 489 490static __inline u_int 491pmap_context_alloc(void) 492{ 493 u_int context; 494 495 mtx_assert(&sched_lock, MA_OWNED); 496 context = PCPU_GET(tlb_ctx); 497 if (context + 1 == PCPU_GET(tlb_ctx_max)) 498 pmap_context_rollover(); 499 else 500 PCPU_SET(tlb_ctx, context + 1); 501 return (context); 502} 503 504/* 505 * Initialize the pmap module. 506 */ 507void 508pmap_init(vm_offset_t phys_start, vm_offset_t phys_end) 509{ 510 vm_offset_t addr; 511 vm_size_t size; 512 int result; 513 int i; 514 515 for (i = 0; i < vm_page_array_size; i++) { 516 vm_page_t m; 517 518 m = &vm_page_array[i]; 519 STAILQ_INIT(&m->md.tte_list); 520 } 521 522 for (i = 0; i < translations_size; i++) { 523 addr = translations[i].om_start; 524 size = translations[i].om_size; 525 if (addr < 0xf0000000) /* XXX */ 526 continue; 527 result = vm_map_find(kernel_map, NULL, 0, &addr, size, TRUE, 528 VM_PROT_ALL, VM_PROT_ALL, 0); 529 if (result != KERN_SUCCESS || addr != translations[i].om_start) 530 panic("pmap_init: vm_map_find"); 531 } 532 533 pmap_initialized = TRUE; 534} 535 536/* 537 * Initialize the address space (zone) for the pv_entries. Set a 538 * high water mark so that the system can recover from excessive 539 * numbers of pv entries. 540 */ 541void 542pmap_init2(void) 543{ 544} 545 546/* 547 * Extract the physical page address associated with the given 548 * map/virtual_address pair. 549 */ 550vm_offset_t 551pmap_extract(pmap_t pm, vm_offset_t va) 552{ 553 struct tte *tp; 554 555 if (pm == kernel_pmap) 556 return (pmap_kextract(va)); 557 tp = tsb_tte_lookup(pm, va); 558 if (tp == NULL) 559 return (0); 560 else 561 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp))); 562} 563 564/* 565 * Extract the physical page address associated with the given kernel virtual 566 * address. 567 */ 568vm_offset_t 569pmap_kextract(vm_offset_t va) 570{ 571 struct tte *tp; 572 573 tp = tsb_kvtotte(va); 574 if ((tp->tte_data & TD_V) == 0) 575 return (0); 576 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp))); 577} 578 579int 580pmap_cache_enter(vm_page_t m, vm_offset_t va) 581{ 582 struct tte *tp; 583 int c, i; 584 585 CTR2(KTR_PMAP, "pmap_cache_enter: m=%p va=%#lx", m, va); 586 PMAP_STATS_INC(pmap_ncache_enter); 587 for (i = 0, c = 0; i < DCACHE_COLORS; i++) { 588 if (i != DCACHE_COLOR(va)) 589 c += m->md.colors[i]; 590 } 591 m->md.colors[DCACHE_COLOR(va)]++; 592 if (c == 0) { 593 CTR0(KTR_PMAP, "pmap_cache_enter: cacheable"); 594 return (1); 595 } 596 PMAP_STATS_INC(pmap_ncache_enter_nc); 597 if (c != 1) { 598 CTR0(KTR_PMAP, "pmap_cache_enter: already uncacheable"); 599 return (0); 600 } 601 CTR0(KTR_PMAP, "pmap_cache_enter: marking uncacheable"); 602 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 603 tp->tte_data &= ~TD_CV; 604 tlb_page_demap(TLB_DTLB | TLB_ITLB, TTE_GET_PMAP(tp), 605 TTE_GET_VA(tp)); 606 } 607 dcache_page_inval(VM_PAGE_TO_PHYS(m)); 608 return (0); 609} 610 611void 612pmap_cache_remove(vm_page_t m, vm_offset_t va) 613{ 614 struct tte *tp; 615 int c, i; 616 617 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va, 618 m->md.colors[DCACHE_COLOR(va)]); 619 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0, 620 ("pmap_cache_remove: no mappings %d <= 0", 621 m->md.colors[DCACHE_COLOR(va)])); 622 m->md.colors[DCACHE_COLOR(va)]--; 623 for (i = 0, c = 0; i < DCACHE_COLORS; i++) { 624 if (m->md.colors[i] != 0) 625 c++; 626 } 627 if (c != 1) 628 return; 629 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 630 tp->tte_data |= TD_CV; 631 tlb_page_demap(TLB_DTLB | TLB_ITLB, TTE_GET_PMAP(tp), 632 TTE_GET_VA(tp)); 633 } 634} 635 636/* 637 * Map a wired page into kernel virtual address space. 638 */ 639void 640pmap_kenter(vm_offset_t va, vm_offset_t pa) 641{ 642 vm_offset_t ova; 643 struct tte *tp; 644 vm_page_t om; 645 vm_page_t m; 646 u_long data; 647 648 tp = tsb_kvtotte(va); 649 m = PHYS_TO_VM_PAGE(pa); 650 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx", 651 va, pa, tp, tp->tte_data); 652 if ((tp->tte_data & TD_V) != 0) { 653 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 654 ova = TTE_GET_VA(tp); 655 STAILQ_REMOVE(&om->md.tte_list, tp, tte, tte_link); 656 pmap_cache_remove(om, ova); 657 if (va != ova) 658 tlb_page_demap(TLB_DTLB, kernel_pmap, ova); 659 } 660 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP | TD_P | TD_W; 661 if (pmap_cache_enter(m, va) != 0) 662 data |= TD_CV; 663 tp->tte_vpn = TV_VPN(va); 664 tp->tte_data = data; 665 STAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link); 666 tp->tte_pmap = kernel_pmap; 667} 668 669/* 670 * Map a wired page into kernel virtual address space. This additionally 671 * takes a flag argument wich is or'ed to the TTE data. This is used by 672 * bus_space_map(). 673 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility 674 * to flush entries that might still be in the cache, if applicable. 675 */ 676void 677pmap_kenter_flags(vm_offset_t va, vm_offset_t pa, u_long flags) 678{ 679 struct tte *tp; 680 681 tp = tsb_kvtotte(va); 682 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx", 683 va, pa, tp, tp->tte_data); 684 tp->tte_vpn = TV_VPN(va); 685 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags; 686} 687 688/* 689 * Make a temporary mapping for a physical address. This is only intended 690 * to be used for panic dumps. 691 */ 692void * 693pmap_kenter_temporary(vm_offset_t pa, int i) 694{ 695 696 TODO; 697} 698 699/* 700 * Remove a wired page from kernel virtual address space. 701 */ 702void 703pmap_kremove(vm_offset_t va) 704{ 705 struct tte *tp; 706 vm_page_t m; 707 708 tp = tsb_kvtotte(va); 709 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp, 710 tp->tte_data); 711 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 712 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 713 pmap_cache_remove(m, va); 714 TTE_ZERO(tp); 715} 716 717/* 718 * Map a range of physical addresses into kernel virtual address space. 719 * 720 * The value passed in *virt is a suggested virtual address for the mapping. 721 * Architectures which can support a direct-mapped physical to virtual region 722 * can return the appropriate address within that region, leaving '*virt' 723 * unchanged. We cannot and therefore do not; *virt is updated with the 724 * first usable address after the mapped region. 725 */ 726vm_offset_t 727pmap_map(vm_offset_t *virt, vm_offset_t pa_start, vm_offset_t pa_end, int prot) 728{ 729 struct tte *tp; 730 vm_offset_t sva; 731 vm_offset_t va; 732 vm_offset_t pa; 733 734 pa = pa_start; 735 sva = *virt; 736 va = sva; 737 for (; pa < pa_end; pa += PAGE_SIZE, va += PAGE_SIZE) { 738 tp = tsb_kvtotte(va); 739 tp->tte_vpn = TV_VPN(va); 740 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | 741 TD_CP | TD_CV | TD_P | TD_W; 742 } 743 tlb_range_demap(kernel_pmap, sva, sva + (pa_end - pa_start) - 1); 744 *virt = va; 745 return (sva); 746} 747 748/* 749 * Map a list of wired pages into kernel virtual address space. This is 750 * intended for temporary mappings which do not need page modification or 751 * references recorded. Existing mappings in the region are overwritten. 752 */ 753void 754pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 755{ 756 vm_offset_t va; 757 int i; 758 759 va = sva; 760 for (i = 0; i < count; i++, va += PAGE_SIZE) 761 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 762 tlb_range_demap(kernel_pmap, sva, sva + (count * PAGE_SIZE) - 1); 763} 764 765/* 766 * As above, but take an additional flags argument and call 767 * pmap_kenter_flags(). 768 */ 769void 770pmap_qenter_flags(vm_offset_t sva, vm_page_t *m, int count, u_long fl) 771{ 772 vm_offset_t va; 773 int i; 774 775 va = sva; 776 for (i = 0; i < count; i++, va += PAGE_SIZE) 777 pmap_kenter_flags(va, VM_PAGE_TO_PHYS(m[i]), fl); 778 tlb_range_demap(kernel_pmap, sva, sva + (count * PAGE_SIZE) - 1); 779} 780 781/* 782 * Remove page mappings from kernel virtual address space. Intended for 783 * temporary mappings entered by pmap_qenter. 784 */ 785void 786pmap_qremove(vm_offset_t sva, int count) 787{ 788 vm_offset_t va; 789 int i; 790 791 va = sva; 792 for (i = 0; i < count; i++, va += PAGE_SIZE) 793 pmap_kremove(va); 794 tlb_range_demap(kernel_pmap, sva, sva + (count * PAGE_SIZE) - 1); 795} 796 797/* 798 * Create the uarea for a new process. 799 * This routine directly affects the fork perf for a process. 800 */ 801void 802pmap_new_proc(struct proc *p) 803{ 804 vm_page_t ma[UAREA_PAGES]; 805 vm_object_t upobj; 806 vm_offset_t up; 807 vm_page_t m; 808 u_int i; 809 810 /* 811 * Allocate object for the upages. 812 */ 813 upobj = p->p_upages_obj; 814 if (upobj == NULL) { 815 upobj = vm_object_allocate(OBJT_DEFAULT, UAREA_PAGES); 816 p->p_upages_obj = upobj; 817 } 818 819 /* 820 * Get a kernel virtual address for the U area for this process. 821 */ 822 up = (vm_offset_t)p->p_uarea; 823 if (up == 0) { 824 up = kmem_alloc_nofault(kernel_map, UAREA_PAGES * PAGE_SIZE); 825 if (up == 0) 826 panic("pmap_new_proc: upage allocation failed"); 827 p->p_uarea = (struct user *)up; 828 } 829 830 for (i = 0; i < UAREA_PAGES; i++) { 831 /* 832 * Get a uarea page. 833 */ 834 m = vm_page_grab(upobj, i, VM_ALLOC_NORMAL | VM_ALLOC_RETRY); 835 ma[i] = m; 836 837 /* 838 * Wire the page. 839 */ 840 m->wire_count++; 841 cnt.v_wire_count++; 842 843 vm_page_wakeup(m); 844 vm_page_flag_clear(m, PG_ZERO); 845 vm_page_flag_set(m, PG_MAPPED | PG_WRITEABLE); 846 m->valid = VM_PAGE_BITS_ALL; 847 } 848 849 /* 850 * Enter the pages into the kernel address space. 851 */ 852 pmap_qenter(up, ma, UAREA_PAGES); 853} 854 855/* 856 * Dispose the uarea for a process that has exited. 857 * This routine directly impacts the exit perf of a process. 858 */ 859void 860pmap_dispose_proc(struct proc *p) 861{ 862 vm_object_t upobj; 863 vm_offset_t up; 864 vm_page_t m; 865 int i; 866 867 upobj = p->p_upages_obj; 868 up = (vm_offset_t)p->p_uarea; 869 for (i = 0; i < UAREA_PAGES; i++) { 870 m = vm_page_lookup(upobj, i); 871 if (m == NULL) 872 panic("pmap_dispose_proc: upage already missing?"); 873 vm_page_busy(m); 874 vm_page_unwire(m, 0); 875 vm_page_free(m); 876 } 877 pmap_qremove(up, UAREA_PAGES); 878 879 /* 880 * If the process got swapped out some of its UPAGES might have gotten 881 * swapped. Just get rid of the object to clean up the swap use 882 * proactively. NOTE! might block waiting for paging I/O to complete. 883 */ 884 if (upobj->type == OBJT_SWAP) { 885 p->p_upages_obj = NULL; 886 vm_object_deallocate(upobj); 887 } 888} 889 890/* 891 * Allow the uarea for a process to be prejudicially paged out. 892 */ 893void 894pmap_swapout_proc(struct proc *p) 895{ 896 vm_object_t upobj; 897 vm_offset_t up; 898 vm_page_t m; 899 int i; 900 901 upobj = p->p_upages_obj; 902 up = (vm_offset_t)p->p_uarea; 903 for (i = 0; i < UAREA_PAGES; i++) { 904 m = vm_page_lookup(upobj, i); 905 if (m == NULL) 906 panic("pmap_swapout_proc: upage already missing?"); 907 vm_page_dirty(m); 908 vm_page_unwire(m, 0); 909 } 910 pmap_qremove(up, UAREA_PAGES); 911} 912 913/* 914 * Bring the uarea for a specified process back in. 915 */ 916void 917pmap_swapin_proc(struct proc *p) 918{ 919 vm_page_t ma[UAREA_PAGES]; 920 vm_object_t upobj; 921 vm_offset_t up; 922 vm_page_t m; 923 int rv; 924 int i; 925 926 upobj = p->p_upages_obj; 927 up = (vm_offset_t)p->p_uarea; 928 for (i = 0; i < UAREA_PAGES; i++) { 929 m = vm_page_grab(upobj, i, VM_ALLOC_NORMAL | VM_ALLOC_RETRY); 930 if (m->valid != VM_PAGE_BITS_ALL) { 931 rv = vm_pager_get_pages(upobj, &m, 1, 0); 932 if (rv != VM_PAGER_OK) 933 panic("pmap_swapin_proc: cannot get upage"); 934 m = vm_page_lookup(upobj, i); 935 m->valid = VM_PAGE_BITS_ALL; 936 } 937 ma[i] = m; 938 vm_page_wire(m); 939 vm_page_wakeup(m); 940 vm_page_flag_set(m, PG_MAPPED | PG_WRITEABLE); 941 } 942 pmap_qenter(up, ma, UAREA_PAGES); 943} 944 945/* 946 * Create the kernel stack and pcb for a new thread. 947 * This routine directly affects the fork perf for a process and 948 * create performance for a thread. 949 */ 950void 951pmap_new_thread(struct thread *td) 952{ 953 vm_page_t ma[KSTACK_PAGES]; 954 vm_object_t ksobj; 955 vm_offset_t ks; 956 vm_page_t m; 957 u_int i; 958 959 /* 960 * Allocate object for the kstack, 961 */ 962 ksobj = td->td_kstack_obj; 963 if (ksobj == NULL) { 964 ksobj = vm_object_allocate(OBJT_DEFAULT, KSTACK_PAGES); 965 td->td_kstack_obj = ksobj; 966 } 967 968 /* 969 * Get a kernel virtual address for the kstack for this thread. 970 */ 971 ks = td->td_kstack; 972 if (ks == 0) { 973 ks = kmem_alloc_nofault(kernel_map, 974 (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE); 975 if (ks == 0) 976 panic("pmap_new_thread: kstack allocation failed"); 977 if (KSTACK_GUARD_PAGES != 0) { 978 tlb_page_demap(TLB_DTLB, kernel_pmap, ks); 979 ks += KSTACK_GUARD_PAGES * PAGE_SIZE; 980 } 981 td->td_kstack = ks; 982 } 983 984 for (i = 0; i < KSTACK_PAGES; i++) { 985 /* 986 * Get a kernel stack page. 987 */ 988 m = vm_page_grab(ksobj, i, VM_ALLOC_NORMAL | VM_ALLOC_RETRY); 989 ma[i] = m; 990 991 /* 992 * Wire the page. 993 */ 994 m->wire_count++; 995 cnt.v_wire_count++; 996 997 vm_page_wakeup(m); 998 vm_page_flag_clear(m, PG_ZERO); 999 vm_page_flag_set(m, PG_MAPPED | PG_WRITEABLE); 1000 m->valid = VM_PAGE_BITS_ALL; 1001 } 1002 1003 /* 1004 * Enter the page into the kernel address space. 1005 */ 1006 pmap_qenter(ks, ma, KSTACK_PAGES); 1007} 1008 1009/* 1010 * Dispose the kernel stack for a thread that has exited. 1011 * This routine directly impacts the exit perf of a process and thread. 1012 */ 1013void 1014pmap_dispose_thread(struct thread *td) 1015{ 1016 vm_object_t ksobj; 1017 vm_offset_t ks; 1018 vm_page_t m; 1019 int i; 1020 1021 ksobj = td->td_kstack_obj; 1022 ks = td->td_kstack; 1023 for (i = 0; i < KSTACK_PAGES; i++) { 1024 m = vm_page_lookup(ksobj, i); 1025 if (m == NULL) 1026 panic("pmap_dispose_proc: kstack already missing?"); 1027 vm_page_busy(m); 1028 vm_page_unwire(m, 0); 1029 vm_page_free(m); 1030 } 1031 pmap_qremove(ks, KSTACK_PAGES); 1032 1033 /* 1034 * If the thread got swapped out some of its KSTACK might have gotten 1035 * swapped. Just get rid of the object to clean up the swap use 1036 * proactively. NOTE! might block waiting for paging I/O to complete. 1037 */ 1038 if (ksobj->type == OBJT_SWAP) { 1039 td->td_kstack_obj = NULL; 1040 vm_object_deallocate(ksobj); 1041 } 1042} 1043 1044/* 1045 * Allow the kernel stack for a thread to be prejudicially paged out. 1046 */ 1047void 1048pmap_swapout_thread(struct thread *td) 1049{ 1050 vm_object_t ksobj; 1051 vm_offset_t ks; 1052 vm_page_t m; 1053 int i; 1054 1055 ksobj = td->td_kstack_obj; 1056 ks = (vm_offset_t)td->td_kstack; 1057 for (i = 0; i < KSTACK_PAGES; i++) { 1058 m = vm_page_lookup(ksobj, i); 1059 if (m == NULL) 1060 panic("pmap_swapout_thread: kstack already missing?"); 1061 vm_page_dirty(m); 1062 vm_page_unwire(m, 0); 1063 } 1064 pmap_qremove(ks, KSTACK_PAGES); 1065} 1066 1067/* 1068 * Bring the kernel stack for a specified thread back in. 1069 */ 1070void 1071pmap_swapin_thread(struct thread *td) 1072{ 1073 vm_page_t ma[KSTACK_PAGES]; 1074 vm_object_t ksobj; 1075 vm_offset_t ks; 1076 vm_page_t m; 1077 int rv; 1078 int i; 1079 1080 ksobj = td->td_kstack_obj; 1081 ks = td->td_kstack; 1082 for (i = 0; i < KSTACK_PAGES; i++) { 1083 m = vm_page_grab(ksobj, i, VM_ALLOC_NORMAL | VM_ALLOC_RETRY); 1084 if (m->valid != VM_PAGE_BITS_ALL) { 1085 rv = vm_pager_get_pages(ksobj, &m, 1, 0); 1086 if (rv != VM_PAGER_OK) 1087 panic("pmap_swapin_proc: cannot get kstack"); 1088 m = vm_page_lookup(ksobj, i); 1089 m->valid = VM_PAGE_BITS_ALL; 1090 } 1091 ma[i] = m; 1092 vm_page_wire(m); 1093 vm_page_wakeup(m); 1094 vm_page_flag_set(m, PG_MAPPED | PG_WRITEABLE); 1095 } 1096 pmap_qenter(ks, ma, KSTACK_PAGES); 1097} 1098 1099/* 1100 * Initialize the pmap associated with process 0. 1101 */ 1102void 1103pmap_pinit0(pmap_t pm) 1104{ 1105 int i; 1106 1107 for (i = 0; i < MAXCPU; i++) 1108 pm->pm_context[i] = 0; 1109 pm->pm_active = 0; 1110 pm->pm_tsb = NULL; 1111 pm->pm_tsb_obj = NULL; 1112 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1113} 1114 1115/* 1116 * Initialize a preallocated and zeroed pmap structure, uch as one in a 1117 * vmspace structure. 1118 */ 1119void 1120pmap_pinit(pmap_t pm) 1121{ 1122 vm_page_t ma[TSB_PAGES]; 1123 vm_page_t m; 1124 int i; 1125 1126 /* 1127 * Allocate kva space for the tsb. 1128 */ 1129 if (pm->pm_tsb == NULL) { 1130 pm->pm_tsb = (struct tte *)kmem_alloc_pageable(kernel_map, 1131 TSB_BSIZE); 1132 } 1133 1134 /* 1135 * Allocate an object for it. 1136 */ 1137 if (pm->pm_tsb_obj == NULL) 1138 pm->pm_tsb_obj = vm_object_allocate(OBJT_DEFAULT, TSB_PAGES); 1139 1140 for (i = 0; i < TSB_PAGES; i++) { 1141 m = vm_page_grab(pm->pm_tsb_obj, i, 1142 VM_ALLOC_RETRY | VM_ALLOC_ZERO); 1143 if ((m->flags & PG_ZERO) == 0) 1144 pmap_zero_page(m); 1145 1146 m->wire_count++; 1147 cnt.v_wire_count++; 1148 1149 vm_page_flag_clear(m, PG_MAPPED | PG_BUSY); 1150 m->valid = VM_PAGE_BITS_ALL; 1151 1152 ma[i] = m; 1153 } 1154 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES); 1155 1156 for (i = 0; i < MAXCPU; i++) 1157 pm->pm_context[i] = -1; 1158 pm->pm_active = 0; 1159 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1160} 1161 1162void 1163pmap_pinit2(pmap_t pmap) 1164{ 1165 /* XXX: Remove this stub when no longer called */ 1166} 1167 1168/* 1169 * Release any resources held by the given physical map. 1170 * Called when a pmap initialized by pmap_pinit is being released. 1171 * Should only be called if the map contains no valid mappings. 1172 */ 1173void 1174pmap_release(pmap_t pm) 1175{ 1176 vm_object_t obj; 1177 vm_page_t m; 1178 1179 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p", 1180 pm->pm_context[PCPU_GET(cpuid)], pm->pm_tsb); 1181 obj = pm->pm_tsb_obj; 1182 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1")); 1183 KASSERT(pmap_resident_count(pm) == 0, 1184 ("pmap_release: resident pages %ld != 0", 1185 pmap_resident_count(pm))); 1186 TAILQ_FOREACH(m, &obj->memq, listq) { 1187 if (vm_page_sleep_busy(m, FALSE, "pmaprl")) 1188 continue; 1189 vm_page_busy(m); 1190 KASSERT(m->hold_count == 0, 1191 ("pmap_release: freeing held tsb page")); 1192 m->wire_count--; 1193 cnt.v_wire_count--; 1194 vm_page_free_zero(m); 1195 } 1196 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES); 1197} 1198 1199/* 1200 * Grow the number of kernel page table entries. Unneeded. 1201 */ 1202void 1203pmap_growkernel(vm_offset_t addr) 1204{ 1205} 1206 1207/* 1208 * This routine is very drastic, but can save the system 1209 * in a pinch. 1210 */ 1211void 1212pmap_collect(void) 1213{ 1214} 1215 1216int 1217pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp, 1218 vm_offset_t va) 1219{ 1220 vm_page_t m; 1221 1222 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1223 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 1224 if ((tp->tte_data & TD_WIRED) != 0) 1225 pm->pm_stats.wired_count--; 1226 if ((tp->tte_data & TD_PV) != 0) { 1227 if ((tp->tte_data & TD_W) != 0 && 1228 pmap_track_modified(pm, va)) 1229 vm_page_dirty(m); 1230 if ((tp->tte_data & TD_REF) != 0) 1231 vm_page_flag_set(m, PG_REFERENCED); 1232 if (STAILQ_EMPTY(&m->md.tte_list)) 1233 vm_page_flag_clear(m, PG_MAPPED | PG_WRITEABLE); 1234 pm->pm_stats.resident_count--; 1235 } 1236 pmap_cache_remove(m, va); 1237 TTE_ZERO(tp); 1238 if (PMAP_REMOVE_DONE(pm)) 1239 return (0); 1240 return (1); 1241} 1242 1243/* 1244 * Remove the given range of addresses from the specified map. 1245 */ 1246void 1247pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end) 1248{ 1249 struct tte *tp; 1250 vm_offset_t va; 1251 1252 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx", 1253 pm->pm_context[PCPU_GET(cpuid)], start, end); 1254 if (PMAP_REMOVE_DONE(pm)) 1255 return; 1256 if (end - start > PMAP_TSB_THRESH) { 1257 tsb_foreach(pm, NULL, start, end, pmap_remove_tte); 1258 tlb_context_demap(pm); 1259 } else { 1260 for (va = start; va < end; va += PAGE_SIZE) { 1261 if ((tp = tsb_tte_lookup(pm, va)) != NULL) { 1262 if (!pmap_remove_tte(pm, NULL, tp, va)) 1263 break; 1264 } 1265 } 1266 tlb_range_demap(pm, start, end - 1); 1267 } 1268} 1269 1270void 1271pmap_remove_all(vm_page_t m) 1272{ 1273 struct pmap *pm; 1274 struct tte *tpn; 1275 struct tte *tp; 1276 vm_offset_t va; 1277 1278 KASSERT((m->flags & (PG_FICTITIOUS|PG_UNMANAGED)) == 0, 1279 ("pv_remove_all: illegal for unmanaged page %#lx", 1280 VM_PAGE_TO_PHYS(m))); 1281 for (tp = STAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) { 1282 tpn = STAILQ_NEXT(tp, tte_link); 1283 if ((tp->tte_data & TD_PV) == 0) 1284 continue; 1285 pm = TTE_GET_PMAP(tp); 1286 va = TTE_GET_VA(tp); 1287 if ((tp->tte_data & TD_WIRED) != 0) 1288 pm->pm_stats.wired_count--; 1289 if ((tp->tte_data & TD_REF) != 0) 1290 vm_page_flag_set(m, PG_REFERENCED); 1291 if ((tp->tte_data & TD_W) != 0 && 1292 pmap_track_modified(pm, va)) 1293 vm_page_dirty(m); 1294 tp->tte_data &= ~TD_V; 1295 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, va); 1296 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 1297 pm->pm_stats.resident_count--; 1298 pmap_cache_remove(m, va); 1299 TTE_ZERO(tp); 1300 } 1301 vm_page_flag_clear(m, PG_MAPPED | PG_WRITEABLE); 1302} 1303 1304int 1305pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp, 1306 vm_offset_t va) 1307{ 1308 vm_page_t m; 1309 1310 if ((tp->tte_data & TD_PV) != 0) { 1311 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1312 if ((tp->tte_data & TD_REF) != 0) { 1313 vm_page_flag_set(m, PG_REFERENCED); 1314 tp->tte_data &= ~TD_REF; 1315 } 1316 if ((tp->tte_data & TD_W) != 0 && 1317 pmap_track_modified(pm, va)) { 1318 vm_page_dirty(m); 1319 } 1320 } 1321 tp->tte_data &= ~(TD_W | TD_SW); 1322 return (0); 1323} 1324 1325/* 1326 * Set the physical protection on the specified range of this map as requested. 1327 */ 1328void 1329pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1330{ 1331 vm_offset_t va; 1332 struct tte *tp; 1333 1334 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx", 1335 pm->pm_context[PCPU_GET(cpuid)], sva, eva, prot); 1336 1337 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1338 pmap_remove(pm, sva, eva); 1339 return; 1340 } 1341 1342 if (prot & VM_PROT_WRITE) 1343 return; 1344 1345 if (eva - sva > PMAP_TSB_THRESH) { 1346 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte); 1347 tlb_context_demap(pm); 1348 } else { 1349 for (va = sva; va < eva; va += PAGE_SIZE) { 1350 if ((tp = tsb_tte_lookup(pm, va)) != NULL) 1351 pmap_protect_tte(pm, NULL, tp, va); 1352 } 1353 tlb_range_demap(pm, sva, eva - 1); 1354 } 1355} 1356 1357/* 1358 * Map the given physical page at the specified virtual address in the 1359 * target pmap with the protection requested. If specified the page 1360 * will be wired down. 1361 */ 1362void 1363pmap_enter(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1364 boolean_t wired) 1365{ 1366 struct tte *tp; 1367 vm_offset_t pa; 1368 u_long data; 1369 1370 pa = VM_PAGE_TO_PHYS(m); 1371 CTR6(KTR_PMAP, 1372 "pmap_enter: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d", 1373 pm->pm_context[PCPU_GET(cpuid)], m, va, pa, prot, wired); 1374 1375 /* 1376 * If there is an existing mapping, and the physical address has not 1377 * changed, must be protection or wiring change. 1378 */ 1379 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) { 1380 CTR0(KTR_PMAP, "pmap_enter: update"); 1381 PMAP_STATS_INC(pmap_enter_nupdate); 1382 1383 /* 1384 * Wiring change, just update stats. 1385 */ 1386 if (wired) { 1387 if ((tp->tte_data & TD_WIRED) == 0) { 1388 tp->tte_data |= TD_WIRED; 1389 pm->pm_stats.wired_count++; 1390 } 1391 } else { 1392 if ((tp->tte_data & TD_WIRED) != 0) { 1393 tp->tte_data &= ~TD_WIRED; 1394 pm->pm_stats.wired_count--; 1395 } 1396 } 1397 1398 /* 1399 * Save the old bits and clear the ones we're interested in. 1400 */ 1401 data = tp->tte_data; 1402 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W); 1403 1404 /* 1405 * If we're turning off write permissions, sense modify status. 1406 */ 1407 if ((prot & VM_PROT_WRITE) != 0) { 1408 tp->tte_data |= TD_SW; 1409 if (wired) { 1410 tp->tte_data |= TD_W; 1411 } 1412 } else if ((data & TD_W) != 0 && 1413 pmap_track_modified(pm, va)) { 1414 vm_page_dirty(m); 1415 } 1416 1417 /* 1418 * If we're turning on execute permissions, flush the icache. 1419 */ 1420 if ((prot & VM_PROT_EXECUTE) != 0) { 1421 if ((data & TD_EXEC) == 0) { 1422 PMAP_STATS_INC(pmap_niflush); 1423 icache_page_inval(pa); 1424 } 1425 tp->tte_data |= TD_EXEC; 1426 } 1427 1428 /* 1429 * Delete the old mapping. 1430 */ 1431 tlb_tte_demap(tp, pm); 1432 } else { 1433 /* 1434 * If there is an existing mapping, but its for a different 1435 * phsyical address, delete the old mapping. 1436 */ 1437 if (tp != NULL) { 1438 CTR0(KTR_PMAP, "pmap_enter: replace"); 1439 PMAP_STATS_INC(pmap_enter_nreplace); 1440 pmap_remove_tte(pm, NULL, tp, va); 1441 tlb_page_demap(TLB_DTLB | TLB_ITLB, pm, va); 1442 } else { 1443 CTR0(KTR_PMAP, "pmap_enter: new"); 1444 PMAP_STATS_INC(pmap_enter_nnew); 1445 } 1446 1447 /* 1448 * Now set up the data and install the new mapping. 1449 */ 1450 data = TD_V | TD_8K | TD_PA(pa) | TD_CP; 1451 if (pm == kernel_pmap) 1452 data |= TD_P; 1453 if (prot & VM_PROT_WRITE) 1454 data |= TD_SW; 1455 if (prot & VM_PROT_EXECUTE) { 1456 data |= TD_EXEC; 1457 PMAP_STATS_INC(pmap_niflush); 1458 icache_page_inval(pa); 1459 } 1460 1461 /* 1462 * If its wired update stats. We also don't need reference or 1463 * modify tracking for wired mappings, so set the bits now. 1464 */ 1465 if (wired) { 1466 pm->pm_stats.wired_count++; 1467 data |= TD_REF | TD_WIRED; 1468 if ((prot & VM_PROT_WRITE) != 0) 1469 data |= TD_W; 1470 } 1471 1472 tsb_tte_enter(pm, m, va, data); 1473 } 1474} 1475 1476void 1477pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1478 vm_pindex_t pindex, vm_size_t size, int limit) 1479{ 1480 /* XXX */ 1481} 1482 1483void 1484pmap_prefault(pmap_t pm, vm_offset_t va, vm_map_entry_t entry) 1485{ 1486 /* XXX */ 1487} 1488 1489/* 1490 * Change the wiring attribute for a map/virtual-address pair. 1491 * The mapping must already exist in the pmap. 1492 */ 1493void 1494pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 1495{ 1496 struct tte *tp; 1497 1498 if ((tp = tsb_tte_lookup(pm, va)) != NULL) { 1499 if (wired) { 1500 if ((tp->tte_data & TD_WIRED) == 0) 1501 pm->pm_stats.wired_count++; 1502 tp->tte_data |= TD_WIRED; 1503 } else { 1504 if ((tp->tte_data & TD_WIRED) != 0) 1505 pm->pm_stats.wired_count--; 1506 tp->tte_data &= ~TD_WIRED; 1507 } 1508 } 1509} 1510 1511static int 1512pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp, vm_offset_t va) 1513{ 1514 vm_page_t m; 1515 u_long data; 1516 1517 if (tsb_tte_lookup(dst_pmap, va) == NULL) { 1518 data = tp->tte_data & 1519 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W); 1520 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1521 tsb_tte_enter(dst_pmap, m, va, data); 1522 } 1523 return (1); 1524} 1525 1526void 1527pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1528 vm_size_t len, vm_offset_t src_addr) 1529{ 1530 struct tte *tp; 1531 vm_offset_t va; 1532 1533 if (dst_addr != src_addr) 1534 return; 1535 if (len > PMAP_TSB_THRESH) { 1536 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len, 1537 pmap_copy_tte); 1538 tlb_context_demap(dst_pmap); 1539 } else { 1540 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE) { 1541 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL) 1542 pmap_copy_tte(src_pmap, dst_pmap, tp, va); 1543 } 1544 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1); 1545 } 1546} 1547 1548/* 1549 * Zero a page of physical memory by temporarily mapping it into the tlb. 1550 */ 1551void 1552pmap_zero_page(vm_page_t m) 1553{ 1554 vm_offset_t pa; 1555 1556 pa = VM_PAGE_TO_PHYS(m); 1557 CTR1(KTR_PMAP, "pmap_zero_page: pa=%#lx", pa); 1558 dcache_page_inval(pa); 1559 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE); 1560} 1561 1562void 1563pmap_zero_page_area(vm_page_t m, int off, int size) 1564{ 1565 vm_offset_t pa; 1566 1567 pa = VM_PAGE_TO_PHYS(m); 1568 CTR3(KTR_PMAP, "pmap_zero_page_area: pa=%#lx off=%#x size=%#x", 1569 pa, off, size); 1570 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size")); 1571 dcache_page_inval(pa); 1572 aszero(ASI_PHYS_USE_EC, pa + off, size); 1573} 1574 1575/* 1576 * Copy a page of physical memory by temporarily mapping it into the tlb. 1577 */ 1578void 1579pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 1580{ 1581 vm_offset_t dst; 1582 vm_offset_t src; 1583 1584 dst = VM_PAGE_TO_PHYS(mdst); 1585 src = VM_PAGE_TO_PHYS(msrc); 1586 CTR2(KTR_PMAP, "pmap_copy_page: src=%#lx dst=%#lx", src, dst); 1587 dcache_page_inval(dst); 1588 ascopy(ASI_PHYS_USE_EC, src, dst, PAGE_SIZE); 1589} 1590 1591/* 1592 * Make the specified page pageable (or not). Unneeded. 1593 */ 1594void 1595pmap_pageable(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1596 boolean_t pageable) 1597{ 1598} 1599 1600/* 1601 * Returns true if the pmap's pv is one of the first 1602 * 16 pvs linked to from this page. This count may 1603 * be changed upwards or downwards in the future; it 1604 * is only necessary that true be returned for a small 1605 * subset of pmaps for proper page aging. 1606 */ 1607boolean_t 1608pmap_page_exists_quick(pmap_t pm, vm_page_t m) 1609{ 1610 struct tte *tp; 1611 int loops; 1612 1613 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1614 return (FALSE); 1615 loops = 0; 1616 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1617 if ((tp->tte_data & TD_PV) == 0) 1618 continue; 1619 if (TTE_GET_PMAP(tp) == pm) 1620 return (TRUE); 1621 if (++loops >= 16) 1622 break; 1623 } 1624 return (FALSE); 1625} 1626 1627/* 1628 * Remove all pages from specified address space, this aids process exit 1629 * speeds. This is much faster than pmap_remove n the case of running down 1630 * an entire address space. Only works for the current pmap. 1631 */ 1632void 1633pmap_remove_pages(pmap_t pm, vm_offset_t sva, vm_offset_t eva) 1634{ 1635} 1636 1637/* 1638 * Lower the permission for all mappings to a given page. 1639 */ 1640void 1641pmap_page_protect(vm_page_t m, vm_prot_t prot) 1642{ 1643 1644 if ((prot & VM_PROT_WRITE) == 0) { 1645 if (prot & (VM_PROT_READ | VM_PROT_EXECUTE)) 1646 pmap_clear_write(m); 1647 else 1648 pmap_remove_all(m); 1649 } 1650} 1651 1652vm_offset_t 1653pmap_phys_address(int ppn) 1654{ 1655 1656 return (sparc64_ptob(ppn)); 1657} 1658 1659/* 1660 * pmap_ts_referenced: 1661 * 1662 * Return a count of reference bits for a page, clearing those bits. 1663 * It is not necessary for every reference bit to be cleared, but it 1664 * is necessary that 0 only be returned when there are truly no 1665 * reference bits set. 1666 * 1667 * XXX: The exact number of bits to check and clear is a matter that 1668 * should be tested and standardized at some point in the future for 1669 * optimal aging of shared pages. 1670 */ 1671 1672int 1673pmap_ts_referenced(vm_page_t m) 1674{ 1675 struct tte *tpf; 1676 struct tte *tpn; 1677 struct tte *tp; 1678 int count; 1679 1680 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1681 return (0); 1682 count = 0; 1683 if ((tp = STAILQ_FIRST(&m->md.tte_list)) != NULL) { 1684 tpf = tp; 1685 do { 1686 tpn = STAILQ_NEXT(tp, tte_link); 1687 STAILQ_REMOVE(&m->md.tte_list, tp, tte, tte_link); 1688 STAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link); 1689 if ((tp->tte_data & TD_PV) == 0 || 1690 !pmap_track_modified(TTE_GET_PMAP(tp), 1691 TTE_GET_VA(tp))) 1692 continue; 1693 if ((tp->tte_data & TD_REF) != 0) { 1694 tp->tte_data &= ~TD_REF; 1695 if (++count > 4) 1696 break; 1697 } 1698 } while ((tp = tpn) != NULL && tp != tpf); 1699 } 1700 return (count); 1701} 1702 1703boolean_t 1704pmap_is_modified(vm_page_t m) 1705{ 1706 struct tte *tp; 1707 1708 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1709 return FALSE; 1710 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1711 if ((tp->tte_data & TD_PV) == 0 || 1712 !pmap_track_modified(TTE_GET_PMAP(tp), TTE_GET_VA(tp))) 1713 continue; 1714 if ((tp->tte_data & TD_W) != 0) 1715 return (TRUE); 1716 } 1717 return (FALSE); 1718} 1719 1720void 1721pmap_clear_modify(vm_page_t m) 1722{ 1723 struct tte *tp; 1724 1725 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1726 return; 1727 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1728 if ((tp->tte_data & TD_PV) == 0) 1729 continue; 1730 if ((tp->tte_data & TD_W) != 0) { 1731 tp->tte_data &= ~TD_W; 1732 tlb_tte_demap(tp, TTE_GET_PMAP(tp)); 1733 } 1734 } 1735} 1736 1737void 1738pmap_clear_reference(vm_page_t m) 1739{ 1740 struct tte *tp; 1741 1742 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1743 return; 1744 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1745 if ((tp->tte_data & TD_PV) == 0) 1746 continue; 1747 if ((tp->tte_data & TD_REF) != 0) { 1748 tp->tte_data &= ~TD_REF; 1749 tlb_tte_demap(tp, TTE_GET_PMAP(tp)); 1750 } 1751 } 1752} 1753 1754void 1755pmap_clear_write(vm_page_t m) 1756{ 1757 struct tte *tp; 1758 1759 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0) 1760 return; 1761 STAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1762 if ((tp->tte_data & TD_PV) == 0) 1763 continue; 1764 if ((tp->tte_data & (TD_SW | TD_W)) != 0) { 1765 if ((tp->tte_data & TD_W) != 0 && 1766 pmap_track_modified(TTE_GET_PMAP(tp), 1767 TTE_GET_VA(tp))) 1768 vm_page_dirty(m); 1769 tp->tte_data &= ~(TD_SW | TD_W); 1770 tlb_tte_demap(tp, TTE_GET_PMAP(tp)); 1771 } 1772 } 1773} 1774 1775int 1776pmap_mincore(pmap_t pm, vm_offset_t addr) 1777{ 1778 TODO; 1779 return (0); 1780} 1781 1782/* 1783 * Activate a user pmap. The pmap must be activated before its address space 1784 * can be accessed in any way. 1785 */ 1786void 1787pmap_activate(struct thread *td) 1788{ 1789 struct vmspace *vm; 1790 vm_offset_t tsb; 1791 u_long context; 1792 pmap_t pm; 1793 1794 /* 1795 * Load all the data we need up front to encourage the compiler to 1796 * not issue any loads while we have interrupts disable below. 1797 */ 1798 vm = td->td_proc->p_vmspace; 1799 pm = &vm->vm_pmap; 1800 tsb = (vm_offset_t)pm->pm_tsb; 1801 1802 KASSERT(pm->pm_active == 0, ("pmap_activate: pmap already active?")); 1803 KASSERT(pm->pm_context[PCPU_GET(cpuid)] != 0, 1804 ("pmap_activate: activating nucleus context?")); 1805 1806 mtx_lock_spin(&sched_lock); 1807 wrpr(pstate, 0, PSTATE_MMU); 1808 mov(tsb, TSB_REG); 1809 wrpr(pstate, 0, PSTATE_KERNEL); 1810 context = pmap_context_alloc(); 1811 pm->pm_context[PCPU_GET(cpuid)] = context; 1812 pm->pm_active |= PCPU_GET(cpumask); 1813 PCPU_SET(vmspace, vm); 1814 stxa(AA_DMMU_PCXR, ASI_DMMU, context); 1815 membar(Sync); 1816 mtx_unlock_spin(&sched_lock); 1817} 1818 1819vm_offset_t 1820pmap_addr_hint(vm_object_t object, vm_offset_t va, vm_size_t size) 1821{ 1822 1823 return (va); 1824} 1825