pmap.c revision 254649
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 */ 39 40#include <sys/cdefs.h> 41__FBSDID("$FreeBSD: head/sys/sparc64/sparc64/pmap.c 254649 2013-08-22 07:39:53Z kib $"); 42 43/* 44 * Manages physical address maps. 45 * 46 * Since the information managed by this module is also stored by the 47 * logical address mapping module, this module may throw away valid virtual 48 * to physical mappings at almost any time. However, invalidations of 49 * mappings must be done as requested. 50 * 51 * In order to cope with hardware architectures which make virtual to 52 * physical map invalidates expensive, this module may delay invalidate 53 * reduced protection operations until such time as they are actually 54 * necessary. This module is given full information as to which processors 55 * are currently using which maps, and to when physical maps must be made 56 * correct. 57 */ 58 59#include "opt_kstack_pages.h" 60#include "opt_pmap.h" 61 62#include <sys/param.h> 63#include <sys/kernel.h> 64#include <sys/ktr.h> 65#include <sys/lock.h> 66#include <sys/msgbuf.h> 67#include <sys/mutex.h> 68#include <sys/proc.h> 69#include <sys/rwlock.h> 70#include <sys/smp.h> 71#include <sys/sysctl.h> 72#include <sys/systm.h> 73#include <sys/vmmeter.h> 74 75#include <dev/ofw/openfirm.h> 76 77#include <vm/vm.h> 78#include <vm/vm_param.h> 79#include <vm/vm_kern.h> 80#include <vm/vm_page.h> 81#include <vm/vm_map.h> 82#include <vm/vm_object.h> 83#include <vm/vm_extern.h> 84#include <vm/vm_pageout.h> 85#include <vm/vm_pager.h> 86#include <vm/vm_phys.h> 87 88#include <machine/cache.h> 89#include <machine/frame.h> 90#include <machine/instr.h> 91#include <machine/md_var.h> 92#include <machine/metadata.h> 93#include <machine/ofw_mem.h> 94#include <machine/smp.h> 95#include <machine/tlb.h> 96#include <machine/tte.h> 97#include <machine/tsb.h> 98#include <machine/ver.h> 99 100/* 101 * Virtual address of message buffer 102 */ 103struct msgbuf *msgbufp; 104 105/* 106 * Map of physical memory reagions 107 */ 108vm_paddr_t phys_avail[128]; 109static struct ofw_mem_region mra[128]; 110struct ofw_mem_region sparc64_memreg[128]; 111int sparc64_nmemreg; 112static struct ofw_map translations[128]; 113static int translations_size; 114 115static vm_offset_t pmap_idle_map; 116static vm_offset_t pmap_temp_map_1; 117static vm_offset_t pmap_temp_map_2; 118 119/* 120 * First and last available kernel virtual addresses 121 */ 122vm_offset_t virtual_avail; 123vm_offset_t virtual_end; 124vm_offset_t kernel_vm_end; 125 126vm_offset_t vm_max_kernel_address; 127 128/* 129 * Kernel pmap 130 */ 131struct pmap kernel_pmap_store; 132 133struct rwlock_padalign tte_list_global_lock; 134 135/* 136 * Allocate physical memory for use in pmap_bootstrap. 137 */ 138static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size, uint32_t colors); 139 140static void pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data); 141static void pmap_cache_remove(vm_page_t m, vm_offset_t va); 142static int pmap_protect_tte(struct pmap *pm1, struct pmap *pm2, 143 struct tte *tp, vm_offset_t va); 144 145/* 146 * Map the given physical page at the specified virtual address in the 147 * target pmap with the protection requested. If specified the page 148 * will be wired down. 149 * 150 * The page queues and pmap must be locked. 151 */ 152static void pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, 153 vm_prot_t prot, boolean_t wired); 154 155extern int tl1_dmmu_miss_direct_patch_tsb_phys_1[]; 156extern int tl1_dmmu_miss_direct_patch_tsb_phys_end_1[]; 157extern int tl1_dmmu_miss_patch_asi_1[]; 158extern int tl1_dmmu_miss_patch_quad_ldd_1[]; 159extern int tl1_dmmu_miss_patch_tsb_1[]; 160extern int tl1_dmmu_miss_patch_tsb_2[]; 161extern int tl1_dmmu_miss_patch_tsb_mask_1[]; 162extern int tl1_dmmu_miss_patch_tsb_mask_2[]; 163extern int tl1_dmmu_prot_patch_asi_1[]; 164extern int tl1_dmmu_prot_patch_quad_ldd_1[]; 165extern int tl1_dmmu_prot_patch_tsb_1[]; 166extern int tl1_dmmu_prot_patch_tsb_2[]; 167extern int tl1_dmmu_prot_patch_tsb_mask_1[]; 168extern int tl1_dmmu_prot_patch_tsb_mask_2[]; 169extern int tl1_immu_miss_patch_asi_1[]; 170extern int tl1_immu_miss_patch_quad_ldd_1[]; 171extern int tl1_immu_miss_patch_tsb_1[]; 172extern int tl1_immu_miss_patch_tsb_2[]; 173extern int tl1_immu_miss_patch_tsb_mask_1[]; 174extern int tl1_immu_miss_patch_tsb_mask_2[]; 175 176/* 177 * If user pmap is processed with pmap_remove and with pmap_remove and the 178 * resident count drops to 0, there are no more pages to remove, so we 179 * need not continue. 180 */ 181#define PMAP_REMOVE_DONE(pm) \ 182 ((pm) != kernel_pmap && (pm)->pm_stats.resident_count == 0) 183 184/* 185 * The threshold (in bytes) above which tsb_foreach() is used in pmap_remove() 186 * and pmap_protect() instead of trying each virtual address. 187 */ 188#define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE) 189 190SYSCTL_NODE(_debug, OID_AUTO, pmap_stats, CTLFLAG_RD, 0, ""); 191 192PMAP_STATS_VAR(pmap_nenter); 193PMAP_STATS_VAR(pmap_nenter_update); 194PMAP_STATS_VAR(pmap_nenter_replace); 195PMAP_STATS_VAR(pmap_nenter_new); 196PMAP_STATS_VAR(pmap_nkenter); 197PMAP_STATS_VAR(pmap_nkenter_oc); 198PMAP_STATS_VAR(pmap_nkenter_stupid); 199PMAP_STATS_VAR(pmap_nkremove); 200PMAP_STATS_VAR(pmap_nqenter); 201PMAP_STATS_VAR(pmap_nqremove); 202PMAP_STATS_VAR(pmap_ncache_enter); 203PMAP_STATS_VAR(pmap_ncache_enter_c); 204PMAP_STATS_VAR(pmap_ncache_enter_oc); 205PMAP_STATS_VAR(pmap_ncache_enter_cc); 206PMAP_STATS_VAR(pmap_ncache_enter_coc); 207PMAP_STATS_VAR(pmap_ncache_enter_nc); 208PMAP_STATS_VAR(pmap_ncache_enter_cnc); 209PMAP_STATS_VAR(pmap_ncache_remove); 210PMAP_STATS_VAR(pmap_ncache_remove_c); 211PMAP_STATS_VAR(pmap_ncache_remove_oc); 212PMAP_STATS_VAR(pmap_ncache_remove_cc); 213PMAP_STATS_VAR(pmap_ncache_remove_coc); 214PMAP_STATS_VAR(pmap_ncache_remove_nc); 215PMAP_STATS_VAR(pmap_nzero_page); 216PMAP_STATS_VAR(pmap_nzero_page_c); 217PMAP_STATS_VAR(pmap_nzero_page_oc); 218PMAP_STATS_VAR(pmap_nzero_page_nc); 219PMAP_STATS_VAR(pmap_nzero_page_area); 220PMAP_STATS_VAR(pmap_nzero_page_area_c); 221PMAP_STATS_VAR(pmap_nzero_page_area_oc); 222PMAP_STATS_VAR(pmap_nzero_page_area_nc); 223PMAP_STATS_VAR(pmap_nzero_page_idle); 224PMAP_STATS_VAR(pmap_nzero_page_idle_c); 225PMAP_STATS_VAR(pmap_nzero_page_idle_oc); 226PMAP_STATS_VAR(pmap_nzero_page_idle_nc); 227PMAP_STATS_VAR(pmap_ncopy_page); 228PMAP_STATS_VAR(pmap_ncopy_page_c); 229PMAP_STATS_VAR(pmap_ncopy_page_oc); 230PMAP_STATS_VAR(pmap_ncopy_page_nc); 231PMAP_STATS_VAR(pmap_ncopy_page_dc); 232PMAP_STATS_VAR(pmap_ncopy_page_doc); 233PMAP_STATS_VAR(pmap_ncopy_page_sc); 234PMAP_STATS_VAR(pmap_ncopy_page_soc); 235 236PMAP_STATS_VAR(pmap_nnew_thread); 237PMAP_STATS_VAR(pmap_nnew_thread_oc); 238 239static inline u_long dtlb_get_data(u_int tlb, u_int slot); 240 241/* 242 * Quick sort callout for comparing memory regions 243 */ 244static int mr_cmp(const void *a, const void *b); 245static int om_cmp(const void *a, const void *b); 246 247static int 248mr_cmp(const void *a, const void *b) 249{ 250 const struct ofw_mem_region *mra; 251 const struct ofw_mem_region *mrb; 252 253 mra = a; 254 mrb = b; 255 if (mra->mr_start < mrb->mr_start) 256 return (-1); 257 else if (mra->mr_start > mrb->mr_start) 258 return (1); 259 else 260 return (0); 261} 262 263static int 264om_cmp(const void *a, const void *b) 265{ 266 const struct ofw_map *oma; 267 const struct ofw_map *omb; 268 269 oma = a; 270 omb = b; 271 if (oma->om_start < omb->om_start) 272 return (-1); 273 else if (oma->om_start > omb->om_start) 274 return (1); 275 else 276 return (0); 277} 278 279static inline u_long 280dtlb_get_data(u_int tlb, u_int slot) 281{ 282 u_long data; 283 register_t s; 284 285 slot = TLB_DAR_SLOT(tlb, slot); 286 /* 287 * We read ASI_DTLB_DATA_ACCESS_REG twice back-to-back in order to 288 * work around errata of USIII and beyond. 289 */ 290 s = intr_disable(); 291 (void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 292 data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 293 intr_restore(s); 294 return (data); 295} 296 297/* 298 * Bootstrap the system enough to run with virtual memory. 299 */ 300void 301pmap_bootstrap(u_int cpu_impl) 302{ 303 struct pmap *pm; 304 struct tte *tp; 305 vm_offset_t off; 306 vm_offset_t va; 307 vm_paddr_t pa; 308 vm_size_t physsz; 309 vm_size_t virtsz; 310 u_long data; 311 u_long vpn; 312 phandle_t pmem; 313 phandle_t vmem; 314 u_int dtlb_slots_avail; 315 int i; 316 int j; 317 int sz; 318 uint32_t asi; 319 uint32_t colors; 320 uint32_t ldd; 321 322 /* 323 * Set the kernel context. 324 */ 325 pmap_set_kctx(); 326 327 colors = dcache_color_ignore != 0 ? 1 : DCACHE_COLORS; 328 329 /* 330 * Find out what physical memory is available from the PROM and 331 * initialize the phys_avail array. This must be done before 332 * pmap_bootstrap_alloc is called. 333 */ 334 if ((pmem = OF_finddevice("/memory")) == -1) 335 OF_panic("%s: finddevice /memory", __func__); 336 if ((sz = OF_getproplen(pmem, "available")) == -1) 337 OF_panic("%s: getproplen /memory/available", __func__); 338 if (sizeof(phys_avail) < sz) 339 OF_panic("%s: phys_avail too small", __func__); 340 if (sizeof(mra) < sz) 341 OF_panic("%s: mra too small", __func__); 342 bzero(mra, sz); 343 if (OF_getprop(pmem, "available", mra, sz) == -1) 344 OF_panic("%s: getprop /memory/available", __func__); 345 sz /= sizeof(*mra); 346 CTR0(KTR_PMAP, "pmap_bootstrap: physical memory"); 347 qsort(mra, sz, sizeof (*mra), mr_cmp); 348 physsz = 0; 349 getenv_quad("hw.physmem", &physmem); 350 physmem = btoc(physmem); 351 for (i = 0, j = 0; i < sz; i++, j += 2) { 352 CTR2(KTR_PMAP, "start=%#lx size=%#lx", mra[i].mr_start, 353 mra[i].mr_size); 354 if (physmem != 0 && btoc(physsz + mra[i].mr_size) >= physmem) { 355 if (btoc(physsz) < physmem) { 356 phys_avail[j] = mra[i].mr_start; 357 phys_avail[j + 1] = mra[i].mr_start + 358 (ctob(physmem) - physsz); 359 physsz = ctob(physmem); 360 } 361 break; 362 } 363 phys_avail[j] = mra[i].mr_start; 364 phys_avail[j + 1] = mra[i].mr_start + mra[i].mr_size; 365 physsz += mra[i].mr_size; 366 } 367 physmem = btoc(physsz); 368 369 /* 370 * Calculate the size of kernel virtual memory, and the size and mask 371 * for the kernel TSB based on the phsyical memory size but limited 372 * by the amount of dTLB slots available for locked entries if we have 373 * to lock the TSB in the TLB (given that for spitfire-class CPUs all 374 * of the dt64 slots can hold locked entries but there is no large 375 * dTLB for unlocked ones, we don't use more than half of it for the 376 * TSB). 377 * Note that for reasons unknown OpenSolaris doesn't take advantage of 378 * ASI_ATOMIC_QUAD_LDD_PHYS on UltraSPARC-III. However, given that no 379 * public documentation is available for these, the latter just might 380 * not support it, yet. 381 */ 382 if (cpu_impl == CPU_IMPL_SPARC64V || 383 cpu_impl >= CPU_IMPL_ULTRASPARCIIIp) { 384 tsb_kernel_ldd_phys = 1; 385 virtsz = roundup(5 / 3 * physsz, PAGE_SIZE_4M << 386 (PAGE_SHIFT - TTE_SHIFT)); 387 } else { 388 dtlb_slots_avail = 0; 389 for (i = 0; i < dtlb_slots; i++) { 390 data = dtlb_get_data(cpu_impl == 391 CPU_IMPL_ULTRASPARCIII ? TLB_DAR_T16 : 392 TLB_DAR_T32, i); 393 if ((data & (TD_V | TD_L)) != (TD_V | TD_L)) 394 dtlb_slots_avail++; 395 } 396#ifdef SMP 397 dtlb_slots_avail -= PCPU_PAGES; 398#endif 399 if (cpu_impl >= CPU_IMPL_ULTRASPARCI && 400 cpu_impl < CPU_IMPL_ULTRASPARCIII) 401 dtlb_slots_avail /= 2; 402 virtsz = roundup(physsz, PAGE_SIZE_4M << 403 (PAGE_SHIFT - TTE_SHIFT)); 404 virtsz = MIN(virtsz, (dtlb_slots_avail * PAGE_SIZE_4M) << 405 (PAGE_SHIFT - TTE_SHIFT)); 406 } 407 vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz; 408 tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT); 409 tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1; 410 411 /* 412 * Allocate the kernel TSB and lock it in the TLB if necessary. 413 */ 414 pa = pmap_bootstrap_alloc(tsb_kernel_size, colors); 415 if (pa & PAGE_MASK_4M) 416 OF_panic("%s: TSB unaligned", __func__); 417 tsb_kernel_phys = pa; 418 if (tsb_kernel_ldd_phys == 0) { 419 tsb_kernel = 420 (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size); 421 pmap_map_tsb(); 422 bzero(tsb_kernel, tsb_kernel_size); 423 } else { 424 tsb_kernel = 425 (struct tte *)TLB_PHYS_TO_DIRECT(tsb_kernel_phys); 426 aszero(ASI_PHYS_USE_EC, tsb_kernel_phys, tsb_kernel_size); 427 } 428 429 /* 430 * Allocate and map the dynamic per-CPU area for the BSP. 431 */ 432 pa = pmap_bootstrap_alloc(DPCPU_SIZE, colors); 433 dpcpu0 = (void *)TLB_PHYS_TO_DIRECT(pa); 434 435 /* 436 * Allocate and map the message buffer. 437 */ 438 pa = pmap_bootstrap_alloc(msgbufsize, colors); 439 msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(pa); 440 441 /* 442 * Patch the TSB addresses and mask as well as the ASIs used to load 443 * it into the trap table. 444 */ 445 446#define LDDA_R_I_R(rd, imm_asi, rs1, rs2) \ 447 (EIF_OP(IOP_LDST) | EIF_F3_RD(rd) | EIF_F3_OP3(INS3_LDDA) | \ 448 EIF_F3_RS1(rs1) | EIF_F3_I(0) | EIF_F3_IMM_ASI(imm_asi) | \ 449 EIF_F3_RS2(rs2)) 450#define OR_R_I_R(rd, imm13, rs1) \ 451 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \ 452 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13)) 453#define SETHI(rd, imm22) \ 454 (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \ 455 EIF_IMM((imm22) >> 10, 22)) 456#define WR_R_I(rd, imm13, rs1) \ 457 (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_WR) | \ 458 EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13)) 459 460#define PATCH_ASI(addr, asi) do { \ 461 if (addr[0] != WR_R_I(IF_F3_RD(addr[0]), 0x0, \ 462 IF_F3_RS1(addr[0]))) \ 463 OF_panic("%s: patched instructions have changed", \ 464 __func__); \ 465 addr[0] |= EIF_IMM((asi), 13); \ 466 flush(addr); \ 467} while (0) 468 469#define PATCH_LDD(addr, asi) do { \ 470 if (addr[0] != LDDA_R_I_R(IF_F3_RD(addr[0]), 0x0, \ 471 IF_F3_RS1(addr[0]), IF_F3_RS2(addr[0]))) \ 472 OF_panic("%s: patched instructions have changed", \ 473 __func__); \ 474 addr[0] |= EIF_F3_IMM_ASI(asi); \ 475 flush(addr); \ 476} while (0) 477 478#define PATCH_TSB(addr, val) do { \ 479 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \ 480 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \ 481 IF_F3_RS1(addr[1])) || \ 482 addr[3] != SETHI(IF_F2_RD(addr[3]), 0x0)) \ 483 OF_panic("%s: patched instructions have changed", \ 484 __func__); \ 485 addr[0] |= EIF_IMM((val) >> 42, 22); \ 486 addr[1] |= EIF_IMM((val) >> 32, 10); \ 487 addr[3] |= EIF_IMM((val) >> 10, 22); \ 488 flush(addr); \ 489 flush(addr + 1); \ 490 flush(addr + 3); \ 491} while (0) 492 493#define PATCH_TSB_MASK(addr, val) do { \ 494 if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \ 495 addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, \ 496 IF_F3_RS1(addr[1]))) \ 497 OF_panic("%s: patched instructions have changed", \ 498 __func__); \ 499 addr[0] |= EIF_IMM((val) >> 10, 22); \ 500 addr[1] |= EIF_IMM((val), 10); \ 501 flush(addr); \ 502 flush(addr + 1); \ 503} while (0) 504 505 if (tsb_kernel_ldd_phys == 0) { 506 asi = ASI_N; 507 ldd = ASI_NUCLEUS_QUAD_LDD; 508 off = (vm_offset_t)tsb_kernel; 509 } else { 510 asi = ASI_PHYS_USE_EC; 511 ldd = ASI_ATOMIC_QUAD_LDD_PHYS; 512 off = (vm_offset_t)tsb_kernel_phys; 513 } 514 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_1, tsb_kernel_phys); 515 PATCH_TSB(tl1_dmmu_miss_direct_patch_tsb_phys_end_1, 516 tsb_kernel_phys + tsb_kernel_size - 1); 517 PATCH_ASI(tl1_dmmu_miss_patch_asi_1, asi); 518 PATCH_LDD(tl1_dmmu_miss_patch_quad_ldd_1, ldd); 519 PATCH_TSB(tl1_dmmu_miss_patch_tsb_1, off); 520 PATCH_TSB(tl1_dmmu_miss_patch_tsb_2, off); 521 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_1, tsb_kernel_mask); 522 PATCH_TSB_MASK(tl1_dmmu_miss_patch_tsb_mask_2, tsb_kernel_mask); 523 PATCH_ASI(tl1_dmmu_prot_patch_asi_1, asi); 524 PATCH_LDD(tl1_dmmu_prot_patch_quad_ldd_1, ldd); 525 PATCH_TSB(tl1_dmmu_prot_patch_tsb_1, off); 526 PATCH_TSB(tl1_dmmu_prot_patch_tsb_2, off); 527 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_1, tsb_kernel_mask); 528 PATCH_TSB_MASK(tl1_dmmu_prot_patch_tsb_mask_2, tsb_kernel_mask); 529 PATCH_ASI(tl1_immu_miss_patch_asi_1, asi); 530 PATCH_LDD(tl1_immu_miss_patch_quad_ldd_1, ldd); 531 PATCH_TSB(tl1_immu_miss_patch_tsb_1, off); 532 PATCH_TSB(tl1_immu_miss_patch_tsb_2, off); 533 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_1, tsb_kernel_mask); 534 PATCH_TSB_MASK(tl1_immu_miss_patch_tsb_mask_2, tsb_kernel_mask); 535 536 /* 537 * Enter fake 8k pages for the 4MB kernel pages, so that 538 * pmap_kextract() will work for them. 539 */ 540 for (i = 0; i < kernel_tlb_slots; i++) { 541 pa = kernel_tlbs[i].te_pa; 542 va = kernel_tlbs[i].te_va; 543 for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) { 544 tp = tsb_kvtotte(va + off); 545 vpn = TV_VPN(va + off, TS_8K); 546 data = TD_V | TD_8K | TD_PA(pa + off) | TD_REF | 547 TD_SW | TD_CP | TD_CV | TD_P | TD_W; 548 pmap_bootstrap_set_tte(tp, vpn, data); 549 } 550 } 551 552 /* 553 * Set the start and end of KVA. The kernel is loaded starting 554 * at the first available 4MB super page, so we advance to the 555 * end of the last one used for it. 556 */ 557 virtual_avail = KERNBASE + kernel_tlb_slots * PAGE_SIZE_4M; 558 virtual_end = vm_max_kernel_address; 559 kernel_vm_end = vm_max_kernel_address; 560 561 /* 562 * Allocate kva space for temporary mappings. 563 */ 564 pmap_idle_map = virtual_avail; 565 virtual_avail += PAGE_SIZE * colors; 566 pmap_temp_map_1 = virtual_avail; 567 virtual_avail += PAGE_SIZE * colors; 568 pmap_temp_map_2 = virtual_avail; 569 virtual_avail += PAGE_SIZE * colors; 570 571 /* 572 * Allocate a kernel stack with guard page for thread0 and map it 573 * into the kernel TSB. We must ensure that the virtual address is 574 * colored properly for corresponding CPUs, since we're allocating 575 * from phys_avail so the memory won't have an associated vm_page_t. 576 */ 577 pa = pmap_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, colors); 578 kstack0_phys = pa; 579 virtual_avail += roundup(KSTACK_GUARD_PAGES, colors) * PAGE_SIZE; 580 kstack0 = virtual_avail; 581 virtual_avail += roundup(KSTACK_PAGES, colors) * PAGE_SIZE; 582 if (dcache_color_ignore == 0) 583 KASSERT(DCACHE_COLOR(kstack0) == DCACHE_COLOR(kstack0_phys), 584 ("pmap_bootstrap: kstack0 miscolored")); 585 for (i = 0; i < KSTACK_PAGES; i++) { 586 pa = kstack0_phys + i * PAGE_SIZE; 587 va = kstack0 + i * PAGE_SIZE; 588 tp = tsb_kvtotte(va); 589 vpn = TV_VPN(va, TS_8K); 590 data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_SW | TD_CP | 591 TD_CV | TD_P | TD_W; 592 pmap_bootstrap_set_tte(tp, vpn, data); 593 } 594 595 /* 596 * Calculate the last available physical address. 597 */ 598 for (i = 0; phys_avail[i + 2] != 0; i += 2) 599 ; 600 Maxmem = sparc64_btop(phys_avail[i + 1]); 601 602 /* 603 * Add the PROM mappings to the kernel TSB. 604 */ 605 if ((vmem = OF_finddevice("/virtual-memory")) == -1) 606 OF_panic("%s: finddevice /virtual-memory", __func__); 607 if ((sz = OF_getproplen(vmem, "translations")) == -1) 608 OF_panic("%s: getproplen translations", __func__); 609 if (sizeof(translations) < sz) 610 OF_panic("%s: translations too small", __func__); 611 bzero(translations, sz); 612 if (OF_getprop(vmem, "translations", translations, sz) == -1) 613 OF_panic("%s: getprop /virtual-memory/translations", 614 __func__); 615 sz /= sizeof(*translations); 616 translations_size = sz; 617 CTR0(KTR_PMAP, "pmap_bootstrap: translations"); 618 qsort(translations, sz, sizeof (*translations), om_cmp); 619 for (i = 0; i < sz; i++) { 620 CTR3(KTR_PMAP, 621 "translation: start=%#lx size=%#lx tte=%#lx", 622 translations[i].om_start, translations[i].om_size, 623 translations[i].om_tte); 624 if ((translations[i].om_tte & TD_V) == 0) 625 continue; 626 if (translations[i].om_start < VM_MIN_PROM_ADDRESS || 627 translations[i].om_start > VM_MAX_PROM_ADDRESS) 628 continue; 629 for (off = 0; off < translations[i].om_size; 630 off += PAGE_SIZE) { 631 va = translations[i].om_start + off; 632 tp = tsb_kvtotte(va); 633 vpn = TV_VPN(va, TS_8K); 634 data = ((translations[i].om_tte & 635 ~((TD_SOFT2_MASK << TD_SOFT2_SHIFT) | 636 (cpu_impl >= CPU_IMPL_ULTRASPARCI && 637 cpu_impl < CPU_IMPL_ULTRASPARCIII ? 638 (TD_DIAG_SF_MASK << TD_DIAG_SF_SHIFT) : 639 (TD_RSVD_CH_MASK << TD_RSVD_CH_SHIFT)) | 640 (TD_SOFT_MASK << TD_SOFT_SHIFT))) | TD_EXEC) + 641 off; 642 pmap_bootstrap_set_tte(tp, vpn, data); 643 } 644 } 645 646 /* 647 * Get the available physical memory ranges from /memory/reg. These 648 * are only used for kernel dumps, but it may not be wise to do PROM 649 * calls in that situation. 650 */ 651 if ((sz = OF_getproplen(pmem, "reg")) == -1) 652 OF_panic("%s: getproplen /memory/reg", __func__); 653 if (sizeof(sparc64_memreg) < sz) 654 OF_panic("%s: sparc64_memreg too small", __func__); 655 if (OF_getprop(pmem, "reg", sparc64_memreg, sz) == -1) 656 OF_panic("%s: getprop /memory/reg", __func__); 657 sparc64_nmemreg = sz / sizeof(*sparc64_memreg); 658 659 /* 660 * Initialize the kernel pmap (which is statically allocated). 661 */ 662 pm = kernel_pmap; 663 PMAP_LOCK_INIT(pm); 664 for (i = 0; i < MAXCPU; i++) 665 pm->pm_context[i] = TLB_CTX_KERNEL; 666 CPU_FILL(&pm->pm_active); 667 668 /* 669 * Initialize the global tte list lock, which is more commonly 670 * known as the pmap pv global lock. 671 */ 672 rw_init(&tte_list_global_lock, "pmap pv global"); 673 674 /* 675 * Flush all non-locked TLB entries possibly left over by the 676 * firmware. 677 */ 678 tlb_flush_nonlocked(); 679} 680 681/* 682 * Map the 4MB kernel TSB pages. 683 */ 684void 685pmap_map_tsb(void) 686{ 687 vm_offset_t va; 688 vm_paddr_t pa; 689 u_long data; 690 int i; 691 692 for (i = 0; i < tsb_kernel_size; i += PAGE_SIZE_4M) { 693 va = (vm_offset_t)tsb_kernel + i; 694 pa = tsb_kernel_phys + i; 695 data = TD_V | TD_4M | TD_PA(pa) | TD_L | TD_CP | TD_CV | 696 TD_P | TD_W; 697 stxa(AA_DMMU_TAR, ASI_DMMU, TLB_TAR_VA(va) | 698 TLB_TAR_CTX(TLB_CTX_KERNEL)); 699 stxa_sync(0, ASI_DTLB_DATA_IN_REG, data); 700 } 701} 702 703/* 704 * Set the secondary context to be the kernel context (needed for FP block 705 * operations in the kernel). 706 */ 707void 708pmap_set_kctx(void) 709{ 710 711 stxa(AA_DMMU_SCXR, ASI_DMMU, (ldxa(AA_DMMU_SCXR, ASI_DMMU) & 712 TLB_CXR_PGSZ_MASK) | TLB_CTX_KERNEL); 713 flush(KERNBASE); 714} 715 716/* 717 * Allocate a physical page of memory directly from the phys_avail map. 718 * Can only be called from pmap_bootstrap before avail start and end are 719 * calculated. 720 */ 721static vm_paddr_t 722pmap_bootstrap_alloc(vm_size_t size, uint32_t colors) 723{ 724 vm_paddr_t pa; 725 int i; 726 727 size = roundup(size, PAGE_SIZE * colors); 728 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 729 if (phys_avail[i + 1] - phys_avail[i] < size) 730 continue; 731 pa = phys_avail[i]; 732 phys_avail[i] += size; 733 return (pa); 734 } 735 OF_panic("%s: no suitable region found", __func__); 736} 737 738/* 739 * Set a TTE. This function is intended as a helper when tsb_kernel is 740 * direct-mapped but we haven't taken over the trap table, yet, as it's the 741 * case when we are taking advantage of ASI_ATOMIC_QUAD_LDD_PHYS to access 742 * the kernel TSB. 743 */ 744void 745pmap_bootstrap_set_tte(struct tte *tp, u_long vpn, u_long data) 746{ 747 748 if (tsb_kernel_ldd_phys == 0) { 749 tp->tte_vpn = vpn; 750 tp->tte_data = data; 751 } else { 752 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_vpn), 753 ASI_PHYS_USE_EC, vpn); 754 stxa((vm_paddr_t)tp + offsetof(struct tte, tte_data), 755 ASI_PHYS_USE_EC, data); 756 } 757} 758 759/* 760 * Initialize a vm_page's machine-dependent fields. 761 */ 762void 763pmap_page_init(vm_page_t m) 764{ 765 766 TAILQ_INIT(&m->md.tte_list); 767 m->md.color = DCACHE_COLOR(VM_PAGE_TO_PHYS(m)); 768 m->md.pmap = NULL; 769} 770 771/* 772 * Initialize the pmap module. 773 */ 774void 775pmap_init(void) 776{ 777 vm_offset_t addr; 778 vm_size_t size; 779 int result; 780 int i; 781 782 for (i = 0; i < translations_size; i++) { 783 addr = translations[i].om_start; 784 size = translations[i].om_size; 785 if ((translations[i].om_tte & TD_V) == 0) 786 continue; 787 if (addr < VM_MIN_PROM_ADDRESS || addr > VM_MAX_PROM_ADDRESS) 788 continue; 789 result = vm_map_find(kernel_map, NULL, 0, &addr, size, 790 VMFS_NO_SPACE, VM_PROT_ALL, VM_PROT_ALL, MAP_NOFAULT); 791 if (result != KERN_SUCCESS || addr != translations[i].om_start) 792 panic("pmap_init: vm_map_find"); 793 } 794} 795 796/* 797 * Extract the physical page address associated with the given 798 * map/virtual_address pair. 799 */ 800vm_paddr_t 801pmap_extract(pmap_t pm, vm_offset_t va) 802{ 803 struct tte *tp; 804 vm_paddr_t pa; 805 806 if (pm == kernel_pmap) 807 return (pmap_kextract(va)); 808 PMAP_LOCK(pm); 809 tp = tsb_tte_lookup(pm, va); 810 if (tp == NULL) 811 pa = 0; 812 else 813 pa = TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp)); 814 PMAP_UNLOCK(pm); 815 return (pa); 816} 817 818/* 819 * Atomically extract and hold the physical page with the given 820 * pmap and virtual address pair if that mapping permits the given 821 * protection. 822 */ 823vm_page_t 824pmap_extract_and_hold(pmap_t pm, vm_offset_t va, vm_prot_t prot) 825{ 826 struct tte *tp; 827 vm_page_t m; 828 vm_paddr_t pa; 829 830 m = NULL; 831 pa = 0; 832 PMAP_LOCK(pm); 833retry: 834 if (pm == kernel_pmap) { 835 if (va >= VM_MIN_DIRECT_ADDRESS) { 836 tp = NULL; 837 m = PHYS_TO_VM_PAGE(TLB_DIRECT_TO_PHYS(va)); 838 (void)vm_page_pa_tryrelock(pm, TLB_DIRECT_TO_PHYS(va), 839 &pa); 840 vm_page_hold(m); 841 } else { 842 tp = tsb_kvtotte(va); 843 if ((tp->tte_data & TD_V) == 0) 844 tp = NULL; 845 } 846 } else 847 tp = tsb_tte_lookup(pm, va); 848 if (tp != NULL && ((tp->tte_data & TD_SW) || 849 (prot & VM_PROT_WRITE) == 0)) { 850 if (vm_page_pa_tryrelock(pm, TTE_GET_PA(tp), &pa)) 851 goto retry; 852 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 853 vm_page_hold(m); 854 } 855 PA_UNLOCK_COND(pa); 856 PMAP_UNLOCK(pm); 857 return (m); 858} 859 860/* 861 * Extract the physical page address associated with the given kernel virtual 862 * address. 863 */ 864vm_paddr_t 865pmap_kextract(vm_offset_t va) 866{ 867 struct tte *tp; 868 869 if (va >= VM_MIN_DIRECT_ADDRESS) 870 return (TLB_DIRECT_TO_PHYS(va)); 871 tp = tsb_kvtotte(va); 872 if ((tp->tte_data & TD_V) == 0) 873 return (0); 874 return (TTE_GET_PA(tp) | (va & TTE_GET_PAGE_MASK(tp))); 875} 876 877int 878pmap_cache_enter(vm_page_t m, vm_offset_t va) 879{ 880 struct tte *tp; 881 int color; 882 883 rw_assert(&tte_list_global_lock, RA_WLOCKED); 884 KASSERT((m->flags & PG_FICTITIOUS) == 0, 885 ("pmap_cache_enter: fake page")); 886 PMAP_STATS_INC(pmap_ncache_enter); 887 888 if (dcache_color_ignore != 0) 889 return (1); 890 891 /* 892 * Find the color for this virtual address and note the added mapping. 893 */ 894 color = DCACHE_COLOR(va); 895 m->md.colors[color]++; 896 897 /* 898 * If all existing mappings have the same color, the mapping is 899 * cacheable. 900 */ 901 if (m->md.color == color) { 902 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] == 0, 903 ("pmap_cache_enter: cacheable, mappings of other color")); 904 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m))) 905 PMAP_STATS_INC(pmap_ncache_enter_c); 906 else 907 PMAP_STATS_INC(pmap_ncache_enter_oc); 908 return (1); 909 } 910 911 /* 912 * If there are no mappings of the other color, and the page still has 913 * the wrong color, this must be a new mapping. Change the color to 914 * match the new mapping, which is cacheable. We must flush the page 915 * from the cache now. 916 */ 917 if (m->md.colors[DCACHE_OTHER_COLOR(color)] == 0) { 918 KASSERT(m->md.colors[color] == 1, 919 ("pmap_cache_enter: changing color, not new mapping")); 920 dcache_page_inval(VM_PAGE_TO_PHYS(m)); 921 m->md.color = color; 922 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m))) 923 PMAP_STATS_INC(pmap_ncache_enter_cc); 924 else 925 PMAP_STATS_INC(pmap_ncache_enter_coc); 926 return (1); 927 } 928 929 /* 930 * If the mapping is already non-cacheable, just return. 931 */ 932 if (m->md.color == -1) { 933 PMAP_STATS_INC(pmap_ncache_enter_nc); 934 return (0); 935 } 936 937 PMAP_STATS_INC(pmap_ncache_enter_cnc); 938 939 /* 940 * Mark all mappings as uncacheable, flush any lines with the other 941 * color out of the dcache, and set the color to none (-1). 942 */ 943 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 944 atomic_clear_long(&tp->tte_data, TD_CV); 945 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp)); 946 } 947 dcache_page_inval(VM_PAGE_TO_PHYS(m)); 948 m->md.color = -1; 949 return (0); 950} 951 952static void 953pmap_cache_remove(vm_page_t m, vm_offset_t va) 954{ 955 struct tte *tp; 956 int color; 957 958 rw_assert(&tte_list_global_lock, RA_WLOCKED); 959 CTR3(KTR_PMAP, "pmap_cache_remove: m=%p va=%#lx c=%d", m, va, 960 m->md.colors[DCACHE_COLOR(va)]); 961 KASSERT((m->flags & PG_FICTITIOUS) == 0, 962 ("pmap_cache_remove: fake page")); 963 PMAP_STATS_INC(pmap_ncache_remove); 964 965 if (dcache_color_ignore != 0) 966 return; 967 968 KASSERT(m->md.colors[DCACHE_COLOR(va)] > 0, 969 ("pmap_cache_remove: no mappings %d <= 0", 970 m->md.colors[DCACHE_COLOR(va)])); 971 972 /* 973 * Find the color for this virtual address and note the removal of 974 * the mapping. 975 */ 976 color = DCACHE_COLOR(va); 977 m->md.colors[color]--; 978 979 /* 980 * If the page is cacheable, just return and keep the same color, even 981 * if there are no longer any mappings. 982 */ 983 if (m->md.color != -1) { 984 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m))) 985 PMAP_STATS_INC(pmap_ncache_remove_c); 986 else 987 PMAP_STATS_INC(pmap_ncache_remove_oc); 988 return; 989 } 990 991 KASSERT(m->md.colors[DCACHE_OTHER_COLOR(color)] != 0, 992 ("pmap_cache_remove: uncacheable, no mappings of other color")); 993 994 /* 995 * If the page is not cacheable (color is -1), and the number of 996 * mappings for this color is not zero, just return. There are 997 * mappings of the other color still, so remain non-cacheable. 998 */ 999 if (m->md.colors[color] != 0) { 1000 PMAP_STATS_INC(pmap_ncache_remove_nc); 1001 return; 1002 } 1003 1004 /* 1005 * The number of mappings for this color is now zero. Recache the 1006 * other colored mappings, and change the page color to the other 1007 * color. There should be no lines in the data cache for this page, 1008 * so flushing should not be needed. 1009 */ 1010 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1011 atomic_set_long(&tp->tte_data, TD_CV); 1012 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp)); 1013 } 1014 m->md.color = DCACHE_OTHER_COLOR(color); 1015 1016 if (m->md.color == DCACHE_COLOR(VM_PAGE_TO_PHYS(m))) 1017 PMAP_STATS_INC(pmap_ncache_remove_cc); 1018 else 1019 PMAP_STATS_INC(pmap_ncache_remove_coc); 1020} 1021 1022/* 1023 * Map a wired page into kernel virtual address space. 1024 */ 1025void 1026pmap_kenter(vm_offset_t va, vm_page_t m) 1027{ 1028 vm_offset_t ova; 1029 struct tte *tp; 1030 vm_page_t om; 1031 u_long data; 1032 1033 rw_assert(&tte_list_global_lock, RA_WLOCKED); 1034 PMAP_STATS_INC(pmap_nkenter); 1035 tp = tsb_kvtotte(va); 1036 CTR4(KTR_PMAP, "pmap_kenter: va=%#lx pa=%#lx tp=%p data=%#lx", 1037 va, VM_PAGE_TO_PHYS(m), tp, tp->tte_data); 1038 if (DCACHE_COLOR(VM_PAGE_TO_PHYS(m)) != DCACHE_COLOR(va)) { 1039 CTR5(KTR_SPARE2, 1040 "pmap_kenter: off color va=%#lx pa=%#lx o=%p ot=%d pi=%#lx", 1041 va, VM_PAGE_TO_PHYS(m), m->object, 1042 m->object ? m->object->type : -1, 1043 m->pindex); 1044 PMAP_STATS_INC(pmap_nkenter_oc); 1045 } 1046 if ((tp->tte_data & TD_V) != 0) { 1047 om = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1048 ova = TTE_GET_VA(tp); 1049 if (m == om && va == ova) { 1050 PMAP_STATS_INC(pmap_nkenter_stupid); 1051 return; 1052 } 1053 TAILQ_REMOVE(&om->md.tte_list, tp, tte_link); 1054 pmap_cache_remove(om, ova); 1055 if (va != ova) 1056 tlb_page_demap(kernel_pmap, ova); 1057 } 1058 data = TD_V | TD_8K | VM_PAGE_TO_PHYS(m) | TD_REF | TD_SW | TD_CP | 1059 TD_P | TD_W; 1060 if (pmap_cache_enter(m, va) != 0) 1061 data |= TD_CV; 1062 tp->tte_vpn = TV_VPN(va, TS_8K); 1063 tp->tte_data = data; 1064 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link); 1065} 1066 1067/* 1068 * Map a wired page into kernel virtual address space. This additionally 1069 * takes a flag argument which is or'ed to the TTE data. This is used by 1070 * sparc64_bus_mem_map(). 1071 * NOTE: if the mapping is non-cacheable, it's the caller's responsibility 1072 * to flush entries that might still be in the cache, if applicable. 1073 */ 1074void 1075pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags) 1076{ 1077 struct tte *tp; 1078 1079 tp = tsb_kvtotte(va); 1080 CTR4(KTR_PMAP, "pmap_kenter_flags: va=%#lx pa=%#lx tp=%p data=%#lx", 1081 va, pa, tp, tp->tte_data); 1082 tp->tte_vpn = TV_VPN(va, TS_8K); 1083 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_REF | TD_P | flags; 1084} 1085 1086/* 1087 * Remove a wired page from kernel virtual address space. 1088 */ 1089void 1090pmap_kremove(vm_offset_t va) 1091{ 1092 struct tte *tp; 1093 vm_page_t m; 1094 1095 rw_assert(&tte_list_global_lock, RA_WLOCKED); 1096 PMAP_STATS_INC(pmap_nkremove); 1097 tp = tsb_kvtotte(va); 1098 CTR3(KTR_PMAP, "pmap_kremove: va=%#lx tp=%p data=%#lx", va, tp, 1099 tp->tte_data); 1100 if ((tp->tte_data & TD_V) == 0) 1101 return; 1102 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1103 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link); 1104 pmap_cache_remove(m, va); 1105 TTE_ZERO(tp); 1106} 1107 1108/* 1109 * Inverse of pmap_kenter_flags, used by bus_space_unmap(). 1110 */ 1111void 1112pmap_kremove_flags(vm_offset_t va) 1113{ 1114 struct tte *tp; 1115 1116 tp = tsb_kvtotte(va); 1117 CTR3(KTR_PMAP, "pmap_kremove_flags: va=%#lx tp=%p data=%#lx", va, tp, 1118 tp->tte_data); 1119 TTE_ZERO(tp); 1120} 1121 1122/* 1123 * Map a range of physical addresses into kernel virtual address space. 1124 * 1125 * The value passed in *virt is a suggested virtual address for the mapping. 1126 * Architectures which can support a direct-mapped physical to virtual region 1127 * can return the appropriate address within that region, leaving '*virt' 1128 * unchanged. 1129 */ 1130vm_offset_t 1131pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1132{ 1133 1134 return (TLB_PHYS_TO_DIRECT(start)); 1135} 1136 1137/* 1138 * Map a list of wired pages into kernel virtual address space. This is 1139 * intended for temporary mappings which do not need page modification or 1140 * references recorded. Existing mappings in the region are overwritten. 1141 */ 1142void 1143pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) 1144{ 1145 vm_offset_t va; 1146 1147 PMAP_STATS_INC(pmap_nqenter); 1148 va = sva; 1149 rw_wlock(&tte_list_global_lock); 1150 while (count-- > 0) { 1151 pmap_kenter(va, *m); 1152 va += PAGE_SIZE; 1153 m++; 1154 } 1155 rw_wunlock(&tte_list_global_lock); 1156 tlb_range_demap(kernel_pmap, sva, va); 1157} 1158 1159/* 1160 * Remove page mappings from kernel virtual address space. Intended for 1161 * temporary mappings entered by pmap_qenter. 1162 */ 1163void 1164pmap_qremove(vm_offset_t sva, int count) 1165{ 1166 vm_offset_t va; 1167 1168 PMAP_STATS_INC(pmap_nqremove); 1169 va = sva; 1170 rw_wlock(&tte_list_global_lock); 1171 while (count-- > 0) { 1172 pmap_kremove(va); 1173 va += PAGE_SIZE; 1174 } 1175 rw_wunlock(&tte_list_global_lock); 1176 tlb_range_demap(kernel_pmap, sva, va); 1177} 1178 1179/* 1180 * Initialize the pmap associated with process 0. 1181 */ 1182void 1183pmap_pinit0(pmap_t pm) 1184{ 1185 int i; 1186 1187 PMAP_LOCK_INIT(pm); 1188 for (i = 0; i < MAXCPU; i++) 1189 pm->pm_context[i] = TLB_CTX_KERNEL; 1190 CPU_ZERO(&pm->pm_active); 1191 pm->pm_tsb = NULL; 1192 pm->pm_tsb_obj = NULL; 1193 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1194} 1195 1196/* 1197 * Initialize a preallocated and zeroed pmap structure, such as one in a 1198 * vmspace structure. 1199 */ 1200int 1201pmap_pinit(pmap_t pm) 1202{ 1203 vm_page_t ma[TSB_PAGES]; 1204 vm_page_t m; 1205 int i; 1206 1207 PMAP_LOCK_INIT(pm); 1208 1209 /* 1210 * Allocate KVA space for the TSB. 1211 */ 1212 if (pm->pm_tsb == NULL) { 1213 pm->pm_tsb = (struct tte *)kva_alloc(TSB_BSIZE); 1214 if (pm->pm_tsb == NULL) { 1215 PMAP_LOCK_DESTROY(pm); 1216 return (0); 1217 } 1218 } 1219 1220 /* 1221 * Allocate an object for it. 1222 */ 1223 if (pm->pm_tsb_obj == NULL) 1224 pm->pm_tsb_obj = vm_object_allocate(OBJT_PHYS, TSB_PAGES); 1225 1226 for (i = 0; i < MAXCPU; i++) 1227 pm->pm_context[i] = -1; 1228 CPU_ZERO(&pm->pm_active); 1229 1230 VM_OBJECT_WLOCK(pm->pm_tsb_obj); 1231 for (i = 0; i < TSB_PAGES; i++) { 1232 m = vm_page_grab(pm->pm_tsb_obj, i, VM_ALLOC_NOBUSY | 1233 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1234 m->valid = VM_PAGE_BITS_ALL; 1235 m->md.pmap = pm; 1236 ma[i] = m; 1237 } 1238 VM_OBJECT_WUNLOCK(pm->pm_tsb_obj); 1239 pmap_qenter((vm_offset_t)pm->pm_tsb, ma, TSB_PAGES); 1240 1241 bzero(&pm->pm_stats, sizeof(pm->pm_stats)); 1242 return (1); 1243} 1244 1245/* 1246 * Release any resources held by the given physical map. 1247 * Called when a pmap initialized by pmap_pinit is being released. 1248 * Should only be called if the map contains no valid mappings. 1249 */ 1250void 1251pmap_release(pmap_t pm) 1252{ 1253 vm_object_t obj; 1254 vm_page_t m; 1255#ifdef SMP 1256 struct pcpu *pc; 1257#endif 1258 1259 CTR2(KTR_PMAP, "pmap_release: ctx=%#x tsb=%p", 1260 pm->pm_context[curcpu], pm->pm_tsb); 1261 KASSERT(pmap_resident_count(pm) == 0, 1262 ("pmap_release: resident pages %ld != 0", 1263 pmap_resident_count(pm))); 1264 1265 /* 1266 * After the pmap was freed, it might be reallocated to a new process. 1267 * When switching, this might lead us to wrongly assume that we need 1268 * not switch contexts because old and new pmap pointer are equal. 1269 * Therefore, make sure that this pmap is not referenced by any PCPU 1270 * pointer any more. This could happen in two cases: 1271 * - A process that referenced the pmap is currently exiting on a CPU. 1272 * However, it is guaranteed to not switch in any more after setting 1273 * its state to PRS_ZOMBIE. 1274 * - A process that referenced this pmap ran on a CPU, but we switched 1275 * to a kernel thread, leaving the pmap pointer unchanged. 1276 */ 1277#ifdef SMP 1278 sched_pin(); 1279 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) 1280 atomic_cmpset_rel_ptr((uintptr_t *)&pc->pc_pmap, 1281 (uintptr_t)pm, (uintptr_t)NULL); 1282 sched_unpin(); 1283#else 1284 critical_enter(); 1285 if (PCPU_GET(pmap) == pm) 1286 PCPU_SET(pmap, NULL); 1287 critical_exit(); 1288#endif 1289 1290 pmap_qremove((vm_offset_t)pm->pm_tsb, TSB_PAGES); 1291 obj = pm->pm_tsb_obj; 1292 VM_OBJECT_WLOCK(obj); 1293 KASSERT(obj->ref_count == 1, ("pmap_release: tsbobj ref count != 1")); 1294 while (!TAILQ_EMPTY(&obj->memq)) { 1295 m = TAILQ_FIRST(&obj->memq); 1296 m->md.pmap = NULL; 1297 m->wire_count--; 1298 atomic_subtract_int(&cnt.v_wire_count, 1); 1299 vm_page_free_zero(m); 1300 } 1301 VM_OBJECT_WUNLOCK(obj); 1302 PMAP_LOCK_DESTROY(pm); 1303} 1304 1305/* 1306 * Grow the number of kernel page table entries. Unneeded. 1307 */ 1308void 1309pmap_growkernel(vm_offset_t addr) 1310{ 1311 1312 panic("pmap_growkernel: can't grow kernel"); 1313} 1314 1315int 1316pmap_remove_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp, 1317 vm_offset_t va) 1318{ 1319 vm_page_t m; 1320 u_long data; 1321 1322 rw_assert(&tte_list_global_lock, RA_WLOCKED); 1323 data = atomic_readandclear_long(&tp->tte_data); 1324 if ((data & TD_FAKE) == 0) { 1325 m = PHYS_TO_VM_PAGE(TD_PA(data)); 1326 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link); 1327 if ((data & TD_WIRED) != 0) 1328 pm->pm_stats.wired_count--; 1329 if ((data & TD_PV) != 0) { 1330 if ((data & TD_W) != 0) 1331 vm_page_dirty(m); 1332 if ((data & TD_REF) != 0) 1333 vm_page_aflag_set(m, PGA_REFERENCED); 1334 if (TAILQ_EMPTY(&m->md.tte_list)) 1335 vm_page_aflag_clear(m, PGA_WRITEABLE); 1336 pm->pm_stats.resident_count--; 1337 } 1338 pmap_cache_remove(m, va); 1339 } 1340 TTE_ZERO(tp); 1341 if (PMAP_REMOVE_DONE(pm)) 1342 return (0); 1343 return (1); 1344} 1345 1346/* 1347 * Remove the given range of addresses from the specified map. 1348 */ 1349void 1350pmap_remove(pmap_t pm, vm_offset_t start, vm_offset_t end) 1351{ 1352 struct tte *tp; 1353 vm_offset_t va; 1354 1355 CTR3(KTR_PMAP, "pmap_remove: ctx=%#lx start=%#lx end=%#lx", 1356 pm->pm_context[curcpu], start, end); 1357 if (PMAP_REMOVE_DONE(pm)) 1358 return; 1359 rw_wlock(&tte_list_global_lock); 1360 PMAP_LOCK(pm); 1361 if (end - start > PMAP_TSB_THRESH) { 1362 tsb_foreach(pm, NULL, start, end, pmap_remove_tte); 1363 tlb_context_demap(pm); 1364 } else { 1365 for (va = start; va < end; va += PAGE_SIZE) 1366 if ((tp = tsb_tte_lookup(pm, va)) != NULL && 1367 !pmap_remove_tte(pm, NULL, tp, va)) 1368 break; 1369 tlb_range_demap(pm, start, end - 1); 1370 } 1371 PMAP_UNLOCK(pm); 1372 rw_wunlock(&tte_list_global_lock); 1373} 1374 1375void 1376pmap_remove_all(vm_page_t m) 1377{ 1378 struct pmap *pm; 1379 struct tte *tpn; 1380 struct tte *tp; 1381 vm_offset_t va; 1382 1383 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1384 ("pmap_remove_all: page %p is not managed", m)); 1385 rw_wlock(&tte_list_global_lock); 1386 for (tp = TAILQ_FIRST(&m->md.tte_list); tp != NULL; tp = tpn) { 1387 tpn = TAILQ_NEXT(tp, tte_link); 1388 if ((tp->tte_data & TD_PV) == 0) 1389 continue; 1390 pm = TTE_GET_PMAP(tp); 1391 va = TTE_GET_VA(tp); 1392 PMAP_LOCK(pm); 1393 if ((tp->tte_data & TD_WIRED) != 0) 1394 pm->pm_stats.wired_count--; 1395 if ((tp->tte_data & TD_REF) != 0) 1396 vm_page_aflag_set(m, PGA_REFERENCED); 1397 if ((tp->tte_data & TD_W) != 0) 1398 vm_page_dirty(m); 1399 tp->tte_data &= ~TD_V; 1400 tlb_page_demap(pm, va); 1401 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link); 1402 pm->pm_stats.resident_count--; 1403 pmap_cache_remove(m, va); 1404 TTE_ZERO(tp); 1405 PMAP_UNLOCK(pm); 1406 } 1407 vm_page_aflag_clear(m, PGA_WRITEABLE); 1408 rw_wunlock(&tte_list_global_lock); 1409} 1410 1411static int 1412pmap_protect_tte(struct pmap *pm, struct pmap *pm2, struct tte *tp, 1413 vm_offset_t va) 1414{ 1415 u_long data; 1416 vm_page_t m; 1417 1418 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1419 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W); 1420 if ((data & (TD_PV | TD_W)) == (TD_PV | TD_W)) { 1421 m = PHYS_TO_VM_PAGE(TD_PA(data)); 1422 vm_page_dirty(m); 1423 } 1424 return (1); 1425} 1426 1427/* 1428 * Set the physical protection on the specified range of this map as requested. 1429 */ 1430void 1431pmap_protect(pmap_t pm, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1432{ 1433 vm_offset_t va; 1434 struct tte *tp; 1435 1436 CTR4(KTR_PMAP, "pmap_protect: ctx=%#lx sva=%#lx eva=%#lx prot=%#lx", 1437 pm->pm_context[curcpu], sva, eva, prot); 1438 1439 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1440 pmap_remove(pm, sva, eva); 1441 return; 1442 } 1443 1444 if (prot & VM_PROT_WRITE) 1445 return; 1446 1447 PMAP_LOCK(pm); 1448 if (eva - sva > PMAP_TSB_THRESH) { 1449 tsb_foreach(pm, NULL, sva, eva, pmap_protect_tte); 1450 tlb_context_demap(pm); 1451 } else { 1452 for (va = sva; va < eva; va += PAGE_SIZE) 1453 if ((tp = tsb_tte_lookup(pm, va)) != NULL) 1454 pmap_protect_tte(pm, NULL, tp, va); 1455 tlb_range_demap(pm, sva, eva - 1); 1456 } 1457 PMAP_UNLOCK(pm); 1458} 1459 1460/* 1461 * Map the given physical page at the specified virtual address in the 1462 * target pmap with the protection requested. If specified the page 1463 * will be wired down. 1464 */ 1465void 1466pmap_enter(pmap_t pm, vm_offset_t va, vm_prot_t access, vm_page_t m, 1467 vm_prot_t prot, boolean_t wired) 1468{ 1469 1470 rw_wlock(&tte_list_global_lock); 1471 PMAP_LOCK(pm); 1472 pmap_enter_locked(pm, va, m, prot, wired); 1473 rw_wunlock(&tte_list_global_lock); 1474 PMAP_UNLOCK(pm); 1475} 1476 1477/* 1478 * Map the given physical page at the specified virtual address in the 1479 * target pmap with the protection requested. If specified the page 1480 * will be wired down. 1481 * 1482 * The page queues and pmap must be locked. 1483 */ 1484static void 1485pmap_enter_locked(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot, 1486 boolean_t wired) 1487{ 1488 struct tte *tp; 1489 vm_paddr_t pa; 1490 vm_page_t real; 1491 u_long data; 1492 1493 rw_assert(&tte_list_global_lock, RA_WLOCKED); 1494 PMAP_LOCK_ASSERT(pm, MA_OWNED); 1495 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1496 VM_OBJECT_ASSERT_LOCKED(m->object); 1497 PMAP_STATS_INC(pmap_nenter); 1498 pa = VM_PAGE_TO_PHYS(m); 1499 1500 /* 1501 * If this is a fake page from the device_pager, but it covers actual 1502 * physical memory, convert to the real backing page. 1503 */ 1504 if ((m->flags & PG_FICTITIOUS) != 0) { 1505 real = vm_phys_paddr_to_vm_page(pa); 1506 if (real != NULL) 1507 m = real; 1508 } 1509 1510 CTR6(KTR_PMAP, 1511 "pmap_enter_locked: ctx=%p m=%p va=%#lx pa=%#lx prot=%#x wired=%d", 1512 pm->pm_context[curcpu], m, va, pa, prot, wired); 1513 1514 /* 1515 * If there is an existing mapping, and the physical address has not 1516 * changed, must be protection or wiring change. 1517 */ 1518 if ((tp = tsb_tte_lookup(pm, va)) != NULL && TTE_GET_PA(tp) == pa) { 1519 CTR0(KTR_PMAP, "pmap_enter_locked: update"); 1520 PMAP_STATS_INC(pmap_nenter_update); 1521 1522 /* 1523 * Wiring change, just update stats. 1524 */ 1525 if (wired) { 1526 if ((tp->tte_data & TD_WIRED) == 0) { 1527 tp->tte_data |= TD_WIRED; 1528 pm->pm_stats.wired_count++; 1529 } 1530 } else { 1531 if ((tp->tte_data & TD_WIRED) != 0) { 1532 tp->tte_data &= ~TD_WIRED; 1533 pm->pm_stats.wired_count--; 1534 } 1535 } 1536 1537 /* 1538 * Save the old bits and clear the ones we're interested in. 1539 */ 1540 data = tp->tte_data; 1541 tp->tte_data &= ~(TD_EXEC | TD_SW | TD_W); 1542 1543 /* 1544 * If we're turning off write permissions, sense modify status. 1545 */ 1546 if ((prot & VM_PROT_WRITE) != 0) { 1547 tp->tte_data |= TD_SW; 1548 if (wired) 1549 tp->tte_data |= TD_W; 1550 if ((m->oflags & VPO_UNMANAGED) == 0) 1551 vm_page_aflag_set(m, PGA_WRITEABLE); 1552 } else if ((data & TD_W) != 0) 1553 vm_page_dirty(m); 1554 1555 /* 1556 * If we're turning on execute permissions, flush the icache. 1557 */ 1558 if ((prot & VM_PROT_EXECUTE) != 0) { 1559 if ((data & TD_EXEC) == 0) 1560 icache_page_inval(pa); 1561 tp->tte_data |= TD_EXEC; 1562 } 1563 1564 /* 1565 * Delete the old mapping. 1566 */ 1567 tlb_page_demap(pm, TTE_GET_VA(tp)); 1568 } else { 1569 /* 1570 * If there is an existing mapping, but its for a different 1571 * physical address, delete the old mapping. 1572 */ 1573 if (tp != NULL) { 1574 CTR0(KTR_PMAP, "pmap_enter_locked: replace"); 1575 PMAP_STATS_INC(pmap_nenter_replace); 1576 pmap_remove_tte(pm, NULL, tp, va); 1577 tlb_page_demap(pm, va); 1578 } else { 1579 CTR0(KTR_PMAP, "pmap_enter_locked: new"); 1580 PMAP_STATS_INC(pmap_nenter_new); 1581 } 1582 1583 /* 1584 * Now set up the data and install the new mapping. 1585 */ 1586 data = TD_V | TD_8K | TD_PA(pa); 1587 if (pm == kernel_pmap) 1588 data |= TD_P; 1589 if ((prot & VM_PROT_WRITE) != 0) { 1590 data |= TD_SW; 1591 if ((m->oflags & VPO_UNMANAGED) == 0) 1592 vm_page_aflag_set(m, PGA_WRITEABLE); 1593 } 1594 if (prot & VM_PROT_EXECUTE) { 1595 data |= TD_EXEC; 1596 icache_page_inval(pa); 1597 } 1598 1599 /* 1600 * If its wired update stats. We also don't need reference or 1601 * modify tracking for wired mappings, so set the bits now. 1602 */ 1603 if (wired) { 1604 pm->pm_stats.wired_count++; 1605 data |= TD_REF | TD_WIRED; 1606 if ((prot & VM_PROT_WRITE) != 0) 1607 data |= TD_W; 1608 } 1609 1610 tsb_tte_enter(pm, m, va, TS_8K, data); 1611 } 1612} 1613 1614/* 1615 * Maps a sequence of resident pages belonging to the same object. 1616 * The sequence begins with the given page m_start. This page is 1617 * mapped at the given virtual address start. Each subsequent page is 1618 * mapped at a virtual address that is offset from start by the same 1619 * amount as the page is offset from m_start within the object. The 1620 * last page in the sequence is the page with the largest offset from 1621 * m_start that can be mapped at a virtual address less than the given 1622 * virtual address end. Not every virtual page between start and end 1623 * is mapped; only those for which a resident page exists with the 1624 * corresponding offset from m_start are mapped. 1625 */ 1626void 1627pmap_enter_object(pmap_t pm, vm_offset_t start, vm_offset_t end, 1628 vm_page_t m_start, vm_prot_t prot) 1629{ 1630 vm_page_t m; 1631 vm_pindex_t diff, psize; 1632 1633 VM_OBJECT_ASSERT_LOCKED(m_start->object); 1634 1635 psize = atop(end - start); 1636 m = m_start; 1637 rw_wlock(&tte_list_global_lock); 1638 PMAP_LOCK(pm); 1639 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1640 pmap_enter_locked(pm, start + ptoa(diff), m, prot & 1641 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1642 m = TAILQ_NEXT(m, listq); 1643 } 1644 rw_wunlock(&tte_list_global_lock); 1645 PMAP_UNLOCK(pm); 1646} 1647 1648void 1649pmap_enter_quick(pmap_t pm, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1650{ 1651 1652 rw_wlock(&tte_list_global_lock); 1653 PMAP_LOCK(pm); 1654 pmap_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE), 1655 FALSE); 1656 rw_wunlock(&tte_list_global_lock); 1657 PMAP_UNLOCK(pm); 1658} 1659 1660void 1661pmap_object_init_pt(pmap_t pm, vm_offset_t addr, vm_object_t object, 1662 vm_pindex_t pindex, vm_size_t size) 1663{ 1664 1665 VM_OBJECT_ASSERT_WLOCKED(object); 1666 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 1667 ("pmap_object_init_pt: non-device object")); 1668} 1669 1670/* 1671 * Change the wiring attribute for a map/virtual-address pair. 1672 * The mapping must already exist in the pmap. 1673 */ 1674void 1675pmap_change_wiring(pmap_t pm, vm_offset_t va, boolean_t wired) 1676{ 1677 struct tte *tp; 1678 u_long data; 1679 1680 PMAP_LOCK(pm); 1681 if ((tp = tsb_tte_lookup(pm, va)) != NULL) { 1682 if (wired) { 1683 data = atomic_set_long(&tp->tte_data, TD_WIRED); 1684 if ((data & TD_WIRED) == 0) 1685 pm->pm_stats.wired_count++; 1686 } else { 1687 data = atomic_clear_long(&tp->tte_data, TD_WIRED); 1688 if ((data & TD_WIRED) != 0) 1689 pm->pm_stats.wired_count--; 1690 } 1691 } 1692 PMAP_UNLOCK(pm); 1693} 1694 1695static int 1696pmap_copy_tte(pmap_t src_pmap, pmap_t dst_pmap, struct tte *tp, 1697 vm_offset_t va) 1698{ 1699 vm_page_t m; 1700 u_long data; 1701 1702 if ((tp->tte_data & TD_FAKE) != 0) 1703 return (1); 1704 if (tsb_tte_lookup(dst_pmap, va) == NULL) { 1705 data = tp->tte_data & 1706 ~(TD_PV | TD_REF | TD_SW | TD_CV | TD_W); 1707 m = PHYS_TO_VM_PAGE(TTE_GET_PA(tp)); 1708 tsb_tte_enter(dst_pmap, m, va, TS_8K, data); 1709 } 1710 return (1); 1711} 1712 1713void 1714pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 1715 vm_size_t len, vm_offset_t src_addr) 1716{ 1717 struct tte *tp; 1718 vm_offset_t va; 1719 1720 if (dst_addr != src_addr) 1721 return; 1722 rw_wlock(&tte_list_global_lock); 1723 if (dst_pmap < src_pmap) { 1724 PMAP_LOCK(dst_pmap); 1725 PMAP_LOCK(src_pmap); 1726 } else { 1727 PMAP_LOCK(src_pmap); 1728 PMAP_LOCK(dst_pmap); 1729 } 1730 if (len > PMAP_TSB_THRESH) { 1731 tsb_foreach(src_pmap, dst_pmap, src_addr, src_addr + len, 1732 pmap_copy_tte); 1733 tlb_context_demap(dst_pmap); 1734 } else { 1735 for (va = src_addr; va < src_addr + len; va += PAGE_SIZE) 1736 if ((tp = tsb_tte_lookup(src_pmap, va)) != NULL) 1737 pmap_copy_tte(src_pmap, dst_pmap, tp, va); 1738 tlb_range_demap(dst_pmap, src_addr, src_addr + len - 1); 1739 } 1740 rw_wunlock(&tte_list_global_lock); 1741 PMAP_UNLOCK(src_pmap); 1742 PMAP_UNLOCK(dst_pmap); 1743} 1744 1745void 1746pmap_zero_page(vm_page_t m) 1747{ 1748 struct tte *tp; 1749 vm_offset_t va; 1750 vm_paddr_t pa; 1751 1752 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1753 ("pmap_zero_page: fake page")); 1754 PMAP_STATS_INC(pmap_nzero_page); 1755 pa = VM_PAGE_TO_PHYS(m); 1756 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) { 1757 PMAP_STATS_INC(pmap_nzero_page_c); 1758 va = TLB_PHYS_TO_DIRECT(pa); 1759 cpu_block_zero((void *)va, PAGE_SIZE); 1760 } else if (m->md.color == -1) { 1761 PMAP_STATS_INC(pmap_nzero_page_nc); 1762 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE); 1763 } else { 1764 PMAP_STATS_INC(pmap_nzero_page_oc); 1765 PMAP_LOCK(kernel_pmap); 1766 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE); 1767 tp = tsb_kvtotte(va); 1768 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W; 1769 tp->tte_vpn = TV_VPN(va, TS_8K); 1770 cpu_block_zero((void *)va, PAGE_SIZE); 1771 tlb_page_demap(kernel_pmap, va); 1772 PMAP_UNLOCK(kernel_pmap); 1773 } 1774} 1775 1776void 1777pmap_zero_page_area(vm_page_t m, int off, int size) 1778{ 1779 struct tte *tp; 1780 vm_offset_t va; 1781 vm_paddr_t pa; 1782 1783 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1784 ("pmap_zero_page_area: fake page")); 1785 KASSERT(off + size <= PAGE_SIZE, ("pmap_zero_page_area: bad off/size")); 1786 PMAP_STATS_INC(pmap_nzero_page_area); 1787 pa = VM_PAGE_TO_PHYS(m); 1788 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) { 1789 PMAP_STATS_INC(pmap_nzero_page_area_c); 1790 va = TLB_PHYS_TO_DIRECT(pa); 1791 bzero((void *)(va + off), size); 1792 } else if (m->md.color == -1) { 1793 PMAP_STATS_INC(pmap_nzero_page_area_nc); 1794 aszero(ASI_PHYS_USE_EC, pa + off, size); 1795 } else { 1796 PMAP_STATS_INC(pmap_nzero_page_area_oc); 1797 PMAP_LOCK(kernel_pmap); 1798 va = pmap_temp_map_1 + (m->md.color * PAGE_SIZE); 1799 tp = tsb_kvtotte(va); 1800 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W; 1801 tp->tte_vpn = TV_VPN(va, TS_8K); 1802 bzero((void *)(va + off), size); 1803 tlb_page_demap(kernel_pmap, va); 1804 PMAP_UNLOCK(kernel_pmap); 1805 } 1806} 1807 1808void 1809pmap_zero_page_idle(vm_page_t m) 1810{ 1811 struct tte *tp; 1812 vm_offset_t va; 1813 vm_paddr_t pa; 1814 1815 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1816 ("pmap_zero_page_idle: fake page")); 1817 PMAP_STATS_INC(pmap_nzero_page_idle); 1818 pa = VM_PAGE_TO_PHYS(m); 1819 if (dcache_color_ignore != 0 || m->md.color == DCACHE_COLOR(pa)) { 1820 PMAP_STATS_INC(pmap_nzero_page_idle_c); 1821 va = TLB_PHYS_TO_DIRECT(pa); 1822 cpu_block_zero((void *)va, PAGE_SIZE); 1823 } else if (m->md.color == -1) { 1824 PMAP_STATS_INC(pmap_nzero_page_idle_nc); 1825 aszero(ASI_PHYS_USE_EC, pa, PAGE_SIZE); 1826 } else { 1827 PMAP_STATS_INC(pmap_nzero_page_idle_oc); 1828 va = pmap_idle_map + (m->md.color * PAGE_SIZE); 1829 tp = tsb_kvtotte(va); 1830 tp->tte_data = TD_V | TD_8K | TD_PA(pa) | TD_CP | TD_CV | TD_W; 1831 tp->tte_vpn = TV_VPN(va, TS_8K); 1832 cpu_block_zero((void *)va, PAGE_SIZE); 1833 tlb_page_demap(kernel_pmap, va); 1834 } 1835} 1836 1837void 1838pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 1839{ 1840 vm_offset_t vdst; 1841 vm_offset_t vsrc; 1842 vm_paddr_t pdst; 1843 vm_paddr_t psrc; 1844 struct tte *tp; 1845 1846 KASSERT((mdst->flags & PG_FICTITIOUS) == 0, 1847 ("pmap_copy_page: fake dst page")); 1848 KASSERT((msrc->flags & PG_FICTITIOUS) == 0, 1849 ("pmap_copy_page: fake src page")); 1850 PMAP_STATS_INC(pmap_ncopy_page); 1851 pdst = VM_PAGE_TO_PHYS(mdst); 1852 psrc = VM_PAGE_TO_PHYS(msrc); 1853 if (dcache_color_ignore != 0 || 1854 (msrc->md.color == DCACHE_COLOR(psrc) && 1855 mdst->md.color == DCACHE_COLOR(pdst))) { 1856 PMAP_STATS_INC(pmap_ncopy_page_c); 1857 vdst = TLB_PHYS_TO_DIRECT(pdst); 1858 vsrc = TLB_PHYS_TO_DIRECT(psrc); 1859 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE); 1860 } else if (msrc->md.color == -1 && mdst->md.color == -1) { 1861 PMAP_STATS_INC(pmap_ncopy_page_nc); 1862 ascopy(ASI_PHYS_USE_EC, psrc, pdst, PAGE_SIZE); 1863 } else if (msrc->md.color == -1) { 1864 if (mdst->md.color == DCACHE_COLOR(pdst)) { 1865 PMAP_STATS_INC(pmap_ncopy_page_dc); 1866 vdst = TLB_PHYS_TO_DIRECT(pdst); 1867 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst, 1868 PAGE_SIZE); 1869 } else { 1870 PMAP_STATS_INC(pmap_ncopy_page_doc); 1871 PMAP_LOCK(kernel_pmap); 1872 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE); 1873 tp = tsb_kvtotte(vdst); 1874 tp->tte_data = 1875 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W; 1876 tp->tte_vpn = TV_VPN(vdst, TS_8K); 1877 ascopyfrom(ASI_PHYS_USE_EC, psrc, (void *)vdst, 1878 PAGE_SIZE); 1879 tlb_page_demap(kernel_pmap, vdst); 1880 PMAP_UNLOCK(kernel_pmap); 1881 } 1882 } else if (mdst->md.color == -1) { 1883 if (msrc->md.color == DCACHE_COLOR(psrc)) { 1884 PMAP_STATS_INC(pmap_ncopy_page_sc); 1885 vsrc = TLB_PHYS_TO_DIRECT(psrc); 1886 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst, 1887 PAGE_SIZE); 1888 } else { 1889 PMAP_STATS_INC(pmap_ncopy_page_soc); 1890 PMAP_LOCK(kernel_pmap); 1891 vsrc = pmap_temp_map_1 + (msrc->md.color * PAGE_SIZE); 1892 tp = tsb_kvtotte(vsrc); 1893 tp->tte_data = 1894 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W; 1895 tp->tte_vpn = TV_VPN(vsrc, TS_8K); 1896 ascopyto((void *)vsrc, ASI_PHYS_USE_EC, pdst, 1897 PAGE_SIZE); 1898 tlb_page_demap(kernel_pmap, vsrc); 1899 PMAP_UNLOCK(kernel_pmap); 1900 } 1901 } else { 1902 PMAP_STATS_INC(pmap_ncopy_page_oc); 1903 PMAP_LOCK(kernel_pmap); 1904 vdst = pmap_temp_map_1 + (mdst->md.color * PAGE_SIZE); 1905 tp = tsb_kvtotte(vdst); 1906 tp->tte_data = 1907 TD_V | TD_8K | TD_PA(pdst) | TD_CP | TD_CV | TD_W; 1908 tp->tte_vpn = TV_VPN(vdst, TS_8K); 1909 vsrc = pmap_temp_map_2 + (msrc->md.color * PAGE_SIZE); 1910 tp = tsb_kvtotte(vsrc); 1911 tp->tte_data = 1912 TD_V | TD_8K | TD_PA(psrc) | TD_CP | TD_CV | TD_W; 1913 tp->tte_vpn = TV_VPN(vsrc, TS_8K); 1914 cpu_block_copy((void *)vsrc, (void *)vdst, PAGE_SIZE); 1915 tlb_page_demap(kernel_pmap, vdst); 1916 tlb_page_demap(kernel_pmap, vsrc); 1917 PMAP_UNLOCK(kernel_pmap); 1918 } 1919} 1920 1921int unmapped_buf_allowed; 1922 1923void 1924pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 1925 vm_offset_t b_offset, int xfersize) 1926{ 1927 1928 panic("pmap_copy_pages: not implemented"); 1929} 1930 1931/* 1932 * Returns true if the pmap's pv is one of the first 1933 * 16 pvs linked to from this page. This count may 1934 * be changed upwards or downwards in the future; it 1935 * is only necessary that true be returned for a small 1936 * subset of pmaps for proper page aging. 1937 */ 1938boolean_t 1939pmap_page_exists_quick(pmap_t pm, vm_page_t m) 1940{ 1941 struct tte *tp; 1942 int loops; 1943 boolean_t rv; 1944 1945 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1946 ("pmap_page_exists_quick: page %p is not managed", m)); 1947 loops = 0; 1948 rv = FALSE; 1949 rw_wlock(&tte_list_global_lock); 1950 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 1951 if ((tp->tte_data & TD_PV) == 0) 1952 continue; 1953 if (TTE_GET_PMAP(tp) == pm) { 1954 rv = TRUE; 1955 break; 1956 } 1957 if (++loops >= 16) 1958 break; 1959 } 1960 rw_wunlock(&tte_list_global_lock); 1961 return (rv); 1962} 1963 1964/* 1965 * Return the number of managed mappings to the given physical page 1966 * that are wired. 1967 */ 1968int 1969pmap_page_wired_mappings(vm_page_t m) 1970{ 1971 struct tte *tp; 1972 int count; 1973 1974 count = 0; 1975 if ((m->oflags & VPO_UNMANAGED) != 0) 1976 return (count); 1977 rw_wlock(&tte_list_global_lock); 1978 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) 1979 if ((tp->tte_data & (TD_PV | TD_WIRED)) == (TD_PV | TD_WIRED)) 1980 count++; 1981 rw_wunlock(&tte_list_global_lock); 1982 return (count); 1983} 1984 1985/* 1986 * Remove all pages from specified address space, this aids process exit 1987 * speeds. This is much faster than pmap_remove in the case of running down 1988 * an entire address space. Only works for the current pmap. 1989 */ 1990void 1991pmap_remove_pages(pmap_t pm) 1992{ 1993 1994} 1995 1996/* 1997 * Returns TRUE if the given page has a managed mapping. 1998 */ 1999boolean_t 2000pmap_page_is_mapped(vm_page_t m) 2001{ 2002 struct tte *tp; 2003 boolean_t rv; 2004 2005 rv = FALSE; 2006 if ((m->oflags & VPO_UNMANAGED) != 0) 2007 return (rv); 2008 rw_wlock(&tte_list_global_lock); 2009 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) 2010 if ((tp->tte_data & TD_PV) != 0) { 2011 rv = TRUE; 2012 break; 2013 } 2014 rw_wunlock(&tte_list_global_lock); 2015 return (rv); 2016} 2017 2018/* 2019 * Return a count of reference bits for a page, clearing those bits. 2020 * It is not necessary for every reference bit to be cleared, but it 2021 * is necessary that 0 only be returned when there are truly no 2022 * reference bits set. 2023 * 2024 * XXX: The exact number of bits to check and clear is a matter that 2025 * should be tested and standardized at some point in the future for 2026 * optimal aging of shared pages. 2027 */ 2028int 2029pmap_ts_referenced(vm_page_t m) 2030{ 2031 struct tte *tpf; 2032 struct tte *tpn; 2033 struct tte *tp; 2034 u_long data; 2035 int count; 2036 2037 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2038 ("pmap_ts_referenced: page %p is not managed", m)); 2039 count = 0; 2040 rw_wlock(&tte_list_global_lock); 2041 if ((tp = TAILQ_FIRST(&m->md.tte_list)) != NULL) { 2042 tpf = tp; 2043 do { 2044 tpn = TAILQ_NEXT(tp, tte_link); 2045 TAILQ_REMOVE(&m->md.tte_list, tp, tte_link); 2046 TAILQ_INSERT_TAIL(&m->md.tte_list, tp, tte_link); 2047 if ((tp->tte_data & TD_PV) == 0) 2048 continue; 2049 data = atomic_clear_long(&tp->tte_data, TD_REF); 2050 if ((data & TD_REF) != 0 && ++count > 4) 2051 break; 2052 } while ((tp = tpn) != NULL && tp != tpf); 2053 } 2054 rw_wunlock(&tte_list_global_lock); 2055 return (count); 2056} 2057 2058boolean_t 2059pmap_is_modified(vm_page_t m) 2060{ 2061 struct tte *tp; 2062 boolean_t rv; 2063 2064 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2065 ("pmap_is_modified: page %p is not managed", m)); 2066 rv = FALSE; 2067 2068 /* 2069 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2070 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2071 * is clear, no TTEs can have TD_W set. 2072 */ 2073 VM_OBJECT_ASSERT_WLOCKED(m->object); 2074 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2075 return (rv); 2076 rw_wlock(&tte_list_global_lock); 2077 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 2078 if ((tp->tte_data & TD_PV) == 0) 2079 continue; 2080 if ((tp->tte_data & TD_W) != 0) { 2081 rv = TRUE; 2082 break; 2083 } 2084 } 2085 rw_wunlock(&tte_list_global_lock); 2086 return (rv); 2087} 2088 2089/* 2090 * pmap_is_prefaultable: 2091 * 2092 * Return whether or not the specified virtual address is elgible 2093 * for prefault. 2094 */ 2095boolean_t 2096pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2097{ 2098 boolean_t rv; 2099 2100 PMAP_LOCK(pmap); 2101 rv = tsb_tte_lookup(pmap, addr) == NULL; 2102 PMAP_UNLOCK(pmap); 2103 return (rv); 2104} 2105 2106/* 2107 * Return whether or not the specified physical page was referenced 2108 * in any physical maps. 2109 */ 2110boolean_t 2111pmap_is_referenced(vm_page_t m) 2112{ 2113 struct tte *tp; 2114 boolean_t rv; 2115 2116 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2117 ("pmap_is_referenced: page %p is not managed", m)); 2118 rv = FALSE; 2119 rw_wlock(&tte_list_global_lock); 2120 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 2121 if ((tp->tte_data & TD_PV) == 0) 2122 continue; 2123 if ((tp->tte_data & TD_REF) != 0) { 2124 rv = TRUE; 2125 break; 2126 } 2127 } 2128 rw_wunlock(&tte_list_global_lock); 2129 return (rv); 2130} 2131 2132void 2133pmap_clear_modify(vm_page_t m) 2134{ 2135 struct tte *tp; 2136 u_long data; 2137 2138 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2139 ("pmap_clear_modify: page %p is not managed", m)); 2140 VM_OBJECT_ASSERT_WLOCKED(m->object); 2141 KASSERT(!vm_page_xbusied(m), 2142 ("pmap_clear_modify: page %p is exclusive busied", m)); 2143 2144 /* 2145 * If the page is not PGA_WRITEABLE, then no TTEs can have TD_W set. 2146 * If the object containing the page is locked and the page is not 2147 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 2148 */ 2149 if ((m->aflags & PGA_WRITEABLE) == 0) 2150 return; 2151 rw_wlock(&tte_list_global_lock); 2152 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 2153 if ((tp->tte_data & TD_PV) == 0) 2154 continue; 2155 data = atomic_clear_long(&tp->tte_data, TD_W); 2156 if ((data & TD_W) != 0) 2157 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp)); 2158 } 2159 rw_wunlock(&tte_list_global_lock); 2160} 2161 2162void 2163pmap_clear_reference(vm_page_t m) 2164{ 2165 struct tte *tp; 2166 u_long data; 2167 2168 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2169 ("pmap_clear_reference: page %p is not managed", m)); 2170 rw_wlock(&tte_list_global_lock); 2171 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 2172 if ((tp->tte_data & TD_PV) == 0) 2173 continue; 2174 data = atomic_clear_long(&tp->tte_data, TD_REF); 2175 if ((data & TD_REF) != 0) 2176 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp)); 2177 } 2178 rw_wunlock(&tte_list_global_lock); 2179} 2180 2181void 2182pmap_remove_write(vm_page_t m) 2183{ 2184 struct tte *tp; 2185 u_long data; 2186 2187 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2188 ("pmap_remove_write: page %p is not managed", m)); 2189 2190 /* 2191 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2192 * set by another thread while the object is locked. Thus, 2193 * if PGA_WRITEABLE is clear, no page table entries need updating. 2194 */ 2195 VM_OBJECT_ASSERT_WLOCKED(m->object); 2196 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2197 return; 2198 rw_wlock(&tte_list_global_lock); 2199 TAILQ_FOREACH(tp, &m->md.tte_list, tte_link) { 2200 if ((tp->tte_data & TD_PV) == 0) 2201 continue; 2202 data = atomic_clear_long(&tp->tte_data, TD_SW | TD_W); 2203 if ((data & TD_W) != 0) { 2204 vm_page_dirty(m); 2205 tlb_page_demap(TTE_GET_PMAP(tp), TTE_GET_VA(tp)); 2206 } 2207 } 2208 vm_page_aflag_clear(m, PGA_WRITEABLE); 2209 rw_wunlock(&tte_list_global_lock); 2210} 2211 2212int 2213pmap_mincore(pmap_t pm, vm_offset_t addr, vm_paddr_t *locked_pa) 2214{ 2215 2216 /* TODO; */ 2217 return (0); 2218} 2219 2220/* 2221 * Activate a user pmap. The pmap must be activated before its address space 2222 * can be accessed in any way. 2223 */ 2224void 2225pmap_activate(struct thread *td) 2226{ 2227 struct vmspace *vm; 2228 struct pmap *pm; 2229 int context; 2230 2231 critical_enter(); 2232 vm = td->td_proc->p_vmspace; 2233 pm = vmspace_pmap(vm); 2234 2235 context = PCPU_GET(tlb_ctx); 2236 if (context == PCPU_GET(tlb_ctx_max)) { 2237 tlb_flush_user(); 2238 context = PCPU_GET(tlb_ctx_min); 2239 } 2240 PCPU_SET(tlb_ctx, context + 1); 2241 2242 pm->pm_context[curcpu] = context; 2243#ifdef SMP 2244 CPU_SET_ATOMIC(PCPU_GET(cpuid), &pm->pm_active); 2245 atomic_store_acq_ptr((uintptr_t *)PCPU_PTR(pmap), (uintptr_t)pm); 2246#else 2247 CPU_SET(PCPU_GET(cpuid), &pm->pm_active); 2248 PCPU_SET(pmap, pm); 2249#endif 2250 2251 stxa(AA_DMMU_TSB, ASI_DMMU, pm->pm_tsb); 2252 stxa(AA_IMMU_TSB, ASI_IMMU, pm->pm_tsb); 2253 stxa(AA_DMMU_PCXR, ASI_DMMU, (ldxa(AA_DMMU_PCXR, ASI_DMMU) & 2254 TLB_CXR_PGSZ_MASK) | context); 2255 flush(KERNBASE); 2256 critical_exit(); 2257} 2258 2259void 2260pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2261{ 2262 2263} 2264 2265/* 2266 * Increase the starting virtual address of the given mapping if a 2267 * different alignment might result in more superpage mappings. 2268 */ 2269void 2270pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2271 vm_offset_t *addr, vm_size_t size) 2272{ 2273 2274} 2275