lsi64854.c revision 182876
1/*- 2 * Copyright (c) 2004 Scott Long 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28/* $NetBSD: lsi64854.c,v 1.25 2005/02/27 00:27:02 perry Exp $ */ 29 30/*- 31 * Copyright (c) 1998 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Paul Kranenburg. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the NetBSD 48 * Foundation, Inc. and its contributors. 49 * 4. Neither the name of The NetBSD Foundation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 63 * POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66#include <sys/cdefs.h> 67__FBSDID("$FreeBSD: head/sys/sparc64/sbus/lsi64854.c 182876 2008-09-08 20:20:44Z marius $"); 68 69#include <sys/param.h> 70#include <sys/systm.h> 71#include <sys/bus.h> 72#include <sys/kernel.h> 73#include <sys/lock.h> 74#include <sys/mutex.h> 75#include <sys/rman.h> 76 77#include <machine/bus.h> 78 79#include <cam/cam.h> 80#include <cam/cam_ccb.h> 81#include <cam/scsi/scsi_all.h> 82 83#include <sparc64/sbus/lsi64854reg.h> 84#include <sparc64/sbus/lsi64854var.h> 85 86#include <dev/esp/ncr53c9xreg.h> 87#include <dev/esp/ncr53c9xvar.h> 88 89#ifdef DEBUG 90#define LDB_SCSI 1 91#define LDB_ENET 2 92#define LDB_PP 4 93#define LDB_ANY 0xff 94int lsi64854debug = 0; 95#define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 96#else 97#define DPRINTF(a,x) 98#endif 99 100#define MAX_DMA_SZ (16*1024*1024) 101 102static void lsi64854_reset(struct lsi64854_softc *); 103static void lsi64854_map_scsi(void *, bus_dma_segment_t *, int, int); 104static int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *, 105 int, size_t *); 106static int lsi64854_scsi_intr(void *); 107static int lsi64854_enet_intr(void *); 108static int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *, 109 int, size_t *); 110static int lsi64854_pp_intr(void *); 111 112/* 113 * Finish attaching this DMA device. 114 * Front-end must fill in these fields: 115 * sc_res 116 * sc_burst 117 * sc_channel (one of SCSI, ENET, PP) 118 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 119 */ 120int 121lsi64854_attach(struct lsi64854_softc *sc) 122{ 123 bus_dma_lock_t *lockfunc; 124 struct ncr53c9x_softc *nsc; 125 void *lockfuncarg; 126 uint32_t csr; 127 int error; 128 129 lockfunc = NULL; 130 lockfuncarg = NULL; 131 132 switch (sc->sc_channel) { 133 case L64854_CHANNEL_SCSI: 134 nsc = sc->sc_client; 135 if (NCR_LOCK_INITIALIZED(nsc) == 0) { 136 device_printf(sc->sc_dev, "mutex not initialized\n"); 137 return (ENXIO); 138 } 139 lockfunc = busdma_lock_mutex; 140 lockfuncarg = &nsc->sc_lock; 141 sc->intr = lsi64854_scsi_intr; 142 sc->setup = lsi64854_setup; 143 break; 144 case L64854_CHANNEL_ENET: 145 sc->intr = lsi64854_enet_intr; 146 break; 147 case L64854_CHANNEL_PP: 148 sc->intr = lsi64854_pp_intr; 149 sc->setup = lsi64854_setup_pp; 150 break; 151 default: 152 device_printf(sc->sc_dev, "unknown channel\n"); 153 } 154 sc->reset = lsi64854_reset; 155 156 if (sc->setup != NULL) { 157 error = bus_dma_tag_create( 158 sc->sc_parent_dmat, /* parent */ 159 1, 0, /* alignment, boundary */ 160 BUS_SPACE_MAXADDR, /* lowaddr */ 161 BUS_SPACE_MAXADDR, /* highaddr */ 162 NULL, NULL, /* filter, filterarg */ 163 MAX_DMA_SZ, /* maxsize */ 164 1, /* nsegments */ 165 MAX_DMA_SZ, /* maxsegsize */ 166 BUS_DMA_ALLOCNOW, /* flags */ 167 lockfunc, lockfuncarg, /* lockfunc, lockfuncarg */ 168 &sc->sc_buffer_dmat); 169 if (error != 0) { 170 device_printf(sc->sc_dev, 171 "cannot allocate buffer DMA tag\n"); 172 return (error); 173 } 174 175 error = bus_dmamap_create(sc->sc_buffer_dmat, 0, 176 &sc->sc_dmamap); 177 if (error != 0) { 178 device_printf(sc->sc_dev, "DMA map create failed\n"); 179 bus_dma_tag_destroy(sc->sc_buffer_dmat); 180 return (error); 181 } 182 } 183 184 csr = L64854_GCSR(sc); 185 sc->sc_rev = csr & L64854_DEVID; 186 if (sc->sc_rev == DMAREV_HME) 187 return (0); 188 device_printf(sc->sc_dev, "DMA rev. "); 189 switch (sc->sc_rev) { 190 case DMAREV_0: 191 printf("0"); 192 break; 193 case DMAREV_ESC: 194 printf("ESC"); 195 break; 196 case DMAREV_1: 197 printf("1"); 198 break; 199 case DMAREV_PLUS: 200 printf("1+"); 201 break; 202 case DMAREV_2: 203 printf("2"); 204 break; 205 default: 206 printf("unknown (0x%x)", sc->sc_rev); 207 } 208 209 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 210 printf("\n"); 211 212 return (0); 213} 214 215int 216lsi64854_detach(struct lsi64854_softc *sc) 217{ 218 219 if (sc->setup != NULL) { 220 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 221 (L64854_GCSR(sc) & L64854_WRITE) != 0 ? 222 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 223 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 224 bus_dmamap_destroy(sc->sc_buffer_dmat, sc->sc_dmamap); 225 bus_dma_tag_destroy(sc->sc_buffer_dmat); 226 } 227 228 return (0); 229} 230 231/* 232 * DMAWAIT waits while condition is true. 233 */ 234#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 235 int count = 500000; \ 236 while ((COND) && --count > 0) DELAY(1); \ 237 if (count == 0) { \ 238 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 239 (u_long)L64854_GCSR(SC)); \ 240 if (DONTPANIC) \ 241 printf(MSG); \ 242 else \ 243 panic(MSG); \ 244 } \ 245} while (0) 246 247#define DMA_DRAIN(sc, dontpanic) do { \ 248 uint32_t csr; \ 249 /* \ 250 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 251 * and "drain" bits while it is still thinking about a \ 252 * request. \ 253 * other revs: D_ESC_R_PEND bit reads as 0 \ 254 */ \ 255 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 256 if (sc->sc_rev != DMAREV_HME) { \ 257 /* \ 258 * Select drain bit based on revision \ 259 * also clears errors and D_TC flag \ 260 */ \ 261 csr = L64854_GCSR(sc); \ 262 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 263 csr |= D_ESC_DRAIN; \ 264 else \ 265 csr |= L64854_INVALIDATE; \ 266 \ 267 L64854_SCSR(sc,csr); \ 268 } \ 269 /* \ 270 * Wait for draining to finish \ 271 * rev0 & rev1 call this PACKCNT \ 272 */ \ 273 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 274} while(0) 275 276#define DMA_FLUSH(sc, dontpanic) do { \ 277 uint32_t csr; \ 278 /* \ 279 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 280 * and "drain" bits while it is still thinking about a \ 281 * request. \ 282 * other revs: D_ESC_R_PEND bit reads as 0 \ 283 */ \ 284 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 285 csr = L64854_GCSR(sc); \ 286 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 287 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 288 L64854_SCSR(sc,csr); \ 289} while(0) 290 291static void 292lsi64854_reset(struct lsi64854_softc *sc) 293{ 294 uint32_t csr; 295 296 DMA_FLUSH(sc, 1); 297 csr = L64854_GCSR(sc); 298 299 DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr)); 300 301 if (sc->sc_dmasize != 0) { 302 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 303 (csr & D_WRITE) != 0 ? BUS_DMASYNC_PREREAD : 304 BUS_DMASYNC_PREWRITE); 305 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 306 } 307 308 if (sc->sc_rev == DMAREV_HME) 309 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 310 311 csr |= L64854_RESET; /* reset DMA */ 312 L64854_SCSR(sc, csr); 313 DELAY(200); /* > 10 Sbus clocks(?) */ 314 315 /*DMAWAIT1(sc); why was this here? */ 316 csr = L64854_GCSR(sc); 317 csr &= ~L64854_RESET; /* de-assert reset line */ 318 L64854_SCSR(sc, csr); 319 DELAY(5); /* allow a few ticks to settle */ 320 321 csr = L64854_GCSR(sc); 322 csr |= L64854_INT_EN; /* enable interrupts */ 323 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 324 if (sc->sc_rev == DMAREV_HME) 325 csr |= D_TWO_CYCLE; 326 else 327 csr |= D_FASTER; 328 } 329 330 /* Set burst */ 331 switch (sc->sc_rev) { 332 case DMAREV_HME: 333 case DMAREV_2: 334 csr &= ~L64854_BURST_SIZE; 335 if (sc->sc_burst == 32) 336 csr |= L64854_BURST_32; 337 else if (sc->sc_burst == 16) 338 csr |= L64854_BURST_16; 339 else 340 csr |= L64854_BURST_0; 341 break; 342 case DMAREV_ESC: 343 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 344 if (sc->sc_burst == 32) 345 csr &= ~D_ESC_BURST; 346 else 347 csr |= D_ESC_BURST; 348 break; 349 default: 350 break; 351 } 352 L64854_SCSR(sc, csr); 353 354 if (sc->sc_rev == DMAREV_HME) { 355 bus_write_4(sc->sc_res, L64854_REG_ADDR, 0); 356 sc->sc_dmactl = csr; 357 } 358 sc->sc_active = 0; 359 360 DPRINTF(LDB_ANY, ("%s: done, csr 0x%x\n", __func__, csr)); 361} 362 363static void 364lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error) 365{ 366 struct lsi64854_softc *sc; 367 368 sc = (struct lsi64854_softc *)arg; 369 370 if (nseg != 1) 371 panic("%s: cannot map %d segments\n", __func__, nseg); 372 373 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 374 sc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 375 bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr); 376} 377 378#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ - 1))) 379/* 380 * setup a DMA transfer 381 */ 382static int 383lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len, 384 int datain, size_t *dmasize) 385{ 386 long bcnt; 387 uint32_t csr; 388 389 DMA_FLUSH(sc, 0); 390 391#if 0 392 DMACSR(sc) &= ~D_INT_EN; 393#endif 394 sc->sc_dmaaddr = addr; 395 sc->sc_dmalen = len; 396 sc->sc_datain = datain; 397 398 /* 399 * The rules say we cannot transfer more than the limit 400 * of this DMA chip (64k for old and 16Mb for new), 401 * and we cannot cross a 16Mb boundary. 402 */ 403 *dmasize = sc->sc_dmasize = 404 ulmin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr)); 405 406 DPRINTF(LDB_ANY, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize)); 407 408 /* 409 * XXX what length? 410 */ 411 if (sc->sc_rev == DMAREV_HME) { 412 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 413 L64854_SCSR(sc, sc->sc_dmactl); 414 415 bus_write_4(sc->sc_res, L64854_REG_CNT, *dmasize); 416 } 417 418 /* Program the DMA address */ 419 if (sc->sc_dmasize != 0) 420 if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap, 421 *sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_scsi, sc, 0)) 422 panic("%s: cannot allocate DVMA address", __func__); 423 424 if (sc->sc_rev == DMAREV_ESC) { 425 /* DMA ESC chip bug work-around */ 426 bcnt = sc->sc_dmasize; 427 if (((bcnt + (long)*sc->sc_dmaaddr) & PAGE_MASK_8K) != 0) 428 bcnt = roundup(bcnt, PAGE_SIZE_8K); 429 bus_write_4(sc->sc_res, L64854_REG_CNT, bcnt); 430 } 431 432 /* Setup DMA control register */ 433 csr = L64854_GCSR(sc); 434 435 if (datain) 436 csr |= L64854_WRITE; 437 else 438 csr &= ~L64854_WRITE; 439 csr |= L64854_INT_EN; 440 441 if (sc->sc_rev == DMAREV_HME) 442 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 443 444 L64854_SCSR(sc, csr); 445 446 return (0); 447} 448 449/* 450 * Pseudo (chained) interrupt from the esp driver to kick the 451 * current running DMA transfer. Called from ncr53c9x_intr() 452 * for now. 453 * 454 * return 1 if it was a DMA continue. 455 */ 456static int 457lsi64854_scsi_intr(void *arg) 458{ 459 struct lsi64854_softc *sc = arg; 460 struct ncr53c9x_softc *nsc = sc->sc_client; 461 int trans, resid; 462 uint32_t csr; 463 464 csr = L64854_GCSR(sc); 465 466 DPRINTF(LDB_SCSI, ("%s: addr 0x%x, csr %b\n", __func__, 467 bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, DDMACSR_BITS)); 468 469 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 470 device_printf(sc->sc_dev, "error: csr=%b\n", csr, DDMACSR_BITS); 471 csr &= ~D_EN_DMA; /* Stop DMA */ 472 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 473 csr |= D_INVALIDATE|D_SLAVE_ERR; 474 L64854_SCSR(sc, csr); 475 return (-1); 476 } 477 478 /* This is an "assertion" :) */ 479 if (sc->sc_active == 0) 480 panic("%s: DMA wasn't active", __func__); 481 482 DMA_DRAIN(sc, 0); 483 484 /* DMA has stopped */ 485 csr &= ~D_EN_DMA; 486 L64854_SCSR(sc, csr); 487 sc->sc_active = 0; 488 489 if (sc->sc_dmasize == 0) { 490 /* A "Transfer Pad" operation completed */ 491 DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", 492 __func__, NCR_READ_REG(nsc, NCR_TCL) | 493 (NCR_READ_REG(nsc, NCR_TCM) << 8), 494 NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM))); 495 return (0); 496 } 497 498 resid = 0; 499 /* 500 * If a transfer onto the SCSI bus gets interrupted by the device 501 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 502 * as residual since the NCR53C9X counter registers get decremented 503 * as bytes are clocked into the FIFO. 504 */ 505 if (!(csr & D_WRITE) && 506 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 507 DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", __func__, 508 resid)); 509 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 510 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 511 resid <<= 1; 512 } 513 514 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 515 /* 516 * `Terminal count' is off, so read the residue 517 * out of the NCR53C9X counter registers. 518 */ 519 resid += (NCR_READ_REG(nsc, NCR_TCL) | 520 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 521 ((nsc->sc_cfg2 & NCRCFG2_FE) ? 522 (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0)); 523 524 if (resid == 0 && sc->sc_dmasize == 65536 && 525 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 526 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 527 resid = 65536; 528 } 529 530 trans = sc->sc_dmasize - resid; 531 if (trans < 0) { /* transfered < 0? */ 532#if 0 533 /* 534 * This situation can happen in perfectly normal operation 535 * if the ESP is reselected while using DMA to select 536 * another target. As such, don't print the warning. 537 */ 538 device_printf(sc->sc_dev, "xfer (%d) > req (%d)\n", trans, 539 sc->sc_dmasize); 540#endif 541 trans = sc->sc_dmasize; 542 } 543 544 DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 545 __func__, NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM), 546 (nsc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(nsc, NCR_TCH) : 0, 547 trans, resid)); 548 549 if (sc->sc_dmasize != 0) { 550 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 551 (csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD : 552 BUS_DMASYNC_POSTWRITE); 553 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 554 } 555 556 *sc->sc_dmalen -= trans; 557 *sc->sc_dmaaddr += trans; 558 559#if 0 /* this is not normal operation just yet */ 560 if (*sc->sc_dmalen == 0 || nsc->sc_phase != nsc->sc_prevphase) 561 return (0); 562 563 /* and again */ 564 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 565 return (1); 566#endif 567 return (0); 568} 569 570/* 571 * Pseudo (chained) interrupt to le driver to handle DMA errors. 572 */ 573static int 574lsi64854_enet_intr(void *arg) 575{ 576 struct lsi64854_softc *sc = arg; 577 uint32_t csr; 578 int i, rv; 579 580 csr = L64854_GCSR(sc); 581 582 /* If the DMA logic shows an interrupt, claim it */ 583 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 584 585 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 586 device_printf(sc->sc_dev, "error: csr=%b\n", csr, EDMACSR_BITS); 587 csr &= ~L64854_EN_DMA; /* Stop DMA */ 588 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 589 csr |= E_INVALIDATE|E_SLAVE_ERR; 590 L64854_SCSR(sc, csr); 591 /* Will be drained with the LE_C0_IDON interrupt. */ 592 sc->sc_dodrain = 1; 593 return (-1); 594 } 595 596 /* XXX - is this necessary with E_DSBL_WR_INVAL on? */ 597 if (sc->sc_dodrain) { 598 i = 10; 599 csr |= E_DRAIN; 600 L64854_SCSR(sc, csr); 601 while (i-- > 0 && (L64854_GCSR(sc) & E_DRAINING)) 602 DELAY(1); 603 sc->sc_dodrain = 0; 604 } 605 606 return (rv); 607} 608 609static void 610lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 611{ 612 struct lsi64854_softc *sc; 613 614 sc = (struct lsi64854_softc *)arg; 615 616 if (nsegs != 1) 617 panic("%s: cannot map %d segments\n", __func__, nsegs); 618 619 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ? 620 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 621 bus_write_4(sc->sc_res, L64854_REG_ADDR, segs[0].ds_addr); 622 623 bus_write_4(sc->sc_res, L64854_REG_CNT, sc->sc_dmasize); 624} 625 626/* 627 * setup a DMA transfer 628 */ 629static int 630lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len, 631 int datain, size_t *dmasize) 632{ 633 uint32_t csr; 634 635 DMA_FLUSH(sc, 0); 636 637 sc->sc_dmaaddr = addr; 638 sc->sc_dmalen = len; 639 sc->sc_datain = datain; 640 641 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", __func__, 642 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 643 644 /* 645 * the rules say we cannot transfer more than the limit 646 * of this DMA chip (64k for old and 16Mb for new), 647 * and we cannot cross a 16Mb boundary. 648 */ 649 *dmasize = sc->sc_dmasize = 650 ulmin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr)); 651 652 DPRINTF(LDB_PP, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize)); 653 654 /* Program the DMA address */ 655 if (sc->sc_dmasize != 0) 656 if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap, 657 *sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_pp, sc, 0)) 658 panic("%s: pp cannot allocate DVMA address", __func__); 659 660 /* Setup DMA control register */ 661 csr = L64854_GCSR(sc); 662 csr &= ~L64854_BURST_SIZE; 663 if (sc->sc_burst == 32) 664 csr |= L64854_BURST_32; 665 else if (sc->sc_burst == 16) 666 csr |= L64854_BURST_16; 667 else 668 csr |= L64854_BURST_0; 669 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 670#if 0 671 /* This bit is read-only in PP csr register */ 672 if (datain) 673 csr |= P_WRITE; 674 else 675 csr &= ~P_WRITE; 676#endif 677 L64854_SCSR(sc, csr); 678 679 return (0); 680} 681 682/* 683 * Parallel port DMA interrupt. 684 */ 685static int 686lsi64854_pp_intr(void *arg) 687{ 688 struct lsi64854_softc *sc = arg; 689 int ret, trans, resid = 0; 690 uint32_t csr; 691 692 csr = L64854_GCSR(sc); 693 694 DPRINTF(LDB_PP, ("%s: addr 0x%x, csr %b\n", __func__, 695 bus_read_4(sc->sc_res, L64854_REG_ADDR), csr, PDMACSR_BITS)); 696 697 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 698 resid = bus_read_4(sc->sc_res, L64854_REG_CNT); 699 device_printf(sc->sc_dev, "error: resid %d csr=%b\n", resid, 700 csr, PDMACSR_BITS); 701 csr &= ~P_EN_DMA; /* Stop DMA */ 702 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 703 csr |= P_INVALIDATE|P_SLAVE_ERR; 704 L64854_SCSR(sc, csr); 705 return (-1); 706 } 707 708 ret = (csr & P_INT_PEND) != 0; 709 710 if (sc->sc_active != 0) { 711 DMA_DRAIN(sc, 0); 712 resid = bus_read_4(sc->sc_res, L64854_REG_CNT); 713 } 714 715 /* DMA has stopped */ 716 csr &= ~D_EN_DMA; 717 L64854_SCSR(sc, csr); 718 sc->sc_active = 0; 719 720 trans = sc->sc_dmasize - resid; 721 if (trans < 0) /* transfered < 0? */ 722 trans = sc->sc_dmasize; 723 *sc->sc_dmalen -= trans; 724 *sc->sc_dmaaddr += trans; 725 726 if (sc->sc_dmasize != 0) { 727 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 728 (csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD : 729 BUS_DMASYNC_POSTWRITE); 730 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 731 } 732 733 return (ret != 0); 734} 735