1139825Simp/*- 286231Stmm * Copyright (c) 1999 Matthew R. Green 386231Stmm * All rights reserved. 486231Stmm * 586231Stmm * Redistribution and use in source and binary forms, with or without 686231Stmm * modification, are permitted provided that the following conditions 786231Stmm * are met: 886231Stmm * 1. Redistributions of source code must retain the above copyright 986231Stmm * notice, this list of conditions and the following disclaimer. 1086231Stmm * 2. Redistributions in binary form must reproduce the above copyright 1186231Stmm * notice, this list of conditions and the following disclaimer in the 1286231Stmm * documentation and/or other materials provided with the distribution. 1386231Stmm * 3. The name of the author may not be used to endorse or promote products 1486231Stmm * derived from this software without specific prior written permission. 1586231Stmm * 1686231Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1786231Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1886231Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1986231Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2086231Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 2186231Stmm * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2286231Stmm * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2386231Stmm * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2486231Stmm * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2586231Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2686231Stmm * SUCH DAMAGE. 27219567Smarius */ 28219567Smarius 29219567Smarius/*- 30219567Smarius * Copyright (c) 1998, 1999 Eduardo E. Horvath 31219567Smarius * All rights reserved. 3286231Stmm * 33219567Smarius * Redistribution and use in source and binary forms, with or without 34219567Smarius * modification, are permitted provided that the following conditions 35219567Smarius * are met: 36219567Smarius * 1. Redistributions of source code must retain the above copyright 37219567Smarius * notice, this list of conditions and the following disclaimer. 38219567Smarius * 2. Redistributions in binary form must reproduce the above copyright 39219567Smarius * notice, this list of conditions and the following disclaimer in the 40219567Smarius * documentation and/or other materials provided with the distribution. 41219567Smarius * 3. The name of the author may not be used to endorse or promote products 42219567Smarius * derived from this software without specific prior written permission. 4386231Stmm * 44219567Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45219567Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46219567Smarius * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47219567Smarius * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48219567Smarius * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49219567Smarius * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50219567Smarius * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51219567Smarius * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52219567Smarius * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53219567Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54219567Smarius * SUCH DAMAGE. 55219567Smarius * 56219567Smarius * from: NetBSD: psychoreg.h,v 1.14 2008/05/30 02:29:37 mrg Exp 57219567Smarius * 5886231Stmm * $FreeBSD$ 5986231Stmm */ 6086231Stmm 6186231Stmm#ifndef _SPARC64_PCI_PSYCHOREG_H_ 6286231Stmm#define _SPARC64_PCI_PSYCHOREG_H_ 6386231Stmm 6486231Stmm/* 6586231Stmm * Sun4u PCI definitions. Here's where we deal w/the machine 66152696Smarius * dependencies of Psycho and the PCI controller on the UltraIIi. 6786231Stmm * 6886231Stmm * All PCI registers are bit-swapped, however they are not byte-swapped. 6986231Stmm * This means that they must be accessed using little-endian access modes, 7086231Stmm * either map the pages little-endian or use little-endian ASIs. 7186231Stmm * 7286231Stmm * PSYCHO implements two PCI buses, A and B. 7386231Stmm */ 7486231Stmm 75152696Smarius#define PSYCHO_NINTR 6 76152696Smarius#define PSYCHO_NRANGE 4 77152696Smarius 7890617Stmm/* 79152696Smarius * Psycho register offsets 8090617Stmm * 8190617Stmm * NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000 8290617Stmm * respectively. 8390617Stmm */ 8490617Stmm#define PSR_UPA_PORTID 0x0000 /* UPA port ID register */ 8590617Stmm#define PSR_UPA_CONFIG 0x0008 /* UPA config register */ 8690617Stmm#define PSR_CS 0x0010 /* PSYCHO control/status register */ 8790617Stmm#define PSR_ECCC 0x0020 /* ECC control register */ 8890617Stmm#define PSR_UE_AFS 0x0030 /* Uncorrectable Error AFSR */ 8990617Stmm#define PSR_UE_AFA 0x0038 /* Uncorrectable Error AFAR */ 9090617Stmm#define PSR_CE_AFS 0x0040 /* Correctable Error AFSR */ 9190617Stmm#define PSR_CE_AFA 0x0048 /* Correctable Error AFAR */ 9290617Stmm#define PSR_PM_CTL 0x0100 /* Performance monitor control reg */ 9390617Stmm#define PSR_PM_COUNT 0x0108 /* Performance monitor counter reg */ 94152696Smarius#define PSR_IOMMU 0x0200 /* IOMMU registers */ 9590617Stmm#define PSR_PCIA0_INT_MAP 0x0c00 /* PCI bus a slot 0 irq map reg */ 9690617Stmm#define PSR_PCIA1_INT_MAP 0x0c08 /* PCI bus a slot 1 irq map reg */ 9790617Stmm#define PSR_PCIA2_INT_MAP 0x0c10 /* PCI bus a slot 2 irq map reg (IIi) */ 9890617Stmm#define PSR_PCIA3_INT_MAP 0x0c18 /* PCI bus a slot 3 irq map reg (IIi) */ 9990617Stmm#define PSR_PCIB0_INT_MAP 0x0c20 /* PCI bus b slot 0 irq map reg */ 10090617Stmm#define PSR_PCIB1_INT_MAP 0x0c28 /* PCI bus b slot 1 irq map reg */ 10190617Stmm#define PSR_PCIB2_INT_MAP 0x0c30 /* PCI bus b slot 2 irq map reg */ 10290617Stmm#define PSR_PCIB3_INT_MAP 0x0c38 /* PCI bus b slot 3 irq map reg */ 10390617Stmm#define PSR_SCSI_INT_MAP 0x1000 /* SCSI interrupt map reg */ 10490617Stmm#define PSR_ETHER_INT_MAP 0x1008 /* ethernet interrupt map reg */ 10590617Stmm#define PSR_BPP_INT_MAP 0x1010 /* parallel interrupt map reg */ 10690617Stmm#define PSR_AUDIOR_INT_MAP 0x1018 /* audio record interrupt map reg */ 10790617Stmm#define PSR_AUDIOP_INT_MAP 0x1020 /* audio playback interrupt map reg */ 10890617Stmm#define PSR_POWER_INT_MAP 0x1028 /* power fail interrupt map reg */ 10990617Stmm#define PSR_SKBDMS_INT_MAP 0x1030 /* serial/kbd/mouse interrupt map reg */ 11090617Stmm#define PSR_FD_INT_MAP 0x1038 /* floppy interrupt map reg */ 11190617Stmm#define PSR_SPARE_INT_MAP 0x1040 /* spare interrupt map reg */ 11290617Stmm#define PSR_KBD_INT_MAP 0x1048 /* kbd [unused] interrupt map reg */ 11390617Stmm#define PSR_MOUSE_INT_MAP 0x1050 /* mouse [unused] interrupt map reg */ 11490617Stmm#define PSR_SERIAL_INT_MAP 0x1058 /* second serial interrupt map reg */ 11590617Stmm#define PSR_TIMER0_INT_MAP 0x1060 /* timer 0 interrupt map reg */ 11690617Stmm#define PSR_TIMER1_INT_MAP 0x1068 /* timer 1 interrupt map reg */ 11790617Stmm#define PSR_UE_INT_MAP 0x1070 /* UE interrupt map reg */ 11890617Stmm#define PSR_CE_INT_MAP 0x1078 /* CE interrupt map reg */ 11990617Stmm#define PSR_PCIAERR_INT_MAP 0x1080 /* PCI bus a error interrupt map reg */ 12090617Stmm#define PSR_PCIBERR_INT_MAP 0x1088 /* PCI bus b error interrupt map reg */ 12190617Stmm#define PSR_PWRMGT_INT_MAP 0x1090 /* power mgmt wake interrupt map reg */ 12290617Stmm#define PSR_FFB0_INT_MAP 0x1098 /* FFB0 graphics interrupt map reg */ 12390617Stmm#define PSR_FFB1_INT_MAP 0x10a0 /* FFB1 graphics interrupt map reg */ 12490617Stmm/* Note: clear interrupt 0 registers are not really used */ 12590617Stmm#define PSR_PCIA0_INT_CLR 0x1400 /* PCI a slot 0 clear int regs 0..3 */ 12690617Stmm#define PSR_PCIA1_INT_CLR 0x1420 /* PCI a slot 1 clear int regs 0..3 */ 127107471Stmm#define PSR_PCIA2_INT_CLR 0x1440 /* PCI a slot 2 clear int regs 0..3 */ 128107471Stmm#define PSR_PCIA3_INT_CLR 0x1460 /* PCI a slot 3 clear int regs 0..3 */ 12990617Stmm#define PSR_PCIB0_INT_CLR 0x1480 /* PCI b slot 0 clear int regs 0..3 */ 13090617Stmm#define PSR_PCIB1_INT_CLR 0x14a0 /* PCI b slot 1 clear int regs 0..3 */ 13190617Stmm#define PSR_PCIB2_INT_CLR 0x14c0 /* PCI b slot 2 clear int regs 0..3 */ 13290617Stmm#define PSR_PCIB3_INT_CLR 0x14d0 /* PCI b slot 3 clear int regs 0..3 */ 13390617Stmm#define PSR_SCSI_INT_CLR 0x1800 /* SCSI clear int reg */ 13490617Stmm#define PSR_ETHER_INT_CLR 0x1808 /* ethernet clear int reg */ 13590617Stmm#define PSR_BPP_INT_CLR 0x1810 /* parallel clear int reg */ 13690617Stmm#define PSR_AUDIOR_INT_CLR 0x1818 /* audio record clear int reg */ 13790617Stmm#define PSR_AUDIOP_INT_CLR 0x1820 /* audio playback clear int reg */ 13890617Stmm#define PSR_POWER_INT_CLR 0x1828 /* power fail clear int reg */ 13990617Stmm#define PSR_SKBDMS_INT_CLR 0x1830 /* serial/kbd/mouse clear int reg */ 14090617Stmm#define PSR_FD_INT_CLR 0x1838 /* floppy clear int reg */ 14190617Stmm#define PSR_SPARE_INT_CLR 0x1840 /* spare clear int reg */ 14290617Stmm#define PSR_KBD_INT_CLR 0x1848 /* kbd [unused] clear int reg */ 14390617Stmm#define PSR_MOUSE_INT_CLR 0x1850 /* mouse [unused] clear int reg */ 14490617Stmm#define PSR_SERIAL_INT_CLR 0x1858 /* second serial clear int reg */ 14590617Stmm#define PSR_TIMER0_INT_CLR 0x1860 /* timer 0 clear int reg */ 14690617Stmm#define PSR_TIMER1_INT_CLR 0x1868 /* timer 1 clear int reg */ 14790617Stmm#define PSR_UE_INT_CLR 0x1870 /* UE clear int reg */ 14890617Stmm#define PSR_CE_INT_CLR 0x1878 /* CE clear int reg */ 14990617Stmm#define PSR_PCIAERR_INT_CLR 0x1880 /* PCI bus a error clear int reg */ 15090617Stmm#define PSR_PCIBERR_INT_CLR 0x1888 /* PCI bus b error clear int reg */ 15190617Stmm#define PSR_PWRMGT_INT_CLR 0x1890 /* power mgmt wake clr interrupt reg */ 15290617Stmm#define PSR_INTR_RETRY_TIM 0x1a00 /* interrupt retry timer */ 15390617Stmm#define PSR_TC0 0x1c00 /* timer/counter 0 */ 15490617Stmm#define PSR_TC1 0x1c10 /* timer/counter 1 */ 15590617Stmm#define PSR_DMA_WRITE_SYNC 0x1c20 /* PCI DMA write sync register (IIi) */ 156152696Smarius#define PSR_PCICTL0 0x2000 /* PCICTL registers for 1st Psycho */ 157152696Smarius#define PSR_PCICTL1 0x4000 /* PCICTL registers for 2nd Psycho */ 15890617Stmm#define PSR_DMA_SCB_DIAG0 0xa000 /* DMA scoreboard diag reg 0 */ 15990617Stmm#define PSR_DMA_SCB_DIAG1 0xa008 /* DMA scoreboard diag reg 1 */ 16090617Stmm#define PSR_IOMMU_SVADIAG 0xa400 /* IOMMU virtual addr diag reg */ 16190617Stmm#define PSR_IOMMU_TLB_CMP_DIAG 0xa408 /* IOMMU TLB tag compare diag reg */ 16290617Stmm#define PSR_IOMMU_QUEUE_DIAG 0xa500 /* IOMMU LRU queue diag regs 0..15 */ 16390617Stmm#define PSR_IOMMU_TLB_TAG_DIAG 0xa580 /* TLB tag diag regs 0..15 */ 16490617Stmm#define PSR_IOMMU_TLB_DATA_DIAG 0xa600 /* TLB data RAM diag regs 0..15 */ 16590617Stmm#define PSR_PCI_INT_DIAG 0xa800 /* PCI int state diag reg */ 16690617Stmm#define PSR_OBIO_INT_DIAG 0xa808 /* OBIO and misc int state diag reg */ 16790617Stmm#define PSR_STRBUF_DIAG 0xb000 /* Streaming buffer diag regs */ 16890617Stmm/* 16990617Stmm * Here is the rest of the map, which we're not specifying: 17090617Stmm * 17190617Stmm * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 17290617Stmm * 1fe.0100.0000 - 1fe.0100.00ff PCI B configuration header 17390617Stmm * 1fe.0101.0000 - 1fe.0101.00ff PCI A configuration header 17490617Stmm * 1fe.0200.0000 - 1fe.0200.ffff PCI A I/O space 17590617Stmm * 1fe.0201.0000 - 1fe.0201.ffff PCI B I/O space 17690617Stmm * 1ff.0000.0000 - 1ff.7fff.ffff PCI A memory space 17790617Stmm * 1ff.8000.0000 - 1ff.ffff.ffff PCI B memory space 17890617Stmm * 17990617Stmm * NB: config and I/O space can use 1-4 byte accesses, not 8 byte 18090617Stmm * accesses. Memory space can use any sized accesses. 18190617Stmm * 18290617Stmm * Note that the SUNW,sabre/SUNW,simba combinations found on the 18390617Stmm * Ultra5 and Ultra10 machines uses slightly differrent addresses 18490617Stmm * than the above. This is mostly due to the fact that the APB is 18590617Stmm * a multi-function PCI device with two PCI bridges, and the U2P is 18690617Stmm * two separate PCI bridges. It uses the same PCI configuration 18790617Stmm * space, though the configuration header for each PCI bus is 18890617Stmm * located differently due to the SUNW,simba PCI busses being 189152696Smarius * function 0 and function 1 of the APB, whereas the Psycho's are 19090617Stmm * each their own PCI device. The I/O and memory spaces are each 19190617Stmm * split into 8 equally sized areas (8x2MB blocks for I/O space, 19290617Stmm * and 8x512MB blocks for memory space). These are allocated in to 19390617Stmm * either PCI A or PCI B, or neither in the APB's `I/O Address Map 19490617Stmm * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf) 195152696Smarius * registers of each Simba. We must ensure that both of the 19690617Stmm * following are correct (the prom should do this for us): 19790617Stmm * 19890617Stmm * (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0 19990617Stmm * 20090617Stmm * (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0 20190617Stmm * 20290617Stmm * 1fe.0100.0000 - 1fe.01ff.ffff PCI configuration space 20390617Stmm * 1fe.0100.0800 - 1fe.0100.08ff PCI B configuration header 20490617Stmm * 1fe.0100.0900 - 1fe.0100.09ff PCI A configuration header 20590617Stmm * 1fe.0200.0000 - 1fe.02ff.ffff PCI I/O space (divided) 20690617Stmm * 1ff.0000.0000 - 1ff.ffff.ffff PCI memory space (divided) 20790617Stmm */ 20886231Stmm 20990617Stmm/* 21090617Stmm * PSR_CS defines: 21190617Stmm * 21290617Stmm * 63 59 55 50 45 4 3 2 1 0 21390617Stmm * +------+------+------+------+--//---+--------+-------+-----+------+ 21490617Stmm * | IMPL | VERS | MID | IGN | xxx | APCKEN | APERR | IAP | MODE | 21590617Stmm * +------+------+------+------+--//---+--------+-------+-----+------+ 21690617Stmm * 21790617Stmm */ 21886231Stmm#define PSYCHO_GCSR_IMPL(csr) ((u_int)(((csr) >> 60) & 0xf)) 21986231Stmm#define PSYCHO_GCSR_VERS(csr) ((u_int)(((csr) >> 56) & 0xf)) 22086231Stmm#define PSYCHO_GCSR_MID(csr) ((u_int)(((csr) >> 51) & 0x1f)) 22186231Stmm#define PSYCHO_GCSR_IGN(csr) ((u_int)(((csr) >> 46) & 0x1f)) 22286231Stmm#define PSYCHO_CSR_APCKEN 8 /* UPA addr parity check enable */ 22386231Stmm#define PSYCHO_CSR_APERR 4 /* UPA addr parity error */ 22486231Stmm#define PSYCHO_CSR_IAP 2 /* invert UPA address parity */ 22586231Stmm#define PSYCHO_CSR_MODE 1 /* UPA/PCI handshake */ 22686231Stmm 227152696Smarius/* Offsets into the PSR_PCICTL* register block */ 22890617Stmm#define PCR_CS 0x0000 /* PCI control/status register */ 22990617Stmm#define PCR_AFS 0x0010 /* PCI AFSR register */ 23090617Stmm#define PCR_AFA 0x0018 /* PCI AFAR register */ 23190617Stmm#define PCR_DIAG 0x0020 /* PCI diagnostic register */ 23290617Stmm#define PCR_TAS 0x0028 /* PCI target address space reg (IIi) */ 23390617Stmm#define PCR_STRBUF 0x0800 /* IOMMU streaming buffer registers. */ 23486231Stmm 235172066Smarius/* INO defines */ 236172066Smarius#define PSYCHO_MAX_INO 0x3f 237172066Smarius 238152696Smarius/* Device space defines */ 23986231Stmm#define PSYCHO_CONF_SIZE 0x1000000 24086231Stmm#define PSYCHO_CONF_BUS_SHIFT 16 24186231Stmm#define PSYCHO_CONF_DEV_SHIFT 11 24286231Stmm#define PSYCHO_CONF_FUNC_SHIFT 8 24386231Stmm#define PSYCHO_CONF_REG_SHIFT 0 24486231Stmm#define PSYCHO_IO_SIZE 0x1000000 24586231Stmm#define PSYCHO_MEM_SIZE 0x100000000 24686231Stmm 24786231Stmm#define PSYCHO_CONF_OFF(bus, slot, func, reg) \ 24886231Stmm (((bus) << PSYCHO_CONF_BUS_SHIFT) | \ 24986231Stmm ((slot) << PSYCHO_CONF_DEV_SHIFT) | \ 25086231Stmm ((func) << PSYCHO_CONF_FUNC_SHIFT) | \ 25186231Stmm ((reg) << PSYCHO_CONF_REG_SHIFT)) 25286231Stmm 25386231Stmm/* what the bits mean! */ 25486231Stmm 255153052Smarius/* 256153052Smarius * PCI [a|b] control/status register 257153052Smarius * Note that the Hummingbird/Sabre only has one set of PCI control/status 258153052Smarius * registers. 259153052Smarius */ 260165886Smarius#define PCICTL_SBHERR 0x0000000800000000 /* strm. byte hole error; W1C */ 26186231Stmm#define PCICTL_SERR 0x0000000400000000 /* SERR asserted; W1C */ 262165886Smarius#define PCICTL_PCISPEED 0x0000000200000000 /* 0:half 1:full bus speed */ 26386231Stmm#define PCICTL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */ 264165886Smarius#define PCICTL_SBHINTEN 0x0000000000000400 /* strm. byte hole int. en. */ 265165886Smarius#define PCICTL_WAKEUPEN 0x0000000000000200 /* power mgmt. wakeup enable */ 26686231Stmm#define PCICTL_ERRINTEN 0x0000000000000100 /* PCI error interrupt enable */ 267165886Smarius#define PCICTL_ARB_4 0x000000000000000f /* DVMA arb. 4 PCI slots mask */ 268165886Smarius#define PCICTL_ARB_6 0x000000000000003f /* DVMA arb. 6 PCI slots mask */ 269165886Smarius/* The following are Hummingbird/Sabre only. */ 270165886Smarius#define PCICTL_MRLM 0x0000001000000000 /* Memory Read Line/Multiple */ 271165886Smarius#define PCICTL_CPU_PRIO 0x0000000000100000 /* CPU extra arb. prio. en. */ 272165886Smarius#define PCICTL_ARB_PRIO 0x00000000000f0000 /* PCI extra arb. prio. en. */ 273165886Smarius#define PCICTL_RTRYWAIT 0x0000000000000080 /* 0:wait 1:retry DMA write */ 27486231Stmm 275165886Smarius/* Uncorrectable error asynchronous fault status register */ 276152696Smarius#define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction */ 277152696Smarius#define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error */ 278152696Smarius#define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error */ 279152696Smarius#define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write */ 280152696Smarius#define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read */ 281152696Smarius#define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access */ 282152696Smarius#define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write */ 283152696Smarius#define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read */ 284152696Smarius#define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access */ 28593053Stmm 286165886Smarius/* Correctable error asynchronous fault status register */ 287152696Smarius#define CEAFSR_BLK (1UL << 23) /* Error caused by block transaction */ 288152696Smarius#define CEAFSR_S_DWR (1UL << 58) /* Sec. error caused by DVMA write */ 289152696Smarius#define CEAFSR_S_DRD (1UL << 59) /* Sec. error caused by DVMA read */ 290152696Smarius#define CEAFSR_S_PIO (1UL << 60) /* Sec. error caused by PIO access */ 291152696Smarius#define CEAFSR_P_DWR (1UL << 61) /* Pri. error caused by DVMA write */ 292152696Smarius#define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read */ 293152696Smarius#define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access */ 294119737Stmm 295165886Smarius/* PCI asynchronous fault status register */ 296165886Smarius#define PCIAFSR_P_MA (1UL << 63) /* Pri. master abort */ 297165886Smarius#define PCIAFSR_P_TA (1UL << 62) /* Pri. target abort */ 298165886Smarius#define PCIAFSR_P_RTRY (1UL << 61) /* Pri. excessive retries */ 299165886Smarius#define PCIAFSR_P_RERR (1UL << 60) /* Pri. parity error */ 300165886Smarius#define PCIAFSR_S_MA (1UL << 59) /* Sec. master abort */ 301165886Smarius#define PCIAFSR_S_TA (1UL << 58) /* Sec. target abort */ 302165886Smarius#define PCIAFSR_S_RTRY (1UL << 57) /* Sec. excessive retries */ 303165886Smarius#define PCIAFSR_S_RERR (1UL << 56) /* Sec. parity error */ 304165886Smarius#define PCIAFSR_BMASK (0xffffUL << 32)/* Bytemask of failed pri. transfer */ 305165886Smarius#define PCIAFSR_BLK (1UL << 31) /* failed pri. transfer was block r/w */ 306165886Smarius#define PCIAFSR_MID (0x3eUL << 25) /* UPA MID causing error transaction */ 307165886Smarius 308165886Smarius/* PCI diagnostic register */ 309165886Smarius#define DIAG_RTRY_DIS 0x0000000000000040 /* dis. retry limit */ 310165886Smarius#define DIAG_ISYNC_DIS 0x0000000000000020 /* dis. DMA write / int sync */ 311165886Smarius#define DIAG_DWSYNC_DIS 0x0000000000000010 /* dis. DMA write / PIO sync */ 312165886Smarius 313152696Smarius/* Definitions for the target address space register */ 314108800Stmm#define PCITAS_ADDR_SHIFT 29 315108800Stmm 316152696Smarius/* Definitions for the Psycho configuration space */ 317152696Smarius#define PCS_DEVICE 0 /* Device number of Psycho CS entry */ 318152696Smarius#define PCS_FUNC 0 /* Function number of Psycho CS entry */ 31998148Stmm 32098148Stmm/* Non-Standard registers in the configration space */ 32198148Stmm#define PCSR_SECBUS 0x40 /* Secondary bus number register */ 32298148Stmm#define PCSR_SUBBUS 0x41 /* Subordinate bus number register */ 32398148Stmm 324171730Smarius/* Width of the physical addresses the IOMMU translates to */ 325171730Smarius#define PSYCHO_IOMMU_BITS 41 326171730Smarius#define SABRE_IOMMU_BITS 34 327171730Smarius 328152696Smarius#endif /* !_SPARC64_PCI_PSYCHOREG_H_ */ 329