pmap.c revision 254667
1176771Sraj/*- 2192532Sraj * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3176771Sraj * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4176771Sraj * All rights reserved. 5176771Sraj * 6176771Sraj * Redistribution and use in source and binary forms, with or without 7176771Sraj * modification, are permitted provided that the following conditions 8176771Sraj * are met: 9176771Sraj * 1. Redistributions of source code must retain the above copyright 10176771Sraj * notice, this list of conditions and the following disclaimer. 11176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176771Sraj * notice, this list of conditions and the following disclaimer in the 13176771Sraj * documentation and/or other materials provided with the distribution. 14176771Sraj * 15176771Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18176771Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20176771Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21176771Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22176771Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23176771Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24176771Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176771Sraj * 26176771Sraj * Some hw specific parts of this pmap were derived or influenced 27176771Sraj * by NetBSD's ibm4xx pmap module. More generic code is shared with 28176771Sraj * a few other pmap modules from the FreeBSD tree. 29176771Sraj */ 30176771Sraj 31176771Sraj /* 32176771Sraj * VM layout notes: 33176771Sraj * 34176771Sraj * Kernel and user threads run within one common virtual address space 35176771Sraj * defined by AS=0. 36176771Sraj * 37176771Sraj * Virtual address space layout: 38176771Sraj * ----------------------------- 39187151Sraj * 0x0000_0000 - 0xafff_ffff : user process 40187151Sraj * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41187151Sraj * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42190701Smarcel * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43187151Sraj * 0xc100_0000 - 0xfeef_ffff : KVA 44187151Sraj * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45187151Sraj * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46187151Sraj * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47187151Sraj * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48187151Sraj * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49176771Sraj */ 50176771Sraj 51176771Sraj#include <sys/cdefs.h> 52176771Sraj__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 254667 2013-08-22 18:12:24Z kib $"); 53176771Sraj 54176771Sraj#include <sys/param.h> 55176771Sraj#include <sys/malloc.h> 56187149Sraj#include <sys/ktr.h> 57176771Sraj#include <sys/proc.h> 58176771Sraj#include <sys/user.h> 59176771Sraj#include <sys/queue.h> 60176771Sraj#include <sys/systm.h> 61176771Sraj#include <sys/kernel.h> 62224611Smarcel#include <sys/linker.h> 63176771Sraj#include <sys/msgbuf.h> 64176771Sraj#include <sys/lock.h> 65176771Sraj#include <sys/mutex.h> 66242535Salc#include <sys/rwlock.h> 67222813Sattilio#include <sys/sched.h> 68192532Sraj#include <sys/smp.h> 69176771Sraj#include <sys/vmmeter.h> 70176771Sraj 71176771Sraj#include <vm/vm.h> 72176771Sraj#include <vm/vm_page.h> 73176771Sraj#include <vm/vm_kern.h> 74176771Sraj#include <vm/vm_pageout.h> 75176771Sraj#include <vm/vm_extern.h> 76176771Sraj#include <vm/vm_object.h> 77176771Sraj#include <vm/vm_param.h> 78176771Sraj#include <vm/vm_map.h> 79176771Sraj#include <vm/vm_pager.h> 80176771Sraj#include <vm/uma.h> 81176771Sraj 82176771Sraj#include <machine/cpu.h> 83176771Sraj#include <machine/pcb.h> 84192067Snwhitehorn#include <machine/platform.h> 85176771Sraj 86176771Sraj#include <machine/tlb.h> 87176771Sraj#include <machine/spr.h> 88176771Sraj#include <machine/md_var.h> 89176771Sraj#include <machine/mmuvar.h> 90176771Sraj#include <machine/pmap.h> 91176771Sraj#include <machine/pte.h> 92176771Sraj 93176771Sraj#include "mmu_if.h" 94176771Sraj 95176771Sraj#ifdef DEBUG 96176771Sraj#define debugf(fmt, args...) printf(fmt, ##args) 97176771Sraj#else 98176771Sraj#define debugf(fmt, args...) 99176771Sraj#endif 100176771Sraj 101176771Sraj#define TODO panic("%s: not implemented", __func__); 102176771Sraj 103176771Srajextern struct mtx sched_lock; 104176771Sraj 105190701Smarcelextern int dumpsys_minidump; 106190701Smarcel 107190701Smarcelextern unsigned char _etext[]; 108190701Smarcelextern unsigned char _end[]; 109190701Smarcel 110224611Smarcelextern uint32_t *bootinfo; 111224611Smarcel 112224611Smarcel#ifdef SMP 113242526Smarcelextern uint32_t bp_ntlb1s; 114224611Smarcel#endif 115224611Smarcel 116242526Smarcelvm_paddr_t ccsrbar_pa; 117224611Smarcelvm_paddr_t kernload; 118190701Smarcelvm_offset_t kernstart; 119190701Smarcelvm_size_t kernsize; 120176771Sraj 121190701Smarcel/* Message buffer and tables. */ 122190701Smarcelstatic vm_offset_t data_start; 123190701Smarcelstatic vm_size_t data_end; 124190701Smarcel 125192067Snwhitehorn/* Phys/avail memory regions. */ 126192067Snwhitehornstatic struct mem_region *availmem_regions; 127192067Snwhitehornstatic int availmem_regions_sz; 128192067Snwhitehornstatic struct mem_region *physmem_regions; 129192067Snwhitehornstatic int physmem_regions_sz; 130176771Sraj 131176771Sraj/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 132176771Srajstatic vm_offset_t zero_page_va; 133176771Srajstatic struct mtx zero_page_mutex; 134176771Sraj 135187149Srajstatic struct mtx tlbivax_mutex; 136187149Sraj 137176771Sraj/* 138176771Sraj * Reserved KVA space for mmu_booke_zero_page_idle. This is used 139176771Sraj * by idle thred only, no lock required. 140176771Sraj */ 141176771Srajstatic vm_offset_t zero_page_idle_va; 142176771Sraj 143176771Sraj/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 144176771Srajstatic vm_offset_t copy_page_src_va; 145176771Srajstatic vm_offset_t copy_page_dst_va; 146176771Srajstatic struct mtx copy_page_mutex; 147176771Sraj 148176771Sraj/**************************************************************************/ 149176771Sraj/* PMAP */ 150176771Sraj/**************************************************************************/ 151176771Sraj 152176771Srajstatic void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 153176771Sraj vm_prot_t, boolean_t); 154176771Sraj 155176771Srajunsigned int kptbl_min; /* Index of the first kernel ptbl. */ 156176771Srajunsigned int kernel_ptbls; /* Number of KVA ptbls. */ 157176771Sraj 158176771Sraj/* 159176771Sraj * If user pmap is processed with mmu_booke_remove and the resident count 160176771Sraj * drops to 0, there are no more pages to remove, so we need not continue. 161176771Sraj */ 162176771Sraj#define PMAP_REMOVE_DONE(pmap) \ 163176771Sraj ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 164176771Sraj 165187149Srajextern void tid_flush(tlbtid_t); 166176771Sraj 167176771Sraj/**************************************************************************/ 168176771Sraj/* TLB and TID handling */ 169176771Sraj/**************************************************************************/ 170176771Sraj 171176771Sraj/* Translation ID busy table */ 172187149Srajstatic volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 173176771Sraj 174176771Sraj/* 175187149Sraj * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 176187149Sraj * core revisions and should be read from h/w registers during early config. 177176771Sraj */ 178187149Srajuint32_t tlb0_entries; 179187149Srajuint32_t tlb0_ways; 180187149Srajuint32_t tlb0_entries_per_way; 181176771Sraj 182187149Sraj#define TLB0_ENTRIES (tlb0_entries) 183187149Sraj#define TLB0_WAYS (tlb0_ways) 184187149Sraj#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185176771Sraj 186187149Sraj#define TLB1_ENTRIES 16 187176771Sraj 188176771Sraj/* In-ram copy of the TLB1 */ 189187149Srajstatic tlb_entry_t tlb1[TLB1_ENTRIES]; 190176771Sraj 191176771Sraj/* Next free entry in the TLB1 */ 192176771Srajstatic unsigned int tlb1_idx; 193176771Sraj 194176771Srajstatic tlbtid_t tid_alloc(struct pmap *); 195176771Sraj 196187149Srajstatic void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 197176771Sraj 198187149Srajstatic int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 199176771Srajstatic void tlb1_write_entry(unsigned int); 200176771Srajstatic int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 201224611Smarcelstatic vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 202176771Sraj 203176771Srajstatic vm_size_t tsize2size(unsigned int); 204176771Srajstatic unsigned int size2tsize(vm_size_t); 205176771Srajstatic unsigned int ilog2(unsigned int); 206176771Sraj 207176771Srajstatic void set_mas4_defaults(void); 208176771Sraj 209187149Srajstatic inline void tlb0_flush_entry(vm_offset_t); 210176771Srajstatic inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 211176771Sraj 212176771Sraj/**************************************************************************/ 213176771Sraj/* Page table management */ 214176771Sraj/**************************************************************************/ 215176771Sraj 216242535Salcstatic struct rwlock_padalign pvh_global_lock; 217242535Salc 218176771Sraj/* Data for the pv entry allocation mechanism */ 219176771Srajstatic uma_zone_t pvzone; 220176771Srajstatic int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 221176771Sraj 222176771Sraj#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 223176771Sraj 224176771Sraj#ifndef PMAP_SHPGPERPROC 225176771Sraj#define PMAP_SHPGPERPROC 200 226176771Sraj#endif 227176771Sraj 228176771Srajstatic void ptbl_init(void); 229176771Srajstatic struct ptbl_buf *ptbl_buf_alloc(void); 230176771Srajstatic void ptbl_buf_free(struct ptbl_buf *); 231176771Srajstatic void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 232176771Sraj 233187149Srajstatic pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 234176771Srajstatic void ptbl_free(mmu_t, pmap_t, unsigned int); 235176771Srajstatic void ptbl_hold(mmu_t, pmap_t, unsigned int); 236176771Srajstatic int ptbl_unhold(mmu_t, pmap_t, unsigned int); 237176771Sraj 238176771Srajstatic vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 239176771Srajstatic pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 240187149Srajstatic void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 241187149Srajstatic int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 242176771Sraj 243187149Srajstatic pv_entry_t pv_alloc(void); 244176771Srajstatic void pv_free(pv_entry_t); 245176771Srajstatic void pv_insert(pmap_t, vm_offset_t, vm_page_t); 246176771Srajstatic void pv_remove(pmap_t, vm_offset_t, vm_page_t); 247176771Sraj 248176771Sraj/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 249176771Sraj#define PTBL_BUFS (128 * 16) 250176771Sraj 251176771Srajstruct ptbl_buf { 252176771Sraj TAILQ_ENTRY(ptbl_buf) link; /* list link */ 253176771Sraj vm_offset_t kva; /* va of mapping */ 254176771Sraj}; 255176771Sraj 256176771Sraj/* ptbl free list and a lock used for access synchronization. */ 257176771Srajstatic TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 258176771Srajstatic struct mtx ptbl_buf_freelist_lock; 259176771Sraj 260176771Sraj/* Base address of kva space allocated fot ptbl bufs. */ 261176771Srajstatic vm_offset_t ptbl_buf_pool_vabase; 262176771Sraj 263176771Sraj/* Pointer to ptbl_buf structures. */ 264176771Srajstatic struct ptbl_buf *ptbl_bufs; 265176771Sraj 266192532Srajvoid pmap_bootstrap_ap(volatile uint32_t *); 267192532Sraj 268176771Sraj/* 269176771Sraj * Kernel MMU interface 270176771Sraj */ 271176771Srajstatic void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 272176771Srajstatic void mmu_booke_clear_modify(mmu_t, vm_page_t); 273176771Srajstatic void mmu_booke_clear_reference(mmu_t, vm_page_t); 274194101Srajstatic void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 275194101Sraj vm_size_t, vm_offset_t); 276176771Srajstatic void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 277248280Skibstatic void mmu_booke_copy_pages(mmu_t, vm_page_t *, 278248280Skib vm_offset_t, vm_page_t *, vm_offset_t, int); 279176771Srajstatic void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 280176771Sraj vm_prot_t, boolean_t); 281176771Srajstatic void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 282176771Sraj vm_page_t, vm_prot_t); 283176771Srajstatic void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 284176771Sraj vm_prot_t); 285176771Srajstatic vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 286176771Srajstatic vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 287176771Sraj vm_prot_t); 288176771Srajstatic void mmu_booke_init(mmu_t); 289176771Srajstatic boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 290176771Srajstatic boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 291207155Salcstatic boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 292238357Salcstatic int mmu_booke_ts_referenced(mmu_t, vm_page_t); 293235936Srajstatic vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, 294176771Sraj int); 295208504Salcstatic int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 296208504Salc vm_paddr_t *); 297176771Srajstatic void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 298176771Sraj vm_object_t, vm_pindex_t, vm_size_t); 299176771Srajstatic boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 300176771Srajstatic void mmu_booke_page_init(mmu_t, vm_page_t); 301176771Srajstatic int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 302176771Srajstatic void mmu_booke_pinit(mmu_t, pmap_t); 303176771Srajstatic void mmu_booke_pinit0(mmu_t, pmap_t); 304176771Srajstatic void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 305176771Sraj vm_prot_t); 306176771Srajstatic void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 307176771Srajstatic void mmu_booke_qremove(mmu_t, vm_offset_t, int); 308176771Srajstatic void mmu_booke_release(mmu_t, pmap_t); 309176771Srajstatic void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 310176771Srajstatic void mmu_booke_remove_all(mmu_t, vm_page_t); 311176771Srajstatic void mmu_booke_remove_write(mmu_t, vm_page_t); 312176771Srajstatic void mmu_booke_zero_page(mmu_t, vm_page_t); 313176771Srajstatic void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 314176771Srajstatic void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 315176771Srajstatic void mmu_booke_activate(mmu_t, struct thread *); 316176771Srajstatic void mmu_booke_deactivate(mmu_t, struct thread *); 317176771Srajstatic void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 318235936Srajstatic void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t); 319176771Srajstatic void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 320235936Srajstatic vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t); 321235936Srajstatic void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t); 322176771Srajstatic void mmu_booke_kremove(mmu_t, vm_offset_t); 323235936Srajstatic boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t); 324198341Smarcelstatic void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 325198341Smarcel vm_size_t); 326190701Smarcelstatic vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 327190701Smarcel vm_size_t, vm_size_t *); 328190701Smarcelstatic void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 329190701Smarcel vm_size_t, vm_offset_t); 330190701Smarcelstatic struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 331176771Sraj 332176771Srajstatic mmu_method_t mmu_booke_methods[] = { 333176771Sraj /* pmap dispatcher interface */ 334176771Sraj MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 335176771Sraj MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 336176771Sraj MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 337176771Sraj MMUMETHOD(mmu_copy, mmu_booke_copy), 338176771Sraj MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 339248280Skib MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages), 340176771Sraj MMUMETHOD(mmu_enter, mmu_booke_enter), 341176771Sraj MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 342176771Sraj MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 343176771Sraj MMUMETHOD(mmu_extract, mmu_booke_extract), 344176771Sraj MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 345176771Sraj MMUMETHOD(mmu_init, mmu_booke_init), 346176771Sraj MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 347176771Sraj MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 348207155Salc MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 349176771Sraj MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 350176771Sraj MMUMETHOD(mmu_map, mmu_booke_map), 351176771Sraj MMUMETHOD(mmu_mincore, mmu_booke_mincore), 352176771Sraj MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 353176771Sraj MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 354176771Sraj MMUMETHOD(mmu_page_init, mmu_booke_page_init), 355176771Sraj MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 356176771Sraj MMUMETHOD(mmu_pinit, mmu_booke_pinit), 357176771Sraj MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 358176771Sraj MMUMETHOD(mmu_protect, mmu_booke_protect), 359176771Sraj MMUMETHOD(mmu_qenter, mmu_booke_qenter), 360176771Sraj MMUMETHOD(mmu_qremove, mmu_booke_qremove), 361176771Sraj MMUMETHOD(mmu_release, mmu_booke_release), 362176771Sraj MMUMETHOD(mmu_remove, mmu_booke_remove), 363176771Sraj MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 364176771Sraj MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 365198341Smarcel MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 366176771Sraj MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 367176771Sraj MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 368176771Sraj MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 369176771Sraj MMUMETHOD(mmu_activate, mmu_booke_activate), 370176771Sraj MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 371176771Sraj 372176771Sraj /* Internal interfaces */ 373176771Sraj MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374176771Sraj MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375176771Sraj MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376176771Sraj MMUMETHOD(mmu_kenter, mmu_booke_kenter), 377176771Sraj MMUMETHOD(mmu_kextract, mmu_booke_kextract), 378176771Sraj/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 379176771Sraj MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 380176771Sraj 381190701Smarcel /* dumpsys() support */ 382190701Smarcel MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 383190701Smarcel MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 384190701Smarcel MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 385190701Smarcel 386176771Sraj { 0, 0 } 387176771Sraj}; 388176771Sraj 389212627SgrehanMMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 390176771Sraj 391192532Srajstatic inline void 392192532Srajtlb_miss_lock(void) 393192532Sraj{ 394192532Sraj#ifdef SMP 395192532Sraj struct pcpu *pc; 396192532Sraj 397192532Sraj if (!smp_started) 398192532Sraj return; 399192532Sraj 400222531Snwhitehorn STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 401192532Sraj if (pc != pcpup) { 402192532Sraj 403192532Sraj CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 404192532Sraj "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 405192532Sraj 406192532Sraj KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 407192532Sraj ("tlb_miss_lock: tried to lock self")); 408192532Sraj 409192532Sraj tlb_lock(pc->pc_booke_tlb_lock); 410192532Sraj 411192532Sraj CTR1(KTR_PMAP, "%s: locked", __func__); 412192532Sraj } 413192532Sraj } 414192532Sraj#endif 415192532Sraj} 416192532Sraj 417192532Srajstatic inline void 418192532Srajtlb_miss_unlock(void) 419192532Sraj{ 420192532Sraj#ifdef SMP 421192532Sraj struct pcpu *pc; 422192532Sraj 423192532Sraj if (!smp_started) 424192532Sraj return; 425192532Sraj 426222531Snwhitehorn STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 427192532Sraj if (pc != pcpup) { 428192532Sraj CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 429192532Sraj __func__, pc->pc_cpuid); 430192532Sraj 431192532Sraj tlb_unlock(pc->pc_booke_tlb_lock); 432192532Sraj 433192532Sraj CTR1(KTR_PMAP, "%s: unlocked", __func__); 434192532Sraj } 435192532Sraj } 436192532Sraj#endif 437192532Sraj} 438192532Sraj 439176771Sraj/* Return number of entries in TLB0. */ 440176771Srajstatic __inline void 441176771Srajtlb0_get_tlbconf(void) 442176771Sraj{ 443176771Sraj uint32_t tlb0_cfg; 444176771Sraj 445176771Sraj tlb0_cfg = mfspr(SPR_TLB0CFG); 446187149Sraj tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 447187149Sraj tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 448187149Sraj tlb0_entries_per_way = tlb0_entries / tlb0_ways; 449176771Sraj} 450176771Sraj 451176771Sraj/* Initialize pool of kva ptbl buffers. */ 452176771Srajstatic void 453176771Srajptbl_init(void) 454176771Sraj{ 455176771Sraj int i; 456176771Sraj 457187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 458187151Sraj (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 459187151Sraj CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 460187151Sraj __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 461176771Sraj 462176771Sraj mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 463176771Sraj TAILQ_INIT(&ptbl_buf_freelist); 464176771Sraj 465176771Sraj for (i = 0; i < PTBL_BUFS; i++) { 466176771Sraj ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 467176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 468176771Sraj } 469176771Sraj} 470176771Sraj 471182362Sraj/* Get a ptbl_buf from the freelist. */ 472176771Srajstatic struct ptbl_buf * 473176771Srajptbl_buf_alloc(void) 474176771Sraj{ 475176771Sraj struct ptbl_buf *buf; 476176771Sraj 477176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 478176771Sraj buf = TAILQ_FIRST(&ptbl_buf_freelist); 479176771Sraj if (buf != NULL) 480176771Sraj TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 481176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 482176771Sraj 483187151Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 484187151Sraj 485176771Sraj return (buf); 486176771Sraj} 487176771Sraj 488176771Sraj/* Return ptbl buff to free pool. */ 489176771Srajstatic void 490176771Srajptbl_buf_free(struct ptbl_buf *buf) 491176771Sraj{ 492176771Sraj 493187149Sraj CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 494176771Sraj 495176771Sraj mtx_lock(&ptbl_buf_freelist_lock); 496176771Sraj TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 497176771Sraj mtx_unlock(&ptbl_buf_freelist_lock); 498176771Sraj} 499176771Sraj 500176771Sraj/* 501187149Sraj * Search the list of allocated ptbl bufs and find on list of allocated ptbls 502176771Sraj */ 503176771Srajstatic void 504176771Srajptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 505176771Sraj{ 506176771Sraj struct ptbl_buf *pbuf; 507176771Sraj 508187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 509176771Sraj 510187149Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 511187149Sraj 512187149Sraj TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 513176771Sraj if (pbuf->kva == (vm_offset_t)ptbl) { 514176771Sraj /* Remove from pmap ptbl buf list. */ 515187149Sraj TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 516176771Sraj 517187149Sraj /* Free corresponding ptbl buf. */ 518176771Sraj ptbl_buf_free(pbuf); 519176771Sraj break; 520176771Sraj } 521176771Sraj} 522176771Sraj 523176771Sraj/* Allocate page table. */ 524187149Srajstatic pte_t * 525176771Srajptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 526176771Sraj{ 527176771Sraj vm_page_t mtbl[PTBL_PAGES]; 528176771Sraj vm_page_t m; 529176771Sraj struct ptbl_buf *pbuf; 530176771Sraj unsigned int pidx; 531187149Sraj pte_t *ptbl; 532176771Sraj int i; 533176771Sraj 534187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 535187149Sraj (pmap == kernel_pmap), pdir_idx); 536176771Sraj 537176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 538176771Sraj ("ptbl_alloc: invalid pdir_idx")); 539176771Sraj KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 540176771Sraj ("pte_alloc: valid ptbl entry exists!")); 541176771Sraj 542176771Sraj pbuf = ptbl_buf_alloc(); 543176771Sraj if (pbuf == NULL) 544176771Sraj panic("pte_alloc: couldn't alloc kernel virtual memory"); 545187149Sraj 546187149Sraj ptbl = (pte_t *)pbuf->kva; 547176771Sraj 548187149Sraj CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 549187149Sraj 550176771Sraj /* Allocate ptbl pages, this will sleep! */ 551176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 552176771Sraj pidx = (PTBL_PAGES * pdir_idx) + i; 553187149Sraj while ((m = vm_page_alloc(NULL, pidx, 554187149Sraj VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 555187149Sraj 556176771Sraj PMAP_UNLOCK(pmap); 557242535Salc rw_wunlock(&pvh_global_lock); 558176771Sraj VM_WAIT; 559242535Salc rw_wlock(&pvh_global_lock); 560176771Sraj PMAP_LOCK(pmap); 561176771Sraj } 562176771Sraj mtbl[i] = m; 563176771Sraj } 564176771Sraj 565187149Sraj /* Map allocated pages into kernel_pmap. */ 566187149Sraj mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 567176771Sraj 568176771Sraj /* Zero whole ptbl. */ 569187149Sraj bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 570176771Sraj 571176771Sraj /* Add pbuf to the pmap ptbl bufs list. */ 572187149Sraj TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 573176771Sraj 574187149Sraj return (ptbl); 575176771Sraj} 576176771Sraj 577176771Sraj/* Free ptbl pages and invalidate pdir entry. */ 578176771Srajstatic void 579176771Srajptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 580176771Sraj{ 581176771Sraj pte_t *ptbl; 582176771Sraj vm_paddr_t pa; 583176771Sraj vm_offset_t va; 584176771Sraj vm_page_t m; 585176771Sraj int i; 586176771Sraj 587187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 588187149Sraj (pmap == kernel_pmap), pdir_idx); 589176771Sraj 590176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 591176771Sraj ("ptbl_free: invalid pdir_idx")); 592176771Sraj 593176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 594176771Sraj 595187149Sraj CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 596187149Sraj 597176771Sraj KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 598176771Sraj 599187149Sraj /* 600187149Sraj * Invalidate the pdir entry as soon as possible, so that other CPUs 601187149Sraj * don't attempt to look up the page tables we are releasing. 602187149Sraj */ 603187149Sraj mtx_lock_spin(&tlbivax_mutex); 604192532Sraj tlb_miss_lock(); 605187149Sraj 606187149Sraj pmap->pm_pdir[pdir_idx] = NULL; 607187149Sraj 608192532Sraj tlb_miss_unlock(); 609187149Sraj mtx_unlock_spin(&tlbivax_mutex); 610187149Sraj 611176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 612176771Sraj va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 613176771Sraj pa = pte_vatopa(mmu, kernel_pmap, va); 614176771Sraj m = PHYS_TO_VM_PAGE(pa); 615176771Sraj vm_page_free_zero(m); 616176771Sraj atomic_subtract_int(&cnt.v_wire_count, 1); 617176771Sraj mmu_booke_kremove(mmu, va); 618176771Sraj } 619176771Sraj 620176771Sraj ptbl_free_pmap_ptbl(pmap, ptbl); 621176771Sraj} 622176771Sraj 623176771Sraj/* 624176771Sraj * Decrement ptbl pages hold count and attempt to free ptbl pages. 625176771Sraj * Called when removing pte entry from ptbl. 626176771Sraj * 627176771Sraj * Return 1 if ptbl pages were freed. 628176771Sraj */ 629176771Srajstatic int 630176771Srajptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 631176771Sraj{ 632176771Sraj pte_t *ptbl; 633176771Sraj vm_paddr_t pa; 634176771Sraj vm_page_t m; 635176771Sraj int i; 636176771Sraj 637187151Sraj CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 638187151Sraj (pmap == kernel_pmap), pdir_idx); 639176771Sraj 640176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 641176771Sraj ("ptbl_unhold: invalid pdir_idx")); 642176771Sraj KASSERT((pmap != kernel_pmap), 643176771Sraj ("ptbl_unhold: unholding kernel ptbl!")); 644176771Sraj 645176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 646176771Sraj 647176771Sraj //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 648176771Sraj KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 649176771Sraj ("ptbl_unhold: non kva ptbl")); 650176771Sraj 651176771Sraj /* decrement hold count */ 652176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 653187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 654187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 655176771Sraj m = PHYS_TO_VM_PAGE(pa); 656176771Sraj m->wire_count--; 657176771Sraj } 658176771Sraj 659176771Sraj /* 660176771Sraj * Free ptbl pages if there are no pte etries in this ptbl. 661187151Sraj * wire_count has the same value for all ptbl pages, so check the last 662187151Sraj * page. 663176771Sraj */ 664176771Sraj if (m->wire_count == 0) { 665176771Sraj ptbl_free(mmu, pmap, pdir_idx); 666176771Sraj 667176771Sraj //debugf("ptbl_unhold: e (freed ptbl)\n"); 668176771Sraj return (1); 669176771Sraj } 670176771Sraj 671176771Sraj return (0); 672176771Sraj} 673176771Sraj 674176771Sraj/* 675187151Sraj * Increment hold count for ptbl pages. This routine is used when a new pte 676187151Sraj * entry is being inserted into the ptbl. 677176771Sraj */ 678176771Srajstatic void 679176771Srajptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 680176771Sraj{ 681176771Sraj vm_paddr_t pa; 682176771Sraj pte_t *ptbl; 683176771Sraj vm_page_t m; 684176771Sraj int i; 685176771Sraj 686187151Sraj CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 687187151Sraj pdir_idx); 688176771Sraj 689176771Sraj KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 690176771Sraj ("ptbl_hold: invalid pdir_idx")); 691176771Sraj KASSERT((pmap != kernel_pmap), 692176771Sraj ("ptbl_hold: holding kernel ptbl!")); 693176771Sraj 694176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 695176771Sraj 696176771Sraj KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 697176771Sraj 698176771Sraj for (i = 0; i < PTBL_PAGES; i++) { 699187151Sraj pa = pte_vatopa(mmu, kernel_pmap, 700187151Sraj (vm_offset_t)ptbl + (i * PAGE_SIZE)); 701176771Sraj m = PHYS_TO_VM_PAGE(pa); 702176771Sraj m->wire_count++; 703176771Sraj } 704176771Sraj} 705176771Sraj 706176771Sraj/* Allocate pv_entry structure. */ 707176771Srajpv_entry_t 708176771Srajpv_alloc(void) 709176771Sraj{ 710176771Sraj pv_entry_t pv; 711176771Sraj 712176771Sraj pv_entry_count++; 713194123Salc if (pv_entry_count > pv_entry_high_water) 714194123Salc pagedaemon_wakeup(); 715176771Sraj pv = uma_zalloc(pvzone, M_NOWAIT); 716176771Sraj 717176771Sraj return (pv); 718176771Sraj} 719176771Sraj 720176771Sraj/* Free pv_entry structure. */ 721176771Srajstatic __inline void 722176771Srajpv_free(pv_entry_t pve) 723176771Sraj{ 724176771Sraj 725176771Sraj pv_entry_count--; 726176771Sraj uma_zfree(pvzone, pve); 727176771Sraj} 728176771Sraj 729176771Sraj 730176771Sraj/* Allocate and initialize pv_entry structure. */ 731176771Srajstatic void 732176771Srajpv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 733176771Sraj{ 734176771Sraj pv_entry_t pve; 735176771Sraj 736176771Sraj //int su = (pmap == kernel_pmap); 737176771Sraj //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 738176771Sraj // (u_int32_t)pmap, va, (u_int32_t)m); 739176771Sraj 740176771Sraj pve = pv_alloc(); 741176771Sraj if (pve == NULL) 742176771Sraj panic("pv_insert: no pv entries!"); 743176771Sraj 744176771Sraj pve->pv_pmap = pmap; 745176771Sraj pve->pv_va = va; 746176771Sraj 747176771Sraj /* add to pv_list */ 748176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 749242535Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 750176771Sraj 751176771Sraj TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 752176771Sraj 753176771Sraj //debugf("pv_insert: e\n"); 754176771Sraj} 755176771Sraj 756176771Sraj/* Destroy pv entry. */ 757176771Srajstatic void 758176771Srajpv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 759176771Sraj{ 760176771Sraj pv_entry_t pve; 761176771Sraj 762176771Sraj //int su = (pmap == kernel_pmap); 763176771Sraj //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 764176771Sraj 765176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 766242535Salc rw_assert(&pvh_global_lock, RA_WLOCKED); 767176771Sraj 768176771Sraj /* find pv entry */ 769176771Sraj TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 770176771Sraj if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 771176771Sraj /* remove from pv_list */ 772176771Sraj TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 773176771Sraj if (TAILQ_EMPTY(&m->md.pv_list)) 774225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 775176771Sraj 776176771Sraj /* free pv entry struct */ 777176771Sraj pv_free(pve); 778176771Sraj break; 779176771Sraj } 780176771Sraj } 781176771Sraj 782176771Sraj //debugf("pv_remove: e\n"); 783176771Sraj} 784176771Sraj 785176771Sraj/* 786176771Sraj * Clean pte entry, try to free page table page if requested. 787176771Sraj * 788176771Sraj * Return 1 if ptbl pages were freed, otherwise return 0. 789176771Sraj */ 790176771Srajstatic int 791187151Srajpte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 792176771Sraj{ 793176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 794176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 795176771Sraj vm_page_t m; 796176771Sraj pte_t *ptbl; 797176771Sraj pte_t *pte; 798176771Sraj 799176771Sraj //int su = (pmap == kernel_pmap); 800176771Sraj //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 801176771Sraj // su, (u_int32_t)pmap, va, flags); 802176771Sraj 803176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 804176771Sraj KASSERT(ptbl, ("pte_remove: null ptbl")); 805176771Sraj 806176771Sraj pte = &ptbl[ptbl_idx]; 807176771Sraj 808176771Sraj if (pte == NULL || !PTE_ISVALID(pte)) 809176771Sraj return (0); 810176771Sraj 811176771Sraj if (PTE_ISWIRED(pte)) 812176771Sraj pmap->pm_stats.wired_count--; 813176771Sraj 814191445Smarcel /* Handle managed entry. */ 815191445Smarcel if (PTE_ISMANAGED(pte)) { 816191445Smarcel /* Get vm_page_t for mapped pte. */ 817191445Smarcel m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 818176771Sraj 819191445Smarcel if (PTE_ISMODIFIED(pte)) 820191445Smarcel vm_page_dirty(m); 821176771Sraj 822191445Smarcel if (PTE_ISREFERENCED(pte)) 823225418Skib vm_page_aflag_set(m, PGA_REFERENCED); 824176771Sraj 825191445Smarcel pv_remove(pmap, va, m); 826176771Sraj } 827176771Sraj 828187149Sraj mtx_lock_spin(&tlbivax_mutex); 829192532Sraj tlb_miss_lock(); 830187149Sraj 831187149Sraj tlb0_flush_entry(va); 832176771Sraj pte->flags = 0; 833176771Sraj pte->rpn = 0; 834187149Sraj 835192532Sraj tlb_miss_unlock(); 836187149Sraj mtx_unlock_spin(&tlbivax_mutex); 837187149Sraj 838176771Sraj pmap->pm_stats.resident_count--; 839176771Sraj 840176771Sraj if (flags & PTBL_UNHOLD) { 841176771Sraj //debugf("pte_remove: e (unhold)\n"); 842176771Sraj return (ptbl_unhold(mmu, pmap, pdir_idx)); 843176771Sraj } 844176771Sraj 845176771Sraj //debugf("pte_remove: e\n"); 846176771Sraj return (0); 847176771Sraj} 848176771Sraj 849176771Sraj/* 850176771Sraj * Insert PTE for a given page and virtual address. 851176771Sraj */ 852187149Srajstatic void 853187149Srajpte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 854176771Sraj{ 855176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 856176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 857187149Sraj pte_t *ptbl, *pte; 858176771Sraj 859187149Sraj CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 860187149Sraj pmap == kernel_pmap, pmap, va); 861176771Sraj 862176771Sraj /* Get the page table pointer. */ 863176771Sraj ptbl = pmap->pm_pdir[pdir_idx]; 864176771Sraj 865187149Sraj if (ptbl == NULL) { 866187149Sraj /* Allocate page table pages. */ 867187149Sraj ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 868187149Sraj } else { 869176771Sraj /* 870176771Sraj * Check if there is valid mapping for requested 871176771Sraj * va, if there is, remove it. 872176771Sraj */ 873176771Sraj pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 874176771Sraj if (PTE_ISVALID(pte)) { 875176771Sraj pte_remove(mmu, pmap, va, PTBL_HOLD); 876176771Sraj } else { 877176771Sraj /* 878176771Sraj * pte is not used, increment hold count 879176771Sraj * for ptbl pages. 880176771Sraj */ 881176771Sraj if (pmap != kernel_pmap) 882176771Sraj ptbl_hold(mmu, pmap, pdir_idx); 883176771Sraj } 884176771Sraj } 885176771Sraj 886176771Sraj /* 887187149Sraj * Insert pv_entry into pv_list for mapped page if part of managed 888187149Sraj * memory. 889176771Sraj */ 890224746Skib if ((m->oflags & VPO_UNMANAGED) == 0) { 891224746Skib flags |= PTE_MANAGED; 892176771Sraj 893224746Skib /* Create and insert pv entry. */ 894224746Skib pv_insert(pmap, va, m); 895176771Sraj } 896176771Sraj 897176771Sraj pmap->pm_stats.resident_count++; 898187149Sraj 899187149Sraj mtx_lock_spin(&tlbivax_mutex); 900192532Sraj tlb_miss_lock(); 901187149Sraj 902187149Sraj tlb0_flush_entry(va); 903187149Sraj if (pmap->pm_pdir[pdir_idx] == NULL) { 904187149Sraj /* 905187149Sraj * If we just allocated a new page table, hook it in 906187149Sraj * the pdir. 907187149Sraj */ 908187149Sraj pmap->pm_pdir[pdir_idx] = ptbl; 909187149Sraj } 910187149Sraj pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 911176771Sraj pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 912176771Sraj pte->flags |= (PTE_VALID | flags); 913176771Sraj 914192532Sraj tlb_miss_unlock(); 915187149Sraj mtx_unlock_spin(&tlbivax_mutex); 916176771Sraj} 917176771Sraj 918176771Sraj/* Return the pa for the given pmap/va. */ 919176771Srajstatic vm_paddr_t 920176771Srajpte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 921176771Sraj{ 922176771Sraj vm_paddr_t pa = 0; 923176771Sraj pte_t *pte; 924176771Sraj 925176771Sraj pte = pte_find(mmu, pmap, va); 926176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 927176771Sraj pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 928176771Sraj return (pa); 929176771Sraj} 930176771Sraj 931176771Sraj/* Get a pointer to a PTE in a page table. */ 932176771Srajstatic pte_t * 933176771Srajpte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 934176771Sraj{ 935176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 936176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 937176771Sraj 938176771Sraj KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 939176771Sraj 940176771Sraj if (pmap->pm_pdir[pdir_idx]) 941176771Sraj return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 942176771Sraj 943176771Sraj return (NULL); 944176771Sraj} 945176771Sraj 946176771Sraj/**************************************************************************/ 947176771Sraj/* PMAP related */ 948176771Sraj/**************************************************************************/ 949176771Sraj 950176771Sraj/* 951222400Smarcel * This is called during booke_init, before the system is really initialized. 952176771Sraj */ 953176771Srajstatic void 954190701Smarcelmmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 955176771Sraj{ 956176771Sraj vm_offset_t phys_kernelend; 957176771Sraj struct mem_region *mp, *mp1; 958176771Sraj int cnt, i, j; 959176771Sraj u_int s, e, sz; 960176771Sraj u_int phys_avail_count; 961182198Sraj vm_size_t physsz, hwphyssz, kstack0_sz; 962193489Sraj vm_offset_t kernel_pdir, kstack0, va; 963182198Sraj vm_paddr_t kstack0_phys; 964194784Sjeff void *dpcpu; 965193489Sraj pte_t *pte; 966176771Sraj 967176771Sraj debugf("mmu_booke_bootstrap: entered\n"); 968176771Sraj 969187149Sraj /* Initialize invalidation mutex */ 970187149Sraj mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 971187149Sraj 972187149Sraj /* Read TLB0 size and associativity. */ 973187149Sraj tlb0_get_tlbconf(); 974187149Sraj 975224611Smarcel /* 976224611Smarcel * Align kernel start and end address (kernel image). 977224611Smarcel * Note that kernel end does not necessarily relate to kernsize. 978224611Smarcel * kernsize is the size of the kernel that is actually mapped. 979235932Smarcel * Also note that "start - 1" is deliberate. With SMP, the 980235932Smarcel * entry point is exactly a page from the actual load address. 981235932Smarcel * As such, trunc_page() has no effect and we're off by a page. 982235932Smarcel * Since we always have the ELF header between the load address 983235932Smarcel * and the entry point, we can safely subtract 1 to compensate. 984224611Smarcel */ 985235932Smarcel kernstart = trunc_page(start - 1); 986190701Smarcel data_start = round_page(kernelend); 987190701Smarcel data_end = data_start; 988190701Smarcel 989224611Smarcel /* 990224611Smarcel * Addresses of preloaded modules (like file systems) use 991224611Smarcel * physical addresses. Make sure we relocate those into 992224611Smarcel * virtual addresses. 993224611Smarcel */ 994224611Smarcel preload_addr_relocate = kernstart - kernload; 995224611Smarcel 996224611Smarcel /* Allocate the dynamic per-cpu area. */ 997224611Smarcel dpcpu = (void *)data_end; 998224611Smarcel data_end += DPCPU_SIZE; 999224611Smarcel 1000176771Sraj /* Allocate space for the message buffer. */ 1001190701Smarcel msgbufp = (struct msgbuf *)data_end; 1002217688Spluknet data_end += msgbufsize; 1003187149Sraj debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1004190701Smarcel data_end); 1005176771Sraj 1006190701Smarcel data_end = round_page(data_end); 1007176771Sraj 1008176771Sraj /* Allocate space for ptbl_bufs. */ 1009190701Smarcel ptbl_bufs = (struct ptbl_buf *)data_end; 1010190701Smarcel data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1011187149Sraj debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1012190701Smarcel data_end); 1013176771Sraj 1014190701Smarcel data_end = round_page(data_end); 1015176771Sraj 1016176771Sraj /* Allocate PTE tables for kernel KVA. */ 1017190701Smarcel kernel_pdir = data_end; 1018176771Sraj kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1019176771Sraj PDIR_SIZE - 1) / PDIR_SIZE; 1020190701Smarcel data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1021176771Sraj debugf(" kernel ptbls: %d\n", kernel_ptbls); 1022190701Smarcel debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1023176771Sraj 1024190701Smarcel debugf(" data_end: 0x%08x\n", data_end); 1025224611Smarcel if (data_end - kernstart > kernsize) { 1026224611Smarcel kernsize += tlb1_mapin_region(kernstart + kernsize, 1027224611Smarcel kernload + kernsize, (data_end - kernstart) - kernsize); 1028224611Smarcel } 1029224611Smarcel data_end = kernstart + kernsize; 1030190701Smarcel debugf(" updated data_end: 0x%08x\n", data_end); 1031187149Sraj 1032182362Sraj /* 1033182362Sraj * Clear the structures - note we can only do it safely after the 1034187149Sraj * possible additional TLB1 translations are in place (above) so that 1035190701Smarcel * all range up to the currently calculated 'data_end' is covered. 1036182362Sraj */ 1037224611Smarcel dpcpu_init(dpcpu, 0); 1038182362Sraj memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1039182362Sraj memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1040182362Sraj 1041176771Sraj /*******************************************************/ 1042176771Sraj /* Set the start and end of kva. */ 1043176771Sraj /*******************************************************/ 1044190701Smarcel virtual_avail = round_page(data_end); 1045176771Sraj virtual_end = VM_MAX_KERNEL_ADDRESS; 1046176771Sraj 1047176771Sraj /* Allocate KVA space for page zero/copy operations. */ 1048176771Sraj zero_page_va = virtual_avail; 1049176771Sraj virtual_avail += PAGE_SIZE; 1050176771Sraj zero_page_idle_va = virtual_avail; 1051176771Sraj virtual_avail += PAGE_SIZE; 1052176771Sraj copy_page_src_va = virtual_avail; 1053176771Sraj virtual_avail += PAGE_SIZE; 1054176771Sraj copy_page_dst_va = virtual_avail; 1055176771Sraj virtual_avail += PAGE_SIZE; 1056187149Sraj debugf("zero_page_va = 0x%08x\n", zero_page_va); 1057187149Sraj debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1058187149Sraj debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1059187149Sraj debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1060176771Sraj 1061176771Sraj /* Initialize page zero/copy mutexes. */ 1062176771Sraj mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1063176771Sraj mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1064176771Sraj 1065176771Sraj /* Allocate KVA space for ptbl bufs. */ 1066176771Sraj ptbl_buf_pool_vabase = virtual_avail; 1067176771Sraj virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1068187149Sraj debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1069187149Sraj ptbl_buf_pool_vabase, virtual_avail); 1070176771Sraj 1071176771Sraj /* Calculate corresponding physical addresses for the kernel region. */ 1072190701Smarcel phys_kernelend = kernload + kernsize; 1073176771Sraj debugf("kernel image and allocated data:\n"); 1074176771Sraj debugf(" kernload = 0x%08x\n", kernload); 1075190701Smarcel debugf(" kernstart = 0x%08x\n", kernstart); 1076190701Smarcel debugf(" kernsize = 0x%08x\n", kernsize); 1077176771Sraj 1078176771Sraj if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1079176771Sraj panic("mmu_booke_bootstrap: phys_avail too small"); 1080176771Sraj 1081176771Sraj /* 1082187151Sraj * Remove kernel physical address range from avail regions list. Page 1083187151Sraj * align all regions. Non-page aligned memory isn't very interesting 1084187151Sraj * to us. Also, sort the entries for ascending addresses. 1085176771Sraj */ 1086192067Snwhitehorn 1087192067Snwhitehorn /* Retrieve phys/avail mem regions */ 1088192067Snwhitehorn mem_regions(&physmem_regions, &physmem_regions_sz, 1089192067Snwhitehorn &availmem_regions, &availmem_regions_sz); 1090176771Sraj sz = 0; 1091176771Sraj cnt = availmem_regions_sz; 1092176771Sraj debugf("processing avail regions:\n"); 1093176771Sraj for (mp = availmem_regions; mp->mr_size; mp++) { 1094176771Sraj s = mp->mr_start; 1095176771Sraj e = mp->mr_start + mp->mr_size; 1096176771Sraj debugf(" %08x-%08x -> ", s, e); 1097176771Sraj /* Check whether this region holds all of the kernel. */ 1098176771Sraj if (s < kernload && e > phys_kernelend) { 1099176771Sraj availmem_regions[cnt].mr_start = phys_kernelend; 1100176771Sraj availmem_regions[cnt++].mr_size = e - phys_kernelend; 1101176771Sraj e = kernload; 1102176771Sraj } 1103176771Sraj /* Look whether this regions starts within the kernel. */ 1104176771Sraj if (s >= kernload && s < phys_kernelend) { 1105176771Sraj if (e <= phys_kernelend) 1106176771Sraj goto empty; 1107176771Sraj s = phys_kernelend; 1108176771Sraj } 1109176771Sraj /* Now look whether this region ends within the kernel. */ 1110176771Sraj if (e > kernload && e <= phys_kernelend) { 1111176771Sraj if (s >= kernload) 1112176771Sraj goto empty; 1113176771Sraj e = kernload; 1114176771Sraj } 1115176771Sraj /* Now page align the start and size of the region. */ 1116176771Sraj s = round_page(s); 1117176771Sraj e = trunc_page(e); 1118176771Sraj if (e < s) 1119176771Sraj e = s; 1120176771Sraj sz = e - s; 1121176771Sraj debugf("%08x-%08x = %x\n", s, e, sz); 1122176771Sraj 1123176771Sraj /* Check whether some memory is left here. */ 1124176771Sraj if (sz == 0) { 1125176771Sraj empty: 1126176771Sraj memmove(mp, mp + 1, 1127176771Sraj (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1128176771Sraj cnt--; 1129176771Sraj mp--; 1130176771Sraj continue; 1131176771Sraj } 1132176771Sraj 1133176771Sraj /* Do an insertion sort. */ 1134176771Sraj for (mp1 = availmem_regions; mp1 < mp; mp1++) 1135176771Sraj if (s < mp1->mr_start) 1136176771Sraj break; 1137176771Sraj if (mp1 < mp) { 1138176771Sraj memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1139176771Sraj mp1->mr_start = s; 1140176771Sraj mp1->mr_size = sz; 1141176771Sraj } else { 1142176771Sraj mp->mr_start = s; 1143176771Sraj mp->mr_size = sz; 1144176771Sraj } 1145176771Sraj } 1146176771Sraj availmem_regions_sz = cnt; 1147176771Sraj 1148176771Sraj /*******************************************************/ 1149182198Sraj /* Steal physical memory for kernel stack from the end */ 1150182198Sraj /* of the first avail region */ 1151182198Sraj /*******************************************************/ 1152182198Sraj kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1153182198Sraj kstack0_phys = availmem_regions[0].mr_start + 1154182198Sraj availmem_regions[0].mr_size; 1155182198Sraj kstack0_phys -= kstack0_sz; 1156182198Sraj availmem_regions[0].mr_size -= kstack0_sz; 1157182198Sraj 1158182198Sraj /*******************************************************/ 1159176771Sraj /* Fill in phys_avail table, based on availmem_regions */ 1160176771Sraj /*******************************************************/ 1161176771Sraj phys_avail_count = 0; 1162176771Sraj physsz = 0; 1163176771Sraj hwphyssz = 0; 1164176771Sraj TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1165176771Sraj 1166176771Sraj debugf("fill in phys_avail:\n"); 1167176771Sraj for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1168176771Sraj 1169176771Sraj debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1170176771Sraj availmem_regions[i].mr_start, 1171187151Sraj availmem_regions[i].mr_start + 1172187151Sraj availmem_regions[i].mr_size, 1173176771Sraj availmem_regions[i].mr_size); 1174176771Sraj 1175182362Sraj if (hwphyssz != 0 && 1176182362Sraj (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1177176771Sraj debugf(" hw.physmem adjust\n"); 1178176771Sraj if (physsz < hwphyssz) { 1179176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1180182362Sraj phys_avail[j + 1] = 1181182362Sraj availmem_regions[i].mr_start + 1182176771Sraj hwphyssz - physsz; 1183176771Sraj physsz = hwphyssz; 1184176771Sraj phys_avail_count++; 1185176771Sraj } 1186176771Sraj break; 1187176771Sraj } 1188176771Sraj 1189176771Sraj phys_avail[j] = availmem_regions[i].mr_start; 1190176771Sraj phys_avail[j + 1] = availmem_regions[i].mr_start + 1191176771Sraj availmem_regions[i].mr_size; 1192176771Sraj phys_avail_count++; 1193176771Sraj physsz += availmem_regions[i].mr_size; 1194176771Sraj } 1195176771Sraj physmem = btoc(physsz); 1196176771Sraj 1197176771Sraj /* Calculate the last available physical address. */ 1198176771Sraj for (i = 0; phys_avail[i + 2] != 0; i += 2) 1199176771Sraj ; 1200176771Sraj Maxmem = powerpc_btop(phys_avail[i + 1]); 1201176771Sraj 1202176771Sraj debugf("Maxmem = 0x%08lx\n", Maxmem); 1203176771Sraj debugf("phys_avail_count = %d\n", phys_avail_count); 1204187151Sraj debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1205187151Sraj physmem); 1206176771Sraj 1207176771Sraj /*******************************************************/ 1208176771Sraj /* Initialize (statically allocated) kernel pmap. */ 1209176771Sraj /*******************************************************/ 1210176771Sraj PMAP_LOCK_INIT(kernel_pmap); 1211176771Sraj kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1212176771Sraj 1213187149Sraj debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1214187149Sraj debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1215176771Sraj debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1216176771Sraj kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1217176771Sraj 1218176771Sraj /* Initialize kernel pdir */ 1219176771Sraj for (i = 0; i < kernel_ptbls; i++) 1220176771Sraj kernel_pmap->pm_pdir[kptbl_min + i] = 1221176771Sraj (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1222176771Sraj 1223187149Sraj for (i = 0; i < MAXCPU; i++) { 1224187149Sraj kernel_pmap->pm_tid[i] = TID_KERNEL; 1225187149Sraj 1226187149Sraj /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1227187149Sraj tidbusy[i][0] = kernel_pmap; 1228187149Sraj } 1229193489Sraj 1230193489Sraj /* 1231193489Sraj * Fill in PTEs covering kernel code and data. They are not required 1232193489Sraj * for address translation, as this area is covered by static TLB1 1233193489Sraj * entries, but for pte_vatopa() to work correctly with kernel area 1234193489Sraj * addresses. 1235193489Sraj */ 1236235932Smarcel for (va = kernstart; va < data_end; va += PAGE_SIZE) { 1237193489Sraj pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1238235932Smarcel pte->rpn = kernload + (va - kernstart); 1239193489Sraj pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1240193489Sraj PTE_VALID; 1241193489Sraj } 1242187149Sraj /* Mark kernel_pmap active on all CPUs */ 1243222813Sattilio CPU_FILL(&kernel_pmap->pm_active); 1244176771Sraj 1245242535Salc /* 1246242535Salc * Initialize the global pv list lock. 1247242535Salc */ 1248242535Salc rw_init(&pvh_global_lock, "pmap pv global"); 1249242535Salc 1250176771Sraj /*******************************************************/ 1251176771Sraj /* Final setup */ 1252176771Sraj /*******************************************************/ 1253187149Sraj 1254182198Sraj /* Enter kstack0 into kernel map, provide guard page */ 1255182198Sraj kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1256182198Sraj thread0.td_kstack = kstack0; 1257182198Sraj thread0.td_kstack_pages = KSTACK_PAGES; 1258182198Sraj 1259182198Sraj debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1260182198Sraj debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1261182198Sraj kstack0_phys, kstack0_phys + kstack0_sz); 1262182198Sraj debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1263182198Sraj 1264182198Sraj virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1265182198Sraj for (i = 0; i < KSTACK_PAGES; i++) { 1266182198Sraj mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1267182198Sraj kstack0 += PAGE_SIZE; 1268182198Sraj kstack0_phys += PAGE_SIZE; 1269182198Sraj } 1270187149Sraj 1271187149Sraj debugf("virtual_avail = %08x\n", virtual_avail); 1272187149Sraj debugf("virtual_end = %08x\n", virtual_end); 1273182198Sraj 1274176771Sraj debugf("mmu_booke_bootstrap: exit\n"); 1275176771Sraj} 1276176771Sraj 1277192532Srajvoid 1278192532Srajpmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1279192532Sraj{ 1280192532Sraj int i; 1281192532Sraj 1282192532Sraj /* 1283192532Sraj * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1284192532Sraj * have the snapshot of its contents in the s/w tlb1[] table, so use 1285192532Sraj * these values directly to (re)program AP's TLB1 hardware. 1286192532Sraj */ 1287242526Smarcel for (i = bp_ntlb1s; i < tlb1_idx; i++) { 1288192532Sraj /* Skip invalid entries */ 1289192532Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 1290192532Sraj continue; 1291192532Sraj 1292192532Sraj tlb1_write_entry(i); 1293192532Sraj } 1294192532Sraj 1295192532Sraj set_mas4_defaults(); 1296192532Sraj} 1297192532Sraj 1298176771Sraj/* 1299176771Sraj * Get the physical page address for the given pmap/virtual address. 1300176771Sraj */ 1301176771Srajstatic vm_paddr_t 1302176771Srajmmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1303176771Sraj{ 1304176771Sraj vm_paddr_t pa; 1305176771Sraj 1306176771Sraj PMAP_LOCK(pmap); 1307176771Sraj pa = pte_vatopa(mmu, pmap, va); 1308176771Sraj PMAP_UNLOCK(pmap); 1309176771Sraj 1310176771Sraj return (pa); 1311176771Sraj} 1312176771Sraj 1313176771Sraj/* 1314176771Sraj * Extract the physical page address associated with the given 1315176771Sraj * kernel virtual address. 1316176771Sraj */ 1317176771Srajstatic vm_paddr_t 1318176771Srajmmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1319176771Sraj{ 1320176771Sraj 1321176771Sraj return (pte_vatopa(mmu, kernel_pmap, va)); 1322176771Sraj} 1323176771Sraj 1324176771Sraj/* 1325176771Sraj * Initialize the pmap module. 1326176771Sraj * Called by vm_init, to initialize any structures that the pmap 1327176771Sraj * system needs to map virtual memory. 1328176771Sraj */ 1329176771Srajstatic void 1330176771Srajmmu_booke_init(mmu_t mmu) 1331176771Sraj{ 1332176771Sraj int shpgperproc = PMAP_SHPGPERPROC; 1333176771Sraj 1334176771Sraj /* 1335176771Sraj * Initialize the address space (zone) for the pv entries. Set a 1336176771Sraj * high water mark so that the system can recover from excessive 1337176771Sraj * numbers of pv entries. 1338176771Sraj */ 1339176771Sraj pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1340176771Sraj NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1341176771Sraj 1342176771Sraj TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1343176771Sraj pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1344176771Sraj 1345176771Sraj TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1346176771Sraj pv_entry_high_water = 9 * (pv_entry_max / 10); 1347176771Sraj 1348247360Sattilio uma_zone_reserve_kva(pvzone, pv_entry_max); 1349176771Sraj 1350176771Sraj /* Pre-fill pvzone with initial number of pv entries. */ 1351176771Sraj uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1352176771Sraj 1353176771Sraj /* Initialize ptbl allocation. */ 1354176771Sraj ptbl_init(); 1355176771Sraj} 1356176771Sraj 1357176771Sraj/* 1358176771Sraj * Map a list of wired pages into kernel virtual address space. This is 1359176771Sraj * intended for temporary mappings which do not need page modification or 1360176771Sraj * references recorded. Existing mappings in the region are overwritten. 1361176771Sraj */ 1362176771Srajstatic void 1363176771Srajmmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1364176771Sraj{ 1365176771Sraj vm_offset_t va; 1366176771Sraj 1367176771Sraj va = sva; 1368176771Sraj while (count-- > 0) { 1369176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1370176771Sraj va += PAGE_SIZE; 1371176771Sraj m++; 1372176771Sraj } 1373176771Sraj} 1374176771Sraj 1375176771Sraj/* 1376176771Sraj * Remove page mappings from kernel virtual address space. Intended for 1377176771Sraj * temporary mappings entered by mmu_booke_qenter. 1378176771Sraj */ 1379176771Srajstatic void 1380176771Srajmmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1381176771Sraj{ 1382176771Sraj vm_offset_t va; 1383176771Sraj 1384176771Sraj va = sva; 1385176771Sraj while (count-- > 0) { 1386176771Sraj mmu_booke_kremove(mmu, va); 1387176771Sraj va += PAGE_SIZE; 1388176771Sraj } 1389176771Sraj} 1390176771Sraj 1391176771Sraj/* 1392176771Sraj * Map a wired page into kernel virtual address space. 1393176771Sraj */ 1394176771Srajstatic void 1395235936Srajmmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa) 1396176771Sraj{ 1397176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1398176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1399187151Sraj uint32_t flags; 1400176771Sraj pte_t *pte; 1401176771Sraj 1402187151Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1403187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1404176771Sraj 1405235932Smarcel flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID; 1406176771Sraj 1407176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1408176771Sraj 1409187149Sraj mtx_lock_spin(&tlbivax_mutex); 1410192532Sraj tlb_miss_lock(); 1411187149Sraj 1412176771Sraj if (PTE_ISVALID(pte)) { 1413187149Sraj 1414187149Sraj CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1415176771Sraj 1416176771Sraj /* Flush entry from TLB0 */ 1417187149Sraj tlb0_flush_entry(va); 1418176771Sraj } 1419176771Sraj 1420176771Sraj pte->rpn = pa & ~PTE_PA_MASK; 1421176771Sraj pte->flags = flags; 1422176771Sraj 1423176771Sraj //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1424176771Sraj // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1425176771Sraj // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1426176771Sraj 1427176771Sraj /* Flush the real memory from the instruction cache. */ 1428176771Sraj if ((flags & (PTE_I | PTE_G)) == 0) { 1429176771Sraj __syncicache((void *)va, PAGE_SIZE); 1430176771Sraj } 1431176771Sraj 1432192532Sraj tlb_miss_unlock(); 1433187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1434176771Sraj} 1435176771Sraj 1436176771Sraj/* 1437176771Sraj * Remove a page from kernel page table. 1438176771Sraj */ 1439176771Srajstatic void 1440176771Srajmmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1441176771Sraj{ 1442176771Sraj unsigned int pdir_idx = PDIR_IDX(va); 1443176771Sraj unsigned int ptbl_idx = PTBL_IDX(va); 1444176771Sraj pte_t *pte; 1445176771Sraj 1446187149Sraj// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1447176771Sraj 1448187149Sraj KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1449187149Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1450176771Sraj ("mmu_booke_kremove: invalid va")); 1451176771Sraj 1452176771Sraj pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1453176771Sraj 1454176771Sraj if (!PTE_ISVALID(pte)) { 1455187149Sraj 1456187149Sraj CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1457187149Sraj 1458176771Sraj return; 1459176771Sraj } 1460176771Sraj 1461187149Sraj mtx_lock_spin(&tlbivax_mutex); 1462192532Sraj tlb_miss_lock(); 1463176771Sraj 1464187149Sraj /* Invalidate entry in TLB0, update PTE. */ 1465187149Sraj tlb0_flush_entry(va); 1466176771Sraj pte->flags = 0; 1467176771Sraj pte->rpn = 0; 1468176771Sraj 1469192532Sraj tlb_miss_unlock(); 1470187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1471176771Sraj} 1472176771Sraj 1473176771Sraj/* 1474176771Sraj * Initialize pmap associated with process 0. 1475176771Sraj */ 1476176771Srajstatic void 1477176771Srajmmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1478176771Sraj{ 1479187151Sraj 1480254667Skib PMAP_LOCK_INIT(pmap); 1481176771Sraj mmu_booke_pinit(mmu, pmap); 1482176771Sraj PCPU_SET(curpmap, pmap); 1483176771Sraj} 1484176771Sraj 1485176771Sraj/* 1486176771Sraj * Initialize a preallocated and zeroed pmap structure, 1487176771Sraj * such as one in a vmspace structure. 1488176771Sraj */ 1489176771Srajstatic void 1490176771Srajmmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1491176771Sraj{ 1492187149Sraj int i; 1493176771Sraj 1494187149Sraj CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1495187149Sraj curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1496176771Sraj 1497187149Sraj KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1498176771Sraj 1499187149Sraj for (i = 0; i < MAXCPU; i++) 1500187149Sraj pmap->pm_tid[i] = TID_NONE; 1501222813Sattilio CPU_ZERO(&kernel_pmap->pm_active); 1502176771Sraj bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1503176771Sraj bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1504187149Sraj TAILQ_INIT(&pmap->pm_ptbl_list); 1505176771Sraj} 1506176771Sraj 1507176771Sraj/* 1508176771Sraj * Release any resources held by the given physical map. 1509176771Sraj * Called when a pmap initialized by mmu_booke_pinit is being released. 1510176771Sraj * Should only be called if the map contains no valid mappings. 1511176771Sraj */ 1512176771Srajstatic void 1513176771Srajmmu_booke_release(mmu_t mmu, pmap_t pmap) 1514176771Sraj{ 1515176771Sraj 1516187151Sraj KASSERT(pmap->pm_stats.resident_count == 0, 1517187151Sraj ("pmap_release: pmap resident count %ld != 0", 1518187151Sraj pmap->pm_stats.resident_count)); 1519176771Sraj} 1520176771Sraj 1521176771Sraj/* 1522176771Sraj * Insert the given physical page at the specified virtual address in the 1523176771Sraj * target physical map with the protection requested. If specified the page 1524176771Sraj * will be wired down. 1525176771Sraj */ 1526176771Srajstatic void 1527176771Srajmmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1528176771Sraj vm_prot_t prot, boolean_t wired) 1529176771Sraj{ 1530187151Sraj 1531242535Salc rw_wlock(&pvh_global_lock); 1532176771Sraj PMAP_LOCK(pmap); 1533176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1534242535Salc rw_wunlock(&pvh_global_lock); 1535176771Sraj PMAP_UNLOCK(pmap); 1536176771Sraj} 1537176771Sraj 1538176771Srajstatic void 1539176771Srajmmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1540176771Sraj vm_prot_t prot, boolean_t wired) 1541176771Sraj{ 1542176771Sraj pte_t *pte; 1543176771Sraj vm_paddr_t pa; 1544187151Sraj uint32_t flags; 1545176771Sraj int su, sync; 1546176771Sraj 1547176771Sraj pa = VM_PAGE_TO_PHYS(m); 1548176771Sraj su = (pmap == kernel_pmap); 1549176771Sraj sync = 0; 1550176771Sraj 1551176771Sraj //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1552176771Sraj // "pa=0x%08x prot=0x%08x wired=%d)\n", 1553176771Sraj // (u_int32_t)pmap, su, pmap->pm_tid, 1554176771Sraj // (u_int32_t)m, va, pa, prot, wired); 1555176771Sraj 1556176771Sraj if (su) { 1557187151Sraj KASSERT(((va >= virtual_avail) && 1558187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1559187151Sraj ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1560176771Sraj } else { 1561176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1562187151Sraj ("mmu_booke_enter_locked: user pmap, non user va")); 1563176771Sraj } 1564254138Sattilio if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 1565250747Salc VM_OBJECT_ASSERT_LOCKED(m->object); 1566176771Sraj 1567176771Sraj PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1568176771Sraj 1569176771Sraj /* 1570176771Sraj * If there is an existing mapping, and the physical address has not 1571176771Sraj * changed, must be protection or wiring change. 1572176771Sraj */ 1573176771Sraj if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1574176771Sraj (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1575187149Sraj 1576187149Sraj /* 1577187149Sraj * Before actually updating pte->flags we calculate and 1578187149Sraj * prepare its new value in a helper var. 1579187149Sraj */ 1580187149Sraj flags = pte->flags; 1581187149Sraj flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1582176771Sraj 1583176771Sraj /* Wiring change, just update stats. */ 1584176771Sraj if (wired) { 1585176771Sraj if (!PTE_ISWIRED(pte)) { 1586187149Sraj flags |= PTE_WIRED; 1587176771Sraj pmap->pm_stats.wired_count++; 1588176771Sraj } 1589176771Sraj } else { 1590176771Sraj if (PTE_ISWIRED(pte)) { 1591187149Sraj flags &= ~PTE_WIRED; 1592176771Sraj pmap->pm_stats.wired_count--; 1593176771Sraj } 1594176771Sraj } 1595176771Sraj 1596176771Sraj if (prot & VM_PROT_WRITE) { 1597176771Sraj /* Add write permissions. */ 1598187149Sraj flags |= PTE_SW; 1599176771Sraj if (!su) 1600187149Sraj flags |= PTE_UW; 1601192795Sraj 1602208846Salc if ((flags & PTE_MANAGED) != 0) 1603225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 1604176771Sraj } else { 1605176771Sraj /* Handle modified pages, sense modify status. */ 1606187149Sraj 1607187149Sraj /* 1608187149Sraj * The PTE_MODIFIED flag could be set by underlying 1609187149Sraj * TLB misses since we last read it (above), possibly 1610187149Sraj * other CPUs could update it so we check in the PTE 1611187149Sraj * directly rather than rely on that saved local flags 1612187149Sraj * copy. 1613187149Sraj */ 1614178626Smarcel if (PTE_ISMODIFIED(pte)) 1615178626Smarcel vm_page_dirty(m); 1616176771Sraj } 1617176771Sraj 1618176771Sraj if (prot & VM_PROT_EXECUTE) { 1619187149Sraj flags |= PTE_SX; 1620176771Sraj if (!su) 1621187149Sraj flags |= PTE_UX; 1622176771Sraj 1623187149Sraj /* 1624187149Sraj * Check existing flags for execute permissions: if we 1625187149Sraj * are turning execute permissions on, icache should 1626187149Sraj * be flushed. 1627187149Sraj */ 1628208720Salc if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1629176771Sraj sync++; 1630176771Sraj } 1631176771Sraj 1632187149Sraj flags &= ~PTE_REFERENCED; 1633187149Sraj 1634187149Sraj /* 1635187149Sraj * The new flags value is all calculated -- only now actually 1636187149Sraj * update the PTE. 1637187149Sraj */ 1638187149Sraj mtx_lock_spin(&tlbivax_mutex); 1639192532Sraj tlb_miss_lock(); 1640187149Sraj 1641187149Sraj tlb0_flush_entry(va); 1642187149Sraj pte->flags = flags; 1643187149Sraj 1644192532Sraj tlb_miss_unlock(); 1645187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1646187149Sraj 1647176771Sraj } else { 1648176771Sraj /* 1649187149Sraj * If there is an existing mapping, but it's for a different 1650176771Sraj * physical address, pte_enter() will delete the old mapping. 1651176771Sraj */ 1652176771Sraj //if ((pte != NULL) && PTE_ISVALID(pte)) 1653176771Sraj // debugf("mmu_booke_enter_locked: replace\n"); 1654176771Sraj //else 1655176771Sraj // debugf("mmu_booke_enter_locked: new\n"); 1656176771Sraj 1657176771Sraj /* Now set up the flags and install the new mapping. */ 1658176771Sraj flags = (PTE_SR | PTE_VALID); 1659187149Sraj flags |= PTE_M; 1660176771Sraj 1661176771Sraj if (!su) 1662176771Sraj flags |= PTE_UR; 1663176771Sraj 1664176771Sraj if (prot & VM_PROT_WRITE) { 1665176771Sraj flags |= PTE_SW; 1666176771Sraj if (!su) 1667176771Sraj flags |= PTE_UW; 1668192795Sraj 1669224746Skib if ((m->oflags & VPO_UNMANAGED) == 0) 1670225418Skib vm_page_aflag_set(m, PGA_WRITEABLE); 1671176771Sraj } 1672176771Sraj 1673176771Sraj if (prot & VM_PROT_EXECUTE) { 1674176771Sraj flags |= PTE_SX; 1675176771Sraj if (!su) 1676176771Sraj flags |= PTE_UX; 1677176771Sraj } 1678176771Sraj 1679176771Sraj /* If its wired update stats. */ 1680176771Sraj if (wired) { 1681176771Sraj pmap->pm_stats.wired_count++; 1682176771Sraj flags |= PTE_WIRED; 1683176771Sraj } 1684176771Sraj 1685176771Sraj pte_enter(mmu, pmap, m, va, flags); 1686176771Sraj 1687176771Sraj /* Flush the real memory from the instruction cache. */ 1688176771Sraj if (prot & VM_PROT_EXECUTE) 1689176771Sraj sync++; 1690176771Sraj } 1691176771Sraj 1692176771Sraj if (sync && (su || pmap == PCPU_GET(curpmap))) { 1693176771Sraj __syncicache((void *)va, PAGE_SIZE); 1694176771Sraj sync = 0; 1695176771Sraj } 1696176771Sraj} 1697176771Sraj 1698176771Sraj/* 1699176771Sraj * Maps a sequence of resident pages belonging to the same object. 1700176771Sraj * The sequence begins with the given page m_start. This page is 1701176771Sraj * mapped at the given virtual address start. Each subsequent page is 1702176771Sraj * mapped at a virtual address that is offset from start by the same 1703176771Sraj * amount as the page is offset from m_start within the object. The 1704176771Sraj * last page in the sequence is the page with the largest offset from 1705176771Sraj * m_start that can be mapped at a virtual address less than the given 1706176771Sraj * virtual address end. Not every virtual page between start and end 1707176771Sraj * is mapped; only those for which a resident page exists with the 1708176771Sraj * corresponding offset from m_start are mapped. 1709176771Sraj */ 1710176771Srajstatic void 1711176771Srajmmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1712176771Sraj vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1713176771Sraj{ 1714176771Sraj vm_page_t m; 1715176771Sraj vm_pindex_t diff, psize; 1716176771Sraj 1717250884Sattilio VM_OBJECT_ASSERT_LOCKED(m_start->object); 1718250884Sattilio 1719176771Sraj psize = atop(end - start); 1720176771Sraj m = m_start; 1721242535Salc rw_wlock(&pvh_global_lock); 1722176771Sraj PMAP_LOCK(pmap); 1723176771Sraj while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1724187151Sraj mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1725187151Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1726176771Sraj m = TAILQ_NEXT(m, listq); 1727176771Sraj } 1728242535Salc rw_wunlock(&pvh_global_lock); 1729176771Sraj PMAP_UNLOCK(pmap); 1730176771Sraj} 1731176771Sraj 1732176771Srajstatic void 1733176771Srajmmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1734176771Sraj vm_prot_t prot) 1735176771Sraj{ 1736176771Sraj 1737242535Salc rw_wlock(&pvh_global_lock); 1738176771Sraj PMAP_LOCK(pmap); 1739176771Sraj mmu_booke_enter_locked(mmu, pmap, va, m, 1740176771Sraj prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1741242535Salc rw_wunlock(&pvh_global_lock); 1742176771Sraj PMAP_UNLOCK(pmap); 1743176771Sraj} 1744176771Sraj 1745176771Sraj/* 1746176771Sraj * Remove the given range of addresses from the specified map. 1747176771Sraj * 1748176771Sraj * It is assumed that the start and end are properly rounded to the page size. 1749176771Sraj */ 1750176771Srajstatic void 1751176771Srajmmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1752176771Sraj{ 1753176771Sraj pte_t *pte; 1754187151Sraj uint8_t hold_flag; 1755176771Sraj 1756176771Sraj int su = (pmap == kernel_pmap); 1757176771Sraj 1758176771Sraj //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1759176771Sraj // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1760176771Sraj 1761176771Sraj if (su) { 1762187151Sraj KASSERT(((va >= virtual_avail) && 1763187151Sraj (va <= VM_MAX_KERNEL_ADDRESS)), 1764187151Sraj ("mmu_booke_remove: kernel pmap, non kernel va")); 1765176771Sraj } else { 1766176771Sraj KASSERT((va <= VM_MAXUSER_ADDRESS), 1767187151Sraj ("mmu_booke_remove: user pmap, non user va")); 1768176771Sraj } 1769176771Sraj 1770176771Sraj if (PMAP_REMOVE_DONE(pmap)) { 1771176771Sraj //debugf("mmu_booke_remove: e (empty)\n"); 1772176771Sraj return; 1773176771Sraj } 1774176771Sraj 1775176771Sraj hold_flag = PTBL_HOLD_FLAG(pmap); 1776176771Sraj //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1777176771Sraj 1778242535Salc rw_wlock(&pvh_global_lock); 1779176771Sraj PMAP_LOCK(pmap); 1780176771Sraj for (; va < endva; va += PAGE_SIZE) { 1781176771Sraj pte = pte_find(mmu, pmap, va); 1782187149Sraj if ((pte != NULL) && PTE_ISVALID(pte)) 1783176771Sraj pte_remove(mmu, pmap, va, hold_flag); 1784176771Sraj } 1785176771Sraj PMAP_UNLOCK(pmap); 1786242535Salc rw_wunlock(&pvh_global_lock); 1787176771Sraj 1788176771Sraj //debugf("mmu_booke_remove: e\n"); 1789176771Sraj} 1790176771Sraj 1791176771Sraj/* 1792176771Sraj * Remove physical page from all pmaps in which it resides. 1793176771Sraj */ 1794176771Srajstatic void 1795176771Srajmmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1796176771Sraj{ 1797176771Sraj pv_entry_t pv, pvn; 1798187151Sraj uint8_t hold_flag; 1799176771Sraj 1800242535Salc rw_wlock(&pvh_global_lock); 1801176771Sraj for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1802176771Sraj pvn = TAILQ_NEXT(pv, pv_link); 1803176771Sraj 1804176771Sraj PMAP_LOCK(pv->pv_pmap); 1805176771Sraj hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1806176771Sraj pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1807176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1808176771Sraj } 1809225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 1810242535Salc rw_wunlock(&pvh_global_lock); 1811176771Sraj} 1812176771Sraj 1813176771Sraj/* 1814176771Sraj * Map a range of physical addresses into kernel virtual address space. 1815176771Sraj */ 1816176771Srajstatic vm_offset_t 1817235936Srajmmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start, 1818235936Sraj vm_paddr_t pa_end, int prot) 1819176771Sraj{ 1820176771Sraj vm_offset_t sva = *virt; 1821176771Sraj vm_offset_t va = sva; 1822176771Sraj 1823176771Sraj //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1824176771Sraj // sva, pa_start, pa_end); 1825176771Sraj 1826176771Sraj while (pa_start < pa_end) { 1827176771Sraj mmu_booke_kenter(mmu, va, pa_start); 1828176771Sraj va += PAGE_SIZE; 1829176771Sraj pa_start += PAGE_SIZE; 1830176771Sraj } 1831176771Sraj *virt = va; 1832176771Sraj 1833176771Sraj //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1834176771Sraj return (sva); 1835176771Sraj} 1836176771Sraj 1837176771Sraj/* 1838176771Sraj * The pmap must be activated before it's address space can be accessed in any 1839176771Sraj * way. 1840176771Sraj */ 1841176771Srajstatic void 1842176771Srajmmu_booke_activate(mmu_t mmu, struct thread *td) 1843176771Sraj{ 1844176771Sraj pmap_t pmap; 1845223758Sattilio u_int cpuid; 1846176771Sraj 1847176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1848176771Sraj 1849187149Sraj CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1850187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1851176771Sraj 1852176771Sraj KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1853176771Sraj 1854176771Sraj mtx_lock_spin(&sched_lock); 1855176771Sraj 1856223758Sattilio cpuid = PCPU_GET(cpuid); 1857223758Sattilio CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1858176771Sraj PCPU_SET(curpmap, pmap); 1859187149Sraj 1860223758Sattilio if (pmap->pm_tid[cpuid] == TID_NONE) 1861176771Sraj tid_alloc(pmap); 1862176771Sraj 1863176771Sraj /* Load PID0 register with pmap tid value. */ 1864223758Sattilio mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1865187149Sraj __asm __volatile("isync"); 1866176771Sraj 1867176771Sraj mtx_unlock_spin(&sched_lock); 1868176771Sraj 1869187149Sraj CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1870187149Sraj pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1871176771Sraj} 1872176771Sraj 1873176771Sraj/* 1874176771Sraj * Deactivate the specified process's address space. 1875176771Sraj */ 1876176771Srajstatic void 1877176771Srajmmu_booke_deactivate(mmu_t mmu, struct thread *td) 1878176771Sraj{ 1879176771Sraj pmap_t pmap; 1880176771Sraj 1881176771Sraj pmap = &td->td_proc->p_vmspace->vm_pmap; 1882187149Sraj 1883187149Sraj CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1884187149Sraj __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1885187149Sraj 1886223758Sattilio CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1887176771Sraj PCPU_SET(curpmap, NULL); 1888176771Sraj} 1889176771Sraj 1890176771Sraj/* 1891176771Sraj * Copy the range specified by src_addr/len 1892176771Sraj * from the source map to the range dst_addr/len 1893176771Sraj * in the destination map. 1894176771Sraj * 1895176771Sraj * This routine is only advisory and need not do anything. 1896176771Sraj */ 1897176771Srajstatic void 1898194101Srajmmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1899194101Sraj vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1900176771Sraj{ 1901176771Sraj 1902176771Sraj} 1903176771Sraj 1904176771Sraj/* 1905176771Sraj * Set the physical protection on the specified range of this map as requested. 1906176771Sraj */ 1907176771Srajstatic void 1908176771Srajmmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1909176771Sraj vm_prot_t prot) 1910176771Sraj{ 1911176771Sraj vm_offset_t va; 1912176771Sraj vm_page_t m; 1913176771Sraj pte_t *pte; 1914176771Sraj 1915176771Sraj if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1916176771Sraj mmu_booke_remove(mmu, pmap, sva, eva); 1917176771Sraj return; 1918176771Sraj } 1919176771Sraj 1920176771Sraj if (prot & VM_PROT_WRITE) 1921176771Sraj return; 1922176771Sraj 1923176771Sraj PMAP_LOCK(pmap); 1924176771Sraj for (va = sva; va < eva; va += PAGE_SIZE) { 1925176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1926176771Sraj if (PTE_ISVALID(pte)) { 1927176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1928176771Sraj 1929187149Sraj mtx_lock_spin(&tlbivax_mutex); 1930192532Sraj tlb_miss_lock(); 1931187149Sraj 1932176771Sraj /* Handle modified pages. */ 1933207437Salc if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1934178626Smarcel vm_page_dirty(m); 1935176771Sraj 1936187149Sraj tlb0_flush_entry(va); 1937207437Salc pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1938187149Sraj 1939192532Sraj tlb_miss_unlock(); 1940187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1941176771Sraj } 1942176771Sraj } 1943176771Sraj } 1944176771Sraj PMAP_UNLOCK(pmap); 1945176771Sraj} 1946176771Sraj 1947176771Sraj/* 1948176771Sraj * Clear the write and modified bits in each of the given page's mappings. 1949176771Sraj */ 1950176771Srajstatic void 1951176771Srajmmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1952176771Sraj{ 1953176771Sraj pv_entry_t pv; 1954176771Sraj pte_t *pte; 1955176771Sraj 1956224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1957208175Salc ("mmu_booke_remove_write: page %p is not managed", m)); 1958208175Salc 1959208175Salc /* 1960254138Sattilio * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 1961254138Sattilio * set by another thread while the object is locked. Thus, 1962254138Sattilio * if PGA_WRITEABLE is clear, no page table entries need updating. 1963208175Salc */ 1964248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 1965254138Sattilio if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 1966176771Sraj return; 1967242535Salc rw_wlock(&pvh_global_lock); 1968176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1969176771Sraj PMAP_LOCK(pv->pv_pmap); 1970176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1971176771Sraj if (PTE_ISVALID(pte)) { 1972176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1973176771Sraj 1974187149Sraj mtx_lock_spin(&tlbivax_mutex); 1975192532Sraj tlb_miss_lock(); 1976187149Sraj 1977176771Sraj /* Handle modified pages. */ 1978178626Smarcel if (PTE_ISMODIFIED(pte)) 1979178626Smarcel vm_page_dirty(m); 1980176771Sraj 1981176771Sraj /* Flush mapping from TLB0. */ 1982207437Salc pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1983187149Sraj 1984192532Sraj tlb_miss_unlock(); 1985187149Sraj mtx_unlock_spin(&tlbivax_mutex); 1986176771Sraj } 1987176771Sraj } 1988176771Sraj PMAP_UNLOCK(pv->pv_pmap); 1989176771Sraj } 1990225418Skib vm_page_aflag_clear(m, PGA_WRITEABLE); 1991242535Salc rw_wunlock(&pvh_global_lock); 1992176771Sraj} 1993176771Sraj 1994198341Smarcelstatic void 1995198341Smarcelmmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1996176771Sraj{ 1997176771Sraj pte_t *pte; 1998198341Smarcel pmap_t pmap; 1999198341Smarcel vm_page_t m; 2000198341Smarcel vm_offset_t addr; 2001198341Smarcel vm_paddr_t pa; 2002198341Smarcel int active, valid; 2003198341Smarcel 2004198341Smarcel va = trunc_page(va); 2005198341Smarcel sz = round_page(sz); 2006176771Sraj 2007242535Salc rw_wlock(&pvh_global_lock); 2008198341Smarcel pmap = PCPU_GET(curpmap); 2009198341Smarcel active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2010198341Smarcel while (sz > 0) { 2011198341Smarcel PMAP_LOCK(pm); 2012198341Smarcel pte = pte_find(mmu, pm, va); 2013198341Smarcel valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2014198341Smarcel if (valid) 2015198341Smarcel pa = PTE_PA(pte); 2016198341Smarcel PMAP_UNLOCK(pm); 2017198341Smarcel if (valid) { 2018198341Smarcel if (!active) { 2019198341Smarcel /* Create a mapping in the active pmap. */ 2020198341Smarcel addr = 0; 2021198341Smarcel m = PHYS_TO_VM_PAGE(pa); 2022198341Smarcel PMAP_LOCK(pmap); 2023198341Smarcel pte_enter(mmu, pmap, m, addr, 2024198341Smarcel PTE_SR | PTE_VALID | PTE_UR); 2025198341Smarcel __syncicache((void *)addr, PAGE_SIZE); 2026198341Smarcel pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2027198341Smarcel PMAP_UNLOCK(pmap); 2028198341Smarcel } else 2029198341Smarcel __syncicache((void *)va, PAGE_SIZE); 2030198341Smarcel } 2031198341Smarcel va += PAGE_SIZE; 2032198341Smarcel sz -= PAGE_SIZE; 2033176771Sraj } 2034242535Salc rw_wunlock(&pvh_global_lock); 2035176771Sraj} 2036176771Sraj 2037176771Sraj/* 2038176771Sraj * Atomically extract and hold the physical page with the given 2039176771Sraj * pmap and virtual address pair if that mapping permits the given 2040176771Sraj * protection. 2041176771Sraj */ 2042176771Srajstatic vm_page_t 2043176771Srajmmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2044176771Sraj vm_prot_t prot) 2045176771Sraj{ 2046176771Sraj pte_t *pte; 2047176771Sraj vm_page_t m; 2048187151Sraj uint32_t pte_wbit; 2049207410Skmacy vm_paddr_t pa; 2050207410Skmacy 2051176771Sraj m = NULL; 2052207410Skmacy pa = 0; 2053176771Sraj PMAP_LOCK(pmap); 2054207410Skmacyretry: 2055176771Sraj pte = pte_find(mmu, pmap, va); 2056176771Sraj if ((pte != NULL) && PTE_ISVALID(pte)) { 2057176771Sraj if (pmap == kernel_pmap) 2058176771Sraj pte_wbit = PTE_SW; 2059176771Sraj else 2060176771Sraj pte_wbit = PTE_UW; 2061176771Sraj 2062176771Sraj if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2063207410Skmacy if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2064207410Skmacy goto retry; 2065176771Sraj m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2066176771Sraj vm_page_hold(m); 2067176771Sraj } 2068176771Sraj } 2069176771Sraj 2070207410Skmacy PA_UNLOCK_COND(pa); 2071176771Sraj PMAP_UNLOCK(pmap); 2072176771Sraj return (m); 2073176771Sraj} 2074176771Sraj 2075176771Sraj/* 2076176771Sraj * Initialize a vm_page's machine-dependent fields. 2077176771Sraj */ 2078176771Srajstatic void 2079176771Srajmmu_booke_page_init(mmu_t mmu, vm_page_t m) 2080176771Sraj{ 2081176771Sraj 2082176771Sraj TAILQ_INIT(&m->md.pv_list); 2083176771Sraj} 2084176771Sraj 2085176771Sraj/* 2086176771Sraj * mmu_booke_zero_page_area zeros the specified hardware page by 2087176771Sraj * mapping it into virtual memory and using bzero to clear 2088176771Sraj * its contents. 2089176771Sraj * 2090176771Sraj * off and size must reside within a single page. 2091176771Sraj */ 2092176771Srajstatic void 2093176771Srajmmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2094176771Sraj{ 2095176771Sraj vm_offset_t va; 2096176771Sraj 2097187151Sraj /* XXX KASSERT off and size are within a single page? */ 2098176771Sraj 2099176771Sraj mtx_lock(&zero_page_mutex); 2100176771Sraj va = zero_page_va; 2101176771Sraj 2102176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2103176771Sraj bzero((caddr_t)va + off, size); 2104176771Sraj mmu_booke_kremove(mmu, va); 2105176771Sraj 2106176771Sraj mtx_unlock(&zero_page_mutex); 2107176771Sraj} 2108176771Sraj 2109176771Sraj/* 2110176771Sraj * mmu_booke_zero_page zeros the specified hardware page. 2111176771Sraj */ 2112176771Srajstatic void 2113176771Srajmmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2114176771Sraj{ 2115176771Sraj 2116176771Sraj mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2117176771Sraj} 2118176771Sraj 2119176771Sraj/* 2120176771Sraj * mmu_booke_copy_page copies the specified (machine independent) page by 2121176771Sraj * mapping the page into virtual memory and using memcopy to copy the page, 2122176771Sraj * one machine dependent page at a time. 2123176771Sraj */ 2124176771Srajstatic void 2125176771Srajmmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2126176771Sraj{ 2127176771Sraj vm_offset_t sva, dva; 2128176771Sraj 2129176771Sraj sva = copy_page_src_va; 2130176771Sraj dva = copy_page_dst_va; 2131176771Sraj 2132187149Sraj mtx_lock(©_page_mutex); 2133176771Sraj mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2134176771Sraj mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2135176771Sraj memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2136176771Sraj mmu_booke_kremove(mmu, dva); 2137176771Sraj mmu_booke_kremove(mmu, sva); 2138176771Sraj mtx_unlock(©_page_mutex); 2139176771Sraj} 2140176771Sraj 2141248280Skibstatic inline void 2142248280Skibmmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset, 2143248280Skib vm_page_t *mb, vm_offset_t b_offset, int xfersize) 2144248280Skib{ 2145248280Skib void *a_cp, *b_cp; 2146248280Skib vm_offset_t a_pg_offset, b_pg_offset; 2147248280Skib int cnt; 2148248280Skib 2149248280Skib mtx_lock(©_page_mutex); 2150248280Skib while (xfersize > 0) { 2151248280Skib a_pg_offset = a_offset & PAGE_MASK; 2152248280Skib cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2153248280Skib mmu_booke_kenter(mmu, copy_page_src_va, 2154248280Skib VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])); 2155248280Skib a_cp = (char *)copy_page_src_va + a_pg_offset; 2156248280Skib b_pg_offset = b_offset & PAGE_MASK; 2157248280Skib cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2158248280Skib mmu_booke_kenter(mmu, copy_page_dst_va, 2159248280Skib VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])); 2160248280Skib b_cp = (char *)copy_page_dst_va + b_pg_offset; 2161248280Skib bcopy(a_cp, b_cp, cnt); 2162248280Skib mmu_booke_kremove(mmu, copy_page_dst_va); 2163248280Skib mmu_booke_kremove(mmu, copy_page_src_va); 2164248280Skib a_offset += cnt; 2165248280Skib b_offset += cnt; 2166248280Skib xfersize -= cnt; 2167248280Skib } 2168248280Skib mtx_unlock(©_page_mutex); 2169248280Skib} 2170248280Skib 2171176771Sraj/* 2172176771Sraj * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2173176771Sraj * into virtual memory and using bzero to clear its contents. This is intended 2174176771Sraj * to be called from the vm_pagezero process only and outside of Giant. No 2175176771Sraj * lock is required. 2176176771Sraj */ 2177176771Srajstatic void 2178176771Srajmmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2179176771Sraj{ 2180176771Sraj vm_offset_t va; 2181176771Sraj 2182176771Sraj va = zero_page_idle_va; 2183176771Sraj mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2184176771Sraj bzero((caddr_t)va, PAGE_SIZE); 2185176771Sraj mmu_booke_kremove(mmu, va); 2186176771Sraj} 2187176771Sraj 2188176771Sraj/* 2189176771Sraj * Return whether or not the specified physical page was modified 2190176771Sraj * in any of physical maps. 2191176771Sraj */ 2192176771Srajstatic boolean_t 2193176771Srajmmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2194176771Sraj{ 2195176771Sraj pte_t *pte; 2196176771Sraj pv_entry_t pv; 2197208504Salc boolean_t rv; 2198176771Sraj 2199224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2200208504Salc ("mmu_booke_is_modified: page %p is not managed", m)); 2201208504Salc rv = FALSE; 2202176771Sraj 2203208504Salc /* 2204254138Sattilio * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2205225418Skib * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2206208504Salc * is clear, no PTEs can be modified. 2207208504Salc */ 2208248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 2209254138Sattilio if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2210208504Salc return (rv); 2211242535Salc rw_wlock(&pvh_global_lock); 2212176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2213176771Sraj PMAP_LOCK(pv->pv_pmap); 2214208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2215208504Salc PTE_ISVALID(pte)) { 2216208504Salc if (PTE_ISMODIFIED(pte)) 2217208504Salc rv = TRUE; 2218176771Sraj } 2219176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2220208504Salc if (rv) 2221208504Salc break; 2222176771Sraj } 2223242535Salc rw_wunlock(&pvh_global_lock); 2224208504Salc return (rv); 2225176771Sraj} 2226176771Sraj 2227176771Sraj/* 2228187151Sraj * Return whether or not the specified virtual address is eligible 2229176771Sraj * for prefault. 2230176771Sraj */ 2231176771Srajstatic boolean_t 2232176771Srajmmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2233176771Sraj{ 2234176771Sraj 2235176771Sraj return (FALSE); 2236176771Sraj} 2237176771Sraj 2238176771Sraj/* 2239207155Salc * Return whether or not the specified physical page was referenced 2240207155Salc * in any physical maps. 2241207155Salc */ 2242207155Salcstatic boolean_t 2243207155Salcmmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2244207155Salc{ 2245207155Salc pte_t *pte; 2246207155Salc pv_entry_t pv; 2247207155Salc boolean_t rv; 2248207155Salc 2249224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2250208574Salc ("mmu_booke_is_referenced: page %p is not managed", m)); 2251207155Salc rv = FALSE; 2252242535Salc rw_wlock(&pvh_global_lock); 2253207155Salc TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2254207155Salc PMAP_LOCK(pv->pv_pmap); 2255207155Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2256208574Salc PTE_ISVALID(pte)) { 2257208574Salc if (PTE_ISREFERENCED(pte)) 2258208574Salc rv = TRUE; 2259208574Salc } 2260207155Salc PMAP_UNLOCK(pv->pv_pmap); 2261207155Salc if (rv) 2262207155Salc break; 2263207155Salc } 2264242535Salc rw_wunlock(&pvh_global_lock); 2265207155Salc return (rv); 2266207155Salc} 2267207155Salc 2268207155Salc/* 2269176771Sraj * Clear the modify bits on the specified physical page. 2270176771Sraj */ 2271176771Srajstatic void 2272176771Srajmmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2273176771Sraj{ 2274176771Sraj pte_t *pte; 2275176771Sraj pv_entry_t pv; 2276176771Sraj 2277224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2278208504Salc ("mmu_booke_clear_modify: page %p is not managed", m)); 2279248084Sattilio VM_OBJECT_ASSERT_WLOCKED(m->object); 2280254138Sattilio KASSERT(!vm_page_xbusied(m), 2281254138Sattilio ("mmu_booke_clear_modify: page %p is exclusive busied", m)); 2282208504Salc 2283208504Salc /* 2284225418Skib * If the page is not PG_AWRITEABLE, then no PTEs can be modified. 2285208504Salc * If the object containing the page is locked and the page is not 2286254138Sattilio * exclusive busied, then PG_AWRITEABLE cannot be concurrently set. 2287208504Salc */ 2288225418Skib if ((m->aflags & PGA_WRITEABLE) == 0) 2289176771Sraj return; 2290242535Salc rw_wlock(&pvh_global_lock); 2291176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2292176771Sraj PMAP_LOCK(pv->pv_pmap); 2293208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2294208504Salc PTE_ISVALID(pte)) { 2295187149Sraj mtx_lock_spin(&tlbivax_mutex); 2296192532Sraj tlb_miss_lock(); 2297187149Sraj 2298176771Sraj if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2299187149Sraj tlb0_flush_entry(pv->pv_va); 2300176771Sraj pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2301176771Sraj PTE_REFERENCED); 2302176771Sraj } 2303187149Sraj 2304192532Sraj tlb_miss_unlock(); 2305187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2306176771Sraj } 2307176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2308176771Sraj } 2309242535Salc rw_wunlock(&pvh_global_lock); 2310176771Sraj} 2311176771Sraj 2312176771Sraj/* 2313176771Sraj * Return a count of reference bits for a page, clearing those bits. 2314176771Sraj * It is not necessary for every reference bit to be cleared, but it 2315176771Sraj * is necessary that 0 only be returned when there are truly no 2316176771Sraj * reference bits set. 2317176771Sraj * 2318176771Sraj * XXX: The exact number of bits to check and clear is a matter that 2319176771Sraj * should be tested and standardized at some point in the future for 2320176771Sraj * optimal aging of shared pages. 2321176771Sraj */ 2322176771Srajstatic int 2323176771Srajmmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2324176771Sraj{ 2325176771Sraj pte_t *pte; 2326176771Sraj pv_entry_t pv; 2327176771Sraj int count; 2328176771Sraj 2329224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2330208990Salc ("mmu_booke_ts_referenced: page %p is not managed", m)); 2331176771Sraj count = 0; 2332242535Salc rw_wlock(&pvh_global_lock); 2333176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2334176771Sraj PMAP_LOCK(pv->pv_pmap); 2335208990Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2336208990Salc PTE_ISVALID(pte)) { 2337176771Sraj if (PTE_ISREFERENCED(pte)) { 2338187149Sraj mtx_lock_spin(&tlbivax_mutex); 2339192532Sraj tlb_miss_lock(); 2340187149Sraj 2341187149Sraj tlb0_flush_entry(pv->pv_va); 2342176771Sraj pte->flags &= ~PTE_REFERENCED; 2343176771Sraj 2344192532Sraj tlb_miss_unlock(); 2345187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2346187149Sraj 2347176771Sraj if (++count > 4) { 2348176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2349176771Sraj break; 2350176771Sraj } 2351176771Sraj } 2352176771Sraj } 2353176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2354176771Sraj } 2355242535Salc rw_wunlock(&pvh_global_lock); 2356176771Sraj return (count); 2357176771Sraj} 2358176771Sraj 2359176771Sraj/* 2360176771Sraj * Clear the reference bit on the specified physical page. 2361176771Sraj */ 2362176771Srajstatic void 2363176771Srajmmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2364176771Sraj{ 2365176771Sraj pte_t *pte; 2366176771Sraj pv_entry_t pv; 2367176771Sraj 2368224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2369208504Salc ("mmu_booke_clear_reference: page %p is not managed", m)); 2370242535Salc rw_wlock(&pvh_global_lock); 2371176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2372176771Sraj PMAP_LOCK(pv->pv_pmap); 2373208504Salc if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2374208504Salc PTE_ISVALID(pte)) { 2375176771Sraj if (PTE_ISREFERENCED(pte)) { 2376187149Sraj mtx_lock_spin(&tlbivax_mutex); 2377192532Sraj tlb_miss_lock(); 2378187149Sraj 2379187149Sraj tlb0_flush_entry(pv->pv_va); 2380176771Sraj pte->flags &= ~PTE_REFERENCED; 2381187149Sraj 2382192532Sraj tlb_miss_unlock(); 2383187149Sraj mtx_unlock_spin(&tlbivax_mutex); 2384176771Sraj } 2385176771Sraj } 2386176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2387176771Sraj } 2388242535Salc rw_wunlock(&pvh_global_lock); 2389176771Sraj} 2390176771Sraj 2391176771Sraj/* 2392176771Sraj * Change wiring attribute for a map/virtual-address pair. 2393176771Sraj */ 2394176771Srajstatic void 2395176771Srajmmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2396176771Sraj{ 2397201758Smbr pte_t *pte; 2398176771Sraj 2399176771Sraj PMAP_LOCK(pmap); 2400176771Sraj if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2401176771Sraj if (wired) { 2402176771Sraj if (!PTE_ISWIRED(pte)) { 2403176771Sraj pte->flags |= PTE_WIRED; 2404176771Sraj pmap->pm_stats.wired_count++; 2405176771Sraj } 2406176771Sraj } else { 2407176771Sraj if (PTE_ISWIRED(pte)) { 2408176771Sraj pte->flags &= ~PTE_WIRED; 2409176771Sraj pmap->pm_stats.wired_count--; 2410176771Sraj } 2411176771Sraj } 2412176771Sraj } 2413176771Sraj PMAP_UNLOCK(pmap); 2414176771Sraj} 2415176771Sraj 2416176771Sraj/* 2417176771Sraj * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2418176771Sraj * page. This count may be changed upwards or downwards in the future; it is 2419176771Sraj * only necessary that true be returned for a small subset of pmaps for proper 2420176771Sraj * page aging. 2421176771Sraj */ 2422176771Srajstatic boolean_t 2423176771Srajmmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2424176771Sraj{ 2425176771Sraj pv_entry_t pv; 2426176771Sraj int loops; 2427208990Salc boolean_t rv; 2428176771Sraj 2429224746Skib KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2430208990Salc ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2431176771Sraj loops = 0; 2432208990Salc rv = FALSE; 2433242535Salc rw_wlock(&pvh_global_lock); 2434176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2435208990Salc if (pv->pv_pmap == pmap) { 2436208990Salc rv = TRUE; 2437208990Salc break; 2438208990Salc } 2439176771Sraj if (++loops >= 16) 2440176771Sraj break; 2441176771Sraj } 2442242535Salc rw_wunlock(&pvh_global_lock); 2443208990Salc return (rv); 2444176771Sraj} 2445176771Sraj 2446176771Sraj/* 2447176771Sraj * Return the number of managed mappings to the given physical page that are 2448176771Sraj * wired. 2449176771Sraj */ 2450176771Srajstatic int 2451176771Srajmmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2452176771Sraj{ 2453176771Sraj pv_entry_t pv; 2454176771Sraj pte_t *pte; 2455176771Sraj int count = 0; 2456176771Sraj 2457224746Skib if ((m->oflags & VPO_UNMANAGED) != 0) 2458176771Sraj return (count); 2459242535Salc rw_wlock(&pvh_global_lock); 2460176771Sraj TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2461176771Sraj PMAP_LOCK(pv->pv_pmap); 2462176771Sraj if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2463176771Sraj if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2464176771Sraj count++; 2465176771Sraj PMAP_UNLOCK(pv->pv_pmap); 2466176771Sraj } 2467242535Salc rw_wunlock(&pvh_global_lock); 2468176771Sraj return (count); 2469176771Sraj} 2470176771Sraj 2471176771Srajstatic int 2472235936Srajmmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2473176771Sraj{ 2474176771Sraj int i; 2475176771Sraj vm_offset_t va; 2476176771Sraj 2477176771Sraj /* 2478176771Sraj * This currently does not work for entries that 2479176771Sraj * overlap TLB1 entries. 2480176771Sraj */ 2481176771Sraj for (i = 0; i < tlb1_idx; i ++) { 2482176771Sraj if (tlb1_iomapped(i, pa, size, &va) == 0) 2483176771Sraj return (0); 2484176771Sraj } 2485176771Sraj 2486176771Sraj return (EFAULT); 2487176771Sraj} 2488176771Sraj 2489190701Smarcelvm_offset_t 2490190701Smarcelmmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2491190701Smarcel vm_size_t *sz) 2492190701Smarcel{ 2493190701Smarcel vm_paddr_t pa, ppa; 2494190701Smarcel vm_offset_t va; 2495190701Smarcel vm_size_t gran; 2496190701Smarcel 2497190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2498190701Smarcel if (md->md_vaddr == ~0UL) { 2499190701Smarcel /* We always map a 256MB page at 256M. */ 2500190701Smarcel gran = 256 * 1024 * 1024; 2501190701Smarcel pa = md->md_paddr + ofs; 2502190701Smarcel ppa = pa & ~(gran - 1); 2503190701Smarcel ofs = pa - ppa; 2504190701Smarcel va = gran; 2505190701Smarcel tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2506190701Smarcel if (*sz > (gran - ofs)) 2507190701Smarcel *sz = gran - ofs; 2508190701Smarcel return (va + ofs); 2509190701Smarcel } 2510190701Smarcel 2511190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2512190701Smarcel va = md->md_vaddr + ofs; 2513190701Smarcel if (va >= kernstart + kernsize) { 2514190701Smarcel gran = PAGE_SIZE - (va & PAGE_MASK); 2515190701Smarcel if (*sz > gran) 2516190701Smarcel *sz = gran; 2517190701Smarcel } 2518190701Smarcel return (va); 2519190701Smarcel} 2520190701Smarcel 2521190701Smarcelvoid 2522190701Smarcelmmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2523190701Smarcel vm_offset_t va) 2524190701Smarcel{ 2525190701Smarcel 2526190701Smarcel /* Raw physical memory dumps don't have a virtual address. */ 2527190701Smarcel if (md->md_vaddr == ~0UL) { 2528190701Smarcel tlb1_idx--; 2529190701Smarcel tlb1[tlb1_idx].mas1 = 0; 2530190701Smarcel tlb1[tlb1_idx].mas2 = 0; 2531190701Smarcel tlb1[tlb1_idx].mas3 = 0; 2532190701Smarcel tlb1_write_entry(tlb1_idx); 2533190701Smarcel return; 2534190701Smarcel } 2535190701Smarcel 2536190701Smarcel /* Minidumps are based on virtual memory addresses. */ 2537190701Smarcel /* Nothing to do... */ 2538190701Smarcel} 2539190701Smarcel 2540190701Smarcelstruct pmap_md * 2541190701Smarcelmmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2542190701Smarcel{ 2543190701Smarcel static struct pmap_md md; 2544190701Smarcel pte_t *pte; 2545190701Smarcel vm_offset_t va; 2546190701Smarcel 2547190701Smarcel if (dumpsys_minidump) { 2548190701Smarcel md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2549190701Smarcel if (prev == NULL) { 2550190701Smarcel /* 1st: kernel .data and .bss. */ 2551190701Smarcel md.md_index = 1; 2552190701Smarcel md.md_vaddr = trunc_page((uintptr_t)_etext); 2553190701Smarcel md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2554190701Smarcel return (&md); 2555190701Smarcel } 2556190701Smarcel switch (prev->md_index) { 2557190701Smarcel case 1: 2558190701Smarcel /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2559190701Smarcel md.md_index = 2; 2560190701Smarcel md.md_vaddr = data_start; 2561190701Smarcel md.md_size = data_end - data_start; 2562190701Smarcel break; 2563190701Smarcel case 2: 2564190701Smarcel /* 3rd: kernel VM. */ 2565190701Smarcel va = prev->md_vaddr + prev->md_size; 2566190701Smarcel /* Find start of next chunk (from va). */ 2567190701Smarcel while (va < virtual_end) { 2568190701Smarcel /* Don't dump the buffer cache. */ 2569190701Smarcel if (va >= kmi.buffer_sva && 2570190701Smarcel va < kmi.buffer_eva) { 2571190701Smarcel va = kmi.buffer_eva; 2572190701Smarcel continue; 2573190701Smarcel } 2574190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2575190701Smarcel if (pte != NULL && PTE_ISVALID(pte)) 2576190701Smarcel break; 2577190701Smarcel va += PAGE_SIZE; 2578190701Smarcel } 2579190701Smarcel if (va < virtual_end) { 2580190701Smarcel md.md_vaddr = va; 2581190701Smarcel va += PAGE_SIZE; 2582190701Smarcel /* Find last page in chunk. */ 2583190701Smarcel while (va < virtual_end) { 2584190701Smarcel /* Don't run into the buffer cache. */ 2585190701Smarcel if (va == kmi.buffer_sva) 2586190701Smarcel break; 2587190701Smarcel pte = pte_find(mmu, kernel_pmap, va); 2588190701Smarcel if (pte == NULL || !PTE_ISVALID(pte)) 2589190701Smarcel break; 2590190701Smarcel va += PAGE_SIZE; 2591190701Smarcel } 2592190701Smarcel md.md_size = va - md.md_vaddr; 2593190701Smarcel break; 2594190701Smarcel } 2595190701Smarcel md.md_index = 3; 2596190701Smarcel /* FALLTHROUGH */ 2597190701Smarcel default: 2598190701Smarcel return (NULL); 2599190701Smarcel } 2600190701Smarcel } else { /* minidumps */ 2601209908Sraj mem_regions(&physmem_regions, &physmem_regions_sz, 2602209908Sraj &availmem_regions, &availmem_regions_sz); 2603209908Sraj 2604190701Smarcel if (prev == NULL) { 2605190701Smarcel /* first physical chunk. */ 2606209908Sraj md.md_paddr = physmem_regions[0].mr_start; 2607209908Sraj md.md_size = physmem_regions[0].mr_size; 2608190701Smarcel md.md_vaddr = ~0UL; 2609190701Smarcel md.md_index = 1; 2610209908Sraj } else if (md.md_index < physmem_regions_sz) { 2611209908Sraj md.md_paddr = physmem_regions[md.md_index].mr_start; 2612209908Sraj md.md_size = physmem_regions[md.md_index].mr_size; 2613190701Smarcel md.md_vaddr = ~0UL; 2614190701Smarcel md.md_index++; 2615190701Smarcel } else { 2616190701Smarcel /* There's no next physical chunk. */ 2617190701Smarcel return (NULL); 2618190701Smarcel } 2619190701Smarcel } 2620190701Smarcel 2621190701Smarcel return (&md); 2622190701Smarcel} 2623190701Smarcel 2624176771Sraj/* 2625176771Sraj * Map a set of physical memory pages into the kernel virtual address space. 2626176771Sraj * Return a pointer to where it is mapped. This routine is intended to be used 2627176771Sraj * for mapping device memory, NOT real memory. 2628176771Sraj */ 2629176771Srajstatic void * 2630235936Srajmmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size) 2631176771Sraj{ 2632184244Smarcel void *res; 2633176771Sraj uintptr_t va; 2634184244Smarcel vm_size_t sz; 2635176771Sraj 2636242526Smarcel /* 2637242526Smarcel * CCSR is premapped. Note that (pa + size - 1) is there to make sure 2638242526Smarcel * we don't wrap around. Devices on the local bus typically extend all 2639242526Smarcel * the way up to and including 0xffffffff. In that case (pa + size) 2640242526Smarcel * would be 0. This creates a false positive (i.e. we think it's 2641242526Smarcel * within the CCSR) and not create a mapping. 2642242526Smarcel */ 2643242526Smarcel if (pa >= ccsrbar_pa && (pa + size - 1) < (ccsrbar_pa + CCSRBAR_SIZE)) { 2644242526Smarcel va = CCSRBAR_VA + (pa - ccsrbar_pa); 2645242526Smarcel return ((void *)va); 2646242526Smarcel } 2647242526Smarcel 2648176771Sraj va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2649184244Smarcel res = (void *)va; 2650184244Smarcel 2651184244Smarcel do { 2652184244Smarcel sz = 1 << (ilog2(size) & ~1); 2653184244Smarcel if (bootverbose) 2654184244Smarcel printf("Wiring VA=%x to PA=%x (size=%x), " 2655184244Smarcel "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2656184244Smarcel tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2657184244Smarcel size -= sz; 2658184244Smarcel pa += sz; 2659184244Smarcel va += sz; 2660184244Smarcel } while (size > 0); 2661184244Smarcel 2662184244Smarcel return (res); 2663176771Sraj} 2664176771Sraj 2665176771Sraj/* 2666176771Sraj * 'Unmap' a range mapped by mmu_booke_mapdev(). 2667176771Sraj */ 2668176771Srajstatic void 2669176771Srajmmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2670176771Sraj{ 2671176771Sraj vm_offset_t base, offset; 2672176771Sraj 2673176771Sraj /* 2674176771Sraj * Unmap only if this is inside kernel virtual space. 2675176771Sraj */ 2676176771Sraj if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2677176771Sraj base = trunc_page(va); 2678176771Sraj offset = va & PAGE_MASK; 2679176771Sraj size = roundup(offset + size, PAGE_SIZE); 2680254025Sjeff kva_free(base, size); 2681176771Sraj } 2682176771Sraj} 2683176771Sraj 2684176771Sraj/* 2685187151Sraj * mmu_booke_object_init_pt preloads the ptes for a given object into the 2686187151Sraj * specified pmap. This eliminates the blast of soft faults on process startup 2687187151Sraj * and immediately after an mmap. 2688176771Sraj */ 2689176771Srajstatic void 2690176771Srajmmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2691176771Sraj vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2692176771Sraj{ 2693187151Sraj 2694248084Sattilio VM_OBJECT_ASSERT_WLOCKED(object); 2695195840Sjhb KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2696176771Sraj ("mmu_booke_object_init_pt: non-device object")); 2697176771Sraj} 2698176771Sraj 2699176771Sraj/* 2700176771Sraj * Perform the pmap work for mincore. 2701176771Sraj */ 2702176771Srajstatic int 2703208504Salcmmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2704208504Salc vm_paddr_t *locked_pa) 2705176771Sraj{ 2706176771Sraj 2707176771Sraj TODO; 2708176771Sraj return (0); 2709176771Sraj} 2710176771Sraj 2711176771Sraj/**************************************************************************/ 2712176771Sraj/* TID handling */ 2713176771Sraj/**************************************************************************/ 2714176771Sraj 2715176771Sraj/* 2716176771Sraj * Allocate a TID. If necessary, steal one from someone else. 2717176771Sraj * The new TID is flushed from the TLB before returning. 2718176771Sraj */ 2719176771Srajstatic tlbtid_t 2720176771Srajtid_alloc(pmap_t pmap) 2721176771Sraj{ 2722176771Sraj tlbtid_t tid; 2723187149Sraj int thiscpu; 2724176771Sraj 2725187149Sraj KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2726176771Sraj 2727187149Sraj CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2728176771Sraj 2729187149Sraj thiscpu = PCPU_GET(cpuid); 2730176771Sraj 2731187149Sraj tid = PCPU_GET(tid_next); 2732187149Sraj if (tid > TID_MAX) 2733187149Sraj tid = TID_MIN; 2734187149Sraj PCPU_SET(tid_next, tid + 1); 2735176771Sraj 2736187149Sraj /* If we are stealing TID then clear the relevant pmap's field */ 2737187149Sraj if (tidbusy[thiscpu][tid] != NULL) { 2738176771Sraj 2739187149Sraj CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2740187149Sraj 2741187149Sraj tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2742176771Sraj 2743187149Sraj /* Flush all entries from TLB0 matching this TID. */ 2744187149Sraj tid_flush(tid); 2745176771Sraj } 2746176771Sraj 2747187149Sraj tidbusy[thiscpu][tid] = pmap; 2748187149Sraj pmap->pm_tid[thiscpu] = tid; 2749187149Sraj __asm __volatile("msync; isync"); 2750176771Sraj 2751187149Sraj CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2752187149Sraj PCPU_GET(tid_next)); 2753176771Sraj 2754176771Sraj return (tid); 2755176771Sraj} 2756176771Sraj 2757176771Sraj/**************************************************************************/ 2758176771Sraj/* TLB0 handling */ 2759176771Sraj/**************************************************************************/ 2760176771Sraj 2761176771Srajstatic void 2762187149Srajtlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2763187149Sraj uint32_t mas7) 2764176771Sraj{ 2765176771Sraj int as; 2766176771Sraj char desc[3]; 2767176771Sraj tlbtid_t tid; 2768176771Sraj vm_size_t size; 2769176771Sraj unsigned int tsize; 2770176771Sraj 2771176771Sraj desc[2] = '\0'; 2772176771Sraj if (mas1 & MAS1_VALID) 2773176771Sraj desc[0] = 'V'; 2774176771Sraj else 2775176771Sraj desc[0] = ' '; 2776176771Sraj 2777176771Sraj if (mas1 & MAS1_IPROT) 2778176771Sraj desc[1] = 'P'; 2779176771Sraj else 2780176771Sraj desc[1] = ' '; 2781176771Sraj 2782187149Sraj as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2783176771Sraj tid = MAS1_GETTID(mas1); 2784176771Sraj 2785176771Sraj tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2786176771Sraj size = 0; 2787176771Sraj if (tsize) 2788176771Sraj size = tsize2size(tsize); 2789176771Sraj 2790176771Sraj debugf("%3d: (%s) [AS=%d] " 2791176771Sraj "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2792176771Sraj "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2793176771Sraj i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2794176771Sraj} 2795176771Sraj 2796176771Sraj/* Convert TLB0 va and way number to tlb0[] table index. */ 2797176771Srajstatic inline unsigned int 2798176771Srajtlb0_tableidx(vm_offset_t va, unsigned int way) 2799176771Sraj{ 2800176771Sraj unsigned int idx; 2801176771Sraj 2802176771Sraj idx = (way * TLB0_ENTRIES_PER_WAY); 2803176771Sraj idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2804176771Sraj return (idx); 2805176771Sraj} 2806176771Sraj 2807176771Sraj/* 2808187149Sraj * Invalidate TLB0 entry. 2809176771Sraj */ 2810187149Srajstatic inline void 2811187149Srajtlb0_flush_entry(vm_offset_t va) 2812176771Sraj{ 2813176771Sraj 2814187149Sraj CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2815176771Sraj 2816187149Sraj mtx_assert(&tlbivax_mutex, MA_OWNED); 2817176771Sraj 2818187149Sraj __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2819187149Sraj __asm __volatile("isync; msync"); 2820187149Sraj __asm __volatile("tlbsync; msync"); 2821176771Sraj 2822187149Sraj CTR1(KTR_PMAP, "%s: e", __func__); 2823176771Sraj} 2824176771Sraj 2825176771Sraj/* Print out contents of the MAS registers for each TLB0 entry */ 2826187149Srajvoid 2827176771Srajtlb0_print_tlbentries(void) 2828176771Sraj{ 2829187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 2830176771Sraj int entryidx, way, idx; 2831176771Sraj 2832176771Sraj debugf("TLB0 entries:\n"); 2833187149Sraj for (way = 0; way < TLB0_WAYS; way ++) 2834176771Sraj for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2835176771Sraj 2836176771Sraj mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2837176771Sraj mtspr(SPR_MAS0, mas0); 2838187149Sraj __asm __volatile("isync"); 2839176771Sraj 2840176771Sraj mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2841176771Sraj mtspr(SPR_MAS2, mas2); 2842176771Sraj 2843187149Sraj __asm __volatile("isync; tlbre"); 2844176771Sraj 2845176771Sraj mas1 = mfspr(SPR_MAS1); 2846176771Sraj mas2 = mfspr(SPR_MAS2); 2847176771Sraj mas3 = mfspr(SPR_MAS3); 2848176771Sraj mas7 = mfspr(SPR_MAS7); 2849176771Sraj 2850176771Sraj idx = tlb0_tableidx(mas2, way); 2851176771Sraj tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2852176771Sraj } 2853176771Sraj} 2854176771Sraj 2855176771Sraj/**************************************************************************/ 2856176771Sraj/* TLB1 handling */ 2857176771Sraj/**************************************************************************/ 2858187149Sraj 2859176771Sraj/* 2860187149Sraj * TLB1 mapping notes: 2861187149Sraj * 2862187149Sraj * TLB1[0] CCSRBAR 2863187149Sraj * TLB1[1] Kernel text and data. 2864187149Sraj * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2865187149Sraj * windows, other devices mappings. 2866187149Sraj */ 2867187149Sraj 2868187149Sraj/* 2869176771Sraj * Write given entry to TLB1 hardware. 2870176771Sraj * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2871176771Sraj */ 2872176771Srajstatic void 2873176771Srajtlb1_write_entry(unsigned int idx) 2874176771Sraj{ 2875187151Sraj uint32_t mas0, mas7; 2876176771Sraj 2877176771Sraj //debugf("tlb1_write_entry: s\n"); 2878176771Sraj 2879176771Sraj /* Clear high order RPN bits */ 2880176771Sraj mas7 = 0; 2881176771Sraj 2882176771Sraj /* Select entry */ 2883176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2884176771Sraj //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2885176771Sraj 2886176771Sraj mtspr(SPR_MAS0, mas0); 2887187151Sraj __asm __volatile("isync"); 2888176771Sraj mtspr(SPR_MAS1, tlb1[idx].mas1); 2889187151Sraj __asm __volatile("isync"); 2890176771Sraj mtspr(SPR_MAS2, tlb1[idx].mas2); 2891187151Sraj __asm __volatile("isync"); 2892176771Sraj mtspr(SPR_MAS3, tlb1[idx].mas3); 2893187151Sraj __asm __volatile("isync"); 2894176771Sraj mtspr(SPR_MAS7, mas7); 2895187151Sraj __asm __volatile("isync; tlbwe; isync; msync"); 2896176771Sraj 2897201758Smbr //debugf("tlb1_write_entry: e\n"); 2898176771Sraj} 2899176771Sraj 2900176771Sraj/* 2901176771Sraj * Return the largest uint value log such that 2^log <= num. 2902176771Sraj */ 2903176771Srajstatic unsigned int 2904176771Srajilog2(unsigned int num) 2905176771Sraj{ 2906176771Sraj int lz; 2907176771Sraj 2908176771Sraj __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2909176771Sraj return (31 - lz); 2910176771Sraj} 2911176771Sraj 2912176771Sraj/* 2913176771Sraj * Convert TLB TSIZE value to mapped region size. 2914176771Sraj */ 2915176771Srajstatic vm_size_t 2916176771Srajtsize2size(unsigned int tsize) 2917176771Sraj{ 2918176771Sraj 2919176771Sraj /* 2920176771Sraj * size = 4^tsize KB 2921176771Sraj * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2922176771Sraj */ 2923176771Sraj 2924176771Sraj return ((1 << (2 * tsize)) * 1024); 2925176771Sraj} 2926176771Sraj 2927176771Sraj/* 2928176771Sraj * Convert region size (must be power of 4) to TLB TSIZE value. 2929176771Sraj */ 2930176771Srajstatic unsigned int 2931176771Srajsize2tsize(vm_size_t size) 2932176771Sraj{ 2933176771Sraj 2934176771Sraj return (ilog2(size) / 2 - 5); 2935176771Sraj} 2936176771Sraj 2937176771Sraj/* 2938187149Sraj * Register permanent kernel mapping in TLB1. 2939176771Sraj * 2940187149Sraj * Entries are created starting from index 0 (current free entry is 2941187149Sraj * kept in tlb1_idx) and are not supposed to be invalidated. 2942176771Sraj */ 2943187149Srajstatic int 2944187149Srajtlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2945187149Sraj uint32_t flags) 2946176771Sraj{ 2947187149Sraj uint32_t ts, tid; 2948176771Sraj int tsize; 2949187149Sraj 2950187149Sraj if (tlb1_idx >= TLB1_ENTRIES) { 2951187149Sraj printf("tlb1_set_entry: TLB1 full!\n"); 2952187149Sraj return (-1); 2953187149Sraj } 2954176771Sraj 2955176771Sraj /* Convert size to TSIZE */ 2956176771Sraj tsize = size2tsize(size); 2957176771Sraj 2958187149Sraj tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2959187149Sraj /* XXX TS is hard coded to 0 for now as we only use single address space */ 2960187149Sraj ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2961176771Sraj 2962187149Sraj /* XXX LOCK tlb1[] */ 2963176771Sraj 2964187149Sraj tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2965187149Sraj tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2966187149Sraj tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2967176771Sraj 2968187149Sraj /* Set supervisor RWX permission bits */ 2969187149Sraj tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2970176771Sraj 2971187149Sraj tlb1_write_entry(tlb1_idx++); 2972176771Sraj 2973187149Sraj /* XXX UNLOCK tlb1[] */ 2974176771Sraj 2975187149Sraj /* 2976187149Sraj * XXX in general TLB1 updates should be propagated between CPUs, 2977187149Sraj * since current design assumes to have the same TLB1 set-up on all 2978187149Sraj * cores. 2979187149Sraj */ 2980176771Sraj return (0); 2981176771Sraj} 2982176771Sraj 2983176771Sraj/* 2984187151Sraj * Map in contiguous RAM region into the TLB1 using maximum of 2985176771Sraj * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2986176771Sraj * 2987187151Sraj * If necessary round up last entry size and return total size 2988176771Sraj * used by all allocated entries. 2989176771Sraj */ 2990176771Srajvm_size_t 2991224611Smarceltlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 2992176771Sraj{ 2993224611Smarcel vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 2994224611Smarcel vm_size_t mapped, pgsz, base, mask; 2995224611Smarcel int idx, nents; 2996176771Sraj 2997224611Smarcel /* Round up to the next 1M */ 2998224611Smarcel size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 2999176771Sraj 3000224611Smarcel mapped = 0; 3001224611Smarcel idx = 0; 3002224611Smarcel base = va; 3003224611Smarcel pgsz = 64*1024*1024; 3004224611Smarcel while (mapped < size) { 3005224611Smarcel while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 3006224611Smarcel while (pgsz > (size - mapped)) 3007224611Smarcel pgsz >>= 2; 3008224611Smarcel pgs[idx++] = pgsz; 3009224611Smarcel mapped += pgsz; 3010224611Smarcel } 3011176771Sraj 3012224611Smarcel /* We under-map. Correct for this. */ 3013224611Smarcel if (mapped < size) { 3014224611Smarcel while (pgs[idx - 1] == pgsz) { 3015224611Smarcel idx--; 3016224611Smarcel mapped -= pgsz; 3017224611Smarcel } 3018224611Smarcel /* XXX We may increase beyond out starting point. */ 3019224611Smarcel pgsz <<= 2; 3020224611Smarcel pgs[idx++] = pgsz; 3021224611Smarcel mapped += pgsz; 3022176771Sraj } 3023224611Smarcel } 3024176771Sraj 3025224611Smarcel nents = idx; 3026224611Smarcel mask = pgs[0] - 1; 3027224611Smarcel /* Align address to the boundary */ 3028224611Smarcel if (va & mask) { 3029224611Smarcel va = (va + mask) & ~mask; 3030224611Smarcel pa = (pa + mask) & ~mask; 3031176771Sraj } 3032176771Sraj 3033224611Smarcel for (idx = 0; idx < nents; idx++) { 3034224611Smarcel pgsz = pgs[idx]; 3035224611Smarcel debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 3036224611Smarcel tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 3037224611Smarcel pa += pgsz; 3038224611Smarcel va += pgsz; 3039176771Sraj } 3040176771Sraj 3041224611Smarcel mapped = (va - base); 3042224611Smarcel debugf("mapped size 0x%08x (wasted space 0x%08x)\n", 3043224611Smarcel mapped, mapped - size); 3044224611Smarcel return (mapped); 3045176771Sraj} 3046176771Sraj 3047176771Sraj/* 3048176771Sraj * TLB1 initialization routine, to be called after the very first 3049176771Sraj * assembler level setup done in locore.S. 3050176771Sraj */ 3051176771Srajvoid 3052176771Srajtlb1_init(vm_offset_t ccsrbar) 3053176771Sraj{ 3054224611Smarcel uint32_t mas0, mas1, mas3; 3055224611Smarcel uint32_t tsz; 3056224611Smarcel u_int i; 3057176771Sraj 3058242526Smarcel ccsrbar_pa = ccsrbar; 3059242526Smarcel 3060224611Smarcel if (bootinfo != NULL && bootinfo[0] != 1) { 3061224611Smarcel tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3062224611Smarcel } else 3063224611Smarcel tlb1_idx = 1; 3064176771Sraj 3065224611Smarcel /* The first entry/entries are used to map the kernel. */ 3066224611Smarcel for (i = 0; i < tlb1_idx; i++) { 3067224611Smarcel mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3068224611Smarcel mtspr(SPR_MAS0, mas0); 3069224611Smarcel __asm __volatile("isync; tlbre"); 3070176771Sraj 3071224611Smarcel mas1 = mfspr(SPR_MAS1); 3072224611Smarcel if ((mas1 & MAS1_VALID) == 0) 3073224611Smarcel continue; 3074224611Smarcel 3075224611Smarcel mas3 = mfspr(SPR_MAS3); 3076224611Smarcel 3077224611Smarcel tlb1[i].mas1 = mas1; 3078224611Smarcel tlb1[i].mas2 = mfspr(SPR_MAS2); 3079224611Smarcel tlb1[i].mas3 = mas3; 3080224611Smarcel 3081224611Smarcel if (i == 0) 3082224611Smarcel kernload = mas3 & MAS3_RPN; 3083224611Smarcel 3084224611Smarcel tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3085224611Smarcel kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 3086224611Smarcel } 3087224611Smarcel 3088224611Smarcel /* Map in CCSRBAR. */ 3089187149Sraj tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3090176771Sraj 3091242526Smarcel#ifdef SMP 3092242526Smarcel bp_ntlb1s = tlb1_idx; 3093242526Smarcel#endif 3094242526Smarcel 3095238031Smarcel /* Purge the remaining entries */ 3096238031Smarcel for (i = tlb1_idx; i < TLB1_ENTRIES; i++) 3097238031Smarcel tlb1_write_entry(i); 3098238031Smarcel 3099176771Sraj /* Setup TLB miss defaults */ 3100176771Sraj set_mas4_defaults(); 3101176771Sraj} 3102176771Sraj 3103176771Sraj/* 3104176771Sraj * Setup MAS4 defaults. 3105176771Sraj * These values are loaded to MAS0-2 on a TLB miss. 3106176771Sraj */ 3107176771Srajstatic void 3108176771Srajset_mas4_defaults(void) 3109176771Sraj{ 3110187151Sraj uint32_t mas4; 3111176771Sraj 3112176771Sraj /* Defaults: TLB0, PID0, TSIZED=4K */ 3113176771Sraj mas4 = MAS4_TLBSELD0; 3114176771Sraj mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3115192532Sraj#ifdef SMP 3116192532Sraj mas4 |= MAS4_MD; 3117192532Sraj#endif 3118176771Sraj mtspr(SPR_MAS4, mas4); 3119187151Sraj __asm __volatile("isync"); 3120176771Sraj} 3121176771Sraj 3122176771Sraj/* 3123176771Sraj * Print out contents of the MAS registers for each TLB1 entry 3124176771Sraj */ 3125176771Srajvoid 3126176771Srajtlb1_print_tlbentries(void) 3127176771Sraj{ 3128187149Sraj uint32_t mas0, mas1, mas2, mas3, mas7; 3129176771Sraj int i; 3130176771Sraj 3131176771Sraj debugf("TLB1 entries:\n"); 3132187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) { 3133176771Sraj 3134176771Sraj mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3135176771Sraj mtspr(SPR_MAS0, mas0); 3136176771Sraj 3137187149Sraj __asm __volatile("isync; tlbre"); 3138176771Sraj 3139176771Sraj mas1 = mfspr(SPR_MAS1); 3140176771Sraj mas2 = mfspr(SPR_MAS2); 3141176771Sraj mas3 = mfspr(SPR_MAS3); 3142176771Sraj mas7 = mfspr(SPR_MAS7); 3143176771Sraj 3144176771Sraj tlb_print_entry(i, mas1, mas2, mas3, mas7); 3145176771Sraj } 3146176771Sraj} 3147176771Sraj 3148176771Sraj/* 3149176771Sraj * Print out contents of the in-ram tlb1 table. 3150176771Sraj */ 3151176771Srajvoid 3152176771Srajtlb1_print_entries(void) 3153176771Sraj{ 3154176771Sraj int i; 3155176771Sraj 3156176771Sraj debugf("tlb1[] table entries:\n"); 3157187149Sraj for (i = 0; i < TLB1_ENTRIES; i++) 3158176771Sraj tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3159176771Sraj} 3160176771Sraj 3161176771Sraj/* 3162176771Sraj * Return 0 if the physical IO range is encompassed by one of the 3163176771Sraj * the TLB1 entries, otherwise return related error code. 3164176771Sraj */ 3165176771Srajstatic int 3166176771Srajtlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3167176771Sraj{ 3168187151Sraj uint32_t prot; 3169176771Sraj vm_paddr_t pa_start; 3170176771Sraj vm_paddr_t pa_end; 3171176771Sraj unsigned int entry_tsize; 3172176771Sraj vm_size_t entry_size; 3173176771Sraj 3174176771Sraj *va = (vm_offset_t)NULL; 3175176771Sraj 3176176771Sraj /* Skip invalid entries */ 3177176771Sraj if (!(tlb1[i].mas1 & MAS1_VALID)) 3178176771Sraj return (EINVAL); 3179176771Sraj 3180176771Sraj /* 3181176771Sraj * The entry must be cache-inhibited, guarded, and r/w 3182176771Sraj * so it can function as an i/o page 3183176771Sraj */ 3184176771Sraj prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3185176771Sraj if (prot != (MAS2_I | MAS2_G)) 3186176771Sraj return (EPERM); 3187176771Sraj 3188176771Sraj prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3189176771Sraj if (prot != (MAS3_SR | MAS3_SW)) 3190176771Sraj return (EPERM); 3191176771Sraj 3192176771Sraj /* The address should be within the entry range. */ 3193176771Sraj entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3194176771Sraj KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3195176771Sraj 3196176771Sraj entry_size = tsize2size(entry_tsize); 3197176771Sraj pa_start = tlb1[i].mas3 & MAS3_RPN; 3198176771Sraj pa_end = pa_start + entry_size - 1; 3199176771Sraj 3200176771Sraj if ((pa < pa_start) || ((pa + size) > pa_end)) 3201176771Sraj return (ERANGE); 3202176771Sraj 3203176771Sraj /* Return virtual address of this mapping. */ 3204187149Sraj *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3205176771Sraj return (0); 3206176771Sraj} 3207