pmap.c revision 224611
1226031Sstas/*- 2226031Sstas * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3226031Sstas * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4226031Sstas * All rights reserved. 5226031Sstas * 6226031Sstas * Redistribution and use in source and binary forms, with or without 7226031Sstas * modification, are permitted provided that the following conditions 8226031Sstas * are met: 9226031Sstas * 1. Redistributions of source code must retain the above copyright 10226031Sstas * notice, this list of conditions and the following disclaimer. 11226031Sstas * 2. Redistributions in binary form must reproduce the above copyright 12226031Sstas * notice, this list of conditions and the following disclaimer in the 13226031Sstas * documentation and/or other materials provided with the distribution. 14226031Sstas * 15226031Sstas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16226031Sstas * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17226031Sstas * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18226031Sstas * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19226031Sstas * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20226031Sstas * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21226031Sstas * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22226031Sstas * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23226031Sstas * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24226031Sstas * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25226031Sstas * 26226031Sstas * Some hw specific parts of this pmap were derived or influenced 27226031Sstas * by NetBSD's ibm4xx pmap module. More generic code is shared with 28226031Sstas * a few other pmap modules from the FreeBSD tree. 29226031Sstas */ 30226031Sstas 31226031Sstas /* 32226031Sstas * VM layout notes: 33226031Sstas * 34226031Sstas * Kernel and user threads run within one common virtual address space 35226031Sstas * defined by AS=0. 36226031Sstas * 37226031Sstas * Virtual address space layout: 38226031Sstas * ----------------------------- 39226031Sstas * 0x0000_0000 - 0xafff_ffff : user process 40226031Sstas * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41226031Sstas * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42226031Sstas * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43226031Sstas * 0xc100_0000 - 0xfeef_ffff : KVA 44226031Sstas * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45226031Sstas * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46226031Sstas * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47226031Sstas * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48226031Sstas * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49226031Sstas */ 50226031Sstas 51226031Sstas#include <sys/cdefs.h> 52226031Sstas__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 224611 2011-08-02 15:35:43Z marcel $"); 53226031Sstas 54226031Sstas#include <sys/types.h> 55226031Sstas#include <sys/param.h> 56226031Sstas#include <sys/malloc.h> 57226031Sstas#include <sys/ktr.h> 58226031Sstas#include <sys/proc.h> 59226031Sstas#include <sys/user.h> 60226031Sstas#include <sys/queue.h> 61226031Sstas#include <sys/systm.h> 62226031Sstas#include <sys/kernel.h> 63226031Sstas#include <sys/linker.h> 64226031Sstas#include <sys/msgbuf.h> 65226031Sstas#include <sys/lock.h> 66226031Sstas#include <sys/mutex.h> 67226031Sstas#include <sys/sched.h> 68226031Sstas#include <sys/smp.h> 69226031Sstas#include <sys/vmmeter.h> 70226031Sstas 71226031Sstas#include <vm/vm.h> 72226031Sstas#include <vm/vm_page.h> 73226031Sstas#include <vm/vm_kern.h> 74226031Sstas#include <vm/vm_pageout.h> 75#include <vm/vm_extern.h> 76#include <vm/vm_object.h> 77#include <vm/vm_param.h> 78#include <vm/vm_map.h> 79#include <vm/vm_pager.h> 80#include <vm/uma.h> 81 82#include <machine/cpu.h> 83#include <machine/pcb.h> 84#include <machine/platform.h> 85 86#include <machine/tlb.h> 87#include <machine/spr.h> 88#include <machine/vmparam.h> 89#include <machine/md_var.h> 90#include <machine/mmuvar.h> 91#include <machine/pmap.h> 92#include <machine/pte.h> 93 94#include "mmu_if.h" 95 96#ifdef DEBUG 97#define debugf(fmt, args...) printf(fmt, ##args) 98#else 99#define debugf(fmt, args...) 100#endif 101 102#define TODO panic("%s: not implemented", __func__); 103 104#include "opt_sched.h" 105#ifndef SCHED_4BSD 106#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 107#endif 108extern struct mtx sched_lock; 109 110extern int dumpsys_minidump; 111 112extern unsigned char _etext[]; 113extern unsigned char _end[]; 114 115extern uint32_t *bootinfo; 116 117#ifdef SMP 118extern uint32_t kernload_ap; 119#endif 120 121vm_paddr_t kernload; 122vm_offset_t kernstart; 123vm_size_t kernsize; 124 125/* Message buffer and tables. */ 126static vm_offset_t data_start; 127static vm_size_t data_end; 128 129/* Phys/avail memory regions. */ 130static struct mem_region *availmem_regions; 131static int availmem_regions_sz; 132static struct mem_region *physmem_regions; 133static int physmem_regions_sz; 134 135/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 136static vm_offset_t zero_page_va; 137static struct mtx zero_page_mutex; 138 139static struct mtx tlbivax_mutex; 140 141/* 142 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 143 * by idle thred only, no lock required. 144 */ 145static vm_offset_t zero_page_idle_va; 146 147/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 148static vm_offset_t copy_page_src_va; 149static vm_offset_t copy_page_dst_va; 150static struct mtx copy_page_mutex; 151 152/**************************************************************************/ 153/* PMAP */ 154/**************************************************************************/ 155 156static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 157 vm_prot_t, boolean_t); 158 159unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 160unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 161 162/* 163 * If user pmap is processed with mmu_booke_remove and the resident count 164 * drops to 0, there are no more pages to remove, so we need not continue. 165 */ 166#define PMAP_REMOVE_DONE(pmap) \ 167 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 168 169extern void tid_flush(tlbtid_t); 170 171/**************************************************************************/ 172/* TLB and TID handling */ 173/**************************************************************************/ 174 175/* Translation ID busy table */ 176static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 177 178/* 179 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 180 * core revisions and should be read from h/w registers during early config. 181 */ 182uint32_t tlb0_entries; 183uint32_t tlb0_ways; 184uint32_t tlb0_entries_per_way; 185 186#define TLB0_ENTRIES (tlb0_entries) 187#define TLB0_WAYS (tlb0_ways) 188#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 189 190#define TLB1_ENTRIES 16 191 192/* In-ram copy of the TLB1 */ 193static tlb_entry_t tlb1[TLB1_ENTRIES]; 194 195/* Next free entry in the TLB1 */ 196static unsigned int tlb1_idx; 197 198static tlbtid_t tid_alloc(struct pmap *); 199 200static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 201 202static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 203static void tlb1_write_entry(unsigned int); 204static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 205static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t); 206 207static vm_size_t tsize2size(unsigned int); 208static unsigned int size2tsize(vm_size_t); 209static unsigned int ilog2(unsigned int); 210 211static void set_mas4_defaults(void); 212 213static inline void tlb0_flush_entry(vm_offset_t); 214static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 215 216/**************************************************************************/ 217/* Page table management */ 218/**************************************************************************/ 219 220/* Data for the pv entry allocation mechanism */ 221static uma_zone_t pvzone; 222static struct vm_object pvzone_obj; 223static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 224 225#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 226 227#ifndef PMAP_SHPGPERPROC 228#define PMAP_SHPGPERPROC 200 229#endif 230 231static void ptbl_init(void); 232static struct ptbl_buf *ptbl_buf_alloc(void); 233static void ptbl_buf_free(struct ptbl_buf *); 234static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 235 236static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 237static void ptbl_free(mmu_t, pmap_t, unsigned int); 238static void ptbl_hold(mmu_t, pmap_t, unsigned int); 239static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 240 241static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 242static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 243static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 244static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 245 246static pv_entry_t pv_alloc(void); 247static void pv_free(pv_entry_t); 248static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 249static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 250 251/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 252#define PTBL_BUFS (128 * 16) 253 254struct ptbl_buf { 255 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 256 vm_offset_t kva; /* va of mapping */ 257}; 258 259/* ptbl free list and a lock used for access synchronization. */ 260static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 261static struct mtx ptbl_buf_freelist_lock; 262 263/* Base address of kva space allocated fot ptbl bufs. */ 264static vm_offset_t ptbl_buf_pool_vabase; 265 266/* Pointer to ptbl_buf structures. */ 267static struct ptbl_buf *ptbl_bufs; 268 269void pmap_bootstrap_ap(volatile uint32_t *); 270 271/* 272 * Kernel MMU interface 273 */ 274static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 275static void mmu_booke_clear_modify(mmu_t, vm_page_t); 276static void mmu_booke_clear_reference(mmu_t, vm_page_t); 277static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 278 vm_size_t, vm_offset_t); 279static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 280static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 281 vm_prot_t, boolean_t); 282static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 283 vm_page_t, vm_prot_t); 284static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 285 vm_prot_t); 286static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 287static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 288 vm_prot_t); 289static void mmu_booke_init(mmu_t); 290static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 291static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 292static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 293static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 294static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 295 int); 296static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 297 vm_paddr_t *); 298static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 299 vm_object_t, vm_pindex_t, vm_size_t); 300static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 301static void mmu_booke_page_init(mmu_t, vm_page_t); 302static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 303static void mmu_booke_pinit(mmu_t, pmap_t); 304static void mmu_booke_pinit0(mmu_t, pmap_t); 305static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 306 vm_prot_t); 307static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 308static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 309static void mmu_booke_release(mmu_t, pmap_t); 310static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 311static void mmu_booke_remove_all(mmu_t, vm_page_t); 312static void mmu_booke_remove_write(mmu_t, vm_page_t); 313static void mmu_booke_zero_page(mmu_t, vm_page_t); 314static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 315static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 316static void mmu_booke_activate(mmu_t, struct thread *); 317static void mmu_booke_deactivate(mmu_t, struct thread *); 318static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 319static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 320static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 321static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 322static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 323static void mmu_booke_kremove(mmu_t, vm_offset_t); 324static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 325static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 326 vm_size_t); 327static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 328 vm_size_t, vm_size_t *); 329static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 330 vm_size_t, vm_offset_t); 331static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 332 333static mmu_method_t mmu_booke_methods[] = { 334 /* pmap dispatcher interface */ 335 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 336 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 337 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 338 MMUMETHOD(mmu_copy, mmu_booke_copy), 339 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 340 MMUMETHOD(mmu_enter, mmu_booke_enter), 341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 343 MMUMETHOD(mmu_extract, mmu_booke_extract), 344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 345 MMUMETHOD(mmu_init, mmu_booke_init), 346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 350 MMUMETHOD(mmu_map, mmu_booke_map), 351 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 354 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 356 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 358 MMUMETHOD(mmu_protect, mmu_booke_protect), 359 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 360 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 361 MMUMETHOD(mmu_release, mmu_booke_release), 362 MMUMETHOD(mmu_remove, mmu_booke_remove), 363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 369 MMUMETHOD(mmu_activate, mmu_booke_activate), 370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 371 372 /* Internal interfaces */ 373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 376 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 377 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 378/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 380 381 /* dumpsys() support */ 382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 385 386 { 0, 0 } 387}; 388 389MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 390 391static inline void 392tlb_miss_lock(void) 393{ 394#ifdef SMP 395 struct pcpu *pc; 396 397 if (!smp_started) 398 return; 399 400 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 401 if (pc != pcpup) { 402 403 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 404 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 405 406 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 407 ("tlb_miss_lock: tried to lock self")); 408 409 tlb_lock(pc->pc_booke_tlb_lock); 410 411 CTR1(KTR_PMAP, "%s: locked", __func__); 412 } 413 } 414#endif 415} 416 417static inline void 418tlb_miss_unlock(void) 419{ 420#ifdef SMP 421 struct pcpu *pc; 422 423 if (!smp_started) 424 return; 425 426 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) { 427 if (pc != pcpup) { 428 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 429 __func__, pc->pc_cpuid); 430 431 tlb_unlock(pc->pc_booke_tlb_lock); 432 433 CTR1(KTR_PMAP, "%s: unlocked", __func__); 434 } 435 } 436#endif 437} 438 439/* Return number of entries in TLB0. */ 440static __inline void 441tlb0_get_tlbconf(void) 442{ 443 uint32_t tlb0_cfg; 444 445 tlb0_cfg = mfspr(SPR_TLB0CFG); 446 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 447 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 448 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 449} 450 451/* Initialize pool of kva ptbl buffers. */ 452static void 453ptbl_init(void) 454{ 455 int i; 456 457 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 458 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 459 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 460 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 461 462 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 463 TAILQ_INIT(&ptbl_buf_freelist); 464 465 for (i = 0; i < PTBL_BUFS; i++) { 466 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 467 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 468 } 469} 470 471/* Get a ptbl_buf from the freelist. */ 472static struct ptbl_buf * 473ptbl_buf_alloc(void) 474{ 475 struct ptbl_buf *buf; 476 477 mtx_lock(&ptbl_buf_freelist_lock); 478 buf = TAILQ_FIRST(&ptbl_buf_freelist); 479 if (buf != NULL) 480 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 481 mtx_unlock(&ptbl_buf_freelist_lock); 482 483 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 484 485 return (buf); 486} 487 488/* Return ptbl buff to free pool. */ 489static void 490ptbl_buf_free(struct ptbl_buf *buf) 491{ 492 493 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 494 495 mtx_lock(&ptbl_buf_freelist_lock); 496 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 497 mtx_unlock(&ptbl_buf_freelist_lock); 498} 499 500/* 501 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 502 */ 503static void 504ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 505{ 506 struct ptbl_buf *pbuf; 507 508 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 509 510 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 511 512 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 513 if (pbuf->kva == (vm_offset_t)ptbl) { 514 /* Remove from pmap ptbl buf list. */ 515 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 516 517 /* Free corresponding ptbl buf. */ 518 ptbl_buf_free(pbuf); 519 break; 520 } 521} 522 523/* Allocate page table. */ 524static pte_t * 525ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 526{ 527 vm_page_t mtbl[PTBL_PAGES]; 528 vm_page_t m; 529 struct ptbl_buf *pbuf; 530 unsigned int pidx; 531 pte_t *ptbl; 532 int i; 533 534 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 535 (pmap == kernel_pmap), pdir_idx); 536 537 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 538 ("ptbl_alloc: invalid pdir_idx")); 539 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 540 ("pte_alloc: valid ptbl entry exists!")); 541 542 pbuf = ptbl_buf_alloc(); 543 if (pbuf == NULL) 544 panic("pte_alloc: couldn't alloc kernel virtual memory"); 545 546 ptbl = (pte_t *)pbuf->kva; 547 548 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 549 550 /* Allocate ptbl pages, this will sleep! */ 551 for (i = 0; i < PTBL_PAGES; i++) { 552 pidx = (PTBL_PAGES * pdir_idx) + i; 553 while ((m = vm_page_alloc(NULL, pidx, 554 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 555 556 PMAP_UNLOCK(pmap); 557 vm_page_unlock_queues(); 558 VM_WAIT; 559 vm_page_lock_queues(); 560 PMAP_LOCK(pmap); 561 } 562 mtbl[i] = m; 563 } 564 565 /* Map allocated pages into kernel_pmap. */ 566 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 567 568 /* Zero whole ptbl. */ 569 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 570 571 /* Add pbuf to the pmap ptbl bufs list. */ 572 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 573 574 return (ptbl); 575} 576 577/* Free ptbl pages and invalidate pdir entry. */ 578static void 579ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 580{ 581 pte_t *ptbl; 582 vm_paddr_t pa; 583 vm_offset_t va; 584 vm_page_t m; 585 int i; 586 587 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 588 (pmap == kernel_pmap), pdir_idx); 589 590 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 591 ("ptbl_free: invalid pdir_idx")); 592 593 ptbl = pmap->pm_pdir[pdir_idx]; 594 595 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 596 597 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 598 599 /* 600 * Invalidate the pdir entry as soon as possible, so that other CPUs 601 * don't attempt to look up the page tables we are releasing. 602 */ 603 mtx_lock_spin(&tlbivax_mutex); 604 tlb_miss_lock(); 605 606 pmap->pm_pdir[pdir_idx] = NULL; 607 608 tlb_miss_unlock(); 609 mtx_unlock_spin(&tlbivax_mutex); 610 611 for (i = 0; i < PTBL_PAGES; i++) { 612 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 613 pa = pte_vatopa(mmu, kernel_pmap, va); 614 m = PHYS_TO_VM_PAGE(pa); 615 vm_page_free_zero(m); 616 atomic_subtract_int(&cnt.v_wire_count, 1); 617 mmu_booke_kremove(mmu, va); 618 } 619 620 ptbl_free_pmap_ptbl(pmap, ptbl); 621} 622 623/* 624 * Decrement ptbl pages hold count and attempt to free ptbl pages. 625 * Called when removing pte entry from ptbl. 626 * 627 * Return 1 if ptbl pages were freed. 628 */ 629static int 630ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 631{ 632 pte_t *ptbl; 633 vm_paddr_t pa; 634 vm_page_t m; 635 int i; 636 637 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 638 (pmap == kernel_pmap), pdir_idx); 639 640 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 641 ("ptbl_unhold: invalid pdir_idx")); 642 KASSERT((pmap != kernel_pmap), 643 ("ptbl_unhold: unholding kernel ptbl!")); 644 645 ptbl = pmap->pm_pdir[pdir_idx]; 646 647 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 648 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 649 ("ptbl_unhold: non kva ptbl")); 650 651 /* decrement hold count */ 652 for (i = 0; i < PTBL_PAGES; i++) { 653 pa = pte_vatopa(mmu, kernel_pmap, 654 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 655 m = PHYS_TO_VM_PAGE(pa); 656 m->wire_count--; 657 } 658 659 /* 660 * Free ptbl pages if there are no pte etries in this ptbl. 661 * wire_count has the same value for all ptbl pages, so check the last 662 * page. 663 */ 664 if (m->wire_count == 0) { 665 ptbl_free(mmu, pmap, pdir_idx); 666 667 //debugf("ptbl_unhold: e (freed ptbl)\n"); 668 return (1); 669 } 670 671 return (0); 672} 673 674/* 675 * Increment hold count for ptbl pages. This routine is used when a new pte 676 * entry is being inserted into the ptbl. 677 */ 678static void 679ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 680{ 681 vm_paddr_t pa; 682 pte_t *ptbl; 683 vm_page_t m; 684 int i; 685 686 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 687 pdir_idx); 688 689 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 690 ("ptbl_hold: invalid pdir_idx")); 691 KASSERT((pmap != kernel_pmap), 692 ("ptbl_hold: holding kernel ptbl!")); 693 694 ptbl = pmap->pm_pdir[pdir_idx]; 695 696 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 697 698 for (i = 0; i < PTBL_PAGES; i++) { 699 pa = pte_vatopa(mmu, kernel_pmap, 700 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 701 m = PHYS_TO_VM_PAGE(pa); 702 m->wire_count++; 703 } 704} 705 706/* Allocate pv_entry structure. */ 707pv_entry_t 708pv_alloc(void) 709{ 710 pv_entry_t pv; 711 712 pv_entry_count++; 713 if (pv_entry_count > pv_entry_high_water) 714 pagedaemon_wakeup(); 715 pv = uma_zalloc(pvzone, M_NOWAIT); 716 717 return (pv); 718} 719 720/* Free pv_entry structure. */ 721static __inline void 722pv_free(pv_entry_t pve) 723{ 724 725 pv_entry_count--; 726 uma_zfree(pvzone, pve); 727} 728 729 730/* Allocate and initialize pv_entry structure. */ 731static void 732pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 733{ 734 pv_entry_t pve; 735 736 //int su = (pmap == kernel_pmap); 737 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 738 // (u_int32_t)pmap, va, (u_int32_t)m); 739 740 pve = pv_alloc(); 741 if (pve == NULL) 742 panic("pv_insert: no pv entries!"); 743 744 pve->pv_pmap = pmap; 745 pve->pv_va = va; 746 747 /* add to pv_list */ 748 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 749 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 750 751 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 752 753 //debugf("pv_insert: e\n"); 754} 755 756/* Destroy pv entry. */ 757static void 758pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 759{ 760 pv_entry_t pve; 761 762 //int su = (pmap == kernel_pmap); 763 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 764 765 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 766 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 767 768 /* find pv entry */ 769 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 770 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 771 /* remove from pv_list */ 772 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 773 if (TAILQ_EMPTY(&m->md.pv_list)) 774 vm_page_flag_clear(m, PG_WRITEABLE); 775 776 /* free pv entry struct */ 777 pv_free(pve); 778 break; 779 } 780 } 781 782 //debugf("pv_remove: e\n"); 783} 784 785/* 786 * Clean pte entry, try to free page table page if requested. 787 * 788 * Return 1 if ptbl pages were freed, otherwise return 0. 789 */ 790static int 791pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 792{ 793 unsigned int pdir_idx = PDIR_IDX(va); 794 unsigned int ptbl_idx = PTBL_IDX(va); 795 vm_page_t m; 796 pte_t *ptbl; 797 pte_t *pte; 798 799 //int su = (pmap == kernel_pmap); 800 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 801 // su, (u_int32_t)pmap, va, flags); 802 803 ptbl = pmap->pm_pdir[pdir_idx]; 804 KASSERT(ptbl, ("pte_remove: null ptbl")); 805 806 pte = &ptbl[ptbl_idx]; 807 808 if (pte == NULL || !PTE_ISVALID(pte)) 809 return (0); 810 811 if (PTE_ISWIRED(pte)) 812 pmap->pm_stats.wired_count--; 813 814 /* Handle managed entry. */ 815 if (PTE_ISMANAGED(pte)) { 816 /* Get vm_page_t for mapped pte. */ 817 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 818 819 if (PTE_ISMODIFIED(pte)) 820 vm_page_dirty(m); 821 822 if (PTE_ISREFERENCED(pte)) 823 vm_page_flag_set(m, PG_REFERENCED); 824 825 pv_remove(pmap, va, m); 826 } 827 828 mtx_lock_spin(&tlbivax_mutex); 829 tlb_miss_lock(); 830 831 tlb0_flush_entry(va); 832 pte->flags = 0; 833 pte->rpn = 0; 834 835 tlb_miss_unlock(); 836 mtx_unlock_spin(&tlbivax_mutex); 837 838 pmap->pm_stats.resident_count--; 839 840 if (flags & PTBL_UNHOLD) { 841 //debugf("pte_remove: e (unhold)\n"); 842 return (ptbl_unhold(mmu, pmap, pdir_idx)); 843 } 844 845 //debugf("pte_remove: e\n"); 846 return (0); 847} 848 849/* 850 * Insert PTE for a given page and virtual address. 851 */ 852static void 853pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 854{ 855 unsigned int pdir_idx = PDIR_IDX(va); 856 unsigned int ptbl_idx = PTBL_IDX(va); 857 pte_t *ptbl, *pte; 858 859 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 860 pmap == kernel_pmap, pmap, va); 861 862 /* Get the page table pointer. */ 863 ptbl = pmap->pm_pdir[pdir_idx]; 864 865 if (ptbl == NULL) { 866 /* Allocate page table pages. */ 867 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 868 } else { 869 /* 870 * Check if there is valid mapping for requested 871 * va, if there is, remove it. 872 */ 873 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 874 if (PTE_ISVALID(pte)) { 875 pte_remove(mmu, pmap, va, PTBL_HOLD); 876 } else { 877 /* 878 * pte is not used, increment hold count 879 * for ptbl pages. 880 */ 881 if (pmap != kernel_pmap) 882 ptbl_hold(mmu, pmap, pdir_idx); 883 } 884 } 885 886 /* 887 * Insert pv_entry into pv_list for mapped page if part of managed 888 * memory. 889 */ 890 if ((m->flags & PG_FICTITIOUS) == 0) { 891 if ((m->flags & PG_UNMANAGED) == 0) { 892 flags |= PTE_MANAGED; 893 894 /* Create and insert pv entry. */ 895 pv_insert(pmap, va, m); 896 } 897 } 898 899 pmap->pm_stats.resident_count++; 900 901 mtx_lock_spin(&tlbivax_mutex); 902 tlb_miss_lock(); 903 904 tlb0_flush_entry(va); 905 if (pmap->pm_pdir[pdir_idx] == NULL) { 906 /* 907 * If we just allocated a new page table, hook it in 908 * the pdir. 909 */ 910 pmap->pm_pdir[pdir_idx] = ptbl; 911 } 912 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 913 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 914 pte->flags |= (PTE_VALID | flags); 915 916 tlb_miss_unlock(); 917 mtx_unlock_spin(&tlbivax_mutex); 918} 919 920/* Return the pa for the given pmap/va. */ 921static vm_paddr_t 922pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 923{ 924 vm_paddr_t pa = 0; 925 pte_t *pte; 926 927 pte = pte_find(mmu, pmap, va); 928 if ((pte != NULL) && PTE_ISVALID(pte)) 929 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 930 return (pa); 931} 932 933/* Get a pointer to a PTE in a page table. */ 934static pte_t * 935pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 936{ 937 unsigned int pdir_idx = PDIR_IDX(va); 938 unsigned int ptbl_idx = PTBL_IDX(va); 939 940 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 941 942 if (pmap->pm_pdir[pdir_idx]) 943 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 944 945 return (NULL); 946} 947 948/**************************************************************************/ 949/* PMAP related */ 950/**************************************************************************/ 951 952/* 953 * This is called during booke_init, before the system is really initialized. 954 */ 955static void 956mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 957{ 958 vm_offset_t phys_kernelend; 959 struct mem_region *mp, *mp1; 960 int cnt, i, j; 961 u_int s, e, sz; 962 u_int phys_avail_count; 963 vm_size_t physsz, hwphyssz, kstack0_sz; 964 vm_offset_t kernel_pdir, kstack0, va; 965 vm_paddr_t kstack0_phys; 966 void *dpcpu; 967 pte_t *pte; 968 969 debugf("mmu_booke_bootstrap: entered\n"); 970 971#ifdef SMP 972 kernload_ap = kernload; 973#endif 974 975 976 /* Initialize invalidation mutex */ 977 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 978 979 /* Read TLB0 size and associativity. */ 980 tlb0_get_tlbconf(); 981 982 /* 983 * Align kernel start and end address (kernel image). 984 * Note that kernel end does not necessarily relate to kernsize. 985 * kernsize is the size of the kernel that is actually mapped. 986 */ 987 kernstart = trunc_page(start); 988 data_start = round_page(kernelend); 989 data_end = data_start; 990 991 /* 992 * Addresses of preloaded modules (like file systems) use 993 * physical addresses. Make sure we relocate those into 994 * virtual addresses. 995 */ 996 preload_addr_relocate = kernstart - kernload; 997 998 /* Allocate the dynamic per-cpu area. */ 999 dpcpu = (void *)data_end; 1000 data_end += DPCPU_SIZE; 1001 1002 /* Allocate space for the message buffer. */ 1003 msgbufp = (struct msgbuf *)data_end; 1004 data_end += msgbufsize; 1005 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 1006 data_end); 1007 1008 data_end = round_page(data_end); 1009 1010 /* Allocate space for ptbl_bufs. */ 1011 ptbl_bufs = (struct ptbl_buf *)data_end; 1012 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 1013 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 1014 data_end); 1015 1016 data_end = round_page(data_end); 1017 1018 /* Allocate PTE tables for kernel KVA. */ 1019 kernel_pdir = data_end; 1020 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1021 PDIR_SIZE - 1) / PDIR_SIZE; 1022 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1023 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1024 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1025 1026 debugf(" data_end: 0x%08x\n", data_end); 1027 if (data_end - kernstart > kernsize) { 1028 kernsize += tlb1_mapin_region(kernstart + kernsize, 1029 kernload + kernsize, (data_end - kernstart) - kernsize); 1030 } 1031 data_end = kernstart + kernsize; 1032 debugf(" updated data_end: 0x%08x\n", data_end); 1033 1034 /* 1035 * Clear the structures - note we can only do it safely after the 1036 * possible additional TLB1 translations are in place (above) so that 1037 * all range up to the currently calculated 'data_end' is covered. 1038 */ 1039 dpcpu_init(dpcpu, 0); 1040 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1041 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1042 1043 /*******************************************************/ 1044 /* Set the start and end of kva. */ 1045 /*******************************************************/ 1046 virtual_avail = round_page(data_end); 1047 virtual_end = VM_MAX_KERNEL_ADDRESS; 1048 1049 /* Allocate KVA space for page zero/copy operations. */ 1050 zero_page_va = virtual_avail; 1051 virtual_avail += PAGE_SIZE; 1052 zero_page_idle_va = virtual_avail; 1053 virtual_avail += PAGE_SIZE; 1054 copy_page_src_va = virtual_avail; 1055 virtual_avail += PAGE_SIZE; 1056 copy_page_dst_va = virtual_avail; 1057 virtual_avail += PAGE_SIZE; 1058 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1059 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1060 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1061 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1062 1063 /* Initialize page zero/copy mutexes. */ 1064 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1065 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1066 1067 /* Allocate KVA space for ptbl bufs. */ 1068 ptbl_buf_pool_vabase = virtual_avail; 1069 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1070 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1071 ptbl_buf_pool_vabase, virtual_avail); 1072 1073 /* Calculate corresponding physical addresses for the kernel region. */ 1074 phys_kernelend = kernload + kernsize; 1075 debugf("kernel image and allocated data:\n"); 1076 debugf(" kernload = 0x%08x\n", kernload); 1077 debugf(" kernstart = 0x%08x\n", kernstart); 1078 debugf(" kernsize = 0x%08x\n", kernsize); 1079 1080 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1081 panic("mmu_booke_bootstrap: phys_avail too small"); 1082 1083 /* 1084 * Remove kernel physical address range from avail regions list. Page 1085 * align all regions. Non-page aligned memory isn't very interesting 1086 * to us. Also, sort the entries for ascending addresses. 1087 */ 1088 1089 /* Retrieve phys/avail mem regions */ 1090 mem_regions(&physmem_regions, &physmem_regions_sz, 1091 &availmem_regions, &availmem_regions_sz); 1092 sz = 0; 1093 cnt = availmem_regions_sz; 1094 debugf("processing avail regions:\n"); 1095 for (mp = availmem_regions; mp->mr_size; mp++) { 1096 s = mp->mr_start; 1097 e = mp->mr_start + mp->mr_size; 1098 debugf(" %08x-%08x -> ", s, e); 1099 /* Check whether this region holds all of the kernel. */ 1100 if (s < kernload && e > phys_kernelend) { 1101 availmem_regions[cnt].mr_start = phys_kernelend; 1102 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1103 e = kernload; 1104 } 1105 /* Look whether this regions starts within the kernel. */ 1106 if (s >= kernload && s < phys_kernelend) { 1107 if (e <= phys_kernelend) 1108 goto empty; 1109 s = phys_kernelend; 1110 } 1111 /* Now look whether this region ends within the kernel. */ 1112 if (e > kernload && e <= phys_kernelend) { 1113 if (s >= kernload) 1114 goto empty; 1115 e = kernload; 1116 } 1117 /* Now page align the start and size of the region. */ 1118 s = round_page(s); 1119 e = trunc_page(e); 1120 if (e < s) 1121 e = s; 1122 sz = e - s; 1123 debugf("%08x-%08x = %x\n", s, e, sz); 1124 1125 /* Check whether some memory is left here. */ 1126 if (sz == 0) { 1127 empty: 1128 memmove(mp, mp + 1, 1129 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1130 cnt--; 1131 mp--; 1132 continue; 1133 } 1134 1135 /* Do an insertion sort. */ 1136 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1137 if (s < mp1->mr_start) 1138 break; 1139 if (mp1 < mp) { 1140 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1141 mp1->mr_start = s; 1142 mp1->mr_size = sz; 1143 } else { 1144 mp->mr_start = s; 1145 mp->mr_size = sz; 1146 } 1147 } 1148 availmem_regions_sz = cnt; 1149 1150 /*******************************************************/ 1151 /* Steal physical memory for kernel stack from the end */ 1152 /* of the first avail region */ 1153 /*******************************************************/ 1154 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1155 kstack0_phys = availmem_regions[0].mr_start + 1156 availmem_regions[0].mr_size; 1157 kstack0_phys -= kstack0_sz; 1158 availmem_regions[0].mr_size -= kstack0_sz; 1159 1160 /*******************************************************/ 1161 /* Fill in phys_avail table, based on availmem_regions */ 1162 /*******************************************************/ 1163 phys_avail_count = 0; 1164 physsz = 0; 1165 hwphyssz = 0; 1166 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1167 1168 debugf("fill in phys_avail:\n"); 1169 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1170 1171 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1172 availmem_regions[i].mr_start, 1173 availmem_regions[i].mr_start + 1174 availmem_regions[i].mr_size, 1175 availmem_regions[i].mr_size); 1176 1177 if (hwphyssz != 0 && 1178 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1179 debugf(" hw.physmem adjust\n"); 1180 if (physsz < hwphyssz) { 1181 phys_avail[j] = availmem_regions[i].mr_start; 1182 phys_avail[j + 1] = 1183 availmem_regions[i].mr_start + 1184 hwphyssz - physsz; 1185 physsz = hwphyssz; 1186 phys_avail_count++; 1187 } 1188 break; 1189 } 1190 1191 phys_avail[j] = availmem_regions[i].mr_start; 1192 phys_avail[j + 1] = availmem_regions[i].mr_start + 1193 availmem_regions[i].mr_size; 1194 phys_avail_count++; 1195 physsz += availmem_regions[i].mr_size; 1196 } 1197 physmem = btoc(physsz); 1198 1199 /* Calculate the last available physical address. */ 1200 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1201 ; 1202 Maxmem = powerpc_btop(phys_avail[i + 1]); 1203 1204 debugf("Maxmem = 0x%08lx\n", Maxmem); 1205 debugf("phys_avail_count = %d\n", phys_avail_count); 1206 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1207 physmem); 1208 1209 /*******************************************************/ 1210 /* Initialize (statically allocated) kernel pmap. */ 1211 /*******************************************************/ 1212 PMAP_LOCK_INIT(kernel_pmap); 1213 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1214 1215 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1216 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1217 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1218 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1219 1220 /* Initialize kernel pdir */ 1221 for (i = 0; i < kernel_ptbls; i++) 1222 kernel_pmap->pm_pdir[kptbl_min + i] = 1223 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1224 1225 for (i = 0; i < MAXCPU; i++) { 1226 kernel_pmap->pm_tid[i] = TID_KERNEL; 1227 1228 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1229 tidbusy[i][0] = kernel_pmap; 1230 } 1231 1232 /* 1233 * Fill in PTEs covering kernel code and data. They are not required 1234 * for address translation, as this area is covered by static TLB1 1235 * entries, but for pte_vatopa() to work correctly with kernel area 1236 * addresses. 1237 */ 1238 for (va = KERNBASE; va < data_end; va += PAGE_SIZE) { 1239 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1240 pte->rpn = kernload + (va - KERNBASE); 1241 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1242 PTE_VALID; 1243 } 1244 /* Mark kernel_pmap active on all CPUs */ 1245 CPU_FILL(&kernel_pmap->pm_active); 1246 1247 /*******************************************************/ 1248 /* Final setup */ 1249 /*******************************************************/ 1250 1251 /* Enter kstack0 into kernel map, provide guard page */ 1252 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1253 thread0.td_kstack = kstack0; 1254 thread0.td_kstack_pages = KSTACK_PAGES; 1255 1256 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1257 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1258 kstack0_phys, kstack0_phys + kstack0_sz); 1259 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1260 1261 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1262 for (i = 0; i < KSTACK_PAGES; i++) { 1263 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1264 kstack0 += PAGE_SIZE; 1265 kstack0_phys += PAGE_SIZE; 1266 } 1267 1268 debugf("virtual_avail = %08x\n", virtual_avail); 1269 debugf("virtual_end = %08x\n", virtual_end); 1270 1271 debugf("mmu_booke_bootstrap: exit\n"); 1272} 1273 1274void 1275pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1276{ 1277 int i; 1278 1279 /* 1280 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1281 * have the snapshot of its contents in the s/w tlb1[] table, so use 1282 * these values directly to (re)program AP's TLB1 hardware. 1283 */ 1284 for (i = 0; i < tlb1_idx; i ++) { 1285 /* Skip invalid entries */ 1286 if (!(tlb1[i].mas1 & MAS1_VALID)) 1287 continue; 1288 1289 tlb1_write_entry(i); 1290 } 1291 1292 set_mas4_defaults(); 1293} 1294 1295/* 1296 * Get the physical page address for the given pmap/virtual address. 1297 */ 1298static vm_paddr_t 1299mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1300{ 1301 vm_paddr_t pa; 1302 1303 PMAP_LOCK(pmap); 1304 pa = pte_vatopa(mmu, pmap, va); 1305 PMAP_UNLOCK(pmap); 1306 1307 return (pa); 1308} 1309 1310/* 1311 * Extract the physical page address associated with the given 1312 * kernel virtual address. 1313 */ 1314static vm_paddr_t 1315mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1316{ 1317 1318 return (pte_vatopa(mmu, kernel_pmap, va)); 1319} 1320 1321/* 1322 * Initialize the pmap module. 1323 * Called by vm_init, to initialize any structures that the pmap 1324 * system needs to map virtual memory. 1325 */ 1326static void 1327mmu_booke_init(mmu_t mmu) 1328{ 1329 int shpgperproc = PMAP_SHPGPERPROC; 1330 1331 /* 1332 * Initialize the address space (zone) for the pv entries. Set a 1333 * high water mark so that the system can recover from excessive 1334 * numbers of pv entries. 1335 */ 1336 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1337 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1338 1339 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1340 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1341 1342 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1343 pv_entry_high_water = 9 * (pv_entry_max / 10); 1344 1345 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1346 1347 /* Pre-fill pvzone with initial number of pv entries. */ 1348 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1349 1350 /* Initialize ptbl allocation. */ 1351 ptbl_init(); 1352} 1353 1354/* 1355 * Map a list of wired pages into kernel virtual address space. This is 1356 * intended for temporary mappings which do not need page modification or 1357 * references recorded. Existing mappings in the region are overwritten. 1358 */ 1359static void 1360mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1361{ 1362 vm_offset_t va; 1363 1364 va = sva; 1365 while (count-- > 0) { 1366 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1367 va += PAGE_SIZE; 1368 m++; 1369 } 1370} 1371 1372/* 1373 * Remove page mappings from kernel virtual address space. Intended for 1374 * temporary mappings entered by mmu_booke_qenter. 1375 */ 1376static void 1377mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1378{ 1379 vm_offset_t va; 1380 1381 va = sva; 1382 while (count-- > 0) { 1383 mmu_booke_kremove(mmu, va); 1384 va += PAGE_SIZE; 1385 } 1386} 1387 1388/* 1389 * Map a wired page into kernel virtual address space. 1390 */ 1391static void 1392mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1393{ 1394 unsigned int pdir_idx = PDIR_IDX(va); 1395 unsigned int ptbl_idx = PTBL_IDX(va); 1396 uint32_t flags; 1397 pte_t *pte; 1398 1399 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1400 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1401 1402 flags = 0; 1403 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1404 flags |= PTE_M; 1405 1406 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1407 1408 mtx_lock_spin(&tlbivax_mutex); 1409 tlb_miss_lock(); 1410 1411 if (PTE_ISVALID(pte)) { 1412 1413 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1414 1415 /* Flush entry from TLB0 */ 1416 tlb0_flush_entry(va); 1417 } 1418 1419 pte->rpn = pa & ~PTE_PA_MASK; 1420 pte->flags = flags; 1421 1422 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1423 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1424 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1425 1426 /* Flush the real memory from the instruction cache. */ 1427 if ((flags & (PTE_I | PTE_G)) == 0) { 1428 __syncicache((void *)va, PAGE_SIZE); 1429 } 1430 1431 tlb_miss_unlock(); 1432 mtx_unlock_spin(&tlbivax_mutex); 1433} 1434 1435/* 1436 * Remove a page from kernel page table. 1437 */ 1438static void 1439mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1440{ 1441 unsigned int pdir_idx = PDIR_IDX(va); 1442 unsigned int ptbl_idx = PTBL_IDX(va); 1443 pte_t *pte; 1444 1445// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1446 1447 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1448 (va <= VM_MAX_KERNEL_ADDRESS)), 1449 ("mmu_booke_kremove: invalid va")); 1450 1451 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1452 1453 if (!PTE_ISVALID(pte)) { 1454 1455 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1456 1457 return; 1458 } 1459 1460 mtx_lock_spin(&tlbivax_mutex); 1461 tlb_miss_lock(); 1462 1463 /* Invalidate entry in TLB0, update PTE. */ 1464 tlb0_flush_entry(va); 1465 pte->flags = 0; 1466 pte->rpn = 0; 1467 1468 tlb_miss_unlock(); 1469 mtx_unlock_spin(&tlbivax_mutex); 1470} 1471 1472/* 1473 * Initialize pmap associated with process 0. 1474 */ 1475static void 1476mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1477{ 1478 1479 mmu_booke_pinit(mmu, pmap); 1480 PCPU_SET(curpmap, pmap); 1481} 1482 1483/* 1484 * Initialize a preallocated and zeroed pmap structure, 1485 * such as one in a vmspace structure. 1486 */ 1487static void 1488mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1489{ 1490 int i; 1491 1492 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1493 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1494 1495 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1496 1497 PMAP_LOCK_INIT(pmap); 1498 for (i = 0; i < MAXCPU; i++) 1499 pmap->pm_tid[i] = TID_NONE; 1500 CPU_ZERO(&kernel_pmap->pm_active); 1501 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1502 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1503 TAILQ_INIT(&pmap->pm_ptbl_list); 1504} 1505 1506/* 1507 * Release any resources held by the given physical map. 1508 * Called when a pmap initialized by mmu_booke_pinit is being released. 1509 * Should only be called if the map contains no valid mappings. 1510 */ 1511static void 1512mmu_booke_release(mmu_t mmu, pmap_t pmap) 1513{ 1514 1515 KASSERT(pmap->pm_stats.resident_count == 0, 1516 ("pmap_release: pmap resident count %ld != 0", 1517 pmap->pm_stats.resident_count)); 1518 1519 PMAP_LOCK_DESTROY(pmap); 1520} 1521 1522/* 1523 * Insert the given physical page at the specified virtual address in the 1524 * target physical map with the protection requested. If specified the page 1525 * will be wired down. 1526 */ 1527static void 1528mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1529 vm_prot_t prot, boolean_t wired) 1530{ 1531 1532 vm_page_lock_queues(); 1533 PMAP_LOCK(pmap); 1534 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1535 vm_page_unlock_queues(); 1536 PMAP_UNLOCK(pmap); 1537} 1538 1539static void 1540mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1541 vm_prot_t prot, boolean_t wired) 1542{ 1543 pte_t *pte; 1544 vm_paddr_t pa; 1545 uint32_t flags; 1546 int su, sync; 1547 1548 pa = VM_PAGE_TO_PHYS(m); 1549 su = (pmap == kernel_pmap); 1550 sync = 0; 1551 1552 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1553 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1554 // (u_int32_t)pmap, su, pmap->pm_tid, 1555 // (u_int32_t)m, va, pa, prot, wired); 1556 1557 if (su) { 1558 KASSERT(((va >= virtual_avail) && 1559 (va <= VM_MAX_KERNEL_ADDRESS)), 1560 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1561 } else { 1562 KASSERT((va <= VM_MAXUSER_ADDRESS), 1563 ("mmu_booke_enter_locked: user pmap, non user va")); 1564 } 1565 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1566 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1567 ("mmu_booke_enter_locked: page %p is not busy", m)); 1568 1569 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1570 1571 /* 1572 * If there is an existing mapping, and the physical address has not 1573 * changed, must be protection or wiring change. 1574 */ 1575 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1576 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1577 1578 /* 1579 * Before actually updating pte->flags we calculate and 1580 * prepare its new value in a helper var. 1581 */ 1582 flags = pte->flags; 1583 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1584 1585 /* Wiring change, just update stats. */ 1586 if (wired) { 1587 if (!PTE_ISWIRED(pte)) { 1588 flags |= PTE_WIRED; 1589 pmap->pm_stats.wired_count++; 1590 } 1591 } else { 1592 if (PTE_ISWIRED(pte)) { 1593 flags &= ~PTE_WIRED; 1594 pmap->pm_stats.wired_count--; 1595 } 1596 } 1597 1598 if (prot & VM_PROT_WRITE) { 1599 /* Add write permissions. */ 1600 flags |= PTE_SW; 1601 if (!su) 1602 flags |= PTE_UW; 1603 1604 if ((flags & PTE_MANAGED) != 0) 1605 vm_page_flag_set(m, PG_WRITEABLE); 1606 } else { 1607 /* Handle modified pages, sense modify status. */ 1608 1609 /* 1610 * The PTE_MODIFIED flag could be set by underlying 1611 * TLB misses since we last read it (above), possibly 1612 * other CPUs could update it so we check in the PTE 1613 * directly rather than rely on that saved local flags 1614 * copy. 1615 */ 1616 if (PTE_ISMODIFIED(pte)) 1617 vm_page_dirty(m); 1618 } 1619 1620 if (prot & VM_PROT_EXECUTE) { 1621 flags |= PTE_SX; 1622 if (!su) 1623 flags |= PTE_UX; 1624 1625 /* 1626 * Check existing flags for execute permissions: if we 1627 * are turning execute permissions on, icache should 1628 * be flushed. 1629 */ 1630 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1631 sync++; 1632 } 1633 1634 flags &= ~PTE_REFERENCED; 1635 1636 /* 1637 * The new flags value is all calculated -- only now actually 1638 * update the PTE. 1639 */ 1640 mtx_lock_spin(&tlbivax_mutex); 1641 tlb_miss_lock(); 1642 1643 tlb0_flush_entry(va); 1644 pte->flags = flags; 1645 1646 tlb_miss_unlock(); 1647 mtx_unlock_spin(&tlbivax_mutex); 1648 1649 } else { 1650 /* 1651 * If there is an existing mapping, but it's for a different 1652 * physical address, pte_enter() will delete the old mapping. 1653 */ 1654 //if ((pte != NULL) && PTE_ISVALID(pte)) 1655 // debugf("mmu_booke_enter_locked: replace\n"); 1656 //else 1657 // debugf("mmu_booke_enter_locked: new\n"); 1658 1659 /* Now set up the flags and install the new mapping. */ 1660 flags = (PTE_SR | PTE_VALID); 1661 flags |= PTE_M; 1662 1663 if (!su) 1664 flags |= PTE_UR; 1665 1666 if (prot & VM_PROT_WRITE) { 1667 flags |= PTE_SW; 1668 if (!su) 1669 flags |= PTE_UW; 1670 1671 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1672 vm_page_flag_set(m, PG_WRITEABLE); 1673 } 1674 1675 if (prot & VM_PROT_EXECUTE) { 1676 flags |= PTE_SX; 1677 if (!su) 1678 flags |= PTE_UX; 1679 } 1680 1681 /* If its wired update stats. */ 1682 if (wired) { 1683 pmap->pm_stats.wired_count++; 1684 flags |= PTE_WIRED; 1685 } 1686 1687 pte_enter(mmu, pmap, m, va, flags); 1688 1689 /* Flush the real memory from the instruction cache. */ 1690 if (prot & VM_PROT_EXECUTE) 1691 sync++; 1692 } 1693 1694 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1695 __syncicache((void *)va, PAGE_SIZE); 1696 sync = 0; 1697 } 1698} 1699 1700/* 1701 * Maps a sequence of resident pages belonging to the same object. 1702 * The sequence begins with the given page m_start. This page is 1703 * mapped at the given virtual address start. Each subsequent page is 1704 * mapped at a virtual address that is offset from start by the same 1705 * amount as the page is offset from m_start within the object. The 1706 * last page in the sequence is the page with the largest offset from 1707 * m_start that can be mapped at a virtual address less than the given 1708 * virtual address end. Not every virtual page between start and end 1709 * is mapped; only those for which a resident page exists with the 1710 * corresponding offset from m_start are mapped. 1711 */ 1712static void 1713mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1714 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1715{ 1716 vm_page_t m; 1717 vm_pindex_t diff, psize; 1718 1719 psize = atop(end - start); 1720 m = m_start; 1721 vm_page_lock_queues(); 1722 PMAP_LOCK(pmap); 1723 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1724 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1725 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1726 m = TAILQ_NEXT(m, listq); 1727 } 1728 vm_page_unlock_queues(); 1729 PMAP_UNLOCK(pmap); 1730} 1731 1732static void 1733mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1734 vm_prot_t prot) 1735{ 1736 1737 vm_page_lock_queues(); 1738 PMAP_LOCK(pmap); 1739 mmu_booke_enter_locked(mmu, pmap, va, m, 1740 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1741 vm_page_unlock_queues(); 1742 PMAP_UNLOCK(pmap); 1743} 1744 1745/* 1746 * Remove the given range of addresses from the specified map. 1747 * 1748 * It is assumed that the start and end are properly rounded to the page size. 1749 */ 1750static void 1751mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1752{ 1753 pte_t *pte; 1754 uint8_t hold_flag; 1755 1756 int su = (pmap == kernel_pmap); 1757 1758 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1759 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1760 1761 if (su) { 1762 KASSERT(((va >= virtual_avail) && 1763 (va <= VM_MAX_KERNEL_ADDRESS)), 1764 ("mmu_booke_remove: kernel pmap, non kernel va")); 1765 } else { 1766 KASSERT((va <= VM_MAXUSER_ADDRESS), 1767 ("mmu_booke_remove: user pmap, non user va")); 1768 } 1769 1770 if (PMAP_REMOVE_DONE(pmap)) { 1771 //debugf("mmu_booke_remove: e (empty)\n"); 1772 return; 1773 } 1774 1775 hold_flag = PTBL_HOLD_FLAG(pmap); 1776 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1777 1778 vm_page_lock_queues(); 1779 PMAP_LOCK(pmap); 1780 for (; va < endva; va += PAGE_SIZE) { 1781 pte = pte_find(mmu, pmap, va); 1782 if ((pte != NULL) && PTE_ISVALID(pte)) 1783 pte_remove(mmu, pmap, va, hold_flag); 1784 } 1785 PMAP_UNLOCK(pmap); 1786 vm_page_unlock_queues(); 1787 1788 //debugf("mmu_booke_remove: e\n"); 1789} 1790 1791/* 1792 * Remove physical page from all pmaps in which it resides. 1793 */ 1794static void 1795mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1796{ 1797 pv_entry_t pv, pvn; 1798 uint8_t hold_flag; 1799 1800 vm_page_lock_queues(); 1801 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1802 pvn = TAILQ_NEXT(pv, pv_link); 1803 1804 PMAP_LOCK(pv->pv_pmap); 1805 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1806 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1807 PMAP_UNLOCK(pv->pv_pmap); 1808 } 1809 vm_page_flag_clear(m, PG_WRITEABLE); 1810 vm_page_unlock_queues(); 1811} 1812 1813/* 1814 * Map a range of physical addresses into kernel virtual address space. 1815 */ 1816static vm_offset_t 1817mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1818 vm_offset_t pa_end, int prot) 1819{ 1820 vm_offset_t sva = *virt; 1821 vm_offset_t va = sva; 1822 1823 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1824 // sva, pa_start, pa_end); 1825 1826 while (pa_start < pa_end) { 1827 mmu_booke_kenter(mmu, va, pa_start); 1828 va += PAGE_SIZE; 1829 pa_start += PAGE_SIZE; 1830 } 1831 *virt = va; 1832 1833 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1834 return (sva); 1835} 1836 1837/* 1838 * The pmap must be activated before it's address space can be accessed in any 1839 * way. 1840 */ 1841static void 1842mmu_booke_activate(mmu_t mmu, struct thread *td) 1843{ 1844 pmap_t pmap; 1845 u_int cpuid; 1846 1847 pmap = &td->td_proc->p_vmspace->vm_pmap; 1848 1849 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1850 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1851 1852 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1853 1854 mtx_lock_spin(&sched_lock); 1855 1856 cpuid = PCPU_GET(cpuid); 1857 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 1858 PCPU_SET(curpmap, pmap); 1859 1860 if (pmap->pm_tid[cpuid] == TID_NONE) 1861 tid_alloc(pmap); 1862 1863 /* Load PID0 register with pmap tid value. */ 1864 mtspr(SPR_PID0, pmap->pm_tid[cpuid]); 1865 __asm __volatile("isync"); 1866 1867 mtx_unlock_spin(&sched_lock); 1868 1869 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1870 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1871} 1872 1873/* 1874 * Deactivate the specified process's address space. 1875 */ 1876static void 1877mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1878{ 1879 pmap_t pmap; 1880 1881 pmap = &td->td_proc->p_vmspace->vm_pmap; 1882 1883 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1884 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1885 1886 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active); 1887 PCPU_SET(curpmap, NULL); 1888} 1889 1890/* 1891 * Copy the range specified by src_addr/len 1892 * from the source map to the range dst_addr/len 1893 * in the destination map. 1894 * 1895 * This routine is only advisory and need not do anything. 1896 */ 1897static void 1898mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1899 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1900{ 1901 1902} 1903 1904/* 1905 * Set the physical protection on the specified range of this map as requested. 1906 */ 1907static void 1908mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1909 vm_prot_t prot) 1910{ 1911 vm_offset_t va; 1912 vm_page_t m; 1913 pte_t *pte; 1914 1915 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1916 mmu_booke_remove(mmu, pmap, sva, eva); 1917 return; 1918 } 1919 1920 if (prot & VM_PROT_WRITE) 1921 return; 1922 1923 vm_page_lock_queues(); 1924 PMAP_LOCK(pmap); 1925 for (va = sva; va < eva; va += PAGE_SIZE) { 1926 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1927 if (PTE_ISVALID(pte)) { 1928 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1929 1930 mtx_lock_spin(&tlbivax_mutex); 1931 tlb_miss_lock(); 1932 1933 /* Handle modified pages. */ 1934 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1935 vm_page_dirty(m); 1936 1937 tlb0_flush_entry(va); 1938 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1939 1940 tlb_miss_unlock(); 1941 mtx_unlock_spin(&tlbivax_mutex); 1942 } 1943 } 1944 } 1945 PMAP_UNLOCK(pmap); 1946 vm_page_unlock_queues(); 1947} 1948 1949/* 1950 * Clear the write and modified bits in each of the given page's mappings. 1951 */ 1952static void 1953mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1954{ 1955 pv_entry_t pv; 1956 pte_t *pte; 1957 1958 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1959 ("mmu_booke_remove_write: page %p is not managed", m)); 1960 1961 /* 1962 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1963 * another thread while the object is locked. Thus, if PG_WRITEABLE 1964 * is clear, no page table entries need updating. 1965 */ 1966 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1967 if ((m->oflags & VPO_BUSY) == 0 && 1968 (m->flags & PG_WRITEABLE) == 0) 1969 return; 1970 vm_page_lock_queues(); 1971 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1972 PMAP_LOCK(pv->pv_pmap); 1973 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1974 if (PTE_ISVALID(pte)) { 1975 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1976 1977 mtx_lock_spin(&tlbivax_mutex); 1978 tlb_miss_lock(); 1979 1980 /* Handle modified pages. */ 1981 if (PTE_ISMODIFIED(pte)) 1982 vm_page_dirty(m); 1983 1984 /* Flush mapping from TLB0. */ 1985 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1986 1987 tlb_miss_unlock(); 1988 mtx_unlock_spin(&tlbivax_mutex); 1989 } 1990 } 1991 PMAP_UNLOCK(pv->pv_pmap); 1992 } 1993 vm_page_flag_clear(m, PG_WRITEABLE); 1994 vm_page_unlock_queues(); 1995} 1996 1997static void 1998mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1999{ 2000 pte_t *pte; 2001 pmap_t pmap; 2002 vm_page_t m; 2003 vm_offset_t addr; 2004 vm_paddr_t pa; 2005 int active, valid; 2006 2007 va = trunc_page(va); 2008 sz = round_page(sz); 2009 2010 vm_page_lock_queues(); 2011 pmap = PCPU_GET(curpmap); 2012 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 2013 while (sz > 0) { 2014 PMAP_LOCK(pm); 2015 pte = pte_find(mmu, pm, va); 2016 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2017 if (valid) 2018 pa = PTE_PA(pte); 2019 PMAP_UNLOCK(pm); 2020 if (valid) { 2021 if (!active) { 2022 /* Create a mapping in the active pmap. */ 2023 addr = 0; 2024 m = PHYS_TO_VM_PAGE(pa); 2025 PMAP_LOCK(pmap); 2026 pte_enter(mmu, pmap, m, addr, 2027 PTE_SR | PTE_VALID | PTE_UR); 2028 __syncicache((void *)addr, PAGE_SIZE); 2029 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2030 PMAP_UNLOCK(pmap); 2031 } else 2032 __syncicache((void *)va, PAGE_SIZE); 2033 } 2034 va += PAGE_SIZE; 2035 sz -= PAGE_SIZE; 2036 } 2037 vm_page_unlock_queues(); 2038} 2039 2040/* 2041 * Atomically extract and hold the physical page with the given 2042 * pmap and virtual address pair if that mapping permits the given 2043 * protection. 2044 */ 2045static vm_page_t 2046mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2047 vm_prot_t prot) 2048{ 2049 pte_t *pte; 2050 vm_page_t m; 2051 uint32_t pte_wbit; 2052 vm_paddr_t pa; 2053 2054 m = NULL; 2055 pa = 0; 2056 PMAP_LOCK(pmap); 2057retry: 2058 pte = pte_find(mmu, pmap, va); 2059 if ((pte != NULL) && PTE_ISVALID(pte)) { 2060 if (pmap == kernel_pmap) 2061 pte_wbit = PTE_SW; 2062 else 2063 pte_wbit = PTE_UW; 2064 2065 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2066 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2067 goto retry; 2068 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2069 vm_page_hold(m); 2070 } 2071 } 2072 2073 PA_UNLOCK_COND(pa); 2074 PMAP_UNLOCK(pmap); 2075 return (m); 2076} 2077 2078/* 2079 * Initialize a vm_page's machine-dependent fields. 2080 */ 2081static void 2082mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2083{ 2084 2085 TAILQ_INIT(&m->md.pv_list); 2086} 2087 2088/* 2089 * mmu_booke_zero_page_area zeros the specified hardware page by 2090 * mapping it into virtual memory and using bzero to clear 2091 * its contents. 2092 * 2093 * off and size must reside within a single page. 2094 */ 2095static void 2096mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2097{ 2098 vm_offset_t va; 2099 2100 /* XXX KASSERT off and size are within a single page? */ 2101 2102 mtx_lock(&zero_page_mutex); 2103 va = zero_page_va; 2104 2105 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2106 bzero((caddr_t)va + off, size); 2107 mmu_booke_kremove(mmu, va); 2108 2109 mtx_unlock(&zero_page_mutex); 2110} 2111 2112/* 2113 * mmu_booke_zero_page zeros the specified hardware page. 2114 */ 2115static void 2116mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2117{ 2118 2119 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2120} 2121 2122/* 2123 * mmu_booke_copy_page copies the specified (machine independent) page by 2124 * mapping the page into virtual memory and using memcopy to copy the page, 2125 * one machine dependent page at a time. 2126 */ 2127static void 2128mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2129{ 2130 vm_offset_t sva, dva; 2131 2132 sva = copy_page_src_va; 2133 dva = copy_page_dst_va; 2134 2135 mtx_lock(©_page_mutex); 2136 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2137 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2138 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2139 mmu_booke_kremove(mmu, dva); 2140 mmu_booke_kremove(mmu, sva); 2141 mtx_unlock(©_page_mutex); 2142} 2143 2144/* 2145 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2146 * into virtual memory and using bzero to clear its contents. This is intended 2147 * to be called from the vm_pagezero process only and outside of Giant. No 2148 * lock is required. 2149 */ 2150static void 2151mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2152{ 2153 vm_offset_t va; 2154 2155 va = zero_page_idle_va; 2156 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2157 bzero((caddr_t)va, PAGE_SIZE); 2158 mmu_booke_kremove(mmu, va); 2159} 2160 2161/* 2162 * Return whether or not the specified physical page was modified 2163 * in any of physical maps. 2164 */ 2165static boolean_t 2166mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2167{ 2168 pte_t *pte; 2169 pv_entry_t pv; 2170 boolean_t rv; 2171 2172 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2173 ("mmu_booke_is_modified: page %p is not managed", m)); 2174 rv = FALSE; 2175 2176 /* 2177 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2178 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2179 * is clear, no PTEs can be modified. 2180 */ 2181 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2182 if ((m->oflags & VPO_BUSY) == 0 && 2183 (m->flags & PG_WRITEABLE) == 0) 2184 return (rv); 2185 vm_page_lock_queues(); 2186 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2187 PMAP_LOCK(pv->pv_pmap); 2188 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2189 PTE_ISVALID(pte)) { 2190 if (PTE_ISMODIFIED(pte)) 2191 rv = TRUE; 2192 } 2193 PMAP_UNLOCK(pv->pv_pmap); 2194 if (rv) 2195 break; 2196 } 2197 vm_page_unlock_queues(); 2198 return (rv); 2199} 2200 2201/* 2202 * Return whether or not the specified virtual address is eligible 2203 * for prefault. 2204 */ 2205static boolean_t 2206mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2207{ 2208 2209 return (FALSE); 2210} 2211 2212/* 2213 * Return whether or not the specified physical page was referenced 2214 * in any physical maps. 2215 */ 2216static boolean_t 2217mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2218{ 2219 pte_t *pte; 2220 pv_entry_t pv; 2221 boolean_t rv; 2222 2223 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2224 ("mmu_booke_is_referenced: page %p is not managed", m)); 2225 rv = FALSE; 2226 vm_page_lock_queues(); 2227 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2228 PMAP_LOCK(pv->pv_pmap); 2229 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2230 PTE_ISVALID(pte)) { 2231 if (PTE_ISREFERENCED(pte)) 2232 rv = TRUE; 2233 } 2234 PMAP_UNLOCK(pv->pv_pmap); 2235 if (rv) 2236 break; 2237 } 2238 vm_page_unlock_queues(); 2239 return (rv); 2240} 2241 2242/* 2243 * Clear the modify bits on the specified physical page. 2244 */ 2245static void 2246mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2247{ 2248 pte_t *pte; 2249 pv_entry_t pv; 2250 2251 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2252 ("mmu_booke_clear_modify: page %p is not managed", m)); 2253 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2254 KASSERT((m->oflags & VPO_BUSY) == 0, 2255 ("mmu_booke_clear_modify: page %p is busy", m)); 2256 2257 /* 2258 * If the page is not PG_WRITEABLE, then no PTEs can be modified. 2259 * If the object containing the page is locked and the page is not 2260 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2261 */ 2262 if ((m->flags & PG_WRITEABLE) == 0) 2263 return; 2264 vm_page_lock_queues(); 2265 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2266 PMAP_LOCK(pv->pv_pmap); 2267 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2268 PTE_ISVALID(pte)) { 2269 mtx_lock_spin(&tlbivax_mutex); 2270 tlb_miss_lock(); 2271 2272 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2273 tlb0_flush_entry(pv->pv_va); 2274 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2275 PTE_REFERENCED); 2276 } 2277 2278 tlb_miss_unlock(); 2279 mtx_unlock_spin(&tlbivax_mutex); 2280 } 2281 PMAP_UNLOCK(pv->pv_pmap); 2282 } 2283 vm_page_unlock_queues(); 2284} 2285 2286/* 2287 * Return a count of reference bits for a page, clearing those bits. 2288 * It is not necessary for every reference bit to be cleared, but it 2289 * is necessary that 0 only be returned when there are truly no 2290 * reference bits set. 2291 * 2292 * XXX: The exact number of bits to check and clear is a matter that 2293 * should be tested and standardized at some point in the future for 2294 * optimal aging of shared pages. 2295 */ 2296static int 2297mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2298{ 2299 pte_t *pte; 2300 pv_entry_t pv; 2301 int count; 2302 2303 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2304 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2305 count = 0; 2306 vm_page_lock_queues(); 2307 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2308 PMAP_LOCK(pv->pv_pmap); 2309 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2310 PTE_ISVALID(pte)) { 2311 if (PTE_ISREFERENCED(pte)) { 2312 mtx_lock_spin(&tlbivax_mutex); 2313 tlb_miss_lock(); 2314 2315 tlb0_flush_entry(pv->pv_va); 2316 pte->flags &= ~PTE_REFERENCED; 2317 2318 tlb_miss_unlock(); 2319 mtx_unlock_spin(&tlbivax_mutex); 2320 2321 if (++count > 4) { 2322 PMAP_UNLOCK(pv->pv_pmap); 2323 break; 2324 } 2325 } 2326 } 2327 PMAP_UNLOCK(pv->pv_pmap); 2328 } 2329 vm_page_unlock_queues(); 2330 return (count); 2331} 2332 2333/* 2334 * Clear the reference bit on the specified physical page. 2335 */ 2336static void 2337mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2338{ 2339 pte_t *pte; 2340 pv_entry_t pv; 2341 2342 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2343 ("mmu_booke_clear_reference: page %p is not managed", m)); 2344 vm_page_lock_queues(); 2345 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2346 PMAP_LOCK(pv->pv_pmap); 2347 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2348 PTE_ISVALID(pte)) { 2349 if (PTE_ISREFERENCED(pte)) { 2350 mtx_lock_spin(&tlbivax_mutex); 2351 tlb_miss_lock(); 2352 2353 tlb0_flush_entry(pv->pv_va); 2354 pte->flags &= ~PTE_REFERENCED; 2355 2356 tlb_miss_unlock(); 2357 mtx_unlock_spin(&tlbivax_mutex); 2358 } 2359 } 2360 PMAP_UNLOCK(pv->pv_pmap); 2361 } 2362 vm_page_unlock_queues(); 2363} 2364 2365/* 2366 * Change wiring attribute for a map/virtual-address pair. 2367 */ 2368static void 2369mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2370{ 2371 pte_t *pte; 2372 2373 PMAP_LOCK(pmap); 2374 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2375 if (wired) { 2376 if (!PTE_ISWIRED(pte)) { 2377 pte->flags |= PTE_WIRED; 2378 pmap->pm_stats.wired_count++; 2379 } 2380 } else { 2381 if (PTE_ISWIRED(pte)) { 2382 pte->flags &= ~PTE_WIRED; 2383 pmap->pm_stats.wired_count--; 2384 } 2385 } 2386 } 2387 PMAP_UNLOCK(pmap); 2388} 2389 2390/* 2391 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2392 * page. This count may be changed upwards or downwards in the future; it is 2393 * only necessary that true be returned for a small subset of pmaps for proper 2394 * page aging. 2395 */ 2396static boolean_t 2397mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2398{ 2399 pv_entry_t pv; 2400 int loops; 2401 boolean_t rv; 2402 2403 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2404 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2405 loops = 0; 2406 rv = FALSE; 2407 vm_page_lock_queues(); 2408 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2409 if (pv->pv_pmap == pmap) { 2410 rv = TRUE; 2411 break; 2412 } 2413 if (++loops >= 16) 2414 break; 2415 } 2416 vm_page_unlock_queues(); 2417 return (rv); 2418} 2419 2420/* 2421 * Return the number of managed mappings to the given physical page that are 2422 * wired. 2423 */ 2424static int 2425mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2426{ 2427 pv_entry_t pv; 2428 pte_t *pte; 2429 int count = 0; 2430 2431 if ((m->flags & PG_FICTITIOUS) != 0) 2432 return (count); 2433 vm_page_lock_queues(); 2434 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2435 PMAP_LOCK(pv->pv_pmap); 2436 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2437 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2438 count++; 2439 PMAP_UNLOCK(pv->pv_pmap); 2440 } 2441 vm_page_unlock_queues(); 2442 return (count); 2443} 2444 2445static int 2446mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2447{ 2448 int i; 2449 vm_offset_t va; 2450 2451 /* 2452 * This currently does not work for entries that 2453 * overlap TLB1 entries. 2454 */ 2455 for (i = 0; i < tlb1_idx; i ++) { 2456 if (tlb1_iomapped(i, pa, size, &va) == 0) 2457 return (0); 2458 } 2459 2460 return (EFAULT); 2461} 2462 2463vm_offset_t 2464mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2465 vm_size_t *sz) 2466{ 2467 vm_paddr_t pa, ppa; 2468 vm_offset_t va; 2469 vm_size_t gran; 2470 2471 /* Raw physical memory dumps don't have a virtual address. */ 2472 if (md->md_vaddr == ~0UL) { 2473 /* We always map a 256MB page at 256M. */ 2474 gran = 256 * 1024 * 1024; 2475 pa = md->md_paddr + ofs; 2476 ppa = pa & ~(gran - 1); 2477 ofs = pa - ppa; 2478 va = gran; 2479 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2480 if (*sz > (gran - ofs)) 2481 *sz = gran - ofs; 2482 return (va + ofs); 2483 } 2484 2485 /* Minidumps are based on virtual memory addresses. */ 2486 va = md->md_vaddr + ofs; 2487 if (va >= kernstart + kernsize) { 2488 gran = PAGE_SIZE - (va & PAGE_MASK); 2489 if (*sz > gran) 2490 *sz = gran; 2491 } 2492 return (va); 2493} 2494 2495void 2496mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2497 vm_offset_t va) 2498{ 2499 2500 /* Raw physical memory dumps don't have a virtual address. */ 2501 if (md->md_vaddr == ~0UL) { 2502 tlb1_idx--; 2503 tlb1[tlb1_idx].mas1 = 0; 2504 tlb1[tlb1_idx].mas2 = 0; 2505 tlb1[tlb1_idx].mas3 = 0; 2506 tlb1_write_entry(tlb1_idx); 2507 return; 2508 } 2509 2510 /* Minidumps are based on virtual memory addresses. */ 2511 /* Nothing to do... */ 2512} 2513 2514struct pmap_md * 2515mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2516{ 2517 static struct pmap_md md; 2518 pte_t *pte; 2519 vm_offset_t va; 2520 2521 if (dumpsys_minidump) { 2522 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2523 if (prev == NULL) { 2524 /* 1st: kernel .data and .bss. */ 2525 md.md_index = 1; 2526 md.md_vaddr = trunc_page((uintptr_t)_etext); 2527 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2528 return (&md); 2529 } 2530 switch (prev->md_index) { 2531 case 1: 2532 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2533 md.md_index = 2; 2534 md.md_vaddr = data_start; 2535 md.md_size = data_end - data_start; 2536 break; 2537 case 2: 2538 /* 3rd: kernel VM. */ 2539 va = prev->md_vaddr + prev->md_size; 2540 /* Find start of next chunk (from va). */ 2541 while (va < virtual_end) { 2542 /* Don't dump the buffer cache. */ 2543 if (va >= kmi.buffer_sva && 2544 va < kmi.buffer_eva) { 2545 va = kmi.buffer_eva; 2546 continue; 2547 } 2548 pte = pte_find(mmu, kernel_pmap, va); 2549 if (pte != NULL && PTE_ISVALID(pte)) 2550 break; 2551 va += PAGE_SIZE; 2552 } 2553 if (va < virtual_end) { 2554 md.md_vaddr = va; 2555 va += PAGE_SIZE; 2556 /* Find last page in chunk. */ 2557 while (va < virtual_end) { 2558 /* Don't run into the buffer cache. */ 2559 if (va == kmi.buffer_sva) 2560 break; 2561 pte = pte_find(mmu, kernel_pmap, va); 2562 if (pte == NULL || !PTE_ISVALID(pte)) 2563 break; 2564 va += PAGE_SIZE; 2565 } 2566 md.md_size = va - md.md_vaddr; 2567 break; 2568 } 2569 md.md_index = 3; 2570 /* FALLTHROUGH */ 2571 default: 2572 return (NULL); 2573 } 2574 } else { /* minidumps */ 2575 mem_regions(&physmem_regions, &physmem_regions_sz, 2576 &availmem_regions, &availmem_regions_sz); 2577 2578 if (prev == NULL) { 2579 /* first physical chunk. */ 2580 md.md_paddr = physmem_regions[0].mr_start; 2581 md.md_size = physmem_regions[0].mr_size; 2582 md.md_vaddr = ~0UL; 2583 md.md_index = 1; 2584 } else if (md.md_index < physmem_regions_sz) { 2585 md.md_paddr = physmem_regions[md.md_index].mr_start; 2586 md.md_size = physmem_regions[md.md_index].mr_size; 2587 md.md_vaddr = ~0UL; 2588 md.md_index++; 2589 } else { 2590 /* There's no next physical chunk. */ 2591 return (NULL); 2592 } 2593 } 2594 2595 return (&md); 2596} 2597 2598/* 2599 * Map a set of physical memory pages into the kernel virtual address space. 2600 * Return a pointer to where it is mapped. This routine is intended to be used 2601 * for mapping device memory, NOT real memory. 2602 */ 2603static void * 2604mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2605{ 2606 void *res; 2607 uintptr_t va; 2608 vm_size_t sz; 2609 2610 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2611 res = (void *)va; 2612 2613 do { 2614 sz = 1 << (ilog2(size) & ~1); 2615 if (bootverbose) 2616 printf("Wiring VA=%x to PA=%x (size=%x), " 2617 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2618 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2619 size -= sz; 2620 pa += sz; 2621 va += sz; 2622 } while (size > 0); 2623 2624 return (res); 2625} 2626 2627/* 2628 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2629 */ 2630static void 2631mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2632{ 2633 vm_offset_t base, offset; 2634 2635 /* 2636 * Unmap only if this is inside kernel virtual space. 2637 */ 2638 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2639 base = trunc_page(va); 2640 offset = va & PAGE_MASK; 2641 size = roundup(offset + size, PAGE_SIZE); 2642 kmem_free(kernel_map, base, size); 2643 } 2644} 2645 2646/* 2647 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2648 * specified pmap. This eliminates the blast of soft faults on process startup 2649 * and immediately after an mmap. 2650 */ 2651static void 2652mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2653 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2654{ 2655 2656 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2657 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2658 ("mmu_booke_object_init_pt: non-device object")); 2659} 2660 2661/* 2662 * Perform the pmap work for mincore. 2663 */ 2664static int 2665mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2666 vm_paddr_t *locked_pa) 2667{ 2668 2669 TODO; 2670 return (0); 2671} 2672 2673/**************************************************************************/ 2674/* TID handling */ 2675/**************************************************************************/ 2676 2677/* 2678 * Allocate a TID. If necessary, steal one from someone else. 2679 * The new TID is flushed from the TLB before returning. 2680 */ 2681static tlbtid_t 2682tid_alloc(pmap_t pmap) 2683{ 2684 tlbtid_t tid; 2685 int thiscpu; 2686 2687 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2688 2689 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2690 2691 thiscpu = PCPU_GET(cpuid); 2692 2693 tid = PCPU_GET(tid_next); 2694 if (tid > TID_MAX) 2695 tid = TID_MIN; 2696 PCPU_SET(tid_next, tid + 1); 2697 2698 /* If we are stealing TID then clear the relevant pmap's field */ 2699 if (tidbusy[thiscpu][tid] != NULL) { 2700 2701 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2702 2703 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2704 2705 /* Flush all entries from TLB0 matching this TID. */ 2706 tid_flush(tid); 2707 } 2708 2709 tidbusy[thiscpu][tid] = pmap; 2710 pmap->pm_tid[thiscpu] = tid; 2711 __asm __volatile("msync; isync"); 2712 2713 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2714 PCPU_GET(tid_next)); 2715 2716 return (tid); 2717} 2718 2719/**************************************************************************/ 2720/* TLB0 handling */ 2721/**************************************************************************/ 2722 2723static void 2724tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2725 uint32_t mas7) 2726{ 2727 int as; 2728 char desc[3]; 2729 tlbtid_t tid; 2730 vm_size_t size; 2731 unsigned int tsize; 2732 2733 desc[2] = '\0'; 2734 if (mas1 & MAS1_VALID) 2735 desc[0] = 'V'; 2736 else 2737 desc[0] = ' '; 2738 2739 if (mas1 & MAS1_IPROT) 2740 desc[1] = 'P'; 2741 else 2742 desc[1] = ' '; 2743 2744 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2745 tid = MAS1_GETTID(mas1); 2746 2747 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2748 size = 0; 2749 if (tsize) 2750 size = tsize2size(tsize); 2751 2752 debugf("%3d: (%s) [AS=%d] " 2753 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2754 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2755 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2756} 2757 2758/* Convert TLB0 va and way number to tlb0[] table index. */ 2759static inline unsigned int 2760tlb0_tableidx(vm_offset_t va, unsigned int way) 2761{ 2762 unsigned int idx; 2763 2764 idx = (way * TLB0_ENTRIES_PER_WAY); 2765 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2766 return (idx); 2767} 2768 2769/* 2770 * Invalidate TLB0 entry. 2771 */ 2772static inline void 2773tlb0_flush_entry(vm_offset_t va) 2774{ 2775 2776 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2777 2778 mtx_assert(&tlbivax_mutex, MA_OWNED); 2779 2780 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2781 __asm __volatile("isync; msync"); 2782 __asm __volatile("tlbsync; msync"); 2783 2784 CTR1(KTR_PMAP, "%s: e", __func__); 2785} 2786 2787/* Print out contents of the MAS registers for each TLB0 entry */ 2788void 2789tlb0_print_tlbentries(void) 2790{ 2791 uint32_t mas0, mas1, mas2, mas3, mas7; 2792 int entryidx, way, idx; 2793 2794 debugf("TLB0 entries:\n"); 2795 for (way = 0; way < TLB0_WAYS; way ++) 2796 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2797 2798 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2799 mtspr(SPR_MAS0, mas0); 2800 __asm __volatile("isync"); 2801 2802 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2803 mtspr(SPR_MAS2, mas2); 2804 2805 __asm __volatile("isync; tlbre"); 2806 2807 mas1 = mfspr(SPR_MAS1); 2808 mas2 = mfspr(SPR_MAS2); 2809 mas3 = mfspr(SPR_MAS3); 2810 mas7 = mfspr(SPR_MAS7); 2811 2812 idx = tlb0_tableidx(mas2, way); 2813 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2814 } 2815} 2816 2817/**************************************************************************/ 2818/* TLB1 handling */ 2819/**************************************************************************/ 2820 2821/* 2822 * TLB1 mapping notes: 2823 * 2824 * TLB1[0] CCSRBAR 2825 * TLB1[1] Kernel text and data. 2826 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2827 * windows, other devices mappings. 2828 */ 2829 2830/* 2831 * Write given entry to TLB1 hardware. 2832 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2833 */ 2834static void 2835tlb1_write_entry(unsigned int idx) 2836{ 2837 uint32_t mas0, mas7; 2838 2839 //debugf("tlb1_write_entry: s\n"); 2840 2841 /* Clear high order RPN bits */ 2842 mas7 = 0; 2843 2844 /* Select entry */ 2845 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2846 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2847 2848 mtspr(SPR_MAS0, mas0); 2849 __asm __volatile("isync"); 2850 mtspr(SPR_MAS1, tlb1[idx].mas1); 2851 __asm __volatile("isync"); 2852 mtspr(SPR_MAS2, tlb1[idx].mas2); 2853 __asm __volatile("isync"); 2854 mtspr(SPR_MAS3, tlb1[idx].mas3); 2855 __asm __volatile("isync"); 2856 mtspr(SPR_MAS7, mas7); 2857 __asm __volatile("isync; tlbwe; isync; msync"); 2858 2859 //debugf("tlb1_write_entry: e\n"); 2860} 2861 2862/* 2863 * Return the largest uint value log such that 2^log <= num. 2864 */ 2865static unsigned int 2866ilog2(unsigned int num) 2867{ 2868 int lz; 2869 2870 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2871 return (31 - lz); 2872} 2873 2874/* 2875 * Convert TLB TSIZE value to mapped region size. 2876 */ 2877static vm_size_t 2878tsize2size(unsigned int tsize) 2879{ 2880 2881 /* 2882 * size = 4^tsize KB 2883 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2884 */ 2885 2886 return ((1 << (2 * tsize)) * 1024); 2887} 2888 2889/* 2890 * Convert region size (must be power of 4) to TLB TSIZE value. 2891 */ 2892static unsigned int 2893size2tsize(vm_size_t size) 2894{ 2895 2896 return (ilog2(size) / 2 - 5); 2897} 2898 2899/* 2900 * Register permanent kernel mapping in TLB1. 2901 * 2902 * Entries are created starting from index 0 (current free entry is 2903 * kept in tlb1_idx) and are not supposed to be invalidated. 2904 */ 2905static int 2906tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2907 uint32_t flags) 2908{ 2909 uint32_t ts, tid; 2910 int tsize; 2911 2912 if (tlb1_idx >= TLB1_ENTRIES) { 2913 printf("tlb1_set_entry: TLB1 full!\n"); 2914 return (-1); 2915 } 2916 2917 /* Convert size to TSIZE */ 2918 tsize = size2tsize(size); 2919 2920 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2921 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2922 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2923 2924 /* XXX LOCK tlb1[] */ 2925 2926 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2927 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2928 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2929 2930 /* Set supervisor RWX permission bits */ 2931 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2932 2933 tlb1_write_entry(tlb1_idx++); 2934 2935 /* XXX UNLOCK tlb1[] */ 2936 2937 /* 2938 * XXX in general TLB1 updates should be propagated between CPUs, 2939 * since current design assumes to have the same TLB1 set-up on all 2940 * cores. 2941 */ 2942 return (0); 2943} 2944 2945/* 2946 * Map in contiguous RAM region into the TLB1 using maximum of 2947 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2948 * 2949 * If necessary round up last entry size and return total size 2950 * used by all allocated entries. 2951 */ 2952vm_size_t 2953tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size) 2954{ 2955 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES]; 2956 vm_size_t mapped, pgsz, base, mask; 2957 int idx, nents; 2958 2959 /* Round up to the next 1M */ 2960 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1); 2961 2962 mapped = 0; 2963 idx = 0; 2964 base = va; 2965 pgsz = 64*1024*1024; 2966 while (mapped < size) { 2967 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) { 2968 while (pgsz > (size - mapped)) 2969 pgsz >>= 2; 2970 pgs[idx++] = pgsz; 2971 mapped += pgsz; 2972 } 2973 2974 /* We under-map. Correct for this. */ 2975 if (mapped < size) { 2976 while (pgs[idx - 1] == pgsz) { 2977 idx--; 2978 mapped -= pgsz; 2979 } 2980 /* XXX We may increase beyond out starting point. */ 2981 pgsz <<= 2; 2982 pgs[idx++] = pgsz; 2983 mapped += pgsz; 2984 } 2985 } 2986 2987 nents = idx; 2988 mask = pgs[0] - 1; 2989 /* Align address to the boundary */ 2990 if (va & mask) { 2991 va = (va + mask) & ~mask; 2992 pa = (pa + mask) & ~mask; 2993 } 2994 2995 for (idx = 0; idx < nents; idx++) { 2996 pgsz = pgs[idx]; 2997 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz); 2998 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM); 2999 pa += pgsz; 3000 va += pgsz; 3001 } 3002 3003 mapped = (va - base); 3004 debugf("mapped size 0x%08x (wasted space 0x%08x)\n", 3005 mapped, mapped - size); 3006 return (mapped); 3007} 3008 3009/* 3010 * TLB1 initialization routine, to be called after the very first 3011 * assembler level setup done in locore.S. 3012 */ 3013void 3014tlb1_init(vm_offset_t ccsrbar) 3015{ 3016 uint32_t mas0, mas1, mas3; 3017 uint32_t tsz; 3018 u_int i; 3019 3020 if (bootinfo != NULL && bootinfo[0] != 1) { 3021 tlb1_idx = *((uint16_t *)(bootinfo + 8)); 3022 } else 3023 tlb1_idx = 1; 3024 3025 /* The first entry/entries are used to map the kernel. */ 3026 for (i = 0; i < tlb1_idx; i++) { 3027 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3028 mtspr(SPR_MAS0, mas0); 3029 __asm __volatile("isync; tlbre"); 3030 3031 mas1 = mfspr(SPR_MAS1); 3032 if ((mas1 & MAS1_VALID) == 0) 3033 continue; 3034 3035 mas3 = mfspr(SPR_MAS3); 3036 3037 tlb1[i].mas1 = mas1; 3038 tlb1[i].mas2 = mfspr(SPR_MAS2); 3039 tlb1[i].mas3 = mas3; 3040 3041 if (i == 0) 3042 kernload = mas3 & MAS3_RPN; 3043 3044 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3045 kernsize += (tsz > 0) ? tsize2size(tsz) : 0; 3046 } 3047 3048 /* Map in CCSRBAR. */ 3049 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3050 3051 /* Setup TLB miss defaults */ 3052 set_mas4_defaults(); 3053} 3054 3055/* 3056 * Setup MAS4 defaults. 3057 * These values are loaded to MAS0-2 on a TLB miss. 3058 */ 3059static void 3060set_mas4_defaults(void) 3061{ 3062 uint32_t mas4; 3063 3064 /* Defaults: TLB0, PID0, TSIZED=4K */ 3065 mas4 = MAS4_TLBSELD0; 3066 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3067#ifdef SMP 3068 mas4 |= MAS4_MD; 3069#endif 3070 mtspr(SPR_MAS4, mas4); 3071 __asm __volatile("isync"); 3072} 3073 3074/* 3075 * Print out contents of the MAS registers for each TLB1 entry 3076 */ 3077void 3078tlb1_print_tlbentries(void) 3079{ 3080 uint32_t mas0, mas1, mas2, mas3, mas7; 3081 int i; 3082 3083 debugf("TLB1 entries:\n"); 3084 for (i = 0; i < TLB1_ENTRIES; i++) { 3085 3086 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3087 mtspr(SPR_MAS0, mas0); 3088 3089 __asm __volatile("isync; tlbre"); 3090 3091 mas1 = mfspr(SPR_MAS1); 3092 mas2 = mfspr(SPR_MAS2); 3093 mas3 = mfspr(SPR_MAS3); 3094 mas7 = mfspr(SPR_MAS7); 3095 3096 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3097 } 3098} 3099 3100/* 3101 * Print out contents of the in-ram tlb1 table. 3102 */ 3103void 3104tlb1_print_entries(void) 3105{ 3106 int i; 3107 3108 debugf("tlb1[] table entries:\n"); 3109 for (i = 0; i < TLB1_ENTRIES; i++) 3110 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3111} 3112 3113/* 3114 * Return 0 if the physical IO range is encompassed by one of the 3115 * the TLB1 entries, otherwise return related error code. 3116 */ 3117static int 3118tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3119{ 3120 uint32_t prot; 3121 vm_paddr_t pa_start; 3122 vm_paddr_t pa_end; 3123 unsigned int entry_tsize; 3124 vm_size_t entry_size; 3125 3126 *va = (vm_offset_t)NULL; 3127 3128 /* Skip invalid entries */ 3129 if (!(tlb1[i].mas1 & MAS1_VALID)) 3130 return (EINVAL); 3131 3132 /* 3133 * The entry must be cache-inhibited, guarded, and r/w 3134 * so it can function as an i/o page 3135 */ 3136 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3137 if (prot != (MAS2_I | MAS2_G)) 3138 return (EPERM); 3139 3140 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3141 if (prot != (MAS3_SR | MAS3_SW)) 3142 return (EPERM); 3143 3144 /* The address should be within the entry range. */ 3145 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3146 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3147 3148 entry_size = tsize2size(entry_tsize); 3149 pa_start = tlb1[i].mas3 & MAS3_RPN; 3150 pa_end = pa_start + entry_size - 1; 3151 3152 if ((pa < pa_start) || ((pa + size) > pa_end)) 3153 return (ERANGE); 3154 3155 /* Return virtual address of this mapping. */ 3156 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3157 return (0); 3158} 3159